x86.h@ 7096

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 innotek GmbH
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	/*
27	* x86.mac is generated from this file using:
28	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
29	*/
30
31	#ifndef ___VBox_x86_h
32	#define ___VBox_x86_h
33
34	#include <VBox/types.h>
35
36	/* Workaround for Solaris sys/regset.h defining CS, DS */
37	#if defined(RT_OS_SOLARIS)
38	# undef CS
39	# undef DS
40	#endif
41
42	/** @defgroup grp_x86 x86 Types and Definitions
43	* @{
44	*/
45
46	/**
47	* EFLAGS Bits.
48	*/
49	typedef struct X86EFLAGSBITS
50	{
51	/** Bit 0 - CF - Carry flag - Status flag. */
52	unsigned u1CF : 1;
53	/** Bit 1 - 1 - Reserved flag. */
54	unsigned u1Reserved0 : 1;
55	/** Bit 2 - PF - Parity flag - Status flag. */
56	unsigned u1PF : 1;
57	/** Bit 3 - 0 - Reserved flag. */
58	unsigned u1Reserved1 : 1;
59	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
60	unsigned u1AF : 1;
61	/** Bit 5 - 0 - Reserved flag. */
62	unsigned u1Reserved2 : 1;
63	/** Bit 6 - ZF - Zero flag - Status flag. */
64	unsigned u1ZF : 1;
65	/** Bit 7 - SF - Signed flag - Status flag. */
66	unsigned u1SF : 1;
67	/** Bit 8 - TF - Trap flag - System flag. */
68	unsigned u1TF : 1;
69	/** Bit 9 - IF - Interrupt flag - System flag. */
70	unsigned u1IF : 1;
71	/** Bit 10 - DF - Direction flag - Control flag. */
72	unsigned u1DF : 1;
73	/** Bit 11 - OF - Overflow flag - Status flag. */
74	unsigned u1OF : 1;
75	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
76	unsigned u2IOPL : 2;
77	/** Bit 14 - NT - Nested task flag - System flag. */
78	unsigned u1NT : 1;
79	/** Bit 15 - 0 - Reserved flag. */
80	unsigned u1Reserved3 : 1;
81	/** Bit 16 - RF - Resume flag - System flag. */
82	unsigned u1RF : 1;
83	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
84	unsigned u1VM : 1;
85	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
86	unsigned u1AC : 1;
87	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
88	unsigned u1VIF : 1;
89	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
90	unsigned u1VIP : 1;
91	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
92	unsigned u1ID : 1;
93	/** Bit 22-31 - 0 - Reserved flag. */
94	unsigned u10Reserved4 : 10;
95	} X86EFLAGSBITS;
96	/** Pointer to EFLAGS bits. */
97	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
98	/** Pointer to const EFLAGS bits. */
99	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
100
101	/**
102	* EFLAGS.
103	*/
104	typedef union X86EFLAGS
105	{
106	/** The bitfield view. */
107	X86EFLAGSBITS Bits;
108	/** The 8-bit view. */
109	uint8_t au8[4];
110	/** The 16-bit view. */
111	uint16_t au16[2];
112	/** The 32-bit view. */
113	uint32_t au32[1];
114	/** The 32-bit view. */
115	uint32_t u32;
116	} X86EFLAGS;
117	/** Pointer to EFLAGS. */
118	typedef X86EFLAGS *PX86EFLAGS;
119	/** Pointer to const EFLAGS. */
120	typedef const X86EFLAGS *PCX86EFLAGS;
121
122	/**
123	* RFLAGS (32 upper bits are reserved)
124	*/
125	typedef union X86RFLAGS
126	{
127	/** The bitfield view. */
128	X86EFLAGSBITS Bits;
129	/** The 8-bit view. */
130	uint8_t au8[8];
131	/** The 16-bit view. */
132	uint16_t au16[4];
133	/** The 32-bit view. */
134	uint32_t au32[2];
135	/** The 64-bit view. */
136	uint64_t au64[1];
137	/** The 64-bit view. */
138	uint64_t u64;
139	} X86RFLAGS;
140	/** Pointer to RFLAGS. */
141	typedef X86RFLAGS *PX86RFLAGS;
142	/** Pointer to const RFLAGS. */
143	typedef const X86RFLAGS *PCX86RFLAGS;
144
145
146	/** @name EFLAGS
147	* @{
148	*/
149	/** Bit 0 - CF - Carry flag - Status flag. */
150	#define X86_EFL_CF RT_BIT(0)
151	/** Bit 2 - PF - Parity flag - Status flag. */
152	#define X86_EFL_PF RT_BIT(2)
153	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
154	#define X86_EFL_AF RT_BIT(4)
155	/** Bit 6 - ZF - Zero flag - Status flag. */
156	#define X86_EFL_ZF RT_BIT(6)
157	/** Bit 7 - SF - Signed flag - Status flag. */
158	#define X86_EFL_SF RT_BIT(7)
159	/** Bit 8 - TF - Trap flag - System flag. */
160	#define X86_EFL_TF RT_BIT(8)
161	/** Bit 9 - IF - Interrupt flag - System flag. */
162	#define X86_EFL_IF RT_BIT(9)
163	/** Bit 10 - DF - Direction flag - Control flag. */
164	#define X86_EFL_DF RT_BIT(10)
165	/** Bit 11 - OF - Overflow flag - Status flag. */
166	#define X86_EFL_OF RT_BIT(11)
167	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
168	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
169	/** Bit 14 - NT - Nested task flag - System flag. */
170	#define X86_EFL_NT RT_BIT(14)
171	/** Bit 16 - RF - Resume flag - System flag. */
172	#define X86_EFL_RF RT_BIT(16)
173	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
174	#define X86_EFL_VM RT_BIT(17)
175	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
176	#define X86_EFL_AC RT_BIT(18)
177	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
178	#define X86_EFL_VIF RT_BIT(19)
179	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
180	#define X86_EFL_VIP RT_BIT(20)
181	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
182	#define X86_EFL_ID RT_BIT(21)
183	/** IOPL shift. */
184	#define X86_EFL_IOPL_SHIFT 12
185	/** The the IOPL level from the flags. */
186	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
187	/** @} */
188
189
190	/** CPUID Feature information - ECX.
191	* CPUID query with EAX=1.
192	*/
193	typedef struct X86CPUIDFEATECX
194	{
195	/** Bit 0 - SSE3 - Supports SSE3 or not. */
196	unsigned u1SSE3 : 1;
197	/** Reserved. */
198	unsigned u2Reserved1 : 2;
199	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
200	unsigned u1Monitor : 1;
201	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
202	unsigned u1CPLDS : 1;
203	/** Bit 5 - VMX - Virtual Machine Technology. */
204	unsigned u1VMX : 1;
205	/** Reserved. */
206	unsigned u1Reserved2 : 1;
207	/** Bit 7 - EST - Enh. SpeedStep Tech. */
208	unsigned u1EST : 1;
209	/** Bit 8 - TM2 - Terminal Monitor 2. */
210	unsigned u1TM2 : 1;
211	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
212	unsigned u1SSSE3 : 1;
213	/** Bit 10 - CNTX-ID - L1 Context ID. */
214	unsigned u1CNTXID : 1;
215	/** Reserved. */
216	unsigned u2Reserved4 : 2;
217	/** Bit 13 - CX16 - CMPXCHG16B. */
218	unsigned u1CX16 : 1;
219	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
220	unsigned u1TPRUpdate : 1;
221	/** Reserved. */
222	unsigned u17Reserved5 : 17;
223
224	} X86CPUIDFEATECX;
225	/** Pointer to CPUID Feature Information - ECX. */
226	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
227	/** Pointer to const CPUID Feature Information - ECX. */
228	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
229
230
231	/** CPUID Feature Information - EDX.
232	* CPUID query with EAX=1.
233	*/
234	typedef struct X86CPUIDFEATEDX
235	{
236	/** Bit 0 - FPU - x87 FPU on Chip. */
237	unsigned u1FPU : 1;
238	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
239	unsigned u1VME : 1;
240	/** Bit 2 - DE - Debugging extensions. */
241	unsigned u1DE : 1;
242	/** Bit 3 - PSE - Page Size Extension. */
243	unsigned u1PSE : 1;
244	/** Bit 4 - TSC - Time Stamp Counter. */
245	unsigned u1TSC : 1;
246	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
247	unsigned u1MSR : 1;
248	/** Bit 6 - PAE - Physical Address Extension. */
249	unsigned u1PAE : 1;
250	/** Bit 7 - MCE - Machine Check Exception. */
251	unsigned u1MCE : 1;
252	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
253	unsigned u1CX8 : 1;
254	/** Bit 9 - APIC - APIC On-Chick. */
255	unsigned u1APIC : 1;
256	/** Bit 10 - Reserved. */
257	unsigned u1Reserved1 : 1;
258	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
259	unsigned u1SEP : 1;
260	/** Bit 12 - MTRR - Memory Type Range Registers. */
261	unsigned u1MTRR : 1;
262	/** Bit 13 - PGE - PTE Global Bit. */
263	unsigned u1PGE : 1;
264	/** Bit 14 - MCA - Machine Check Architecture. */
265	unsigned u1MCA : 1;
266	/** Bit 15 - CMOV - Conditional Move Instructions. */
267	unsigned u1CMOV : 1;
268	/** Bit 16 - PAT - Page Attribute Table. */
269	unsigned u1PAT : 1;
270	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
271	unsigned u1PSE36 : 1;
272	/** Bit 18 - PSN - Processor Serial Number. */
273	unsigned u1PSN : 1;
274	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
275	unsigned u1CLFSH : 1;
276	/** Bit 20 - Reserved. */
277	unsigned u1Reserved2 : 1;
278	/** Bit 21 - DS - Debug Store. */
279	unsigned u1DS : 1;
280	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
281	unsigned u1ACPI : 1;
282	/** Bit 23 - MMX - Intel MMX 'Technology'. */
283	unsigned u1MMX : 1;
284	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
285	unsigned u1FXSR : 1;
286	/** Bit 25 - SSE - SSE Support. */
287	unsigned u1SSE : 1;
288	/** Bit 26 - SSE2 - SSE2 Support. */
289	unsigned u1SSE2 : 1;
290	/** Bit 27 - SS - Self Snoop. */
291	unsigned u1SS : 1;
292	/** Bit 28 - HTT - Hyper-Threading Technology. */
293	unsigned u1HTT : 1;
294	/** Bit 29 - TM - Thermal Monitor. */
295	unsigned u1TM : 1;
296	/** Bit 30 - Reserved - . */
297	unsigned u1Reserved3 : 1;
298	/** Bit 31 - PBE - Pending Break Enabled. */
299	unsigned u1PBE : 1;
300	} X86CPUIDFEATEDX;
301	/** Pointer to CPUID Feature Information - EDX. */
302	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
303	/** Pointer to const CPUID Feature Information - EDX. */
304	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
305
306	/** @name CPUID Vendor information.
307	* CPUID query with EAX=0.
308	* @{
309	*/
310	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
311	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
312	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
313
314	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
315	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
316	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
317	/** @} */
318
319
320	/** @name CPUID Feature information.
321	* CPUID query with EAX=1.
322	* @{
323	*/
324	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
325	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
326	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
327	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
328	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
329	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
330	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
331	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
332	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
333	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
334	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
335	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
336	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
337	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
338	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
339	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
340	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
341	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
342	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
343	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
344	/** ECX Bit 23 - POPCOUNT instruction. */
345	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
346
347
348	/** Bit 0 - FPU - x87 FPU on Chip. */
349	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
350	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
351	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
352	/** Bit 2 - DE - Debugging extensions. */
353	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
354	/** Bit 3 - PSE - Page Size Extension. */
355	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
356	/** Bit 4 - TSC - Time Stamp Counter. */
357	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
358	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
359	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
360	/** Bit 6 - PAE - Physical Address Extension. */
361	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
362	/** Bit 7 - MCE - Machine Check Exception. */
363	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
364	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
365	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
366	/** Bit 9 - APIC - APIC On-Chip. */
367	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
368	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
369	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
370	/** Bit 12 - MTRR - Memory Type Range Registers. */
371	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
372	/** Bit 13 - PGE - PTE Global Bit. */
373	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
374	/** Bit 14 - MCA - Machine Check Architecture. */
375	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
376	/** Bit 15 - CMOV - Conditional Move Instructions. */
377	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
378	/** Bit 16 - PAT - Page Attribute Table. */
379	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
380	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
381	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
382	/** Bit 18 - PSN - Processor Serial Number. */
383	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
384	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
385	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
386	/** Bit 21 - DS - Debug Store. */
387	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
388	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
389	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
390	/** Bit 23 - MMX - Intel MMX Technology. */
391	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
392	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
393	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
394	/** Bit 25 - SSE - SSE Support. */
395	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
396	/** Bit 26 - SSE2 - SSE2 Support. */
397	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
398	/** Bit 27 - SS - Self Snoop. */
399	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
400	/** Bit 28 - HTT - Hyper-Threading Technology. */
401	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
402	/** Bit 29 - TM - Therm. Monitor. */
403	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
404	/** Bit 31 - PBE - Pending Break Enabled. */
405	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
406	/** @} */
407
408
409	/** @name CPUID AMD Feature information.
410	* CPUID query with EAX=0x80000001.
411	* @{
412	*/
413	/** Bit 0 - FPU - x87 FPU on Chip. */
414	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
415	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
416	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
417	/** Bit 2 - DE - Debugging extensions. */
418	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
419	/** Bit 3 - PSE - Page Size Extension. */
420	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
421	/** Bit 4 - TSC - Time Stamp Counter. */
422	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
423	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
424	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
425	/** Bit 6 - PAE - Physical Address Extension. */
426	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
427	/** Bit 7 - MCE - Machine Check Exception. */
428	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
429	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
430	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
431	/** Bit 9 - APIC - APIC On-Chip. */
432	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
433	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
434	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
435	/** Bit 12 - MTRR - Memory Type Range Registers. */
436	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
437	/** Bit 13 - PGE - PTE Global Bit. */
438	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
439	/** Bit 14 - MCA - Machine Check Architecture. */
440	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
441	/** Bit 15 - CMOV - Conditional Move Instructions. */
442	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
443	/** Bit 16 - PAT - Page Attribute Table. */
444	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
445	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
446	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
447	/** Bit 20 - NX - AMD No-Execute Page Protection. */
448	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
449	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
450	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
451	/** Bit 23 - MMX - Intel MMX Technology. */
452	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
453	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
454	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
455	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
456	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
457	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
458	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
459	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
460	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
461	/** Bit 29 - LM - AMD Long Mode. */
462	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
463	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
464	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
465	/** Bit 31 - 3DNOW - AMD 3DNow. */
466	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
467
468	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
469	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
470	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
471	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
472	/** Bit 2 - SVM - AMD VM extensions. */
473	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
474	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
475	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
476	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
477	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
478	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
479	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
480	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
481	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
482	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
483	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
484	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
485	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
486	/** Bit 9 - OSVW - AMD OS visible workaround. */
487	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
488	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
490	/** Bit 13 - WDT - AMD Watchdog timer support. */
491	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
492
493	/** @} */
494
495
496	/** @name CR0
497	* @{ */
498	/** Bit 0 - PE - Protection Enabled */
499	#define X86_CR0_PE RT_BIT(0)
500	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
501	/** Bit 1 - MP - Monitor Coprocessor */
502	#define X86_CR0_MP RT_BIT(1)
503	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
504	/** Bit 2 - EM - Emulation. */
505	#define X86_CR0_EM RT_BIT(2)
506	#define X86_CR0_EMULATE_FPU RT_BIT(2)
507	/** Bit 3 - TS - Task Switch. */
508	#define X86_CR0_TS RT_BIT(3)
509	#define X86_CR0_TASK_SWITCH RT_BIT(3)
510	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
511	#define X86_CR0_ET RT_BIT(4)
512	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
513	/** Bit 5 - NE - Numeric error. */
514	#define X86_CR0_NE RT_BIT(5)
515	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
516	/** Bit 16 - WP - Write Protect. */
517	#define X86_CR0_WP RT_BIT(16)
518	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
519	/** Bit 18 - AM - Alignment Mask. */
520	#define X86_CR0_AM RT_BIT(18)
521	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
522	/** Bit 29 - NW - Not Write-though. */
523	#define X86_CR0_NW RT_BIT(29)
524	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
525	/** Bit 30 - WP - Cache Disable. */
526	#define X86_CR0_CD RT_BIT(30)
527	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
528	/** Bit 31 - PG - Paging. */
529	#define X86_CR0_PG RT_BIT(31)
530	#define X86_CR0_PAGING RT_BIT(31)
531	/** @} */
532
533
534	/** @name CR3
535	* @{ */
536	/** Bit 3 - PWT - Page-level Writes Transparent. */
537	#define X86_CR3_PWT RT_BIT(3)
538	/** Bit 4 - PCD - Page-level Cache Disable. */
539	#define X86_CR3_PCD RT_BIT(4)
540	/** Bits 12-31 - - Page directory page number. */
541	#define X86_CR3_PAGE_MASK (0xfffff000)
542	/** Bits 5-31 - - PAE Page directory page number. */
543	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
544	/** @} */
545
546
547	/** @name CR4
548	* @{ */
549	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
550	#define X86_CR4_VME RT_BIT(0)
551	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
552	#define X86_CR4_PVI RT_BIT(1)
553	/** Bit 2 - TSD - Time Stamp Disable. */
554	#define X86_CR4_TSD RT_BIT(2)
555	/** Bit 3 - DE - Debugging Extensions. */
556	#define X86_CR4_DE RT_BIT(3)
557	/** Bit 4 - PSE - Page Size Extension. */
558	#define X86_CR4_PSE RT_BIT(4)
559	/** Bit 5 - PAE - Physical Address Extension. */
560	#define X86_CR4_PAE RT_BIT(5)
561	/** Bit 6 - MCE - Machine-Check Enable. */
562	#define X86_CR4_MCE RT_BIT(6)
563	/** Bit 7 - PGE - Page Global Enable. */
564	#define X86_CR4_PGE RT_BIT(7)
565	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
566	#define X86_CR4_PCE RT_BIT(8)
567	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
568	#define X86_CR4_OSFSXR RT_BIT(9)
569	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
570	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
571	/** Bit 13 - VMXE - VMX mode is enabled. */
572	#define X86_CR4_VMXE RT_BIT(13)
573	/** @} */
574
575
576	/** @name DR6
577	* @{ */
578	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
579	#define X86_DR6_B0 RT_BIT(0)
580	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
581	#define X86_DR6_B1 RT_BIT(1)
582	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
583	#define X86_DR6_B2 RT_BIT(2)
584	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
585	#define X86_DR6_B3 RT_BIT(3)
586	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
587	#define X86_DR6_BD RT_BIT(13)
588	/** Bit 14 - BS - Single step */
589	#define X86_DR6_BS RT_BIT(14)
590	/** Bit 15 - BT - Task switch. (TSS T bit.) */
591	#define X86_DR6_BT RT_BIT(15)
592	/** @} */
593
594
595	/** @name DR7
596	* @{ */
597	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
598	#define X86_DR7_L0 RT_BIT(0)
599	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
600	#define X86_DR7_G0 RT_BIT(1)
601	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
602	#define X86_DR7_L1 RT_BIT(2)
603	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
604	#define X86_DR7_G1 RT_BIT(3)
605	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
606	#define X86_DR7_L2 RT_BIT(4)
607	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
608	#define X86_DR7_G2 RT_BIT(5)
609	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
610	#define X86_DR7_L3 RT_BIT(6)
611	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
612	#define X86_DR7_G3 RT_BIT(7)
613	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
614	#define X86_DR7_LE RT_BIT(8)
615	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
616	#define X86_DR7_GE RT_BIT(9)
617
618	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
619	* any DR register is accessed. */
620	#define X86_DR7_GD RT_BIT(13)
621	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
622	#define X86_DR7_RW0_MASK (3 << 16)
623	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
624	#define X86_DR7_LEN0_MASK (3 << 18)
625	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
626	#define X86_DR7_RW1_MASK (3 << 20)
627	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
628	#define X86_DR7_LEN1_MASK (3 << 22)
629	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
630	#define X86_DR7_RW2_MASK (3 << 24)
631	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
632	#define X86_DR7_LEN2_MASK (3 << 26)
633	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
634	#define X86_DR7_RW3_MASK (3 << 28)
635	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
636	#define X86_DR7_LEN3_MASK (3 << 30)
637
638	/** Bits which must be 1s. */
639	#define X86_DR7_MB1_MASK (RT_BIT(10))
640
641	/** Calcs the L bit of Nth breakpoint.
642	* @param iBp The breakpoint number [0..3].
643	*/
644	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
645
646	/** Calcs the G bit of Nth breakpoint.
647	* @param iBp The breakpoint number [0..3].
648	*/
649	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
650
651	/** @name Read/Write values.
652	* @{ */
653	/** Break on instruction fetch only. */
654	#define X86_DR7_RW_EO 0
655	/** Break on write only. */
656	#define X86_DR7_RW_WO 1
657	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
658	#define X86_DR7_RW_IO 2
659	/** Break on read or write (but not instruction fetches). */
660	#define X86_DR7_RW_RW 3
661	/** @} */
662
663	/** Shifts a X86_DR7_RW_* value to its right place.
664	* @param iBp The breakpoint number [0..3].
665	* @param fRw One of the X86_DR7_RW_* value.
666	*/
667	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
668
669	/** @name Length values.
670	* @{ */
671	#define X86_DR7_LEN_BYTE 0
672	#define X86_DR7_LEN_WORD 1
673	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
674	#define X86_DR7_LEN_DWORD 3
675	/** @} */
676
677	/** Shifts a X86_DR7_LEN_* value to its right place.
678	* @param iBp The breakpoint number [0..3].
679	* @param cb One of the X86_DR7_LEN_* values.
680	*/
681	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
682
683	/** Mask used to check if any breakpoints are enabled. */
684	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(6) \| RT_BIT(7))
685
686	/** @} */
687
688
689	/** @name Machine Specific Registers
690	* @{
691	*/
692	/** CPU Feature control. */
693	#define MSR_IA32_FEATURE_CONTROL 0x3A
694	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
695	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
696
697
698	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
699	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
700	* R0 SS == CS + 8
701	* R3 CS == CS + 16
702	* R3 SS == CS + 24
703	*/
704	#define MSR_IA32_SYSENTER_CS 0x174
705	/** SYSENTER_ESP - the R0 ESP. */
706	#define MSR_IA32_SYSENTER_ESP 0x175
707	/** SYSENTER_EIP - the R0 EIP. */
708	#define MSR_IA32_SYSENTER_EIP 0x176
709	#endif
710
711	/** Basic VMX information. */
712	#define MSR_IA32_VMX_BASIC_INFO 0x480
713	/** Allowed settings for pin-based VM execution controls */
714	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
715	/** Allowed settings for proc-based VM execution controls */
716	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
717	/** Allowed settings for the VMX exit controls. */
718	#define MSR_IA32_VMX_EXIT_CTLS 0x483
719	/** Allowed settings for the VMX entry controls. */
720	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
721	/** Misc VMX info. */
722	#define MSR_IA32_VMX_MISC 0x485
723	/** Fixed cleared bits in CR0. */
724	#define MSR_IA32_VMX_CR0_FIXED0 0x486
725	/** Fixed set bits in CR0. */
726	#define MSR_IA32_VMX_CR0_FIXED1 0x487
727	/** Fixed cleared bits in CR4. */
728	#define MSR_IA32_VMX_CR4_FIXED0 0x488
729	/** Fixed set bits in CR4. */
730	#define MSR_IA32_VMX_CR4_FIXED1 0x489
731	/** Information for enumerating fields in the VMCS. */
732	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
733
734
735	/** K6 EFER - Extended Feature Enable Register. */
736	#define MSR_K6_EFER 0xc0000080
737	/** @todo document EFER */
738	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
739	#define MSR_K6_EFER_SCE RT_BIT(0)
740	/** Bit 8 - LME - Long mode enabled. (R/W) */
741	#define MSR_K6_EFER_LME RT_BIT(8)
742	/** Bit 10 - LMA - Long mode active. (R) */
743	#define MSR_K6_EFER_LMA RT_BIT(10)
744	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
745	#define MSR_K6_EFER_NXE RT_BIT(11)
746	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
747	#define MSR_K6_EFER_SVME RT_BIT(12)
748	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
749	#define MSR_K6_EFER_LMSLE RT_BIT(13)
750	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
751	#define MSR_K6_EFER_FFXSR RT_BIT(14)
752	/** K6 STAR - SYSCALL/RET targets. */
753	#define MSR_K6_STAR 0xc0000081
754	/** Shift value for getting the SYSRET CS and SS value. */
755	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
756	/** Shift value for getting the SYSCALL CS and SS value. */
757	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
758	/** Selector mask for use after shifting. */
759	#define MSR_K6_STAR_SEL_MASK 0xffff
760	/** The mask which give the SYSCALL EIP. */
761	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
762	/** K6 WHCR - Write Handling Control Register. */
763	#define MSR_K6_WHCR 0xc0000082
764	/** K6 UWCCR - UC/WC Cacheability Control Register. */
765	#define MSR_K6_UWCCR 0xc0000085
766	/** K6 PSOR - Processor State Observability Register. */
767	#define MSR_K6_PSOR 0xc0000087
768	/** K6 PFIR - Page Flush/Invalidate Register. */
769	#define MSR_K6_PFIR 0xc0000088
770
771	#define MSR_K7_EVNTSEL0 0xc0010000
772	#define MSR_K7_EVNTSEL1 0xc0010001
773	#define MSR_K7_EVNTSEL2 0xc0010002
774	#define MSR_K7_EVNTSEL3 0xc0010003
775	#define MSR_K7_PERFCTR0 0xc0010004
776	#define MSR_K7_PERFCTR1 0xc0010005
777	#define MSR_K7_PERFCTR2 0xc0010006
778	#define MSR_K7_PERFCTR3 0xc0010007
779
780	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
781	#define MSR_K8_LSTAR 0xc0000082
782	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
783	#define MSR_K8_CSTAR 0xc0000083
784	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
785	#define MSR_K8_SF_MASK 0xc0000084
786	/** K8 FS.base - The 64-bit base FS register. */
787	#define MSR_K8_FS_BASE 0xc0000100
788	/** K8 GS.base - The 64-bit base GS register. */
789	#define MSR_K8_GS_BASE 0xc0000101
790	/** K8 KernelGSbase - Used with SWAPGS. */
791	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
792	#define MSR_K8_TSC_AUX 0xc0000103
793	#define MSR_K8_SYSCFG 0xc0010010
794	#define MSR_K8_HWCR 0xc0010015
795	#define MSR_K8_IORRBASE0 0xc0010016
796	#define MSR_K8_IORRMASK0 0xc0010017
797	#define MSR_K8_IORRBASE1 0xc0010018
798	#define MSR_K8_IORRMASK1 0xc0010019
799	#define MSR_K8_TOP_MEM1 0xc001001a
800	#define MSR_K8_TOP_MEM2 0xc001001d
801	#define MSR_K8_VM_CR 0xc0010114
802	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
803
804	#define MSR_K8_IGNNE 0xc0010115
805	#define MSR_K8_SMM_CTL 0xc0010116
806	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
807	* host state during world switch.
808	*/
809	#define MSR_K8_VM_HSAVE_PA 0xc0010117
810
811	/** @} */
812
813
814	/** @name Page Table / Directory / Directory Pointers / L4.
815	* @{
816	*/
817
818	/** Page table/directory entry as an unsigned integer. */
819	typedef uint32_t X86PGUINT;
820	/** Pointer to a page table/directory table entry as an unsigned integer. */
821	typedef X86PGUINT *PX86PGUINT;
822
823	/** Number of entries in a 32-bit PT/PD. */
824	#define X86_PG_ENTRIES 1024
825
826
827	/** PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
828	typedef uint64_t X86PGPAEUINT;
829	/** Pointer to a PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
830	typedef X86PGPAEUINT *PX86PGPAEUINT;
831
832	/** Number of entries in a PAE PT/PD/PDPTR/L4/L5. */
833	#define X86_PG_PAE_ENTRIES 512
834
835
836	/** The size of a 4KB page. */
837	#define X86_PAGE_4K_SIZE _4K
838	/** The page shift of a 4KB page. */
839	#define X86_PAGE_4K_SHIFT 12
840	/** The 4KB page offset mask. */
841	#define X86_PAGE_4K_OFFSET_MASK 0xfff
842	/** The 4KB page base mask for virtual addresses. */
843	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
844	/** The 4KB page base mask for virtual addresses - 32bit version. */
845	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
846
847	/** The size of a 2MB page. */
848	#define X86_PAGE_2M_SIZE _2M
849	/** The page shift of a 2MB page. */
850	#define X86_PAGE_2M_SHIFT 21
851	/** The 2MB page offset mask. */
852	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
853	/** The 2MB page base mask for virtual addresses. */
854	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
855	/** The 2MB page base mask for virtual addresses - 32bit version. */
856	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
857
858	/** The size of a 4MB page. */
859	#define X86_PAGE_4M_SIZE _4M
860	/** The page shift of a 4MB page. */
861	#define X86_PAGE_4M_SHIFT 22
862	/** The 4MB page offset mask. */
863	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
864	/** The 4MB page base mask for virtual addresses. */
865	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
866	/** The 4MB page base mask for virtual addresses - 32bit version. */
867	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
868
869
870
871	/** @name Page Table Entry
872	* @{
873	*/
874	/** Bit 0 - P - Present bit. */
875	#define X86_PTE_P RT_BIT(0)
876	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
877	#define X86_PTE_RW RT_BIT(1)
878	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
879	#define X86_PTE_US RT_BIT(2)
880	/** Bit 3 - PWT - Page level write thru bit. */
881	#define X86_PTE_PWT RT_BIT(3)
882	/** Bit 4 - PCD - Page level cache disable bit. */
883	#define X86_PTE_PCD RT_BIT(4)
884	/** Bit 5 - A - Access bit. */
885	#define X86_PTE_A RT_BIT(5)
886	/** Bit 6 - D - Dirty bit. */
887	#define X86_PTE_D RT_BIT(6)
888	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
889	#define X86_PTE_PAT RT_BIT(7)
890	/** Bit 8 - G - Global flag. */
891	#define X86_PTE_G RT_BIT(8)
892	/** Bits 9-11 - - Available for use to system software. */
893	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
894	/** Bits 12-31 - - Physical Page number of the next level. */
895	#define X86_PTE_PG_MASK ( 0xfffff000 )
896
897	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
898	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
899	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
900	#else
901	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
902	#endif
903	/** Bits 63 - NX - PAE - No execution flag. */
904	#define X86_PTE_PAE_NX RT_BIT_64(63)
905
906	/**
907	* Page table entry.
908	*/
909	typedef struct X86PTEBITS
910	{
911	/** Flags whether(=1) or not the page is present. */
912	unsigned u1Present : 1;
913	/** Read(=0) / Write(=1) flag. */
914	unsigned u1Write : 1;
915	/** User(=1) / Supervisor (=0) flag. */
916	unsigned u1User : 1;
917	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
918	unsigned u1WriteThru : 1;
919	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
920	unsigned u1CacheDisable : 1;
921	/** Accessed flag.
922	* Indicates that the page have been read or written to. */
923	unsigned u1Accessed : 1;
924	/** Dirty flag.
925	* Indicates that the page have been written to. */
926	unsigned u1Dirty : 1;
927	/** Reserved / If PAT enabled, bit 2 of the index. */
928	unsigned u1PAT : 1;
929	/** Global flag. (Ignored in all but final level.) */
930	unsigned u1Global : 1;
931	/** Available for use to system software. */
932	unsigned u3Available : 3;
933	/** Physical Page number of the next level. */
934	unsigned u20PageNo : 20;
935	} X86PTEBITS;
936	/** Pointer to a page table entry. */
937	typedef X86PTEBITS *PX86PTEBITS;
938	/** Pointer to a const page table entry. */
939	typedef const X86PTEBITS *PCX86PTEBITS;
940
941	/**
942	* Page table entry.
943	*/
944	typedef union X86PTE
945	{
946	/** Bit field view. */
947	X86PTEBITS n;
948	/** Unsigned integer view */
949	X86PGUINT u;
950	/** 32-bit view. */
951	uint32_t au32[1];
952	/** 16-bit view. */
953	uint16_t au16[2];
954	/** 8-bit view. */
955	uint8_t au8[4];
956	} X86PTE;
957	/** Pointer to a page table entry. */
958	typedef X86PTE *PX86PTE;
959	/** Pointer to a const page table entry. */
960	typedef const X86PTE *PCX86PTE;
961
962
963	/**
964	* PAE page table entry.
965	*/
966	typedef struct X86PTEPAEBITS
967	{
968	/** Flags whether(=1) or not the page is present. */
969	uint32_t u1Present : 1;
970	/** Read(=0) / Write(=1) flag. */
971	uint32_t u1Write : 1;
972	/** User(=1) / Supervisor(=0) flag. */
973	uint32_t u1User : 1;
974	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
975	uint32_t u1WriteThru : 1;
976	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
977	uint32_t u1CacheDisable : 1;
978	/** Accessed flag.
979	* Indicates that the page have been read or written to. */
980	uint32_t u1Accessed : 1;
981	/** Dirty flag.
982	* Indicates that the page have been written to. */
983	uint32_t u1Dirty : 1;
984	/** Reserved / If PAT enabled, bit 2 of the index. */
985	uint32_t u1PAT : 1;
986	/** Global flag. (Ignored in all but final level.) */
987	uint32_t u1Global : 1;
988	/** Available for use to system software. */
989	uint32_t u3Available : 3;
990	/** Physical Page number of the next level - Low Part. Don't use this. */
991	uint32_t u20PageNoLow : 20;
992	/** Physical Page number of the next level - High Part. Don't use this. */
993	uint32_t u20PageNoHigh : 20;
994	/** MBZ bits */
995	uint32_t u11Reserved : 11;
996	/** No Execute flag. */
997	uint32_t u1NoExecute : 1;
998	} X86PTEPAEBITS;
999	/** Pointer to a page table entry. */
1000	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1001	/** Pointer to a page table entry. */
1002	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1003
1004	/**
1005	* PAE Page table entry.
1006	*/
1007	typedef union X86PTEPAE
1008	{
1009	/** Bit field view. */
1010	X86PTEPAEBITS n;
1011	/** Unsigned integer view */
1012	X86PGPAEUINT u;
1013	/** 32-bit view. */
1014	uint32_t au32[2];
1015	/** 16-bit view. */
1016	uint16_t au16[4];
1017	/** 8-bit view. */
1018	uint8_t au8[8];
1019	} X86PTEPAE;
1020	/** Pointer to a PAE page table entry. */
1021	typedef X86PTEPAE *PX86PTEPAE;
1022	/** Pointer to a const PAE page table entry. */
1023	typedef const X86PTEPAE *PCX86PTEPAE;
1024	/** @} */
1025
1026	/**
1027	* Page table.
1028	*/
1029	typedef struct X86PT
1030	{
1031	/** PTE Array. */
1032	X86PTE a[X86_PG_ENTRIES];
1033	} X86PT;
1034	/** Pointer to a page table. */
1035	typedef X86PT *PX86PT;
1036	/** Pointer to a const page table. */
1037	typedef const X86PT *PCX86PT;
1038
1039	/** The page shift to get the PT index. */
1040	#define X86_PT_SHIFT 12
1041	/** The PT index mask (apply to a shifted page address). */
1042	#define X86_PT_MASK 0x3ff
1043
1044
1045	/**
1046	* Page directory.
1047	*/
1048	typedef struct X86PTPAE
1049	{
1050	/** PTE Array. */
1051	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1052	} X86PTPAE;
1053	/** Pointer to a page table. */
1054	typedef X86PTPAE *PX86PTPAE;
1055	/** Pointer to a const page table. */
1056	typedef const X86PTPAE *PCX86PTPAE;
1057
1058	/** The page shift to get the PA PTE index. */
1059	#define X86_PT_PAE_SHIFT 12
1060	/** The PAE PT index mask (apply to a shifted page address). */
1061	#define X86_PT_PAE_MASK 0x1ff
1062
1063
1064	/** @name 4KB Page Directory Entry
1065	* @{
1066	*/
1067	/** Bit 0 - P - Present bit. */
1068	#define X86_PDE_P RT_BIT(0)
1069	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1070	#define X86_PDE_RW RT_BIT(1)
1071	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1072	#define X86_PDE_US RT_BIT(2)
1073	/** Bit 3 - PWT - Page level write thru bit. */
1074	#define X86_PDE_PWT RT_BIT(3)
1075	/** Bit 4 - PCD - Page level cache disable bit. */
1076	#define X86_PDE_PCD RT_BIT(4)
1077	/** Bit 5 - A - Access bit. */
1078	#define X86_PDE_A RT_BIT(5)
1079	/** Bit 7 - PS - Page size attribute.
1080	* Clear mean 4KB pages, set means large pages (2/4MB). */
1081	#define X86_PDE_PS RT_BIT(7)
1082	/** Bits 9-11 - - Available for use to system software. */
1083	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1084	/** Bits 12-31 - - Physical Page number of the next level. */
1085	#define X86_PDE_PG_MASK ( 0xfffff000 )
1086
1087	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1088	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1089	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1090	#else
1091	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1092	#endif
1093	/** Bits 63 - NX - PAE - No execution flag. */
1094	#define X86_PDE_PAE_NX RT_BIT_64(63)
1095
1096	/**
1097	* Page directory entry.
1098	*/
1099	typedef struct X86PDEBITS
1100	{
1101	/** Flags whether(=1) or not the page is present. */
1102	unsigned u1Present : 1;
1103	/** Read(=0) / Write(=1) flag. */
1104	unsigned u1Write : 1;
1105	/** User(=1) / Supervisor (=0) flag. */
1106	unsigned u1User : 1;
1107	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1108	unsigned u1WriteThru : 1;
1109	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1110	unsigned u1CacheDisable : 1;
1111	/** Accessed flag.
1112	* Indicates that the page have been read or written to. */
1113	unsigned u1Accessed : 1;
1114	/** Reserved / Ignored (dirty bit). */
1115	unsigned u1Reserved0 : 1;
1116	/** Size bit if PSE is enabled - in any event it's 0. */
1117	unsigned u1Size : 1;
1118	/** Reserved / Ignored (global bit). */
1119	unsigned u1Reserved1 : 1;
1120	/** Available for use to system software. */
1121	unsigned u3Available : 3;
1122	/** Physical Page number of the next level. */
1123	unsigned u20PageNo : 20;
1124	} X86PDEBITS;
1125	/** Pointer to a page directory entry. */
1126	typedef X86PDEBITS *PX86PDEBITS;
1127	/** Pointer to a const page directory entry. */
1128	typedef const X86PDEBITS *PCX86PDEBITS;
1129
1130
1131	/**
1132	* PAE page directory entry.
1133	*/
1134	typedef struct X86PDEPAEBITS
1135	{
1136	/** Flags whether(=1) or not the page is present. */
1137	uint32_t u1Present : 1;
1138	/** Read(=0) / Write(=1) flag. */
1139	uint32_t u1Write : 1;
1140	/** User(=1) / Supervisor (=0) flag. */
1141	uint32_t u1User : 1;
1142	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1143	uint32_t u1WriteThru : 1;
1144	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1145	uint32_t u1CacheDisable : 1;
1146	/** Accessed flag.
1147	* Indicates that the page have been read or written to. */
1148	uint32_t u1Accessed : 1;
1149	/** Reserved / Ignored (dirty bit). */
1150	uint32_t u1Reserved0 : 1;
1151	/** Size bit if PSE is enabled - in any event it's 0. */
1152	uint32_t u1Size : 1;
1153	/** Reserved / Ignored (global bit). / */
1154	uint32_t u1Reserved1 : 1;
1155	/** Available for use to system software. */
1156	uint32_t u3Available : 3;
1157	/** Physical Page number of the next level - Low Part. Don't use! */
1158	uint32_t u20PageNoLow : 20;
1159	/** Physical Page number of the next level - High Part. Don't use! */
1160	uint32_t u20PageNoHigh : 20;
1161	/** MBZ bits */
1162	uint32_t u11Reserved : 11;
1163	/** No Execute flag. */
1164	uint32_t u1NoExecute : 1;
1165	} X86PDEPAEBITS;
1166	/** Pointer to a page directory entry. */
1167	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1168	/** Pointer to a const page directory entry. */
1169	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1170
1171	/** @} */
1172
1173
1174	/** @name 2/4MB Page Directory Entry
1175	* @{
1176	*/
1177	/** Bit 0 - P - Present bit. */
1178	#define X86_PDE4M_P RT_BIT(0)
1179	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1180	#define X86_PDE4M_RW RT_BIT(1)
1181	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1182	#define X86_PDE4M_US RT_BIT(2)
1183	/** Bit 3 - PWT - Page level write thru bit. */
1184	#define X86_PDE4M_PWT RT_BIT(3)
1185	/** Bit 4 - PCD - Page level cache disable bit. */
1186	#define X86_PDE4M_PCD RT_BIT(4)
1187	/** Bit 5 - A - Access bit. */
1188	#define X86_PDE4M_A RT_BIT(5)
1189	/** Bit 6 - D - Dirty bit. */
1190	#define X86_PDE4M_D RT_BIT(6)
1191	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1192	#define X86_PDE4M_PS RT_BIT(7)
1193	/** Bit 8 - G - Global flag. */
1194	#define X86_PDE4M_G RT_BIT(8)
1195	/** Bits 9-11 - AVL - Available for use to system software. */
1196	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1197	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1198	#define X86_PDE4M_PAT RT_BIT(12)
1199	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1200	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1201	/** Bits 22-31 - - Physical Page number. */
1202	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1203	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1204	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1205	/** The number of bits to the high part of the page number. */
1206	#define X86_PDE4M_PG_HIGH_SHIFT 19
1207
1208	/** Bits 12-51 - - PAE - Physical Page number. */
1209	#define X86_PDE4M_PAE_PG_MASK ( 0x000fffffffc00000ULL )
1210	/** Bits 63 - NX - PAE - No execution flag. */
1211	#define X86_PDE4M_PAE_NX RT_BIT_64(63)
1212
1213	/**
1214	* 4MB page directory entry.
1215	*/
1216	typedef struct X86PDE4MBITS
1217	{
1218	/** Flags whether(=1) or not the page is present. */
1219	unsigned u1Present : 1;
1220	/** Read(=0) / Write(=1) flag. */
1221	unsigned u1Write : 1;
1222	/** User(=1) / Supervisor (=0) flag. */
1223	unsigned u1User : 1;
1224	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1225	unsigned u1WriteThru : 1;
1226	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1227	unsigned u1CacheDisable : 1;
1228	/** Accessed flag.
1229	* Indicates that the page have been read or written to. */
1230	unsigned u1Accessed : 1;
1231	/** Dirty flag.
1232	* Indicates that the page have been written to. */
1233	unsigned u1Dirty : 1;
1234	/** Page size flag - always 1 for 4MB entries. */
1235	unsigned u1Size : 1;
1236	/** Global flag. */
1237	unsigned u1Global : 1;
1238	/** Available for use to system software. */
1239	unsigned u3Available : 3;
1240	/** Reserved / If PAT enabled, bit 2 of the index. */
1241	unsigned u1PAT : 1;
1242	/** Bits 32-39 of the page number on AMD64.
1243	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1244	unsigned u8PageNoHigh : 8;
1245	/** Reserved. */
1246	unsigned u1Reserved : 1;
1247	/** Physical Page number of the page. */
1248	unsigned u10PageNo : 10;
1249	} X86PDE4MBITS;
1250	/** Pointer to a page table entry. */
1251	typedef X86PDE4MBITS *PX86PDE4MBITS;
1252	/** Pointer to a const page table entry. */
1253	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1254
1255
1256	/**
1257	* 2MB PAE page directory entry.
1258	*/
1259	typedef struct X86PDE2MPAEBITS
1260	{
1261	/** Flags whether(=1) or not the page is present. */
1262	uint32_t u1Present : 1;
1263	/** Read(=0) / Write(=1) flag. */
1264	uint32_t u1Write : 1;
1265	/** User(=1) / Supervisor(=0) flag. */
1266	uint32_t u1User : 1;
1267	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1268	uint32_t u1WriteThru : 1;
1269	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1270	uint32_t u1CacheDisable : 1;
1271	/** Accessed flag.
1272	* Indicates that the page have been read or written to. */
1273	uint32_t u1Accessed : 1;
1274	/** Dirty flag.
1275	* Indicates that the page have been written to. */
1276	uint32_t u1Dirty : 1;
1277	/** Page size flag - always 1 for 2MB entries. */
1278	uint32_t u1Size : 1;
1279	/** Global flag. */
1280	uint32_t u1Global : 1;
1281	/** Available for use to system software. */
1282	uint32_t u3Available : 3;
1283	/** Reserved / If PAT enabled, bit 2 of the index. */
1284	uint32_t u1PAT : 1;
1285	/** Reserved. */
1286	uint32_t u9Reserved : 9;
1287	/** Physical Page number of the next level - Low part. Don't use! */
1288	uint32_t u10PageNoLow : 10;
1289	/** Physical Page number of the next level - High part. Don't use! */
1290	uint32_t u20PageNoHigh : 20;
1291	/** MBZ bits */
1292	uint32_t u11Reserved : 11;
1293	/** No Execute flag. */
1294	uint32_t u1NoExecute : 1;
1295	} X86PDE2MPAEBITS;
1296	/** Pointer to a 4MB PAE page table entry. */
1297	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1298	/** Pointer to a 4MB PAE page table entry. */
1299	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1300
1301	/** @} */
1302
1303	/**
1304	* Page directory entry.
1305	*/
1306	typedef union X86PDE
1307	{
1308	/** Normal view. */
1309	X86PDEBITS n;
1310	/** 4MB view (big). */
1311	X86PDE4MBITS b;
1312	/** Unsigned integer view. */
1313	X86PGUINT u;
1314	/** 8 bit unsigned integer view. */
1315	uint8_t au8[4];
1316	/** 16 bit unsigned integer view. */
1317	uint16_t au16[2];
1318	/** 32 bit unsigned integer view. */
1319	uint32_t au32[1];
1320	} X86PDE;
1321	/** Pointer to a page directory entry. */
1322	typedef X86PDE *PX86PDE;
1323	/** Pointer to a const page directory entry. */
1324	typedef const X86PDE *PCX86PDE;
1325
1326	/**
1327	* PAE page directory entry.
1328	*/
1329	typedef union X86PDEPAE
1330	{
1331	/** Normal view. */
1332	X86PDEPAEBITS n;
1333	/** 2MB page view (big). */
1334	X86PDE2MPAEBITS b;
1335	/** Unsigned integer view. */
1336	X86PGPAEUINT u;
1337	/** 8 bit unsigned integer view. */
1338	uint8_t au8[8];
1339	/** 16 bit unsigned integer view. */
1340	uint16_t au16[4];
1341	/** 32 bit unsigned integer view. */
1342	uint32_t au32[2];
1343	} X86PDEPAE;
1344	/** Pointer to a page directory entry. */
1345	typedef X86PDEPAE *PX86PDEPAE;
1346	/** Pointer to a const page directory entry. */
1347	typedef const X86PDEPAE *PCX86PDEPAE;
1348
1349	/**
1350	* Page directory.
1351	*/
1352	typedef struct X86PD
1353	{
1354	/** PDE Array. */
1355	X86PDE a[X86_PG_ENTRIES];
1356	} X86PD;
1357	/** Pointer to a page directory. */
1358	typedef X86PD *PX86PD;
1359	/** Pointer to a const page directory. */
1360	typedef const X86PD *PCX86PD;
1361
1362	/** The page shift to get the PD index. */
1363	#define X86_PD_SHIFT 22
1364	/** The PD index mask (apply to a shifted page address). */
1365	#define X86_PD_MASK 0x3ff
1366
1367
1368	/**
1369	* PAE page directory.
1370	*/
1371	typedef struct X86PDPAE
1372	{
1373	/** PDE Array. */
1374	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1375	} X86PDPAE;
1376	/** Pointer to a PAE page directory. */
1377	typedef X86PDPAE *PX86PDPAE;
1378	/** Pointer to a const PAE page directory. */
1379	typedef const X86PDPAE *PCX86PDPAE;
1380
1381	/** The page shift to get the PAE PD index. */
1382	#define X86_PD_PAE_SHIFT 21
1383	/** The PAE PD index mask (apply to a shifted page address). */
1384	#define X86_PD_PAE_MASK 0x1ff
1385
1386
1387	/** @name Page Directory Pointer Table Entry (PAE)
1388	* @{
1389	*/
1390	/** Bit 0 - P - Present bit. */
1391	#define X86_PDPE_P RT_BIT(0)
1392	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1393	#define X86_PDPE_RW RT_BIT(1)
1394	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1395	#define X86_PDPE_US RT_BIT(2)
1396	/** Bit 3 - PWT - Page level write thru bit. */
1397	#define X86_PDPE_PWT RT_BIT(3)
1398	/** Bit 4 - PCD - Page level cache disable bit. */
1399	#define X86_PDPE_PCD RT_BIT(4)
1400	/** Bit 5 - A - Access bit. Long Mode only. */
1401	#define X86_PDPE_A RT_BIT(5)
1402	/** Bits 9-11 - - Available for use to system software. */
1403	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1404	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1405	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1406	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1407	#else
1408	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1409	#endif
1410	/** Bits 63 - NX - PAE - No execution flag. */
1411	#define X86_PDPE_NX RT_BIT_64(63)
1412
1413	/**
1414	* Page directory pointer table entry.
1415	*/
1416	typedef struct X86PDPEBITS
1417	{
1418	/** Flags whether(=1) or not the page is present. */
1419	uint32_t u1Present : 1;
1420	/** Read(=0) / Write(=1) flag. */
1421	uint32_t u1Write : 1;
1422	/** User(=1) / Supervisor (=0) flag. */
1423	uint32_t u1User : 1;
1424	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1425	uint32_t u1WriteThru : 1;
1426	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1427	uint32_t u1CacheDisable : 1;
1428	/** Accessed flag.
1429	* Indicates that the page have been read or written to. */
1430	uint32_t u1Accessed : 1;
1431	/** Chunk of reserved bits. */
1432	uint32_t u3Reserved : 3;
1433	/** Available for use to system software. */
1434	uint32_t u3Available : 3;
1435	/** Physical Page number of the next level - Low Part. Don't use! */
1436	uint32_t u20PageNoLow : 20;
1437	/** Physical Page number of the next level - High Part. Don't use! */
1438	uint32_t u20PageNoHigh : 20;
1439	/** MBZ bits */
1440	uint32_t u11Reserved : 11;
1441	/** No Execute flag. */
1442	uint32_t u1NoExecute : 1;
1443	} X86PDPEBITS;
1444	/** Pointer to a page directory pointer table entry. */
1445	typedef X86PDPEBITS *PX86PTPEBITS;
1446	/** Pointer to a const page directory pointer table entry. */
1447	typedef const X86PDPEBITS *PCX86PTPEBITS;
1448
1449	/**
1450	* Page directory pointer table entry.
1451	*/
1452	typedef union X86PDPE
1453	{
1454	/** Normal view. */
1455	X86PDPEBITS n;
1456	/** Unsigned integer view. */
1457	X86PGPAEUINT u;
1458	/** 8 bit unsigned integer view. */
1459	uint8_t au8[8];
1460	/** 16 bit unsigned integer view. */
1461	uint16_t au16[4];
1462	/** 32 bit unsigned integer view. */
1463	uint32_t au32[2];
1464	} X86PDPE;
1465	/** Pointer to a page directory pointer table entry. */
1466	typedef X86PDPE *PX86PDPE;
1467	/** Pointer to a const page directory pointer table entry. */
1468	typedef const X86PDPE *PCX86PDPE;
1469
1470
1471	/**
1472	* Page directory pointer table.
1473	*/
1474	typedef struct X86PDPTR
1475	{
1476	/** PDE Array. */
1477	X86PDPE a[X86_PG_PAE_ENTRIES];
1478	} X86PDPTR;
1479	/** Pointer to a page directory pointer table. */
1480	typedef X86PDPTR *PX86PDPTR;
1481	/** Pointer to a const page directory pointer table. */
1482	typedef const X86PDPTR *PCX86PDPTR;
1483
1484	/** The page shift to get the PDPTR index. */
1485	#define X86_PDPTR_SHIFT 30
1486	/** The PDPTR index mask (apply to a shifted page address). (32 bits PAE) */
1487	#define X86_PDPTR_MASK_32 0x3
1488	/** The PDPTR index mask (apply to a shifted page address). (64 bits PAE)*/
1489	#define X86_PDPTR_MASK 0x1ff
1490
1491	/** @} */
1492
1493
1494	/** @name Page Map Level-4 Entry (Long Mode PAE)
1495	* @{
1496	*/
1497	/** Bit 0 - P - Present bit. */
1498	#define X86_PML4E_P RT_BIT(0)
1499	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1500	#define X86_PML4E_RW RT_BIT(1)
1501	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1502	#define X86_PML4E_US RT_BIT(2)
1503	/** Bit 3 - PWT - Page level write thru bit. */
1504	#define X86_PML4E_PWT RT_BIT(3)
1505	/** Bit 4 - PCD - Page level cache disable bit. */
1506	#define X86_PML4E_PCD RT_BIT(4)
1507	/** Bit 5 - A - Access bit. */
1508	#define X86_PML4E_A RT_BIT(5)
1509	/** Bits 9-11 - - Available for use to system software. */
1510	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1511	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1512	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1513	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1514	#else
1515	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1516	#endif
1517	/** Bits 63 - NX - PAE - No execution flag. */
1518	#define X86_PML4E_NX RT_BIT_64(63)
1519
1520	/**
1521	* Page Map Level-4 Entry
1522	*/
1523	typedef struct X86PML4EBITS
1524	{
1525	/** Flags whether(=1) or not the page is present. */
1526	uint32_t u1Present : 1;
1527	/** Read(=0) / Write(=1) flag. */
1528	uint32_t u1Write : 1;
1529	/** User(=1) / Supervisor (=0) flag. */
1530	uint32_t u1User : 1;
1531	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1532	uint32_t u1WriteThru : 1;
1533	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1534	uint32_t u1CacheDisable : 1;
1535	/** Accessed flag.
1536	* Indicates that the page have been read or written to. */
1537	uint32_t u1Accessed : 1;
1538	/** Chunk of reserved bits. */
1539	uint32_t u3Reserved : 3;
1540	/** Available for use to system software. */
1541	uint32_t u3Available : 3;
1542	/** Physical Page number of the next level - Low Part. Don't use! */
1543	uint32_t u20PageNoLow : 20;
1544	/** Physical Page number of the next level - High Part. Don't use! */
1545	uint32_t u20PageNoHigh : 20;
1546	/** MBZ bits */
1547	uint32_t u11Reserved : 11;
1548	/** No Execute flag. */
1549	uint32_t u1NoExecute : 1;
1550	} X86PML4EBITS;
1551	/** Pointer to a page map level-4 entry. */
1552	typedef X86PML4EBITS *PX86PML4EBITS;
1553	/** Pointer to a const page map level-4 entry. */
1554	typedef const X86PML4EBITS *PCX86PML4EBITS;
1555
1556	/**
1557	* Page Map Level-4 Entry.
1558	*/
1559	typedef union X86PML4E
1560	{
1561	/** Normal view. */
1562	X86PML4EBITS n;
1563	/** Unsigned integer view. */
1564	X86PGPAEUINT u;
1565	/** 8 bit unsigned integer view. */
1566	uint8_t au8[8];
1567	/** 16 bit unsigned integer view. */
1568	uint16_t au16[4];
1569	/** 32 bit unsigned integer view. */
1570	uint32_t au32[2];
1571	} X86PML4E;
1572	/** Pointer to a page map level-4 entry. */
1573	typedef X86PML4E *PX86PML4E;
1574	/** Pointer to a const page map level-4 entry. */
1575	typedef const X86PML4E *PCX86PML4E;
1576
1577
1578	/**
1579	* Page Map Level-4.
1580	*/
1581	typedef struct X86PML4
1582	{
1583	/** PDE Array. */
1584	X86PML4E a[X86_PG_PAE_ENTRIES];
1585	} X86PML4;
1586	/** Pointer to a page map level-4. */
1587	typedef X86PML4 *PX86PML4;
1588	/** Pointer to a const page map level-4. */
1589	typedef const X86PML4 *PCX86PML4;
1590
1591	/** The page shift to get the PML4 index. */
1592	#define X86_PML4_SHIFT 39
1593	/** The PML4 index mask (apply to a shifted page address). */
1594	#define X86_PML4_MASK 0x1ff
1595
1596	/** @} */
1597
1598	/** @} */
1599
1600
1601	/**
1602	* 80-bit MMX/FPU register type.
1603	*/
1604	typedef struct X86FPUMMX
1605	{
1606	uint8_t reg[10];
1607	} X86FPUMMX;
1608	/** Pointer to a 80-bit MMX/FPU register type. */
1609	typedef X86FPUMMX *PX86FPUMMX;
1610	/** Pointer to a const 80-bit MMX/FPU register type. */
1611	typedef const X86FPUMMX *PCX86FPUMMX;
1612
1613	/**
1614	* FPU state (aka FSAVE/FRSTOR Memory Region).
1615	*/
1616	#pragma pack(1)
1617	typedef struct X86FPUSTATE
1618	{
1619	/** Control word. */
1620	uint16_t FCW;
1621	/** Alignment word */
1622	uint16_t Dummy1;
1623	/** Status word. */
1624	uint16_t FSW;
1625	/** Alignment word */
1626	uint16_t Dummy2;
1627	/** Tag word */
1628	uint16_t FTW;
1629	/** Alignment word */
1630	uint16_t Dummy3;
1631
1632	/** Instruction pointer. */
1633	uint32_t FPUIP;
1634	/** Code selector. */
1635	uint16_t CS;
1636	/** Opcode. */
1637	uint16_t FOP;
1638	/** FOO. */
1639	uint32_t FPUOO;
1640	/** FOS. */
1641	uint32_t FPUOS;
1642	/** FPU view - todo. */
1643	X86FPUMMX regs[8];
1644	} X86FPUSTATE;
1645	#pragma pack()
1646	/** Pointer to a FPU state. */
1647	typedef X86FPUSTATE *PX86FPUSTATE;
1648	/** Pointer to a const FPU state. */
1649	typedef const X86FPUSTATE *PCX86FPUSTATE;
1650
1651	/**
1652	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1653	*/
1654	#pragma pack(1)
1655	typedef struct X86FXSTATE
1656	{
1657	/** Control word. */
1658	uint16_t FCW;
1659	/** Status word. */
1660	uint16_t FSW;
1661	/** Tag word (it's a byte actually). */
1662	uint8_t FTW;
1663	uint8_t huh1;
1664	/** Opcode. */
1665	uint16_t FOP;
1666	/** Instruction pointer. */
1667	uint32_t FPUIP;
1668	/** Code selector. */
1669	uint16_t CS;
1670	uint16_t Rsvrd1;
1671	/* - offset 16 - */
1672	/** Data pointer. */
1673	uint32_t FPUDP;
1674	/** Data segment */
1675	uint16_t DS;
1676	uint16_t Rsrvd2;
1677	uint32_t MXCSR;
1678	uint32_t MXCSR_MASK;
1679	/* - offset 32 - */
1680	union
1681	{
1682	/** MMX view. */
1683	uint64_t mmx;
1684	/** FPU view - todo. */
1685	X86FPUMMX fpu;
1686	/** 8-bit view. */
1687	uint8_t au8[16];
1688	/** 16-bit view. */
1689	uint16_t au16[8];
1690	/** 32-bit view. */
1691	uint32_t au32[4];
1692	/** 64-bit view. */
1693	uint64_t au64[2];
1694	/** 128-bit view. (yeah, very helpful) */
1695	uint128_t au128[1];
1696	} aRegs[8];
1697	/* - offset 160 - */
1698	union
1699	{
1700	/** XMM Register view . /
1701	uint128_t xmm;
1702	/** 8-bit view. */
1703	uint8_t au8[16];
1704	/** 16-bit view. */
1705	uint16_t au16[8];
1706	/** 32-bit view. */
1707	uint32_t au32[4];
1708	/** 64-bit view. */
1709	uint64_t au64[2];
1710	/** 128-bit view. (yeah, very helpful) */
1711	uint128_t au128[1];
1712	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1713	/* - offset 416 - */
1714	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1715	} X86FXSTATE;
1716	#pragma pack()
1717	/** Pointer to a FPU Extended state. */
1718	typedef X86FXSTATE *PX86FXSTATE;
1719	/** Pointer to a const FPU Extended state. */
1720	typedef const X86FXSTATE *PCX86FXSTATE;
1721
1722
1723	/** @name Selector Descriptor
1724	* @{
1725	*/
1726
1727	/**
1728	* Generic descriptor table entry
1729	*/
1730	#pragma pack(1)
1731	typedef struct X86DESCGENERIC
1732	{
1733	/** Limit - Low word. */
1734	unsigned u16LimitLow : 16;
1735	/** Base address - lowe word.
1736	* Don't try set this to 24 because MSC is doing studing things then. */
1737	unsigned u16BaseLow : 16;
1738	/** Base address - first 8 bits of high word. */
1739	unsigned u8BaseHigh1 : 8;
1740	/** Segment Type. */
1741	unsigned u4Type : 4;
1742	/** Descriptor Type. System(=0) or code/data selector */
1743	unsigned u1DescType : 1;
1744	/** Descriptor Privelege level. */
1745	unsigned u2Dpl : 2;
1746	/** Flags selector present(=1) or not. */
1747	unsigned u1Present : 1;
1748	/** Segment limit 16-19. */
1749	unsigned u4LimitHigh : 4;
1750	/** Available for system software. */
1751	unsigned u1Available : 1;
1752	/** Reserved - 0. */
1753	unsigned u1Reserved : 1;
1754	/** This flags meaning depends on the segment type. Try make sense out
1755	* of the intel manual yourself. */
1756	unsigned u1DefBig : 1;
1757	/** Granularity of the limit. If set 4KB granularity is used, if
1758	* clear byte. */
1759	unsigned u1Granularity : 1;
1760	/** Base address - highest 8 bits. */
1761	unsigned u8BaseHigh2 : 8;
1762	} X86DESCGENERIC;
1763	#pragma pack()
1764	/** Pointer to a generic descriptor entry. */
1765	typedef X86DESCGENERIC *PX86DESCGENERIC;
1766	/** Pointer to a const generic descriptor entry. */
1767	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1768
1769
1770	/**
1771	* Descriptor attributes.
1772	*/
1773	typedef struct X86DESCATTRBITS
1774	{
1775	/** Segment Type. */
1776	unsigned u4Type : 4;
1777	/** Descriptor Type. System(=0) or code/data selector */
1778	unsigned u1DescType : 1;
1779	/** Descriptor Privelege level. */
1780	unsigned u2Dpl : 2;
1781	/** Flags selector present(=1) or not. */
1782	unsigned u1Present : 1;
1783	/** Segment limit 16-19. */
1784	unsigned u4LimitHigh : 4;
1785	/** Available for system software. */
1786	unsigned u1Available : 1;
1787	/** Reserved - 0. */
1788	unsigned u1Reserved : 1;
1789	/** This flags meaning depends on the segment type. Try make sense out
1790	* of the intel manual yourself. */
1791	unsigned u1DefBig : 1;
1792	/** Granularity of the limit. If set 4KB granularity is used, if
1793	* clear byte. */
1794	unsigned u1Granularity : 1;
1795	} X86DESCATTRBITS;
1796
1797
1798	#pragma pack(1)
1799	typedef union X86DESCATTR
1800	{
1801	/** Normal view. */
1802	X86DESCATTRBITS n;
1803	/** Unsigned integer view. */
1804	uint32_t u;
1805	} X86DESCATTR;
1806	#pragma pack()
1807
1808	/** Pointer to descriptor attributes. */
1809	typedef X86DESCATTR *PX86DESCATTR;
1810	/** Pointer to const descriptor attributes. */
1811	typedef const X86DESCATTR *PCX86DESCATTR;
1812
1813
1814	/**
1815	* Descriptor table entry.
1816	*/
1817	#pragma pack(1)
1818	typedef union X86DESC
1819	{
1820	/** Generic descriptor view. */
1821	X86DESCGENERIC Gen;
1822	#if 0
1823	/** IDT view. */
1824	VBOXIDTE Idt;
1825	#endif
1826
1827	/** 8 bit unsigned interger view. */
1828	uint8_t au8[8];
1829	/** 16 bit unsigned interger view. */
1830	uint16_t au16[4];
1831	/** 32 bit unsigned interger view. */
1832	uint32_t au32[2];
1833	} X86DESC;
1834	#pragma pack()
1835	/** Pointer to descriptor table entry. */
1836	typedef X86DESC *PX86DESC;
1837	/** Pointer to const descriptor table entry. */
1838	typedef const X86DESC *PCX86DESC;
1839
1840
1841	/**
1842	* 64 bits generic descriptor table entry
1843	* Note: most of these bits have no meaning in long mode.
1844	*/
1845	#pragma pack(1)
1846	typedef struct X86DESC64GENERIC
1847	{
1848	/** Limit - Low word - IGNORED. */
1849	unsigned u16LimitLow : 16;
1850	/** Base address - lowe word. - IGNORED
1851	* Don't try set this to 24 because MSC is doing studing things then. */
1852	unsigned u16BaseLow : 16;
1853	/** Base address - first 8 bits of high word. - IGNORED */
1854	unsigned u8BaseHigh1 : 8;
1855	/** Segment Type. */
1856	unsigned u4Type : 4;
1857	/** Descriptor Type. System(=0) or code/data selector */
1858	unsigned u1DescType : 1;
1859	/** Descriptor Privelege level. */
1860	unsigned u2Dpl : 2;
1861	/** Flags selector present(=1) or not. */
1862	unsigned u1Present : 1;
1863	/** Segment limit 16-19. - IGNORED */
1864	unsigned u4LimitHigh : 4;
1865	/** Available for system software. - IGNORED */
1866	unsigned u1Available : 1;
1867	/** Long mode flag. */
1868	unsigned u1Long : 1;
1869	/** This flags meaning depends on the segment type. Try make sense out
1870	* of the intel manual yourself. */
1871	unsigned u1DefBig : 1;
1872	/** Granularity of the limit. If set 4KB granularity is used, if
1873	* clear byte. - IGNORED */
1874	unsigned u1Granularity : 1;
1875	/** Base address - highest 8 bits. - IGNORED */
1876	unsigned u8BaseHigh2 : 8;
1877	/** Base address - bits 63-32. */
1878	unsigned u32BaseHigh3 : 32;
1879	unsigned u8Reserved : 8;
1880	unsigned u5Zeros : 5;
1881	unsigned u19Reserved : 19;
1882	} X86DESC64GENERIC;
1883	#pragma pack()
1884	/** Pointer to a generic descriptor entry. */
1885	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1886	/** Pointer to a const generic descriptor entry. */
1887	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1888
1889	/**
1890	* System descriptor table entry (64 bits)
1891	*/
1892	#pragma pack(1)
1893	typedef struct X86DESC64SYSTEM
1894	{
1895	/** Limit - Low word. */
1896	unsigned u16LimitLow : 16;
1897	/** Base address - lowe word.
1898	* Don't try set this to 24 because MSC is doing studing things then. */
1899	unsigned u16BaseLow : 16;
1900	/** Base address - first 8 bits of high word. */
1901	unsigned u8BaseHigh1 : 8;
1902	/** Segment Type. */
1903	unsigned u4Type : 4;
1904	/** Descriptor Type. System(=0) or code/data selector */
1905	unsigned u1DescType : 1;
1906	/** Descriptor Privelege level. */
1907	unsigned u2Dpl : 2;
1908	/** Flags selector present(=1) or not. */
1909	unsigned u1Present : 1;
1910	/** Segment limit 16-19. */
1911	unsigned u4LimitHigh : 4;
1912	/** Available for system software. */
1913	unsigned u1Available : 1;
1914	/** Reserved - 0. */
1915	unsigned u1Reserved : 1;
1916	/** This flags meaning depends on the segment type. Try make sense out
1917	* of the intel manual yourself. */
1918	unsigned u1DefBig : 1;
1919	/** Granularity of the limit. If set 4KB granularity is used, if
1920	* clear byte. */
1921	unsigned u1Granularity : 1;
1922	/** Base address - bits 31-24. */
1923	unsigned u8BaseHigh2 : 8;
1924	/** Base address - bits 63-32. */
1925	unsigned u32BaseHigh3 : 32;
1926	unsigned u8Reserved : 8;
1927	unsigned u5Zeros : 5;
1928	unsigned u19Reserved : 19;
1929	} X86DESC64SYSTEM;
1930	#pragma pack()
1931	/** Pointer to a generic descriptor entry. */
1932	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
1933	/** Pointer to a const generic descriptor entry. */
1934	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
1935
1936
1937	/**
1938	* Descriptor table entry.
1939	*/
1940	#pragma pack(1)
1941	typedef union X86DESC64
1942	{
1943	/** Generic descriptor view. */
1944	X86DESC64GENERIC Gen;
1945	/** System descriptor view. */
1946	X86DESC64SYSTEM System;
1947	#if 0
1948	X86DESC64GATE Gate;
1949	#endif
1950
1951	/** 8 bit unsigned interger view. */
1952	uint8_t au8[16];
1953	/** 16 bit unsigned interger view. */
1954	uint16_t au16[8];
1955	/** 32 bit unsigned interger view. */
1956	uint32_t au32[4];
1957	/** 64 bit unsigned interger view. */
1958	uint64_t au64[2];
1959	} X86DESC64;
1960	#pragma pack()
1961	/** Pointer to descriptor table entry. */
1962	typedef X86DESC64 *PX86DESC64;
1963	/** Pointer to const descriptor table entry. */
1964	typedef const X86DESC64 *PCX86DESC64;
1965
1966	#if HC_ARCH_BITS == 64
1967	typedef X86DESC64 X86DESCHC;
1968	typedef X86DESC64 *PX86DESCHC;
1969	#else
1970	typedef X86DESC X86DESCHC;
1971	typedef X86DESC *PX86DESCHC;
1972	#endif
1973
1974	/** @name Selector Descriptor Types.
1975	* @{
1976	*/
1977
1978	/** @name Non-System Selector Types.
1979	* @{ */
1980	/** Code(=set)/Data(=clear) bit. */
1981	#define X86_SEL_TYPE_CODE 8
1982	/** Memory(=set)/System(=clear) bit. */
1983	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
1984	/** Accessed bit. */
1985	#define X86_SEL_TYPE_ACCESSED 1
1986	/** Expand down bit (for data selectors only). */
1987	#define X86_SEL_TYPE_DOWN 4
1988	/** Conforming bit (for code selectors only). */
1989	#define X86_SEL_TYPE_CONF 4
1990	/** Write bit (for data selectors only). */
1991	#define X86_SEL_TYPE_WRITE 2
1992	/** Read bit (for code selectors only). */
1993	#define X86_SEL_TYPE_READ 2
1994
1995	/** Read only selector type. */
1996	#define X86_SEL_TYPE_RO 0
1997	/** Accessed read only selector type. */
1998	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
1999	/** Read write selector type. */
2000	#define X86_SEL_TYPE_RW 2
2001	/** Accessed read write selector type. */
2002	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2003	/** Expand down read only selector type. */
2004	#define X86_SEL_TYPE_RO_DOWN 4
2005	/** Accessed expand down read only selector type. */
2006	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2007	/** Expand down read write selector type. */
2008	#define X86_SEL_TYPE_RW_DOWN 6
2009	/** Accessed expand down read write selector type. */
2010	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2011	/** Execute only selector type. */
2012	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2013	/** Accessed execute only selector type. */
2014	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2015	/** Execute and read selector type. */
2016	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2017	/** Accessed execute and read selector type. */
2018	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2019	/** Conforming execute only selector type. */
2020	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2021	/** Accessed Conforming execute only selector type. */
2022	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2023	/** Conforming execute and write selector type. */
2024	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2025	/** Accessed Conforming execute and write selector type. */
2026	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2027	/** @} */
2028
2029
2030	/** @name System Selector Types.
2031	* @{ */
2032	/** Undefined system selector type. */
2033	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2034	/** 286 TSS selector. */
2035	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2036	/** LDT selector. */
2037	#define X86_SEL_TYPE_SYS_LDT 2
2038	/** 286 TSS selector - Busy. */
2039	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2040	/** 286 Callgate selector. */
2041	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2042	/** Taskgate selector. */
2043	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2044	/** 286 Interrupt gate selector. */
2045	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2046	/** 286 Trapgate selector. */
2047	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2048	/** Undefined system selector. */
2049	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2050	/** 386 TSS selector. */
2051	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2052	/** Undefined system selector. */
2053	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2054	/** 386 TSS selector - Busy. */
2055	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2056	/** 386 Callgate selector. */
2057	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2058	/** Undefined system selector. */
2059	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2060	/** 386 Interruptgate selector. */
2061	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2062	/** 386 Trapgate selector. */
2063	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2064	/** @} */
2065
2066	/** @name AMD64 System Selector Types.
2067	* @{ */
2068	#define AMD64_SEL_TYPE_SYS_LDT 2
2069	/** 286 TSS selector - Busy. */
2070	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2071	/** 386 TSS selector - Busy. */
2072	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2073	/** 386 Callgate selector. */
2074	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2075	/** 386 Interruptgate selector. */
2076	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2077	/** 386 Trapgate selector. */
2078	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2079	/** @} */
2080
2081	/** @} */
2082
2083
2084	/** @name Descriptor Table Entry Flag Masks.
2085	* These are for the 2nd 32-bit word of a descriptor.
2086	* @{ */
2087	/** Bits 8-11 - TYPE - Descriptor type mask. */
2088	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2089	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2090	#define X86_DESC_S RT_BIT(12)
2091	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2092	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2093	/** Bit 15 - P - Present. */
2094	#define X86_DESC_P RT_BIT(15)
2095	/** Bit 20 - AVL - Available for system software. */
2096	#define X86_DESC_AVL RT_BIT(20)
2097	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2098	#define X86_DESC_DB RT_BIT(22)
2099	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2100	* used, if clear byte. */
2101	#define X86_DESC_G RT_BIT(23)
2102	/** @} */
2103
2104	/** @} */
2105
2106
2107	/** @name Selectors.
2108	* @{
2109	*/
2110
2111	/**
2112	* The shift used to convert a selector from and to index an index (C).
2113	*/
2114	#define X86_SEL_SHIFT 3
2115
2116	/**
2117	* The shift used to convert a selector from and to index an index (C).
2118	*/
2119	#define AMD64_SEL_SHIFT 4
2120
2121	#if HC_ARCH_BITS == 64
2122	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2123	#else
2124	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2125	#endif
2126
2127	/**
2128	* The mask used to mask off the table indicator and CPL of an selector.
2129	*/
2130	#define X86_SEL_MASK 0xfff8
2131
2132	/**
2133	* The bit indicating that a selector is in the LDT and not in the GDT.
2134	*/
2135	#define X86_SEL_LDT 0x0004
2136	/**
2137	* The bit mask for getting the RPL of a selector.
2138	*/
2139	#define X86_SEL_RPL 0x0003
2140
2141	/** @} */
2142
2143
2144	/**
2145	* x86 Exceptions/Faults/Traps.
2146	*/
2147	typedef enum X86XCPT
2148	{
2149	/** \#DE - Divide error. */
2150	X86_XCPT_DE = 0x00,
2151	/** \#DB - Debug event (single step, DRx, ..) */
2152	X86_XCPT_DB = 0x01,
2153	/** NMI - Non-Maskable Interrupt */
2154	X86_XCPT_NMI = 0x02,
2155	/** \#BP - Breakpoint (INT3). */
2156	X86_XCPT_BP = 0x03,
2157	/** \#OF - Overflow (INTO). */
2158	X86_XCPT_OF = 0x04,
2159	/** \#BR - Bound range exceeded (BOUND). */
2160	X86_XCPT_BR = 0x05,
2161	/** \#UD - Undefined opcode. */
2162	X86_XCPT_UD = 0x06,
2163	/** \#NM - Device not available (math coprocessor device). */
2164	X86_XCPT_NM = 0x07,
2165	/** \#DF - Double fault. */
2166	X86_XCPT_DF = 0x08,
2167	/** ??? - Coprocessor segment overrun (obsolete). */
2168	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2169	/** \#TS - Taskswitch (TSS). */
2170	X86_XCPT_TS = 0x0a,
2171	/** \#NP - Segment no present. */
2172	X86_XCPT_NP = 0x0b,
2173	/** \#SS - Stack segment fault. */
2174	X86_XCPT_SS = 0x0c,
2175	/** \#GP - General protection fault. */
2176	X86_XCPT_GP = 0x0d,
2177	/** \#PF - Page fault. */
2178	X86_XCPT_PF = 0x0e,
2179	/* 0x0f is reserved. */
2180	/** \#MF - Math fault (FPU). */
2181	X86_XCPT_MF = 0x10,
2182	/** \#AC - Alignment check. */
2183	X86_XCPT_AC = 0x11,
2184	/** \#MC - Machine check. */
2185	X86_XCPT_MC = 0x12,
2186	/** \#XF - SIMD Floating-Pointer Exception. */
2187	X86_XCPT_XF = 0x13
2188	} X86XCPT;
2189	/** Pointer to a x86 exception code. */
2190	typedef X86XCPT *PX86XCPT;
2191	/** Pointer to a const x86 exception code. */
2192	typedef const X86XCPT *PCX86XCPT;
2193
2194
2195	/** @name Trap Error Codes
2196	* @{
2197	*/
2198	/** External indicator. */
2199	#define X86_TRAP_ERR_EXTERNAL 1
2200	/** IDT indicator. */
2201	#define X86_TRAP_ERR_IDT 2
2202	/** Descriptor table indicator - If set LDT, if clear GDT. */
2203	#define X86_TRAP_ERR_TI 4
2204	/** Mask for getting the selector. */
2205	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2206	/** Shift for getting the selector table index (C type index). */
2207	#define X86_TRAP_ERR_SEL_SHIFT 3
2208	/** @} */
2209
2210
2211	/** @name \#PF Trap Error Codes
2212	* @{
2213	*/
2214	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2215	#define X86_TRAP_PF_P RT_BIT(0)
2216	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2217	#define X86_TRAP_PF_RW RT_BIT(1)
2218	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2219	#define X86_TRAP_PF_US RT_BIT(2)
2220	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2221	#define X86_TRAP_PF_RSVD RT_BIT(3)
2222	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2223	#define X86_TRAP_PF_ID RT_BIT(4)
2224	/** @} */
2225
2226	#pragma pack(1)
2227	/**
2228	* 32-bit IDTR/GDTR.
2229	*/
2230	typedef struct X86XDTR32
2231	{
2232	/** Size of the descriptor table. */
2233	uint16_t cb;
2234	/** Address of the descriptor table. */
2235	uint32_t uAddr;
2236	} X86XDTR32, *PX86XDTR32;
2237	#pragma pack()
2238
2239	#pragma pack(1)
2240	/**
2241	* 64-bit IDTR/GDTR.
2242	*/
2243	typedef struct X86XDTR64
2244	{
2245	/** Size of the descriptor table. */
2246	uint16_t cb;
2247	/** Address of the descriptor table. */
2248	uint64_t uAddr;
2249	} X86XDTR64, *PX86XDTR64;
2250	#pragma pack()
2251
2252	/** @} */
2253
2254	#endif
2255

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source: vbox/trunk/include/VBox/x86.h@ 7096

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