x86.h@ 5342

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 innotek GmbH
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License as published by the Free Software Foundation,
12	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13	* distribution. VirtualBox OSE is distributed in the hope that it will
14	* be useful, but WITHOUT ANY WARRANTY of any kind.
15	*/
16
17	/*
18	* x86.mac is generated from this file using:
19	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
20	*/
21
22	#ifndef ___VBox_x86_h
23	#define ___VBox_x86_h
24
25	#include <VBox/types.h>
26
27	/* Workaround for Solaris sys/regset.h defining CS, DS */
28	#if defined(RT_OS_SOLARIS)
29	# undef CS
30	# undef DS
31	#endif
32
33	/** @defgroup grp_x86 x86 Types and Definitions
34	* @{
35	*/
36
37	/**
38	* EFLAGS Bits.
39	*/
40	typedef struct X86EFLAGSBITS
41	{
42	/** Bit 0 - CF - Carry flag - Status flag. */
43	unsigned u1CF : 1;
44	/** Bit 1 - 1 - Reserved flag. */
45	unsigned u1Reserved0 : 1;
46	/** Bit 2 - PF - Parity flag - Status flag. */
47	unsigned u1PF : 1;
48	/** Bit 3 - 0 - Reserved flag. */
49	unsigned u1Reserved1 : 1;
50	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
51	unsigned u1AF : 1;
52	/** Bit 5 - 0 - Reserved flag. */
53	unsigned u1Reserved2 : 1;
54	/** Bit 6 - ZF - Zero flag - Status flag. */
55	unsigned u1ZF : 1;
56	/** Bit 7 - SF - Signed flag - Status flag. */
57	unsigned u1SF : 1;
58	/** Bit 8 - TF - Trap flag - System flag. */
59	unsigned u1TF : 1;
60	/** Bit 9 - IF - Interrupt flag - System flag. */
61	unsigned u1IF : 1;
62	/** Bit 10 - DF - Direction flag - Control flag. */
63	unsigned u1DF : 1;
64	/** Bit 11 - OF - Overflow flag - Status flag. */
65	unsigned u1OF : 1;
66	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
67	unsigned u2IOPL : 2;
68	/** Bit 14 - NT - Nested task flag - System flag. */
69	unsigned u1NT : 1;
70	/** Bit 15 - 0 - Reserved flag. */
71	unsigned u1Reserved3 : 1;
72	/** Bit 16 - RF - Resume flag - System flag. */
73	unsigned u1RF : 1;
74	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
75	unsigned u1VM : 1;
76	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
77	unsigned u1AC : 1;
78	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
79	unsigned u1VIF : 1;
80	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
81	unsigned u1VIP : 1;
82	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
83	unsigned u1ID : 1;
84	/** Bit 22-31 - 0 - Reserved flag. */
85	unsigned u10Reserved4 : 10;
86	} X86EFLAGSBITS;
87	/** Pointer to EFLAGS bits. */
88	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
89	/** Pointer to const EFLAGS bits. */
90	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
91
92	/**
93	* EFLAGS.
94	*/
95	typedef union X86EFLAGS
96	{
97	/** The bitfield view. */
98	X86EFLAGSBITS Bits;
99	/** The 8-bit view. */
100	uint8_t au8[4];
101	/** The 16-bit view. */
102	uint16_t au16[2];
103	/** The 32-bit view. */
104	uint32_t au32[1];
105	/** The 32-bit view. */
106	uint32_t u32;
107	} X86EFLAGS;
108	/** Pointer to EFLAGS. */
109	typedef X86EFLAGS *PX86EFLAGS;
110	/** Pointer to const EFLAGS. */
111	typedef const X86EFLAGS *PCX86EFLAGS;
112
113
114	/** @name EFLAGS
115	* @{
116	*/
117	/** Bit 0 - CF - Carry flag - Status flag. */
118	#define X86_EFL_CF BIT(0)
119	/** Bit 2 - PF - Parity flag - Status flag. */
120	#define X86_EFL_PF BIT(2)
121	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
122	#define X86_EFL_AF BIT(4)
123	/** Bit 6 - ZF - Zero flag - Status flag. */
124	#define X86_EFL_ZF BIT(6)
125	/** Bit 7 - SF - Signed flag - Status flag. */
126	#define X86_EFL_SF BIT(7)
127	/** Bit 8 - TF - Trap flag - System flag. */
128	#define X86_EFL_TF BIT(8)
129	/** Bit 9 - IF - Interrupt flag - System flag. */
130	#define X86_EFL_IF BIT(9)
131	/** Bit 10 - DF - Direction flag - Control flag. */
132	#define X86_EFL_DF BIT(10)
133	/** Bit 11 - OF - Overflow flag - Status flag. */
134	#define X86_EFL_OF BIT(11)
135	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
136	#define X86_EFL_IOPL (BIT(12) \| BIT(13))
137	/** Bit 14 - NT - Nested task flag - System flag. */
138	#define X86_EFL_NT BIT(14)
139	/** Bit 16 - RF - Resume flag - System flag. */
140	#define X86_EFL_RF BIT(16)
141	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
142	#define X86_EFL_VM BIT(17)
143	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
144	#define X86_EFL_AC BIT(18)
145	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
146	#define X86_EFL_VIF BIT(19)
147	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
148	#define X86_EFL_VIP BIT(20)
149	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
150	#define X86_EFL_ID BIT(21)
151	/** IOPL shift. */
152	#define X86_EFL_IOPL_SHIFT 12
153	/** The the IOPL level from the flags. */
154	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
155	/** @} */
156
157
158	/** CPUID Feature information - ECX.
159	* CPUID query with EAX=1.
160	*/
161	typedef struct X86CPUIDFEATECX
162	{
163	/** Bit 0 - SSE3 - Supports SSE3 or not. */
164	unsigned u1SSE3 : 1;
165	/** Reserved. */
166	unsigned u2Reserved1 : 2;
167	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
168	unsigned u1Monitor : 1;
169	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
170	unsigned u1CPLDS : 1;
171	/** Bit 5 - VMX - Virtual Machine Technology. */
172	unsigned u1VMX : 1;
173	/** Reserved. */
174	unsigned u1Reserved2 : 1;
175	/** Bit 7 - EST - Enh. SpeedStep Tech. */
176	unsigned u1EST : 1;
177	/** Bit 8 - TM2 - Terminal Monitor 2. */
178	unsigned u1TM2 : 1;
179	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
180	unsigned u1SSSE3 : 1;
181	/** Bit 10 - CNTX-ID - L1 Context ID. */
182	unsigned u1CNTXID : 1;
183	/** Reserved. */
184	unsigned u2Reserved4 : 2;
185	/** Bit 13 - CX16 - CMPXCHG16B. */
186	unsigned u1CX16 : 1;
187	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
188	unsigned u1TPRUpdate : 1;
189	/** Reserved. */
190	unsigned u17Reserved5 : 17;
191
192	} X86CPUIDFEATECX;
193	/** Pointer to CPUID Feature Information - ECX. */
194	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
195	/** Pointer to const CPUID Feature Information - ECX. */
196	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
197
198
199	/** CPUID Feature Information - EDX.
200	* CPUID query with EAX=1.
201	*/
202	typedef struct X86CPUIDFEATEDX
203	{
204	/** Bit 0 - FPU - x87 FPU on Chip. */
205	unsigned u1FPU : 1;
206	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
207	unsigned u1VME : 1;
208	/** Bit 2 - DE - Debugging extensions. */
209	unsigned u1DE : 1;
210	/** Bit 3 - PSE - Page Size Extension. */
211	unsigned u1PSE : 1;
212	/** Bit 4 - TSC - Time Stamp Counter. */
213	unsigned u1TSC : 1;
214	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
215	unsigned u1MSR : 1;
216	/** Bit 6 - PAE - Physical Address Extension. */
217	unsigned u1PAE : 1;
218	/** Bit 7 - MCE - Machine Check Exception. */
219	unsigned u1MCE : 1;
220	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
221	unsigned u1CX8 : 1;
222	/** Bit 9 - APIC - APIC On-Chick. */
223	unsigned u1APIC : 1;
224	/** Bit 10 - Reserved. */
225	unsigned u1Reserved1 : 1;
226	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
227	unsigned u1SEP : 1;
228	/** Bit 12 - MTRR - Memory Type Range Registers. */
229	unsigned u1MTRR : 1;
230	/** Bit 13 - PGE - PTE Global Bit. */
231	unsigned u1PGE : 1;
232	/** Bit 14 - MCA - Machine Check Architecture. */
233	unsigned u1MCA : 1;
234	/** Bit 15 - CMOV - Conditional Move Instructions. */
235	unsigned u1CMOV : 1;
236	/** Bit 16 - PAT - Page Attribute Table. */
237	unsigned u1PAT : 1;
238	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
239	unsigned u1PSE36 : 1;
240	/** Bit 18 - PSN - Processor Serial Number. */
241	unsigned u1PSN : 1;
242	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
243	unsigned u1CLFSH : 1;
244	/** Bit 20 - Reserved. */
245	unsigned u1Reserved2 : 1;
246	/** Bit 21 - DS - Debug Store. */
247	unsigned u1DS : 1;
248	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
249	unsigned u1ACPI : 1;
250	/** Bit 23 - MMX - Intel MMX 'Technology'. */
251	unsigned u1MMX : 1;
252	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
253	unsigned u1FXSR : 1;
254	/** Bit 25 - SSE - SSE Support. */
255	unsigned u1SSE : 1;
256	/** Bit 26 - SSE2 - SSE2 Support. */
257	unsigned u1SSE2 : 1;
258	/** Bit 27 - SS - Self Snoop. */
259	unsigned u1SS : 1;
260	/** Bit 28 - HTT - Hyper-Threading Technology. */
261	unsigned u1HTT : 1;
262	/** Bit 29 - TM - Thermal Monitor. */
263	unsigned u1TM : 1;
264	/** Bit 30 - Reserved - . */
265	unsigned u1Reserved3 : 1;
266	/** Bit 31 - PBE - Pending Break Enabled. */
267	unsigned u1PBE : 1;
268	} X86CPUIDFEATEDX;
269	/** Pointer to CPUID Feature Information - EDX. */
270	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
271	/** Pointer to const CPUID Feature Information - EDX. */
272	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
273
274	/** @name CPUID Vendor information.
275	* CPUID query with EAX=0.
276	* @{
277	*/
278	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
279	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
280	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
281
282	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
283	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
284	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
285	/** @} */
286
287
288	/** @name CPUID Feature information.
289	* CPUID query with EAX=1.
290	* @{
291	*/
292	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
293	#define X86_CPUID_FEATURE_ECX_SSE3 BIT(0)
294	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
295	#define X86_CPUID_FEATURE_ECX_MONITOR BIT(3)
296	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
297	#define X86_CPUID_FEATURE_ECX_CPLDS BIT(4)
298	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
299	#define X86_CPUID_FEATURE_ECX_VMX BIT(5)
300	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
301	#define X86_CPUID_FEATURE_ECX_EST BIT(7)
302	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
303	#define X86_CPUID_FEATURE_ECX_TM2 BIT(8)
304	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
305	#define X86_CPUID_FEATURE_ECX_SSSE3 BIT(9)
306	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
307	#define X86_CPUID_FEATURE_ECX_CNTXID BIT(10)
308	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
309	#define X86_CPUID_FEATURE_ECX_CX16 BIT(13)
310	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
311	#define X86_CPUID_FEATURE_ECX_TPRUPDATE BIT(14)
312	/** ECX Bit 23 - POPCOUNT instruction. */
313	#define X86_CPUID_FEATURE_ECX_POPCOUNT BIT(23)
314
315
316	/** Bit 0 - FPU - x87 FPU on Chip. */
317	#define X86_CPUID_FEATURE_EDX_FPU BIT(0)
318	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
319	#define X86_CPUID_FEATURE_EDX_VME BIT(1)
320	/** Bit 2 - DE - Debugging extensions. */
321	#define X86_CPUID_FEATURE_EDX_DE BIT(2)
322	/** Bit 3 - PSE - Page Size Extension. */
323	#define X86_CPUID_FEATURE_EDX_PSE BIT(3)
324	/** Bit 4 - TSC - Time Stamp Counter. */
325	#define X86_CPUID_FEATURE_EDX_TSC BIT(4)
326	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
327	#define X86_CPUID_FEATURE_EDX_MSR BIT(5)
328	/** Bit 6 - PAE - Physical Address Extension. */
329	#define X86_CPUID_FEATURE_EDX_PAE BIT(6)
330	/** Bit 7 - MCE - Machine Check Exception. */
331	#define X86_CPUID_FEATURE_EDX_MCE BIT(7)
332	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
333	#define X86_CPUID_FEATURE_EDX_CX8 BIT(8)
334	/** Bit 9 - APIC - APIC On-Chip. */
335	#define X86_CPUID_FEATURE_EDX_APIC BIT(9)
336	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
337	#define X86_CPUID_FEATURE_EDX_SEP BIT(11)
338	/** Bit 12 - MTRR - Memory Type Range Registers. */
339	#define X86_CPUID_FEATURE_EDX_MTRR BIT(12)
340	/** Bit 13 - PGE - PTE Global Bit. */
341	#define X86_CPUID_FEATURE_EDX_PGE BIT(13)
342	/** Bit 14 - MCA - Machine Check Architecture. */
343	#define X86_CPUID_FEATURE_EDX_MCA BIT(14)
344	/** Bit 15 - CMOV - Conditional Move Instructions. */
345	#define X86_CPUID_FEATURE_EDX_CMOV BIT(15)
346	/** Bit 16 - PAT - Page Attribute Table. */
347	#define X86_CPUID_FEATURE_EDX_PAT BIT(16)
348	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
349	#define X86_CPUID_FEATURE_EDX_PSE36 BIT(17)
350	/** Bit 18 - PSN - Processor Serial Number. */
351	#define X86_CPUID_FEATURE_EDX_PSN BIT(18)
352	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
353	#define X86_CPUID_FEATURE_EDX_CLFSH BIT(19)
354	/** Bit 21 - DS - Debug Store. */
355	#define X86_CPUID_FEATURE_EDX_DS BIT(21)
356	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
357	#define X86_CPUID_FEATURE_EDX_ACPI BIT(22)
358	/** Bit 23 - MMX - Intel MMX Technology. */
359	#define X86_CPUID_FEATURE_EDX_MMX BIT(23)
360	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
361	#define X86_CPUID_FEATURE_EDX_FXSR BIT(24)
362	/** Bit 25 - SSE - SSE Support. */
363	#define X86_CPUID_FEATURE_EDX_SSE BIT(25)
364	/** Bit 26 - SSE2 - SSE2 Support. */
365	#define X86_CPUID_FEATURE_EDX_SSE2 BIT(26)
366	/** Bit 27 - SS - Self Snoop. */
367	#define X86_CPUID_FEATURE_EDX_SS BIT(27)
368	/** Bit 28 - HTT - Hyper-Threading Technology. */
369	#define X86_CPUID_FEATURE_EDX_HTT BIT(28)
370	/** Bit 29 - TM - Therm. Monitor. */
371	#define X86_CPUID_FEATURE_EDX_TM BIT(29)
372	/** Bit 31 - PBE - Pending Break Enabled. */
373	#define X86_CPUID_FEATURE_EDX_PBE BIT(31)
374	/** @} */
375
376
377	/** @name CPUID AMD Feature information.
378	* CPUID query with EAX=0x80000001.
379	* @{
380	*/
381	/** Bit 0 - FPU - x87 FPU on Chip. */
382	#define X86_CPUID_AMD_FEATURE_EDX_FPU BIT(0)
383	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
384	#define X86_CPUID_AMD_FEATURE_EDX_VME BIT(1)
385	/** Bit 2 - DE - Debugging extensions. */
386	#define X86_CPUID_AMD_FEATURE_EDX_DE BIT(2)
387	/** Bit 3 - PSE - Page Size Extension. */
388	#define X86_CPUID_AMD_FEATURE_EDX_PSE BIT(3)
389	/** Bit 4 - TSC - Time Stamp Counter. */
390	#define X86_CPUID_AMD_FEATURE_EDX_TSC BIT(4)
391	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
392	#define X86_CPUID_AMD_FEATURE_EDX_MSR BIT(5)
393	/** Bit 6 - PAE - Physical Address Extension. */
394	#define X86_CPUID_AMD_FEATURE_EDX_PAE BIT(6)
395	/** Bit 7 - MCE - Machine Check Exception. */
396	#define X86_CPUID_AMD_FEATURE_EDX_MCE BIT(7)
397	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
398	#define X86_CPUID_AMD_FEATURE_EDX_CX8 BIT(8)
399	/** Bit 9 - APIC - APIC On-Chip. */
400	#define X86_CPUID_AMD_FEATURE_EDX_APIC BIT(9)
401	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
402	#define X86_CPUID_AMD_FEATURE_EDX_SEP BIT(11)
403	/** Bit 12 - MTRR - Memory Type Range Registers. */
404	#define X86_CPUID_AMD_FEATURE_EDX_MTRR BIT(12)
405	/** Bit 13 - PGE - PTE Global Bit. */
406	#define X86_CPUID_AMD_FEATURE_EDX_PGE BIT(13)
407	/** Bit 14 - MCA - Machine Check Architecture. */
408	#define X86_CPUID_AMD_FEATURE_EDX_MCA BIT(14)
409	/** Bit 15 - CMOV - Conditional Move Instructions. */
410	#define X86_CPUID_AMD_FEATURE_EDX_CMOV BIT(15)
411	/** Bit 16 - PAT - Page Attribute Table. */
412	#define X86_CPUID_AMD_FEATURE_EDX_PAT BIT(16)
413	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
414	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 BIT(17)
415	/** Bit 20 - NX - AMD No-Execute Page Protection. */
416	#define X86_CPUID_AMD_FEATURE_EDX_NX BIT(20)
417	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
418	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX BIT(22)
419	/** Bit 23 - MMX - Intel MMX Technology. */
420	#define X86_CPUID_AMD_FEATURE_EDX_MMX BIT(23)
421	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
422	#define X86_CPUID_AMD_FEATURE_EDX_FXSR BIT(24)
423	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
424	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR BIT(25)
425	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
426	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB BIT(26)
427	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
428	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP BIT(27)
429	/** Bit 29 - LM - AMD Long Mode. */
430	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE BIT(29)
431	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
432	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX BIT(30)
433	/** Bit 31 - 3DNOW - AMD 3DNow. */
434	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW BIT(31)
435
436	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
437	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF BIT(0)
438	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
439	#define X86_CPUID_AMD_FEATURE_ECX_CMPL BIT(1)
440	/** Bit 2 - SVM - AMD VM extensions. */
441	#define X86_CPUID_AMD_FEATURE_ECX_SVM BIT(2)
442	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
443	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC BIT(3)
444	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
445	#define X86_CPUID_AMD_FEATURE_ECX_CR8L BIT(4)
446	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
447	#define X86_CPUID_AMD_FEATURE_ECX_ABM BIT(5)
448	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
449	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A BIT(6)
450	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
451	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE BIT(7)
452	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
453	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF BIT(8)
454	/** Bit 9 - OSVW - AMD OS visible workaround. */
455	#define X86_CPUID_AMD_FEATURE_ECX_OSVW BIT(9)
456	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
457	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT BIT(12)
458	/** Bit 13 - WDT - AMD Watchdog timer support. */
459	#define X86_CPUID_AMD_FEATURE_ECX_WDT BIT(13)
460
461	/** @} */
462
463
464	/** @name CR0
465	* @{ */
466	/** Bit 0 - PE - Protection Enabled */
467	#define X86_CR0_PE BIT(0)
468	#define X86_CR0_PROTECTION_ENABLE BIT(0)
469	/** Bit 1 - MP - Monitor Coprocessor */
470	#define X86_CR0_MP BIT(1)
471	#define X86_CR0_MONITOR_COPROCESSOR BIT(1)
472	/** Bit 2 - EM - Emulation. */
473	#define X86_CR0_EM BIT(2)
474	#define X86_CR0_EMULATE_FPU BIT(2)
475	/** Bit 3 - TS - Task Switch. */
476	#define X86_CR0_TS BIT(3)
477	#define X86_CR0_TASK_SWITCH BIT(3)
478	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
479	#define X86_CR0_ET BIT(4)
480	#define X86_CR0_EXTENSION_TYPE BIT(4)
481	/** Bit 5 - NE - Numeric error. */
482	#define X86_CR0_NE BIT(5)
483	#define X86_CR0_NUMERIC_ERROR BIT(5)
484	/** Bit 16 - WP - Write Protect. */
485	#define X86_CR0_WP BIT(16)
486	#define X86_CR0_WRITE_PROTECT BIT(16)
487	/** Bit 18 - AM - Alignment Mask. */
488	#define X86_CR0_AM BIT(18)
489	#define X86_CR0_ALIGMENT_MASK BIT(18)
490	/** Bit 29 - NW - Not Write-though. */
491	#define X86_CR0_NW BIT(29)
492	#define X86_CR0_NOT_WRITE_THROUGH BIT(29)
493	/** Bit 30 - WP - Cache Disable. */
494	#define X86_CR0_CD BIT(30)
495	#define X86_CR0_CACHE_DISABLE BIT(30)
496	/** Bit 31 - PG - Paging. */
497	#define X86_CR0_PG BIT(31)
498	#define X86_CR0_PAGING BIT(31)
499	/** @} */
500
501
502	/** @name CR3
503	* @{ */
504	/** Bit 3 - PWT - Page-level Writes Transparent. */
505	#define X86_CR3_PWT BIT(3)
506	/** Bit 4 - PCD - Page-level Cache Disable. */
507	#define X86_CR3_PCD BIT(4)
508	/** Bits 12-31 - - Page directory page number. */
509	#define X86_CR3_PAGE_MASK (0xfffff000)
510	/** Bits 5-31 - - PAE Page directory page number. */
511	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
512	/** @} */
513
514
515	/** @name CR4
516	* @{ */
517	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
518	#define X86_CR4_VME BIT(0)
519	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
520	#define X86_CR4_PVI BIT(1)
521	/** Bit 2 - TSD - Time Stamp Disable. */
522	#define X86_CR4_TSD BIT(2)
523	/** Bit 3 - DE - Debugging Extensions. */
524	#define X86_CR4_DE BIT(3)
525	/** Bit 4 - PSE - Page Size Extension. */
526	#define X86_CR4_PSE BIT(4)
527	/** Bit 5 - PAE - Physical Address Extension. */
528	#define X86_CR4_PAE BIT(5)
529	/** Bit 6 - MCE - Machine-Check Enable. */
530	#define X86_CR4_MCE BIT(6)
531	/** Bit 7 - PGE - Page Global Enable. */
532	#define X86_CR4_PGE BIT(7)
533	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
534	#define X86_CR4_PCE BIT(8)
535	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
536	#define X86_CR4_OSFSXR BIT(9)
537	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
538	#define X86_CR4_OSXMMEEXCPT BIT(10)
539	/** Bit 13 - VMXE - VMX mode is enabled. */
540	#define X86_CR4_VMXE BIT(13)
541	/** @} */
542
543
544	/** @name DR6
545	* @{ */
546	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
547	#define X86_DR6_B0 BIT(0)
548	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
549	#define X86_DR6_B1 BIT(1)
550	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
551	#define X86_DR6_B2 BIT(2)
552	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
553	#define X86_DR6_B3 BIT(3)
554	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
555	#define X86_DR6_BD BIT(13)
556	/** Bit 14 - BS - Single step */
557	#define X86_DR6_BS BIT(14)
558	/** Bit 15 - BT - Task switch. (TSS T bit.) */
559	#define X86_DR6_BT BIT(15)
560	/** @} */
561
562
563	/** @name DR7
564	* @{ */
565	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
566	#define X86_DR7_L0 BIT(0)
567	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
568	#define X86_DR7_G0 BIT(1)
569	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
570	#define X86_DR7_L1 BIT(2)
571	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
572	#define X86_DR7_G1 BIT(3)
573	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
574	#define X86_DR7_L2 BIT(4)
575	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
576	#define X86_DR7_G2 BIT(5)
577	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
578	#define X86_DR7_L3 BIT(6)
579	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
580	#define X86_DR7_G3 BIT(7)
581	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
582	#define X86_DR7_LE BIT(8)
583	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
584	#define X86_DR7_GE BIT(9)
585
586	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
587	* any DR register is accessed. */
588	#define X86_DR7_GD BIT(13)
589	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
590	#define X86_DR7_RW0_MASK (3 << 16)
591	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
592	#define X86_DR7_LEN0_MASK (3 << 18)
593	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
594	#define X86_DR7_RW1_MASK (3 << 20)
595	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
596	#define X86_DR7_LEN1_MASK (3 << 22)
597	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
598	#define X86_DR7_RW2_MASK (3 << 24)
599	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
600	#define X86_DR7_LEN2_MASK (3 << 26)
601	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
602	#define X86_DR7_RW3_MASK (3 << 28)
603	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
604	#define X86_DR7_LEN3_MASK (3 << 30)
605
606	/** Bits which must be 1s. */
607	#define X86_DR7_MB1_MASK (BIT(10))
608
609	/** Calcs the L bit of Nth breakpoint.
610	* @param iBp The breakpoint number [0..3].
611	*/
612	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
613
614	/** Calcs the G bit of Nth breakpoint.
615	* @param iBp The breakpoint number [0..3].
616	*/
617	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
618
619	/** @name Read/Write values.
620	* @{ */
621	/** Break on instruction fetch only. */
622	#define X86_DR7_RW_EO 0
623	/** Break on write only. */
624	#define X86_DR7_RW_WO 1
625	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
626	#define X86_DR7_RW_IO 2
627	/** Break on read or write (but not instruction fetches). */
628	#define X86_DR7_RW_RW 3
629	/** @} */
630
631	/** Shifts a X86_DR7_RW_* value to its right place.
632	* @param iBp The breakpoint number [0..3].
633	* @param fRw One of the X86_DR7_RW_* value.
634	*/
635	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
636
637	/** @name Length values.
638	* @{ */
639	#define X86_DR7_LEN_BYTE 0
640	#define X86_DR7_LEN_WORD 1
641	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
642	#define X86_DR7_LEN_DWORD 3
643	/** @} */
644
645	/** Shifts a X86_DR7_LEN_* value to its right place.
646	* @param iBp The breakpoint number [0..3].
647	* @param cb One of the X86_DR7_LEN_* values.
648	*/
649	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
650
651	/** Mask used to check if any breakpoints are enabled. */
652	#define X86_DR7_ENABLED_MASK (BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(6) \| BIT(7))
653
654	/** @} */
655
656
657	/** @name Machine Specific Registers
658	* @{
659	*/
660	/** CPU Feature control. */
661	#define MSR_IA32_FEATURE_CONTROL 0x3A
662	#define MSR_IA32_FEATURE_CONTROL_LOCK BIT(0)
663	#define MSR_IA32_FEATURE_CONTROL_VMXON BIT(2)
664
665
666	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
667	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
668	* R0 SS == CS + 8
669	* R3 CS == CS + 16
670	* R3 SS == CS + 24
671	*/
672	#define MSR_IA32_SYSENTER_CS 0x174
673	/** SYSENTER_ESP - the R0 ESP. */
674	#define MSR_IA32_SYSENTER_ESP 0x175
675	/** SYSENTER_EIP - the R0 EIP. */
676	#define MSR_IA32_SYSENTER_EIP 0x176
677	#endif
678
679	/** Basic VMX information. */
680	#define MSR_IA32_VMX_BASIC_INFO 0x480
681	/** Allowed settings for pin-based VM execution controls */
682	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
683	/** Allowed settings for proc-based VM execution controls */
684	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
685	/** Allowed settings for the VMX exit controls. */
686	#define MSR_IA32_VMX_EXIT_CTLS 0x483
687	/** Allowed settings for the VMX entry controls. */
688	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
689	/** Misc VMX info. */
690	#define MSR_IA32_VMX_MISC 0x485
691	/** Fixed cleared bits in CR0. */
692	#define MSR_IA32_VMX_CR0_FIXED0 0x486
693	/** Fixed set bits in CR0. */
694	#define MSR_IA32_VMX_CR0_FIXED1 0x487
695	/** Fixed cleared bits in CR4. */
696	#define MSR_IA32_VMX_CR4_FIXED0 0x488
697	/** Fixed set bits in CR4. */
698	#define MSR_IA32_VMX_CR4_FIXED1 0x489
699	/** Information for enumerating fields in the VMCS. */
700	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
701
702
703	/** K6 EFER - Extended Feature Enable Register. */
704	#define MSR_K6_EFER 0xc0000080
705	/** @todo document EFER */
706	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
707	#define MSR_K6_EFER_SCE BIT(0)
708	/** Bit 8 - LME - Long mode enabled. (R/W) */
709	#define MSR_K6_EFER_LME BIT(8)
710	/** Bit 10 - LMA - Long mode active. (R) */
711	#define MSR_K6_EFER_LMA BIT(10)
712	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
713	#define MSR_K6_EFER_NXE BIT(11)
714	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
715	#define MSR_K6_EFER_SVME BIT(12)
716	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
717	#define MSR_K6_EFER_LMSLE BIT(13)
718	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
719	#define MSR_K6_EFER_FFXSR BIT(14)
720	/** K6 STAR - SYSCALL/RET targets. */
721	#define MSR_K6_STAR 0xc0000081
722	/** Shift value for getting the SYSRET CS and SS value. */
723	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
724	/** Shift value for getting the SYSCALL CS and SS value. */
725	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
726	/** Selector mask for use after shifting. */
727	#define MSR_K6_STAR_SEL_MASK 0xffff
728	/** The mask which give the SYSCALL EIP. */
729	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
730	/** K6 WHCR - Write Handling Control Register. */
731	#define MSR_K6_WHCR 0xc0000082
732	/** K6 UWCCR - UC/WC Cacheability Control Register. */
733	#define MSR_K6_UWCCR 0xc0000085
734	/** K6 PSOR - Processor State Observability Register. */
735	#define MSR_K6_PSOR 0xc0000087
736	/** K6 PFIR - Page Flush/Invalidate Register. */
737	#define MSR_K6_PFIR 0xc0000088
738
739	#define MSR_K7_EVNTSEL0 0xc0010000
740	#define MSR_K7_EVNTSEL1 0xc0010001
741	#define MSR_K7_EVNTSEL2 0xc0010002
742	#define MSR_K7_EVNTSEL3 0xc0010003
743	#define MSR_K7_PERFCTR0 0xc0010004
744	#define MSR_K7_PERFCTR1 0xc0010005
745	#define MSR_K7_PERFCTR2 0xc0010006
746	#define MSR_K7_PERFCTR3 0xc0010007
747
748	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
749	#define MSR_K8_LSTAR 0xc0000082
750	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
751	#define MSR_K8_CSTAR 0xc0000083
752	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
753	#define MSR_K8_SF_MASK 0xc0000084
754	/** K8 FS.base - The 64-bit base FS register. */
755	#define MSR_K8_FS_BASE 0xc0000100
756	/** K8 GS.base - The 64-bit base GS register. */
757	#define MSR_K8_GS_BASE 0xc0000101
758	/** K8 KernelGSbase - Used with SWAPGS. */
759	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
760	#define MSR_K8_TSC_AUX 0xc0000103
761	#define MSR_K8_SYSCFG 0xc0010010
762	#define MSR_K8_HWCR 0xc0010015
763	#define MSR_K8_IORRBASE0 0xc0010016
764	#define MSR_K8_IORRMASK0 0xc0010017
765	#define MSR_K8_IORRBASE1 0xc0010018
766	#define MSR_K8_IORRMASK1 0xc0010019
767	#define MSR_K8_TOP_MEM1 0xc001001a
768	#define MSR_K8_TOP_MEM2 0xc001001d
769	#define MSR_K8_VM_CR 0xc0010114
770	#define MSR_K8_VM_CR_SVM_DISABLE BIT(4)
771
772	#define MSR_K8_IGNNE 0xc0010115
773	#define MSR_K8_SMM_CTL 0xc0010116
774	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
775	* host state during world switch.
776	*/
777	#define MSR_K8_VM_HSAVE_PA 0xc0010117
778
779	/** @} */
780
781
782	/** @name Page Table / Directory / Directory Pointers / L4.
783	* @{
784	*/
785
786	/** Page table/directory entry as an unsigned integer. */
787	typedef uint32_t X86PGUINT;
788	/** Pointer to a page table/directory table entry as an unsigned integer. */
789	typedef X86PGUINT *PX86PGUINT;
790
791	/** Number of entries in a 32-bit PT/PD. */
792	#define X86_PG_ENTRIES 1024
793
794
795	/** PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
796	typedef uint64_t X86PGPAEUINT;
797	/** Pointer to a PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
798	typedef X86PGPAEUINT *PX86PGPAEUINT;
799
800	/** Number of entries in a PAE PT/PD/PDPTR/L4/L5. */
801	#define X86_PG_PAE_ENTRIES 512
802
803
804	/** The size of a 4KB page. */
805	#define X86_PAGE_4K_SIZE _4K
806	/** The page shift of a 4KB page. */
807	#define X86_PAGE_4K_SHIFT 12
808	/** The 4KB page offset mask. */
809	#define X86_PAGE_4K_OFFSET_MASK 0xfff
810	/** The 4KB page base mask for virtual addresses. */
811	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
812	/** The 4KB page base mask for virtual addresses - 32bit version. */
813	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
814
815	/** The size of a 2MB page. */
816	#define X86_PAGE_2M_SIZE _2M
817	/** The page shift of a 2MB page. */
818	#define X86_PAGE_2M_SHIFT 21
819	/** The 2MB page offset mask. */
820	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
821	/** The 2MB page base mask for virtual addresses. */
822	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
823	/** The 2MB page base mask for virtual addresses - 32bit version. */
824	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
825
826	/** The size of a 4MB page. */
827	#define X86_PAGE_4M_SIZE _4M
828	/** The page shift of a 4MB page. */
829	#define X86_PAGE_4M_SHIFT 22
830	/** The 4MB page offset mask. */
831	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
832	/** The 4MB page base mask for virtual addresses. */
833	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
834	/** The 4MB page base mask for virtual addresses - 32bit version. */
835	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
836
837
838
839	/** @name Page Table Entry
840	* @{
841	*/
842	/** Bit 0 - P - Present bit. */
843	#define X86_PTE_P BIT(0)
844	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
845	#define X86_PTE_RW BIT(1)
846	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
847	#define X86_PTE_US BIT(2)
848	/** Bit 3 - PWT - Page level write thru bit. */
849	#define X86_PTE_PWT BIT(3)
850	/** Bit 4 - PCD - Page level cache disable bit. */
851	#define X86_PTE_PCD BIT(4)
852	/** Bit 5 - A - Access bit. */
853	#define X86_PTE_A BIT(5)
854	/** Bit 6 - D - Dirty bit. */
855	#define X86_PTE_D BIT(6)
856	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
857	#define X86_PTE_PAT BIT(7)
858	/** Bit 8 - G - Global flag. */
859	#define X86_PTE_G BIT(8)
860	/** Bits 9-11 - - Available for use to system software. */
861	#define X86_PTE_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
862	/** Bits 12-31 - - Physical Page number of the next level. */
863	#define X86_PTE_PG_MASK ( 0xfffff000 )
864
865	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
866	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
867	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
868	#else
869	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
870	#endif
871	/** Bits 63 - NX - PAE - No execution flag. */
872	#define X86_PTE_PAE_NX BIT64(63)
873
874	/**
875	* Page table entry.
876	*/
877	typedef struct X86PTEBITS
878	{
879	/** Flags whether(=1) or not the page is present. */
880	unsigned u1Present : 1;
881	/** Read(=0) / Write(=1) flag. */
882	unsigned u1Write : 1;
883	/** User(=1) / Supervisor (=0) flag. */
884	unsigned u1User : 1;
885	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
886	unsigned u1WriteThru : 1;
887	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
888	unsigned u1CacheDisable : 1;
889	/** Accessed flag.
890	* Indicates that the page have been read or written to. */
891	unsigned u1Accessed : 1;
892	/** Dirty flag.
893	* Indicates that the page have been written to. */
894	unsigned u1Dirty : 1;
895	/** Reserved / If PAT enabled, bit 2 of the index. */
896	unsigned u1PAT : 1;
897	/** Global flag. (Ignored in all but final level.) */
898	unsigned u1Global : 1;
899	/** Available for use to system software. */
900	unsigned u3Available : 3;
901	/** Physical Page number of the next level. */
902	unsigned u20PageNo : 20;
903	} X86PTEBITS;
904	/** Pointer to a page table entry. */
905	typedef X86PTEBITS *PX86PTEBITS;
906	/** Pointer to a const page table entry. */
907	typedef const X86PTEBITS *PCX86PTEBITS;
908
909	/**
910	* Page table entry.
911	*/
912	typedef union X86PTE
913	{
914	/** Bit field view. */
915	X86PTEBITS n;
916	/** Unsigned integer view */
917	X86PGUINT u;
918	/** 32-bit view. */
919	uint32_t au32[1];
920	/** 16-bit view. */
921	uint16_t au16[2];
922	/** 8-bit view. */
923	uint8_t au8[4];
924	} X86PTE;
925	/** Pointer to a page table entry. */
926	typedef X86PTE *PX86PTE;
927	/** Pointer to a const page table entry. */
928	typedef const X86PTE *PCX86PTE;
929
930
931	/**
932	* PAE page table entry.
933	*/
934	typedef struct X86PTEPAEBITS
935	{
936	/** Flags whether(=1) or not the page is present. */
937	uint32_t u1Present : 1;
938	/** Read(=0) / Write(=1) flag. */
939	uint32_t u1Write : 1;
940	/** User(=1) / Supervisor(=0) flag. */
941	uint32_t u1User : 1;
942	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
943	uint32_t u1WriteThru : 1;
944	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
945	uint32_t u1CacheDisable : 1;
946	/** Accessed flag.
947	* Indicates that the page have been read or written to. */
948	uint32_t u1Accessed : 1;
949	/** Dirty flag.
950	* Indicates that the page have been written to. */
951	uint32_t u1Dirty : 1;
952	/** Reserved / If PAT enabled, bit 2 of the index. */
953	uint32_t u1PAT : 1;
954	/** Global flag. (Ignored in all but final level.) */
955	uint32_t u1Global : 1;
956	/** Available for use to system software. */
957	uint32_t u3Available : 3;
958	/** Physical Page number of the next level - Low Part. Don't use this. */
959	uint32_t u20PageNoLow : 20;
960	/** Physical Page number of the next level - High Part. Don't use this. */
961	uint32_t u20PageNoHigh : 20;
962	/** MBZ bits */
963	uint32_t u11Reserved : 11;
964	/** No Execute flag. */
965	uint32_t u1NoExecute : 1;
966	} X86PTEPAEBITS;
967	/** Pointer to a page table entry. */
968	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
969	/** Pointer to a page table entry. */
970	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
971
972	/**
973	* PAE Page table entry.
974	*/
975	typedef union X86PTEPAE
976	{
977	/** Bit field view. */
978	X86PTEPAEBITS n;
979	/** Unsigned integer view */
980	X86PGPAEUINT u;
981	/** 32-bit view. */
982	uint32_t au32[2];
983	/** 16-bit view. */
984	uint16_t au16[4];
985	/** 8-bit view. */
986	uint8_t au8[8];
987	} X86PTEPAE;
988	/** Pointer to a PAE page table entry. */
989	typedef X86PTEPAE *PX86PTEPAE;
990	/** Pointer to a const PAE page table entry. */
991	typedef const X86PTEPAE *PCX86PTEPAE;
992	/** @} */
993
994	/**
995	* Page table.
996	*/
997	typedef struct X86PT
998	{
999	/** PTE Array. */
1000	X86PTE a[X86_PG_ENTRIES];
1001	} X86PT;
1002	/** Pointer to a page table. */
1003	typedef X86PT *PX86PT;
1004	/** Pointer to a const page table. */
1005	typedef const X86PT *PCX86PT;
1006
1007	/** The page shift to get the PT index. */
1008	#define X86_PT_SHIFT 12
1009	/** The PT index mask (apply to a shifted page address). */
1010	#define X86_PT_MASK 0x3ff
1011
1012
1013	/**
1014	* Page directory.
1015	*/
1016	typedef struct X86PTPAE
1017	{
1018	/** PTE Array. */
1019	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1020	} X86PTPAE;
1021	/** Pointer to a page table. */
1022	typedef X86PTPAE *PX86PTPAE;
1023	/** Pointer to a const page table. */
1024	typedef const X86PTPAE *PCX86PTPAE;
1025
1026	/** The page shift to get the PA PTE index. */
1027	#define X86_PT_PAE_SHIFT 12
1028	/** The PAE PT index mask (apply to a shifted page address). */
1029	#define X86_PT_PAE_MASK 0x1ff
1030
1031
1032	/** @name 4KB Page Directory Entry
1033	* @{
1034	*/
1035	/** Bit 0 - P - Present bit. */
1036	#define X86_PDE_P BIT(0)
1037	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1038	#define X86_PDE_RW BIT(1)
1039	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1040	#define X86_PDE_US BIT(2)
1041	/** Bit 3 - PWT - Page level write thru bit. */
1042	#define X86_PDE_PWT BIT(3)
1043	/** Bit 4 - PCD - Page level cache disable bit. */
1044	#define X86_PDE_PCD BIT(4)
1045	/** Bit 5 - A - Access bit. */
1046	#define X86_PDE_A BIT(5)
1047	/** Bit 7 - PS - Page size attribute.
1048	* Clear mean 4KB pages, set means large pages (2/4MB). */
1049	#define X86_PDE_PS BIT(7)
1050	/** Bits 9-11 - - Available for use to system software. */
1051	#define X86_PDE_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
1052	/** Bits 12-31 - - Physical Page number of the next level. */
1053	#define X86_PDE_PG_MASK ( 0xfffff000 )
1054
1055	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1056	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1057	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1058	#else
1059	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1060	#endif
1061	/** Bits 63 - NX - PAE - No execution flag. */
1062	#define X86_PDE_PAE_NX BIT64(63)
1063
1064	/**
1065	* Page directory entry.
1066	*/
1067	typedef struct X86PDEBITS
1068	{
1069	/** Flags whether(=1) or not the page is present. */
1070	unsigned u1Present : 1;
1071	/** Read(=0) / Write(=1) flag. */
1072	unsigned u1Write : 1;
1073	/** User(=1) / Supervisor (=0) flag. */
1074	unsigned u1User : 1;
1075	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1076	unsigned u1WriteThru : 1;
1077	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1078	unsigned u1CacheDisable : 1;
1079	/** Accessed flag.
1080	* Indicates that the page have been read or written to. */
1081	unsigned u1Accessed : 1;
1082	/** Reserved / Ignored (dirty bit). */
1083	unsigned u1Reserved0 : 1;
1084	/** Size bit if PSE is enabled - in any event it's 0. */
1085	unsigned u1Size : 1;
1086	/** Reserved / Ignored (global bit). */
1087	unsigned u1Reserved1 : 1;
1088	/** Available for use to system software. */
1089	unsigned u3Available : 3;
1090	/** Physical Page number of the next level. */
1091	unsigned u20PageNo : 20;
1092	} X86PDEBITS;
1093	/** Pointer to a page directory entry. */
1094	typedef X86PDEBITS *PX86PDEBITS;
1095	/** Pointer to a const page directory entry. */
1096	typedef const X86PDEBITS *PCX86PDEBITS;
1097
1098
1099	/**
1100	* PAE page directory entry.
1101	*/
1102	typedef struct X86PDEPAEBITS
1103	{
1104	/** Flags whether(=1) or not the page is present. */
1105	uint32_t u1Present : 1;
1106	/** Read(=0) / Write(=1) flag. */
1107	uint32_t u1Write : 1;
1108	/** User(=1) / Supervisor (=0) flag. */
1109	uint32_t u1User : 1;
1110	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1111	uint32_t u1WriteThru : 1;
1112	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1113	uint32_t u1CacheDisable : 1;
1114	/** Accessed flag.
1115	* Indicates that the page have been read or written to. */
1116	uint32_t u1Accessed : 1;
1117	/** Reserved / Ignored (dirty bit). */
1118	uint32_t u1Reserved0 : 1;
1119	/** Size bit if PSE is enabled - in any event it's 0. */
1120	uint32_t u1Size : 1;
1121	/** Reserved / Ignored (global bit). / */
1122	uint32_t u1Reserved1 : 1;
1123	/** Available for use to system software. */
1124	uint32_t u3Available : 3;
1125	/** Physical Page number of the next level - Low Part. Don't use! */
1126	uint32_t u20PageNoLow : 20;
1127	/** Physical Page number of the next level - High Part. Don't use! */
1128	uint32_t u20PageNoHigh : 20;
1129	/** MBZ bits */
1130	uint32_t u11Reserved : 11;
1131	/** No Execute flag. */
1132	uint32_t u1NoExecute : 1;
1133	} X86PDEPAEBITS;
1134	/** Pointer to a page directory entry. */
1135	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1136	/** Pointer to a const page directory entry. */
1137	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1138
1139	/** @} */
1140
1141
1142	/** @name 2/4MB Page Directory Entry
1143	* @{
1144	*/
1145	/** Bit 0 - P - Present bit. */
1146	#define X86_PDE4M_P BIT(0)
1147	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1148	#define X86_PDE4M_RW BIT(1)
1149	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1150	#define X86_PDE4M_US BIT(2)
1151	/** Bit 3 - PWT - Page level write thru bit. */
1152	#define X86_PDE4M_PWT BIT(3)
1153	/** Bit 4 - PCD - Page level cache disable bit. */
1154	#define X86_PDE4M_PCD BIT(4)
1155	/** Bit 5 - A - Access bit. */
1156	#define X86_PDE4M_A BIT(5)
1157	/** Bit 6 - D - Dirty bit. */
1158	#define X86_PDE4M_D BIT(6)
1159	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1160	#define X86_PDE4M_PS BIT(7)
1161	/** Bit 8 - G - Global flag. */
1162	#define X86_PDE4M_G BIT(8)
1163	/** Bits 9-11 - AVL - Available for use to system software. */
1164	#define X86_PDE4M_AVL (BIT(9) \| BIT(10) \| BIT(11))
1165	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1166	#define X86_PDE4M_PAT BIT(12)
1167	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1168	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1169	/** Bits 22-31 - - Physical Page number. */
1170	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1171	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1172	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1173	/** The number of bits to the high part of the page number. */
1174	#define X86_PDE4M_PG_HIGH_SHIFT 19
1175
1176	/** Bits 12-51 - - PAE - Physical Page number. */
1177	#define X86_PDE4M_PAE_PG_MASK ( 0x000fffffffc00000ULL )
1178	/** Bits 63 - NX - PAE - No execution flag. */
1179	#define X86_PDE4M_PAE_NX BIT64(63)
1180
1181	/**
1182	* 4MB page directory entry.
1183	*/
1184	typedef struct X86PDE4MBITS
1185	{
1186	/** Flags whether(=1) or not the page is present. */
1187	unsigned u1Present : 1;
1188	/** Read(=0) / Write(=1) flag. */
1189	unsigned u1Write : 1;
1190	/** User(=1) / Supervisor (=0) flag. */
1191	unsigned u1User : 1;
1192	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1193	unsigned u1WriteThru : 1;
1194	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1195	unsigned u1CacheDisable : 1;
1196	/** Accessed flag.
1197	* Indicates that the page have been read or written to. */
1198	unsigned u1Accessed : 1;
1199	/** Dirty flag.
1200	* Indicates that the page have been written to. */
1201	unsigned u1Dirty : 1;
1202	/** Page size flag - always 1 for 4MB entries. */
1203	unsigned u1Size : 1;
1204	/** Global flag. */
1205	unsigned u1Global : 1;
1206	/** Available for use to system software. */
1207	unsigned u3Available : 3;
1208	/** Reserved / If PAT enabled, bit 2 of the index. */
1209	unsigned u1PAT : 1;
1210	/** Bits 32-39 of the page number on AMD64.
1211	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1212	unsigned u8PageNoHigh : 8;
1213	/** Reserved. */
1214	unsigned u1Reserved : 1;
1215	/** Physical Page number of the page. */
1216	unsigned u10PageNo : 10;
1217	} X86PDE4MBITS;
1218	/** Pointer to a page table entry. */
1219	typedef X86PDE4MBITS *PX86PDE4MBITS;
1220	/** Pointer to a const page table entry. */
1221	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1222
1223
1224	/**
1225	* 2MB PAE page directory entry.
1226	*/
1227	typedef struct X86PDE2MPAEBITS
1228	{
1229	/** Flags whether(=1) or not the page is present. */
1230	uint32_t u1Present : 1;
1231	/** Read(=0) / Write(=1) flag. */
1232	uint32_t u1Write : 1;
1233	/** User(=1) / Supervisor(=0) flag. */
1234	uint32_t u1User : 1;
1235	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1236	uint32_t u1WriteThru : 1;
1237	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1238	uint32_t u1CacheDisable : 1;
1239	/** Accessed flag.
1240	* Indicates that the page have been read or written to. */
1241	uint32_t u1Accessed : 1;
1242	/** Dirty flag.
1243	* Indicates that the page have been written to. */
1244	uint32_t u1Dirty : 1;
1245	/** Page size flag - always 1 for 2MB entries. */
1246	uint32_t u1Size : 1;
1247	/** Global flag. */
1248	uint32_t u1Global : 1;
1249	/** Available for use to system software. */
1250	uint32_t u3Available : 3;
1251	/** Reserved / If PAT enabled, bit 2 of the index. */
1252	uint32_t u1PAT : 1;
1253	/** Reserved. */
1254	uint32_t u9Reserved : 9;
1255	/** Physical Page number of the next level - Low part. Don't use! */
1256	uint32_t u10PageNoLow : 10;
1257	/** Physical Page number of the next level - High part. Don't use! */
1258	uint32_t u20PageNoHigh : 20;
1259	/** MBZ bits */
1260	uint32_t u11Reserved : 11;
1261	/** No Execute flag. */
1262	uint32_t u1NoExecute : 1;
1263	} X86PDE2MPAEBITS;
1264	/** Pointer to a 4MB PAE page table entry. */
1265	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1266	/** Pointer to a 4MB PAE page table entry. */
1267	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1268
1269	/** @} */
1270
1271	/**
1272	* Page directory entry.
1273	*/
1274	typedef union X86PDE
1275	{
1276	/** Normal view. */
1277	X86PDEBITS n;
1278	/** 4MB view (big). */
1279	X86PDE4MBITS b;
1280	/** Unsigned integer view. */
1281	X86PGUINT u;
1282	/** 8 bit unsigned integer view. */
1283	uint8_t au8[4];
1284	/** 16 bit unsigned integer view. */
1285	uint16_t au16[2];
1286	/** 32 bit unsigned integer view. */
1287	uint32_t au32[1];
1288	} X86PDE;
1289	/** Pointer to a page directory entry. */
1290	typedef X86PDE *PX86PDE;
1291	/** Pointer to a const page directory entry. */
1292	typedef const X86PDE *PCX86PDE;
1293
1294	/**
1295	* PAE page directory entry.
1296	*/
1297	typedef union X86PDEPAE
1298	{
1299	/** Normal view. */
1300	X86PDEPAEBITS n;
1301	/** 2MB page view (big). */
1302	X86PDE2MPAEBITS b;
1303	/** Unsigned integer view. */
1304	X86PGPAEUINT u;
1305	/** 8 bit unsigned integer view. */
1306	uint8_t au8[8];
1307	/** 16 bit unsigned integer view. */
1308	uint16_t au16[4];
1309	/** 32 bit unsigned integer view. */
1310	uint32_t au32[2];
1311	} X86PDEPAE;
1312	/** Pointer to a page directory entry. */
1313	typedef X86PDEPAE *PX86PDEPAE;
1314	/** Pointer to a const page directory entry. */
1315	typedef const X86PDEPAE *PCX86PDEPAE;
1316
1317	/**
1318	* Page directory.
1319	*/
1320	typedef struct X86PD
1321	{
1322	/** PDE Array. */
1323	X86PDE a[X86_PG_ENTRIES];
1324	} X86PD;
1325	/** Pointer to a page directory. */
1326	typedef X86PD *PX86PD;
1327	/** Pointer to a const page directory. */
1328	typedef const X86PD *PCX86PD;
1329
1330	/** The page shift to get the PD index. */
1331	#define X86_PD_SHIFT 22
1332	/** The PD index mask (apply to a shifted page address). */
1333	#define X86_PD_MASK 0x3ff
1334
1335
1336	/**
1337	* PAE page directory.
1338	*/
1339	typedef struct X86PDPAE
1340	{
1341	/** PDE Array. */
1342	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1343	} X86PDPAE;
1344	/** Pointer to a PAE page directory. */
1345	typedef X86PDPAE *PX86PDPAE;
1346	/** Pointer to a const PAE page directory. */
1347	typedef const X86PDPAE *PCX86PDPAE;
1348
1349	/** The page shift to get the PAE PD index. */
1350	#define X86_PD_PAE_SHIFT 21
1351	/** The PAE PD index mask (apply to a shifted page address). */
1352	#define X86_PD_PAE_MASK 0x1ff
1353
1354
1355	/** @name Page Directory Pointer Table Entry (PAE)
1356	* @{
1357	*/
1358	/** Bit 0 - P - Present bit. */
1359	#define X86_PDPE_P BIT(0)
1360	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1361	#define X86_PDPE_RW BIT(1)
1362	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1363	#define X86_PDPE_US BIT(2)
1364	/** Bit 3 - PWT - Page level write thru bit. */
1365	#define X86_PDPE_PWT BIT(3)
1366	/** Bit 4 - PCD - Page level cache disable bit. */
1367	#define X86_PDPE_PCD BIT(4)
1368	/** Bit 5 - A - Access bit. Long Mode only. */
1369	#define X86_PDPE_A BIT(5)
1370	/** Bits 9-11 - - Available for use to system software. */
1371	#define X86_PDPE_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
1372	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1373	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1374	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1375	#else
1376	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1377	#endif
1378	/** Bits 63 - NX - PAE - No execution flag. */
1379	#define X86_PDPE_NX BIT64(63)
1380
1381	/**
1382	* Page directory pointer table entry.
1383	*/
1384	typedef struct X86PDPEBITS
1385	{
1386	/** Flags whether(=1) or not the page is present. */
1387	uint32_t u1Present : 1;
1388	/** Read(=0) / Write(=1) flag. */
1389	uint32_t u1Write : 1;
1390	/** User(=1) / Supervisor (=0) flag. */
1391	uint32_t u1User : 1;
1392	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1393	uint32_t u1WriteThru : 1;
1394	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1395	uint32_t u1CacheDisable : 1;
1396	/** Accessed flag.
1397	* Indicates that the page have been read or written to. */
1398	uint32_t u1Accessed : 1;
1399	/** Chunk of reserved bits. */
1400	uint32_t u3Reserved : 3;
1401	/** Available for use to system software. */
1402	uint32_t u3Available : 3;
1403	/** Physical Page number of the next level - Low Part. Don't use! */
1404	uint32_t u20PageNoLow : 20;
1405	/** Physical Page number of the next level - High Part. Don't use! */
1406	uint32_t u20PageNoHigh : 20;
1407	/** MBZ bits */
1408	uint32_t u11Reserved : 11;
1409	/** No Execute flag. */
1410	uint32_t u1NoExecute : 1;
1411	} X86PDPEBITS;
1412	/** Pointer to a page directory pointer table entry. */
1413	typedef X86PDPEBITS *PX86PTPEBITS;
1414	/** Pointer to a const page directory pointer table entry. */
1415	typedef const X86PDPEBITS *PCX86PTPEBITS;
1416
1417	/**
1418	* Page directory pointer table entry.
1419	*/
1420	typedef union X86PDPE
1421	{
1422	/** Normal view. */
1423	X86PDPEBITS n;
1424	/** Unsigned integer view. */
1425	X86PGPAEUINT u;
1426	/** 8 bit unsigned integer view. */
1427	uint8_t au8[8];
1428	/** 16 bit unsigned integer view. */
1429	uint16_t au16[4];
1430	/** 32 bit unsigned integer view. */
1431	uint32_t au32[2];
1432	} X86PDPE;
1433	/** Pointer to a page directory pointer table entry. */
1434	typedef X86PDPE *PX86PDPE;
1435	/** Pointer to a const page directory pointer table entry. */
1436	typedef const X86PDPE *PCX86PDPE;
1437
1438
1439	/**
1440	* Page directory pointer table.
1441	*/
1442	typedef struct X86PDPTR
1443	{
1444	/** PDE Array. */
1445	X86PDPE a[X86_PG_PAE_ENTRIES];
1446	} X86PDPTR;
1447	/** Pointer to a page directory pointer table. */
1448	typedef X86PDPTR *PX86PDPTR;
1449	/** Pointer to a const page directory pointer table. */
1450	typedef const X86PDPTR *PCX86PDPTR;
1451
1452	/** The page shift to get the PDPTR index. */
1453	#define X86_PDPTR_SHIFT 30
1454	/** The PDPTR index mask (apply to a shifted page address). (32 bits PAE) */
1455	#define X86_PDPTR_MASK_32 0x3
1456	/** The PDPTR index mask (apply to a shifted page address). (64 bits PAE)*/
1457	#define X86_PDPTR_MASK 0x1ff
1458
1459	/** @} */
1460
1461
1462	/** @name Page Map Level-4 Entry (Long Mode PAE)
1463	* @{
1464	*/
1465	/** Bit 0 - P - Present bit. */
1466	#define X86_PML4E_P BIT(0)
1467	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1468	#define X86_PML4E_RW BIT(1)
1469	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1470	#define X86_PML4E_US BIT(2)
1471	/** Bit 3 - PWT - Page level write thru bit. */
1472	#define X86_PML4E_PWT BIT(3)
1473	/** Bit 4 - PCD - Page level cache disable bit. */
1474	#define X86_PML4E_PCD BIT(4)
1475	/** Bit 5 - A - Access bit. */
1476	#define X86_PML4E_A BIT(5)
1477	/** Bits 9-11 - - Available for use to system software. */
1478	#define X86_PML4E_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
1479	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1480	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1481	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1482	#else
1483	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1484	#endif
1485	/** Bits 63 - NX - PAE - No execution flag. */
1486	#define X86_PML4E_NX BIT64(63)
1487
1488	/**
1489	* Page Map Level-4 Entry
1490	*/
1491	typedef struct X86PML4EBITS
1492	{
1493	/** Flags whether(=1) or not the page is present. */
1494	uint32_t u1Present : 1;
1495	/** Read(=0) / Write(=1) flag. */
1496	uint32_t u1Write : 1;
1497	/** User(=1) / Supervisor (=0) flag. */
1498	uint32_t u1User : 1;
1499	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1500	uint32_t u1WriteThru : 1;
1501	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1502	uint32_t u1CacheDisable : 1;
1503	/** Accessed flag.
1504	* Indicates that the page have been read or written to. */
1505	uint32_t u1Accessed : 1;
1506	/** Chunk of reserved bits. */
1507	uint32_t u3Reserved : 3;
1508	/** Available for use to system software. */
1509	uint32_t u3Available : 3;
1510	/** Physical Page number of the next level - Low Part. Don't use! */
1511	uint32_t u20PageNoLow : 20;
1512	/** Physical Page number of the next level - High Part. Don't use! */
1513	uint32_t u20PageNoHigh : 20;
1514	/** MBZ bits */
1515	uint32_t u11Reserved : 11;
1516	/** No Execute flag. */
1517	uint32_t u1NoExecute : 1;
1518	} X86PML4EBITS;
1519	/** Pointer to a page map level-4 entry. */
1520	typedef X86PML4EBITS *PX86PML4EBITS;
1521	/** Pointer to a const page map level-4 entry. */
1522	typedef const X86PML4EBITS *PCX86PML4EBITS;
1523
1524	/**
1525	* Page Map Level-4 Entry.
1526	*/
1527	typedef union X86PML4E
1528	{
1529	/** Normal view. */
1530	X86PML4EBITS n;
1531	/** Unsigned integer view. */
1532	X86PGPAEUINT u;
1533	/** 8 bit unsigned integer view. */
1534	uint8_t au8[8];
1535	/** 16 bit unsigned integer view. */
1536	uint16_t au16[4];
1537	/** 32 bit unsigned integer view. */
1538	uint32_t au32[2];
1539	} X86PML4E;
1540	/** Pointer to a page map level-4 entry. */
1541	typedef X86PML4E *PX86PML4E;
1542	/** Pointer to a const page map level-4 entry. */
1543	typedef const X86PML4E *PCX86PML4E;
1544
1545
1546	/**
1547	* Page Map Level-4.
1548	*/
1549	typedef struct X86PML4
1550	{
1551	/** PDE Array. */
1552	X86PML4E a[X86_PG_PAE_ENTRIES];
1553	} X86PML4;
1554	/** Pointer to a page map level-4. */
1555	typedef X86PML4 *PX86PML4;
1556	/** Pointer to a const page map level-4. */
1557	typedef const X86PML4 *PCX86PML4;
1558
1559	/** The page shift to get the PML4 index. */
1560	#define X86_PML4_SHIFT 39
1561	/** The PML4 index mask (apply to a shifted page address). */
1562	#define X86_PML4_MASK 0x1ff
1563
1564	/** @} */
1565
1566	/** @} */
1567
1568
1569	/**
1570	* 80-bit MMX/FPU register type.
1571	*/
1572	typedef struct X86FPUMMX
1573	{
1574	uint8_t reg[10];
1575	} X86FPUMMX;
1576	/** Pointer to a 80-bit MMX/FPU register type. */
1577	typedef X86FPUMMX *PX86FPUMMX;
1578	/** Pointer to a const 80-bit MMX/FPU register type. */
1579	typedef const X86FPUMMX *PCX86FPUMMX;
1580
1581	/**
1582	* FPU state (aka FSAVE/FRSTOR Memory Region).
1583	*/
1584	#pragma pack(1)
1585	typedef struct X86FPUSTATE
1586	{
1587	/** Control word. */
1588	uint16_t FCW;
1589	/** Alignment word */
1590	uint16_t Dummy1;
1591	/** Status word. */
1592	uint16_t FSW;
1593	/** Alignment word */
1594	uint16_t Dummy2;
1595	/** Tag word */
1596	uint16_t FTW;
1597	/** Alignment word */
1598	uint16_t Dummy3;
1599
1600	/** Instruction pointer. */
1601	uint32_t FPUIP;
1602	/** Code selector. */
1603	uint16_t CS;
1604	/** Opcode. */
1605	uint16_t FOP;
1606	/** FOO. */
1607	uint32_t FPUOO;
1608	/** FOS. */
1609	uint32_t FPUOS;
1610	/** FPU view - todo. */
1611	X86FPUMMX regs[8];
1612	} X86FPUSTATE;
1613	#pragma pack()
1614	/** Pointer to a FPU state. */
1615	typedef X86FPUSTATE *PX86FPUSTATE;
1616	/** Pointer to a const FPU state. */
1617	typedef const X86FPUSTATE *PCX86FPUSTATE;
1618
1619	/**
1620	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1621	*/
1622	#pragma pack(1)
1623	typedef struct X86FXSTATE
1624	{
1625	/** Control word. */
1626	uint16_t FCW;
1627	/** Status word. */
1628	uint16_t FSW;
1629	/** Tag word (it's a byte actually). */
1630	uint8_t FTW;
1631	uint8_t huh1;
1632	/** Opcode. */
1633	uint16_t FOP;
1634	/** Instruction pointer. */
1635	uint32_t FPUIP;
1636	/** Code selector. */
1637	uint16_t CS;
1638	uint16_t Rsvrd1;
1639	/* - offset 16 - */
1640	/** Data pointer. */
1641	uint32_t FPUDP;
1642	/** Data segment */
1643	uint16_t DS;
1644	uint16_t Rsrvd2;
1645	uint32_t MXCSR;
1646	uint32_t MXCSR_MASK;
1647	/* - offset 32 - */
1648	union
1649	{
1650	/** MMX view. */
1651	uint64_t mmx;
1652	/** FPU view - todo. */
1653	X86FPUMMX fpu;
1654	/** 8-bit view. */
1655	uint8_t au8[16];
1656	/** 16-bit view. */
1657	uint16_t au16[8];
1658	/** 32-bit view. */
1659	uint32_t au32[4];
1660	/** 64-bit view. */
1661	uint64_t au64[2];
1662	/** 128-bit view. (yeah, very helpful) */
1663	uint128_t au128[1];
1664	} aRegs[8];
1665	/* - offset 160 - */
1666	union
1667	{
1668	/** XMM Register view . /
1669	uint128_t xmm;
1670	/** 8-bit view. */
1671	uint8_t au8[16];
1672	/** 16-bit view. */
1673	uint16_t au16[8];
1674	/** 32-bit view. */
1675	uint32_t au32[4];
1676	/** 64-bit view. */
1677	uint64_t au64[2];
1678	/** 128-bit view. (yeah, very helpful) */
1679	uint128_t au128[1];
1680	} aXMM[8];
1681	/* - offset 288 - */
1682	uint32_t au32RsrvdRest[(512 - 288) / sizeof(uint32_t)];
1683	} X86FXSTATE;
1684	#pragma pack()
1685	/** Pointer to a FPU Extended state. */
1686	typedef X86FXSTATE *PX86FXSTATE;
1687	/** Pointer to a const FPU Extended state. */
1688	typedef const X86FXSTATE *PCX86FXSTATE;
1689
1690
1691	/** @name Selector Descriptor
1692	* @{
1693	*/
1694
1695	/**
1696	* Generic descriptor table entry
1697	*/
1698	#pragma pack(1)
1699	typedef struct X86DESCGENERIC
1700	{
1701	/** Limit - Low word. */
1702	unsigned u16LimitLow : 16;
1703	/** Base address - lowe word.
1704	* Don't try set this to 24 because MSC is doing studing things then. */
1705	unsigned u16BaseLow : 16;
1706	/** Base address - first 8 bits of high word. */
1707	unsigned u8BaseHigh1 : 8;
1708	/** Segment Type. */
1709	unsigned u4Type : 4;
1710	/** Descriptor Type. System(=0) or code/data selector */
1711	unsigned u1DescType : 1;
1712	/** Descriptor Privelege level. */
1713	unsigned u2Dpl : 2;
1714	/** Flags selector present(=1) or not. */
1715	unsigned u1Present : 1;
1716	/** Segment limit 16-19. */
1717	unsigned u4LimitHigh : 4;
1718	/** Available for system software. */
1719	unsigned u1Available : 1;
1720	/** Reserved - 0. */
1721	unsigned u1Reserved : 1;
1722	/** This flags meaning depends on the segment type. Try make sense out
1723	* of the intel manual yourself. */
1724	unsigned u1DefBig : 1;
1725	/** Granularity of the limit. If set 4KB granularity is used, if
1726	* clear byte. */
1727	unsigned u1Granularity : 1;
1728	/** Base address - highest 8 bits. */
1729	unsigned u8BaseHigh2 : 8;
1730	} X86DESCGENERIC;
1731	#pragma pack()
1732	/** Pointer to a generic descriptor entry. */
1733	typedef X86DESCGENERIC *PX86DESCGENERIC;
1734	/** Pointer to a const generic descriptor entry. */
1735	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1736
1737
1738	/**
1739	* Descriptor attributes.
1740	*/
1741	typedef struct X86DESCATTRBITS
1742	{
1743	/** Segment Type. */
1744	unsigned u4Type : 4;
1745	/** Descriptor Type. System(=0) or code/data selector */
1746	unsigned u1DescType : 1;
1747	/** Descriptor Privelege level. */
1748	unsigned u2Dpl : 2;
1749	/** Flags selector present(=1) or not. */
1750	unsigned u1Present : 1;
1751	/** Segment limit 16-19. */
1752	unsigned u4LimitHigh : 4;
1753	/** Available for system software. */
1754	unsigned u1Available : 1;
1755	/** Reserved - 0. */
1756	unsigned u1Reserved : 1;
1757	/** This flags meaning depends on the segment type. Try make sense out
1758	* of the intel manual yourself. */
1759	unsigned u1DefBig : 1;
1760	/** Granularity of the limit. If set 4KB granularity is used, if
1761	* clear byte. */
1762	unsigned u1Granularity : 1;
1763	} X86DESCATTRBITS;
1764
1765
1766	#pragma pack(1)
1767	typedef union X86DESCATTR
1768	{
1769	/** Normal view. */
1770	X86DESCATTRBITS n;
1771	/** Unsigned integer view. */
1772	uint32_t u;
1773	} X86DESCATTR;
1774	#pragma pack()
1775
1776	/** Pointer to descriptor attributes. */
1777	typedef X86DESCATTR *PX86DESCATTR;
1778	/** Pointer to const descriptor attributes. */
1779	typedef const X86DESCATTR *PCX86DESCATTR;
1780
1781
1782	/**
1783	* Descriptor table entry.
1784	*/
1785	#pragma pack(1)
1786	typedef union X86DESC
1787	{
1788	/** Generic descriptor view. */
1789	X86DESCGENERIC Gen;
1790	#if 0
1791	/** IDT view. */
1792	VBOXIDTE Idt;
1793	#endif
1794
1795	/** 8 bit unsigned interger view. */
1796	uint8_t au8[8];
1797	/** 16 bit unsigned interger view. */
1798	uint16_t au16[4];
1799	/** 32 bit unsigned interger view. */
1800	uint32_t au32[2];
1801	} X86DESC;
1802	#pragma pack()
1803	/** Pointer to descriptor table entry. */
1804	typedef X86DESC *PX86DESC;
1805	/** Pointer to const descriptor table entry. */
1806	typedef const X86DESC *PCX86DESC;
1807
1808
1809	/**
1810	* 64 bits generic descriptor table entry
1811	* Note: most of these bits have no meaning in long mode.
1812	*/
1813	#pragma pack(1)
1814	typedef struct X86DESC64GENERIC
1815	{
1816	/** Limit - Low word - IGNORED. */
1817	unsigned u16LimitLow : 16;
1818	/** Base address - lowe word. - IGNORED
1819	* Don't try set this to 24 because MSC is doing studing things then. */
1820	unsigned u16BaseLow : 16;
1821	/** Base address - first 8 bits of high word. - IGNORED */
1822	unsigned u8BaseHigh1 : 8;
1823	/** Segment Type. */
1824	unsigned u4Type : 4;
1825	/** Descriptor Type. System(=0) or code/data selector */
1826	unsigned u1DescType : 1;
1827	/** Descriptor Privelege level. */
1828	unsigned u2Dpl : 2;
1829	/** Flags selector present(=1) or not. */
1830	unsigned u1Present : 1;
1831	/** Segment limit 16-19. - IGNORED */
1832	unsigned u4LimitHigh : 4;
1833	/** Available for system software. - IGNORED */
1834	unsigned u1Available : 1;
1835	/** Long mode flag. */
1836	unsigned u1Long : 1;
1837	/** This flags meaning depends on the segment type. Try make sense out
1838	* of the intel manual yourself. */
1839	unsigned u1DefBig : 1;
1840	/** Granularity of the limit. If set 4KB granularity is used, if
1841	* clear byte. - IGNORED */
1842	unsigned u1Granularity : 1;
1843	/** Base address - highest 8 bits. - IGNORED */
1844	unsigned u8BaseHigh2 : 8;
1845	/** Base address - bits 63-32. */
1846	unsigned u32BaseHigh3 : 32;
1847	unsigned u8Reserved : 8;
1848	unsigned u5Zeros : 5;
1849	unsigned u19Reserved : 19;
1850	} X86DESC64GENERIC;
1851	#pragma pack()
1852	/** Pointer to a generic descriptor entry. */
1853	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1854	/** Pointer to a const generic descriptor entry. */
1855	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1856
1857	/**
1858	* System descriptor table entry (64 bits)
1859	*/
1860	#pragma pack(1)
1861	typedef struct X86DESC64SYSTEM
1862	{
1863	/** Limit - Low word. */
1864	unsigned u16LimitLow : 16;
1865	/** Base address - lowe word.
1866	* Don't try set this to 24 because MSC is doing studing things then. */
1867	unsigned u16BaseLow : 16;
1868	/** Base address - first 8 bits of high word. */
1869	unsigned u8BaseHigh1 : 8;
1870	/** Segment Type. */
1871	unsigned u4Type : 4;
1872	/** Descriptor Type. System(=0) or code/data selector */
1873	unsigned u1DescType : 1;
1874	/** Descriptor Privelege level. */
1875	unsigned u2Dpl : 2;
1876	/** Flags selector present(=1) or not. */
1877	unsigned u1Present : 1;
1878	/** Segment limit 16-19. */
1879	unsigned u4LimitHigh : 4;
1880	/** Available for system software. */
1881	unsigned u1Available : 1;
1882	/** Reserved - 0. */
1883	unsigned u1Reserved : 1;
1884	/** This flags meaning depends on the segment type. Try make sense out
1885	* of the intel manual yourself. */
1886	unsigned u1DefBig : 1;
1887	/** Granularity of the limit. If set 4KB granularity is used, if
1888	* clear byte. */
1889	unsigned u1Granularity : 1;
1890	/** Base address - bits 31-24. */
1891	unsigned u8BaseHigh2 : 8;
1892	/** Base address - bits 63-32. */
1893	unsigned u32BaseHigh3 : 32;
1894	unsigned u8Reserved : 8;
1895	unsigned u5Zeros : 5;
1896	unsigned u19Reserved : 19;
1897	} X86DESC64SYSTEM;
1898	#pragma pack()
1899	/** Pointer to a generic descriptor entry. */
1900	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
1901	/** Pointer to a const generic descriptor entry. */
1902	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
1903
1904
1905	/**
1906	* Descriptor table entry.
1907	*/
1908	#pragma pack(1)
1909	typedef union X86DESC64
1910	{
1911	/** Generic descriptor view. */
1912	X86DESC64GENERIC Gen;
1913	/** System descriptor view. */
1914	X86DESC64SYSTEM System;
1915	#if 0
1916	X86DESC64GATE Gate;
1917	#endif
1918
1919	/** 8 bit unsigned interger view. */
1920	uint8_t au8[16];
1921	/** 16 bit unsigned interger view. */
1922	uint16_t au16[8];
1923	/** 32 bit unsigned interger view. */
1924	uint32_t au32[4];
1925	/** 64 bit unsigned interger view. */
1926	uint64_t au64[2];
1927	} X86DESC64;
1928	#pragma pack()
1929	/** Pointer to descriptor table entry. */
1930	typedef X86DESC64 *PX86DESC64;
1931	/** Pointer to const descriptor table entry. */
1932	typedef const X86DESC64 *PCX86DESC64;
1933
1934	#if HC_ARCH_BITS == 64
1935	typedef X86DESC64 X86DESCHC;
1936	typedef X86DESC64 *PX86DESCHC;
1937	#else
1938	typedef X86DESC X86DESCHC;
1939	typedef X86DESC *PX86DESCHC;
1940	#endif
1941
1942	/** @name Selector Descriptor Types.
1943	* @{
1944	*/
1945
1946	/** @name Non-System Selector Types.
1947	* @{ */
1948	/** Code(=set)/Data(=clear) bit. */
1949	#define X86_SEL_TYPE_CODE 8
1950	/** Memory(=set)/System(=clear) bit. */
1951	#define X86_SEL_TYPE_MEMORY BIT(4)
1952	/** Accessed bit. */
1953	#define X86_SEL_TYPE_ACCESSED 1
1954	/** Expand down bit (for data selectors only). */
1955	#define X86_SEL_TYPE_DOWN 4
1956	/** Conforming bit (for code selectors only). */
1957	#define X86_SEL_TYPE_CONF 4
1958	/** Write bit (for data selectors only). */
1959	#define X86_SEL_TYPE_WRITE 2
1960	/** Read bit (for code selectors only). */
1961	#define X86_SEL_TYPE_READ 2
1962
1963	/** Read only selector type. */
1964	#define X86_SEL_TYPE_RO 0
1965	/** Accessed read only selector type. */
1966	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
1967	/** Read write selector type. */
1968	#define X86_SEL_TYPE_RW 2
1969	/** Accessed read write selector type. */
1970	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
1971	/** Expand down read only selector type. */
1972	#define X86_SEL_TYPE_RO_DOWN 4
1973	/** Accessed expand down read only selector type. */
1974	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
1975	/** Expand down read write selector type. */
1976	#define X86_SEL_TYPE_RW_DOWN 6
1977	/** Accessed expand down read write selector type. */
1978	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
1979	/** Execute only selector type. */
1980	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
1981	/** Accessed execute only selector type. */
1982	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1983	/** Execute and read selector type. */
1984	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
1985	/** Accessed execute and read selector type. */
1986	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1987	/** Conforming execute only selector type. */
1988	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
1989	/** Accessed Conforming execute only selector type. */
1990	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1991	/** Conforming execute and write selector type. */
1992	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
1993	/** Accessed Conforming execute and write selector type. */
1994	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1995	/** @} */
1996
1997
1998	/** @name System Selector Types.
1999	* @{ */
2000	/** Undefined system selector type. */
2001	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2002	/** 286 TSS selector. */
2003	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2004	/** LDT selector. */
2005	#define X86_SEL_TYPE_SYS_LDT 2
2006	/** 286 TSS selector - Busy. */
2007	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2008	/** 286 Callgate selector. */
2009	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2010	/** Taskgate selector. */
2011	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2012	/** 286 Interrupt gate selector. */
2013	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2014	/** 286 Trapgate selector. */
2015	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2016	/** Undefined system selector. */
2017	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2018	/** 386 TSS selector. */
2019	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2020	/** Undefined system selector. */
2021	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2022	/** 386 TSS selector - Busy. */
2023	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2024	/** 386 Callgate selector. */
2025	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2026	/** Undefined system selector. */
2027	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2028	/** 386 Interruptgate selector. */
2029	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2030	/** 386 Trapgate selector. */
2031	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2032	/** @} */
2033
2034	/** @name AMD64 System Selector Types.
2035	* @{ */
2036	#define AMD64_SEL_TYPE_SYS_LDT 2
2037	/** 286 TSS selector - Busy. */
2038	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2039	/** 386 TSS selector - Busy. */
2040	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2041	/** 386 Callgate selector. */
2042	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2043	/** 386 Interruptgate selector. */
2044	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2045	/** 386 Trapgate selector. */
2046	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2047	/** @} */
2048
2049	/** @} */
2050
2051
2052	/** @name Descriptor Table Entry Flag Masks.
2053	* These are for the 2nd 32-bit word of a descriptor.
2054	* @{ */
2055	/** Bits 8-11 - TYPE - Descriptor type mask. */
2056	#define X86_DESC_TYPE_MASK (BIT(8) \| BIT(9) \| BIT(10) \| BIT(11))
2057	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2058	#define X86_DESC_S BIT(12)
2059	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2060	#define X86_DESC_DPL (BIT(13) \| BIT(14))
2061	/** Bit 15 - P - Present. */
2062	#define X86_DESC_P BIT(15)
2063	/** Bit 20 - AVL - Available for system software. */
2064	#define X86_DESC_AVL BIT(20)
2065	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2066	#define X86_DESC_DB BIT(22)
2067	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2068	* used, if clear byte. */
2069	#define X86_DESC_G BIT(23)
2070	/** @} */
2071
2072	/** @} */
2073
2074
2075	/** @name Selectors.
2076	* @{
2077	*/
2078
2079	/**
2080	* The shift used to convert a selector from and to index an index (C).
2081	*/
2082	#define X86_SEL_SHIFT 3
2083
2084	/**
2085	* The shift used to convert a selector from and to index an index (C).
2086	*/
2087	#define AMD64_SEL_SHIFT 4
2088
2089	#if HC_ARCH_BITS == 64
2090	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2091	#else
2092	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2093	#endif
2094
2095	/**
2096	* The mask used to mask off the table indicator and CPL of an selector.
2097	*/
2098	#define X86_SEL_MASK 0xfff8
2099
2100	/**
2101	* The bit indicating that a selector is in the LDT and not in the GDT.
2102	*/
2103	#define X86_SEL_LDT 0x0004
2104	/**
2105	* The bit mask for getting the RPL of a selector.
2106	*/
2107	#define X86_SEL_RPL 0x0003
2108
2109	/** @} */
2110
2111
2112	/**
2113	* x86 Exceptions/Faults/Traps.
2114	*/
2115	typedef enum X86XCPT
2116	{
2117	/** \#DE - Divide error. */
2118	X86_XCPT_DE = 0x00,
2119	/** \#DB - Debug event (single step, DRx, ..) */
2120	X86_XCPT_DB = 0x01,
2121	/** NMI - Non-Maskable Interrupt */
2122	X86_XCPT_NMI = 0x02,
2123	/** \#BP - Breakpoint (INT3). */
2124	X86_XCPT_BP = 0x03,
2125	/** \#OF - Overflow (INTO). */
2126	X86_XCPT_OF = 0x04,
2127	/** \#BR - Bound range exceeded (BOUND). */
2128	X86_XCPT_BR = 0x05,
2129	/** \#UD - Undefined opcode. */
2130	X86_XCPT_UD = 0x06,
2131	/** \#NM - Device not available (math coprocessor device). */
2132	X86_XCPT_NM = 0x07,
2133	/** \#DF - Double fault. */
2134	X86_XCPT_DF = 0x08,
2135	/** ??? - Coprocessor segment overrun (obsolete). */
2136	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2137	/** \#TS - Taskswitch (TSS). */
2138	X86_XCPT_TS = 0x0a,
2139	/** \#NP - Segment no present. */
2140	X86_XCPT_NP = 0x0b,
2141	/** \#SS - Stack segment fault. */
2142	X86_XCPT_SS = 0x0c,
2143	/** \#GP - General protection fault. */
2144	X86_XCPT_GP = 0x0d,
2145	/** \#PF - Page fault. */
2146	X86_XCPT_PF = 0x0e,
2147	/* 0x0f is reserved. */
2148	/** \#MF - Math fault (FPU). */
2149	X86_XCPT_MF = 0x10,
2150	/** \#AC - Alignment check. */
2151	X86_XCPT_AC = 0x11,
2152	/** \#MC - Machine check. */
2153	X86_XCPT_MC = 0x12,
2154	/** \#XF - SIMD Floating-Pointer Exception. */
2155	X86_XCPT_XF = 0x13
2156	} X86XCPT;
2157	/** Pointer to a x86 exception code. */
2158	typedef X86XCPT *PX86XCPT;
2159	/** Pointer to a const x86 exception code. */
2160	typedef const X86XCPT *PCX86XCPT;
2161
2162
2163	/** @name Trap Error Codes
2164	* @{
2165	*/
2166	/** External indicator. */
2167	#define X86_TRAP_ERR_EXTERNAL 1
2168	/** IDT indicator. */
2169	#define X86_TRAP_ERR_IDT 2
2170	/** Descriptor table indicator - If set LDT, if clear GDT. */
2171	#define X86_TRAP_ERR_TI 4
2172	/** Mask for getting the selector. */
2173	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2174	/** Shift for getting the selector table index (C type index). */
2175	#define X86_TRAP_ERR_SEL_SHIFT 3
2176	/** @} */
2177
2178
2179	/** @name \#PF Trap Error Codes
2180	* @{
2181	*/
2182	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2183	#define X86_TRAP_PF_P BIT(0)
2184	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2185	#define X86_TRAP_PF_RW BIT(1)
2186	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2187	#define X86_TRAP_PF_US BIT(2)
2188	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2189	#define X86_TRAP_PF_RSVD BIT(3)
2190	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2191	#define X86_TRAP_PF_ID BIT(4)
2192	/** @} */
2193
2194	#pragma pack(1)
2195	/**
2196	* 32-bit IDTR/GDTR.
2197	*/
2198	typedef struct X86XDTR32
2199	{
2200	/** Size of the descriptor table. */
2201	uint16_t cb;
2202	/** Address of the descriptor table. */
2203	uint32_t uAddr;
2204	} X86XDTR32, *PX86XDTR32;
2205	#pragma pack()
2206
2207	#pragma pack(1)
2208	/**
2209	* 64-bit IDTR/GDTR.
2210	*/
2211	typedef struct X86XDTR64
2212	{
2213	/** Size of the descriptor table. */
2214	uint16_t cb;
2215	/** Address of the descriptor table. */
2216	uint64_t uAddr;
2217	} X86XDTR64, *PX86XDTR64;
2218	#pragma pack()
2219
2220	/** @} */
2221
2222	#endif
2223

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source: vbox/trunk/include/VBox/x86.h@ 5342

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