VirtualBox

source: vbox/trunk/include/VBox/x86.h@ 13469

Last change on this file since 13469 was 13013, checked in by vboxsync, 16 years ago

infrastructure work for X2APIC support

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1/** @file
2 * X86 (and AMD64) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30/*
31 * x86.mac is generated from this file using:
32 * sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33 */
34
35#ifndef ___VBox_x86_h
36#define ___VBox_x86_h
37
38#include <VBox/types.h>
39
40/* Workaround for Solaris sys/regset.h defining CS, DS */
41#if defined(RT_OS_SOLARIS)
42# undef CS
43# undef DS
44#endif
45
46/** @defgroup grp_x86 x86 Types and Definitions
47 * @{
48 */
49
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105/**
106 * EFLAGS.
107 */
108typedef union X86EFLAGS
109{
110 /** The bitfield view. */
111 X86EFLAGSBITS Bits;
112 /** The 8-bit view. */
113 uint8_t au8[4];
114 /** The 16-bit view. */
115 uint16_t au16[2];
116 /** The 32-bit view. */
117 uint32_t au32[1];
118 /** The 32-bit view. */
119 uint32_t u32;
120 /** The plain unsigned view. */
121 uint32_t u;
122} X86EFLAGS;
123/** Pointer to EFLAGS. */
124typedef X86EFLAGS *PX86EFLAGS;
125/** Pointer to const EFLAGS. */
126typedef const X86EFLAGS *PCX86EFLAGS;
127
128/**
129 * RFLAGS (32 upper bits are reserved).
130 */
131typedef union X86RFLAGS
132{
133 /** The bitfield view. */
134 X86EFLAGSBITS Bits;
135 /** The 8-bit view. */
136 uint8_t au8[8];
137 /** The 16-bit view. */
138 uint16_t au16[4];
139 /** The 32-bit view. */
140 uint32_t au32[2];
141 /** The 64-bit view. */
142 uint64_t au64[1];
143 /** The 64-bit view. */
144 uint64_t u64;
145 /** The plain unsigned view. */
146 uint64_t u;
147} X86RFLAGS;
148/** Pointer to RFLAGS. */
149typedef X86RFLAGS *PX86RFLAGS;
150/** Pointer to const RFLAGS. */
151typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154/** @name EFLAGS
155 * @{
156 */
157/** Bit 0 - CF - Carry flag - Status flag. */
158#define X86_EFL_CF RT_BIT(0)
159/** Bit 2 - PF - Parity flag - Status flag. */
160#define X86_EFL_PF RT_BIT(2)
161/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162#define X86_EFL_AF RT_BIT(4)
163/** Bit 6 - ZF - Zero flag - Status flag. */
164#define X86_EFL_ZF RT_BIT(6)
165/** Bit 7 - SF - Signed flag - Status flag. */
166#define X86_EFL_SF RT_BIT(7)
167/** Bit 8 - TF - Trap flag - System flag. */
168#define X86_EFL_TF RT_BIT(8)
169/** Bit 9 - IF - Interrupt flag - System flag. */
170#define X86_EFL_IF RT_BIT(9)
171/** Bit 10 - DF - Direction flag - Control flag. */
172#define X86_EFL_DF RT_BIT(10)
173/** Bit 11 - OF - Overflow flag - Status flag. */
174#define X86_EFL_OF RT_BIT(11)
175/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
177/** Bit 14 - NT - Nested task flag - System flag. */
178#define X86_EFL_NT RT_BIT(14)
179/** Bit 16 - RF - Resume flag - System flag. */
180#define X86_EFL_RF RT_BIT(16)
181/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182#define X86_EFL_VM RT_BIT(17)
183/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184#define X86_EFL_AC RT_BIT(18)
185/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186#define X86_EFL_VIF RT_BIT(19)
187/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188#define X86_EFL_VIP RT_BIT(20)
189/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190#define X86_EFL_ID RT_BIT(21)
191/** IOPL shift. */
192#define X86_EFL_IOPL_SHIFT 12
193/** The the IOPL level from the flags. */
194#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195/** @} */
196
197
198/** CPUID Feature information - ECX.
199 * CPUID query with EAX=1.
200 */
201typedef struct X86CPUIDFEATECX
202{
203 /** Bit 0 - SSE3 - Supports SSE3 or not. */
204 unsigned u1SSE3 : 1;
205 /** Reserved. */
206 unsigned u2Reserved1 : 2;
207 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208 unsigned u1Monitor : 1;
209 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210 unsigned u1CPLDS : 1;
211 /** Bit 5 - VMX - Virtual Machine Technology. */
212 unsigned u1VMX : 1;
213 /** Reserved. */
214 unsigned u1Reserved2 : 1;
215 /** Bit 7 - EST - Enh. SpeedStep Tech. */
216 unsigned u1EST : 1;
217 /** Bit 8 - TM2 - Terminal Monitor 2. */
218 unsigned u1TM2 : 1;
219 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220 unsigned u1SSSE3 : 1;
221 /** Bit 10 - CNTX-ID - L1 Context ID. */
222 unsigned u1CNTXID : 1;
223 /** Reserved. */
224 unsigned u2Reserved4 : 2;
225 /** Bit 13 - CX16 - CMPXCHG16B. */
226 unsigned u1CX16 : 1;
227 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228 unsigned u1TPRUpdate : 1;
229 /** Reserved. */
230 unsigned u17Reserved5 : 17;
231
232} X86CPUIDFEATECX;
233/** Pointer to CPUID Feature Information - ECX. */
234typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235/** Pointer to const CPUID Feature Information - ECX. */
236typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239/** CPUID Feature Information - EDX.
240 * CPUID query with EAX=1.
241 */
242typedef struct X86CPUIDFEATEDX
243{
244 /** Bit 0 - FPU - x87 FPU on Chip. */
245 unsigned u1FPU : 1;
246 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247 unsigned u1VME : 1;
248 /** Bit 2 - DE - Debugging extensions. */
249 unsigned u1DE : 1;
250 /** Bit 3 - PSE - Page Size Extension. */
251 unsigned u1PSE : 1;
252 /** Bit 4 - TSC - Time Stamp Counter. */
253 unsigned u1TSC : 1;
254 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255 unsigned u1MSR : 1;
256 /** Bit 6 - PAE - Physical Address Extension. */
257 unsigned u1PAE : 1;
258 /** Bit 7 - MCE - Machine Check Exception. */
259 unsigned u1MCE : 1;
260 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
261 unsigned u1CX8 : 1;
262 /** Bit 9 - APIC - APIC On-Chip. */
263 unsigned u1APIC : 1;
264 /** Bit 10 - Reserved. */
265 unsigned u1Reserved1 : 1;
266 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267 unsigned u1SEP : 1;
268 /** Bit 12 - MTRR - Memory Type Range Registers. */
269 unsigned u1MTRR : 1;
270 /** Bit 13 - PGE - PTE Global Bit. */
271 unsigned u1PGE : 1;
272 /** Bit 14 - MCA - Machine Check Architecture. */
273 unsigned u1MCA : 1;
274 /** Bit 15 - CMOV - Conditional Move Instructions. */
275 unsigned u1CMOV : 1;
276 /** Bit 16 - PAT - Page Attribute Table. */
277 unsigned u1PAT : 1;
278 /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279 unsigned u1PSE36 : 1;
280 /** Bit 18 - PSN - Processor Serial Number. */
281 unsigned u1PSN : 1;
282 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
283 unsigned u1CLFSH : 1;
284 /** Bit 20 - Reserved. */
285 unsigned u1Reserved2 : 1;
286 /** Bit 21 - DS - Debug Store. */
287 unsigned u1DS : 1;
288 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289 unsigned u1ACPI : 1;
290 /** Bit 23 - MMX - Intel MMX 'Technology'. */
291 unsigned u1MMX : 1;
292 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293 unsigned u1FXSR : 1;
294 /** Bit 25 - SSE - SSE Support. */
295 unsigned u1SSE : 1;
296 /** Bit 26 - SSE2 - SSE2 Support. */
297 unsigned u1SSE2 : 1;
298 /** Bit 27 - SS - Self Snoop. */
299 unsigned u1SS : 1;
300 /** Bit 28 - HTT - Hyper-Threading Technology. */
301 unsigned u1HTT : 1;
302 /** Bit 29 - TM - Thermal Monitor. */
303 unsigned u1TM : 1;
304 /** Bit 30 - Reserved - . */
305 unsigned u1Reserved3 : 1;
306 /** Bit 31 - PBE - Pending Break Enabled. */
307 unsigned u1PBE : 1;
308} X86CPUIDFEATEDX;
309/** Pointer to CPUID Feature Information - EDX. */
310typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311/** Pointer to const CPUID Feature Information - EDX. */
312typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314/** @name CPUID Vendor information.
315 * CPUID query with EAX=0.
316 * @{
317 */
318#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325/** @} */
326
327
328/** @name CPUID Feature information.
329 * CPUID query with EAX=1.
330 * @{
331 */
332/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352/** ECX Bit 21 - x2APIC support. */
353#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
354/** ECX Bit 23 - POPCOUNT instruction. */
355#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
356
357
358/** Bit 0 - FPU - x87 FPU on Chip. */
359#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
360/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
361#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
362/** Bit 2 - DE - Debugging extensions. */
363#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
364/** Bit 3 - PSE - Page Size Extension. */
365#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
366/** Bit 4 - TSC - Time Stamp Counter. */
367#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
368/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
369#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
370/** Bit 6 - PAE - Physical Address Extension. */
371#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
372/** Bit 7 - MCE - Machine Check Exception. */
373#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
374/** Bit 8 - CX8 - CMPXCHG8B instruction. */
375#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
376/** Bit 9 - APIC - APIC On-Chip. */
377#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
378/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
379#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
380/** Bit 12 - MTRR - Memory Type Range Registers. */
381#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
382/** Bit 13 - PGE - PTE Global Bit. */
383#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
384/** Bit 14 - MCA - Machine Check Architecture. */
385#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
386/** Bit 15 - CMOV - Conditional Move Instructions. */
387#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
388/** Bit 16 - PAT - Page Attribute Table. */
389#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
390/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
391#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
392/** Bit 18 - PSN - Processor Serial Number. */
393#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
394/** Bit 19 - CLFSH - CLFLUSH Instruction. */
395#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
396/** Bit 21 - DS - Debug Store. */
397#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
398/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
399#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
400/** Bit 23 - MMX - Intel MMX Technology. */
401#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
402/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
403#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
404/** Bit 25 - SSE - SSE Support. */
405#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
406/** Bit 26 - SSE2 - SSE2 Support. */
407#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
408/** Bit 27 - SS - Self Snoop. */
409#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
410/** Bit 28 - HTT - Hyper-Threading Technology. */
411#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
412/** Bit 29 - TM - Therm. Monitor. */
413#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
414/** Bit 31 - PBE - Pending Break Enabled. */
415#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
416/** @} */
417
418
419/** @name CPUID AMD Feature information.
420 * CPUID query with EAX=0x80000001.
421 * @{
422 */
423/** Bit 0 - FPU - x87 FPU on Chip. */
424#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
425/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
426#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
427/** Bit 2 - DE - Debugging extensions. */
428#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
429/** Bit 3 - PSE - Page Size Extension. */
430#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
431/** Bit 4 - TSC - Time Stamp Counter. */
432#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
433/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
434#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
435/** Bit 6 - PAE - Physical Address Extension. */
436#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
437/** Bit 7 - MCE - Machine Check Exception. */
438#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
439/** Bit 8 - CX8 - CMPXCHG8B instruction. */
440#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
441/** Bit 9 - APIC - APIC On-Chip. */
442#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
443/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
444#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
445/** Bit 12 - MTRR - Memory Type Range Registers. */
446#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
447/** Bit 13 - PGE - PTE Global Bit. */
448#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
449/** Bit 14 - MCA - Machine Check Architecture. */
450#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
451/** Bit 15 - CMOV - Conditional Move Instructions. */
452#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
453/** Bit 16 - PAT - Page Attribute Table. */
454#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
455/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
456#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
457/** Bit 20 - NX - AMD No-Execute Page Protection. */
458#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
459/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
460#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
461/** Bit 23 - MMX - Intel MMX Technology. */
462#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
463/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
464#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
465/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
466#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
467/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
468#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
469/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
470#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
471/** Bit 29 - LM - AMD Long Mode. */
472#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
473/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
474#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
475/** Bit 31 - 3DNOW - AMD 3DNow. */
476#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
477
478/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
479#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
480/** Bit 1 - CMPL - Core multi-processing legacy mode. */
481#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
482/** Bit 2 - SVM - AMD VM extensions. */
483#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
484/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
485#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
486/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
487#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
488/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
489#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
490/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
491#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
492/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
493#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
494/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
495#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
496/** Bit 9 - OSVW - AMD OS visible workaround. */
497#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
498/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
499#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
500/** Bit 13 - WDT - AMD Watchdog timer support. */
501#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
502
503/** @} */
504
505
506/** @name CPUID AMD Feature information.
507 * CPUID query with EAX=0x80000007.
508 * @{
509 */
510/** Bit 0 - TS - Temperature Sensor. */
511#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
512/** Bit 1 - FID - Frequency ID Control. */
513#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
514/** Bit 2 - VID - Voltage ID Control. */
515#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
516/** Bit 3 - TTP - THERMTRIP. */
517#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
518/** Bit 4 - TM - Hardware Thermal Control. */
519#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
520/** Bit 5 - STC - Software Thermal Control. */
521#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
522/** Bit 6 - MC - 100 Mhz Multiplier Control. */
523#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
524/** Bit 7 - HWPSTATE - Hardware P-State Control. */
525#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
526/** Bit 8 - TSCINVAR - TSC Invariant. */
527#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
528/** @} */
529
530
531/** @name CR0
532 * @{ */
533/** Bit 0 - PE - Protection Enabled */
534#define X86_CR0_PE RT_BIT(0)
535#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
536/** Bit 1 - MP - Monitor Coprocessor */
537#define X86_CR0_MP RT_BIT(1)
538#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
539/** Bit 2 - EM - Emulation. */
540#define X86_CR0_EM RT_BIT(2)
541#define X86_CR0_EMULATE_FPU RT_BIT(2)
542/** Bit 3 - TS - Task Switch. */
543#define X86_CR0_TS RT_BIT(3)
544#define X86_CR0_TASK_SWITCH RT_BIT(3)
545/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
546#define X86_CR0_ET RT_BIT(4)
547#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
548/** Bit 5 - NE - Numeric error. */
549#define X86_CR0_NE RT_BIT(5)
550#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
551/** Bit 16 - WP - Write Protect. */
552#define X86_CR0_WP RT_BIT(16)
553#define X86_CR0_WRITE_PROTECT RT_BIT(16)
554/** Bit 18 - AM - Alignment Mask. */
555#define X86_CR0_AM RT_BIT(18)
556#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
557/** Bit 29 - NW - Not Write-though. */
558#define X86_CR0_NW RT_BIT(29)
559#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
560/** Bit 30 - WP - Cache Disable. */
561#define X86_CR0_CD RT_BIT(30)
562#define X86_CR0_CACHE_DISABLE RT_BIT(30)
563/** Bit 31 - PG - Paging. */
564#define X86_CR0_PG RT_BIT(31)
565#define X86_CR0_PAGING RT_BIT(31)
566/** @} */
567
568
569/** @name CR3
570 * @{ */
571/** Bit 3 - PWT - Page-level Writes Transparent. */
572#define X86_CR3_PWT RT_BIT(3)
573/** Bit 4 - PCD - Page-level Cache Disable. */
574#define X86_CR3_PCD RT_BIT(4)
575/** Bits 12-31 - - Page directory page number. */
576#define X86_CR3_PAGE_MASK (0xfffff000)
577/** Bits 5-31 - - PAE Page directory page number. */
578#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
579/** Bits 12-51 - - AMD64 Page directory page number. */
580#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
581/** @} */
582
583
584/** @name CR4
585 * @{ */
586/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
587#define X86_CR4_VME RT_BIT(0)
588/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
589#define X86_CR4_PVI RT_BIT(1)
590/** Bit 2 - TSD - Time Stamp Disable. */
591#define X86_CR4_TSD RT_BIT(2)
592/** Bit 3 - DE - Debugging Extensions. */
593#define X86_CR4_DE RT_BIT(3)
594/** Bit 4 - PSE - Page Size Extension. */
595#define X86_CR4_PSE RT_BIT(4)
596/** Bit 5 - PAE - Physical Address Extension. */
597#define X86_CR4_PAE RT_BIT(5)
598/** Bit 6 - MCE - Machine-Check Enable. */
599#define X86_CR4_MCE RT_BIT(6)
600/** Bit 7 - PGE - Page Global Enable. */
601#define X86_CR4_PGE RT_BIT(7)
602/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
603#define X86_CR4_PCE RT_BIT(8)
604/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
605#define X86_CR4_OSFSXR RT_BIT(9)
606/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
607#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
608/** Bit 13 - VMXE - VMX mode is enabled. */
609#define X86_CR4_VMXE RT_BIT(13)
610/** @} */
611
612
613/** @name DR6
614 * @{ */
615/** Bit 0 - B0 - Breakpoint 0 condition detected. */
616#define X86_DR6_B0 RT_BIT(0)
617/** Bit 1 - B1 - Breakpoint 1 condition detected. */
618#define X86_DR6_B1 RT_BIT(1)
619/** Bit 2 - B2 - Breakpoint 2 condition detected. */
620#define X86_DR6_B2 RT_BIT(2)
621/** Bit 3 - B3 - Breakpoint 3 condition detected. */
622#define X86_DR6_B3 RT_BIT(3)
623/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
624#define X86_DR6_BD RT_BIT(13)
625/** Bit 14 - BS - Single step */
626#define X86_DR6_BS RT_BIT(14)
627/** Bit 15 - BT - Task switch. (TSS T bit.) */
628#define X86_DR6_BT RT_BIT(15)
629/** Value of DR6 after powerup/reset. */
630#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
631/** @} */
632
633
634/** @name DR7
635 * @{ */
636/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
637#define X86_DR7_L0 RT_BIT(0)
638/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
639#define X86_DR7_G0 RT_BIT(1)
640/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
641#define X86_DR7_L1 RT_BIT(2)
642/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
643#define X86_DR7_G1 RT_BIT(3)
644/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
645#define X86_DR7_L2 RT_BIT(4)
646/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
647#define X86_DR7_G2 RT_BIT(5)
648/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
649#define X86_DR7_L3 RT_BIT(6)
650/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
651#define X86_DR7_G3 RT_BIT(7)
652/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
653#define X86_DR7_LE RT_BIT(8)
654/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
655#define X86_DR7_GE RT_BIT(9)
656
657/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
658 * any DR register is accessed. */
659#define X86_DR7_GD RT_BIT(13)
660/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
661#define X86_DR7_RW0_MASK (3 << 16)
662/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
663#define X86_DR7_LEN0_MASK (3 << 18)
664/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
665#define X86_DR7_RW1_MASK (3 << 20)
666/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
667#define X86_DR7_LEN1_MASK (3 << 22)
668/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
669#define X86_DR7_RW2_MASK (3 << 24)
670/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
671#define X86_DR7_LEN2_MASK (3 << 26)
672/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
673#define X86_DR7_RW3_MASK (3 << 28)
674/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
675#define X86_DR7_LEN3_MASK (3 << 30)
676
677/** Bits which must be 1s. */
678#define X86_DR7_MB1_MASK (RT_BIT(10))
679
680/** Calcs the L bit of Nth breakpoint.
681 * @param iBp The breakpoint number [0..3].
682 */
683#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
684
685/** Calcs the G bit of Nth breakpoint.
686 * @param iBp The breakpoint number [0..3].
687 */
688#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
689
690/** @name Read/Write values.
691 * @{ */
692/** Break on instruction fetch only. */
693#define X86_DR7_RW_EO 0U
694/** Break on write only. */
695#define X86_DR7_RW_WO 1U
696/** Break on I/O read/write. This is only defined if CR4.DE is set. */
697#define X86_DR7_RW_IO 2U
698/** Break on read or write (but not instruction fetches). */
699#define X86_DR7_RW_RW 3U
700/** @} */
701
702/** Shifts a X86_DR7_RW_* value to its right place.
703 * @param iBp The breakpoint number [0..3].
704 * @param fRw One of the X86_DR7_RW_* value.
705 */
706#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
707
708/** @name Length values.
709 * @{ */
710#define X86_DR7_LEN_BYTE 0U
711#define X86_DR7_LEN_WORD 1U
712#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
713#define X86_DR7_LEN_DWORD 3U
714/** @} */
715
716/** Shifts a X86_DR7_LEN_* value to its right place.
717 * @param iBp The breakpoint number [0..3].
718 * @param cb One of the X86_DR7_LEN_* values.
719 */
720#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
721
722/** Fetch the breakpoint length bits from the DR7 value.
723 * @param uDR7 DR7 value
724 * @param iBp The breakpoint number [0..3].
725 */
726#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
727
728/** Mask used to check if any breakpoints are enabled. */
729#define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
730
731/** Mask used to check if any io breakpoints are set. */
732#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
733
734/** Value of DR7 after powerup/reset. */
735#define X86_DR7_INIT_VAL 0x400
736/** @} */
737
738
739/** @name Machine Specific Registers
740 * @{
741 */
742
743/** Time Stamp Counter. */
744#define MSR_IA32_TSC 0x10
745
746#define MSR_IA32_PLATFORM_ID 0x17
747
748#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
749#define MSR_IA32_APICBASE 0x1b
750#endif
751
752/** CPU Feature control. */
753#define MSR_IA32_FEATURE_CONTROL 0x3A
754#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
755#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
756
757/** BIOS update trigger (microcode update). */
758#define MSR_IA32_BIOS_UPDT_TRIG 0x79
759
760/** BIOS update signature (microcode). */
761#define MSR_IA32_BIOS_SIGN_ID 0x8B
762
763/** MTRR Capabilities. */
764#define MSR_IA32_MTRR_CAP 0xFE
765
766
767#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
768/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
769 * R0 SS == CS + 8
770 * R3 CS == CS + 16
771 * R3 SS == CS + 24
772 */
773#define MSR_IA32_SYSENTER_CS 0x174
774/** SYSENTER_ESP - the R0 ESP. */
775#define MSR_IA32_SYSENTER_ESP 0x175
776/** SYSENTER_EIP - the R0 EIP. */
777#define MSR_IA32_SYSENTER_EIP 0x176
778#endif
779
780/** Machine Check Global Capabilities Register. */
781#define MSR_IA32_MCP_CAP 0x179
782/** Machine Check Global Status Register. */
783#define MSR_IA32_MCP_STATUS 0x17A
784/** Machine Check Global Control Register. */
785#define MSR_IA32_MCP_CTRL 0x17B
786
787/* Page Attribute Table. */
788#define MSR_IA32_CR_PAT 0x277
789
790/** MTRR Default Range. */
791#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
792
793#define MSR_IA32_MC0_CTL 0x400
794#define MSR_IA32_MC0_STATUS 0x401
795
796/** Basic VMX information. */
797#define MSR_IA32_VMX_BASIC_INFO 0x480
798/** Allowed settings for pin-based VM execution controls */
799#define MSR_IA32_VMX_PINBASED_CTLS 0x481
800/** Allowed settings for proc-based VM execution controls */
801#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
802/** Allowed settings for the VMX exit controls. */
803#define MSR_IA32_VMX_EXIT_CTLS 0x483
804/** Allowed settings for the VMX entry controls. */
805#define MSR_IA32_VMX_ENTRY_CTLS 0x484
806/** Misc VMX info. */
807#define MSR_IA32_VMX_MISC 0x485
808/** Fixed cleared bits in CR0. */
809#define MSR_IA32_VMX_CR0_FIXED0 0x486
810/** Fixed set bits in CR0. */
811#define MSR_IA32_VMX_CR0_FIXED1 0x487
812/** Fixed cleared bits in CR4. */
813#define MSR_IA32_VMX_CR4_FIXED0 0x488
814/** Fixed set bits in CR4. */
815#define MSR_IA32_VMX_CR4_FIXED1 0x489
816/** Information for enumerating fields in the VMCS. */
817#define MSR_IA32_VMX_VMCS_ENUM 0x48A
818/** Allowed settings for secondary proc-based VM execution controls */
819#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
820/** EPT capabilities. */
821#define MSR_IA32_VMX_EPT_CAPS 0x48C
822/** X2APIC MSR ranges. */
823#define MSR_IA32_APIC_START 0x800
824#define MSR_IA32_APIC_END 0x900
825
826/** K6 EFER - Extended Feature Enable Register. */
827#define MSR_K6_EFER 0xc0000080
828/** @todo document EFER */
829/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
830#define MSR_K6_EFER_SCE RT_BIT(0)
831/** Bit 8 - LME - Long mode enabled. (R/W) */
832#define MSR_K6_EFER_LME RT_BIT(8)
833/** Bit 10 - LMA - Long mode active. (R) */
834#define MSR_K6_EFER_LMA RT_BIT(10)
835/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
836#define MSR_K6_EFER_NXE RT_BIT(11)
837/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
838#define MSR_K6_EFER_SVME RT_BIT(12)
839/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
840#define MSR_K6_EFER_LMSLE RT_BIT(13)
841/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
842#define MSR_K6_EFER_FFXSR RT_BIT(14)
843/** K6 STAR - SYSCALL/RET targets. */
844#define MSR_K6_STAR 0xc0000081
845/** Shift value for getting the SYSRET CS and SS value. */
846#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
847/** Shift value for getting the SYSCALL CS and SS value. */
848#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
849/** Selector mask for use after shifting. */
850#define MSR_K6_STAR_SEL_MASK 0xffff
851/** The mask which give the SYSCALL EIP. */
852#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
853/** K6 WHCR - Write Handling Control Register. */
854#define MSR_K6_WHCR 0xc0000082
855/** K6 UWCCR - UC/WC Cacheability Control Register. */
856#define MSR_K6_UWCCR 0xc0000085
857/** K6 PSOR - Processor State Observability Register. */
858#define MSR_K6_PSOR 0xc0000087
859/** K6 PFIR - Page Flush/Invalidate Register. */
860#define MSR_K6_PFIR 0xc0000088
861
862#define MSR_K7_EVNTSEL0 0xc0010000
863#define MSR_K7_EVNTSEL1 0xc0010001
864#define MSR_K7_EVNTSEL2 0xc0010002
865#define MSR_K7_EVNTSEL3 0xc0010003
866#define MSR_K7_PERFCTR0 0xc0010004
867#define MSR_K7_PERFCTR1 0xc0010005
868#define MSR_K7_PERFCTR2 0xc0010006
869#define MSR_K7_PERFCTR3 0xc0010007
870
871/** K8 LSTAR - Long mode SYSCALL target (RIP). */
872#define MSR_K8_LSTAR 0xc0000082
873/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
874#define MSR_K8_CSTAR 0xc0000083
875/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
876#define MSR_K8_SF_MASK 0xc0000084
877/** K8 FS.base - The 64-bit base FS register. */
878#define MSR_K8_FS_BASE 0xc0000100
879/** K8 GS.base - The 64-bit base GS register. */
880#define MSR_K8_GS_BASE 0xc0000101
881/** K8 KernelGSbase - Used with SWAPGS. */
882#define MSR_K8_KERNEL_GS_BASE 0xc0000102
883#define MSR_K8_TSC_AUX 0xc0000103
884#define MSR_K8_SYSCFG 0xc0010010
885#define MSR_K8_HWCR 0xc0010015
886#define MSR_K8_IORRBASE0 0xc0010016
887#define MSR_K8_IORRMASK0 0xc0010017
888#define MSR_K8_IORRBASE1 0xc0010018
889#define MSR_K8_IORRMASK1 0xc0010019
890#define MSR_K8_TOP_MEM1 0xc001001a
891#define MSR_K8_TOP_MEM2 0xc001001d
892#define MSR_K8_VM_CR 0xc0010114
893#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
894
895#define MSR_K8_IGNNE 0xc0010115
896#define MSR_K8_SMM_CTL 0xc0010116
897/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
898 * host state during world switch.
899 */
900#define MSR_K8_VM_HSAVE_PA 0xc0010117
901
902/** @} */
903
904
905/** @name Page Table / Directory / Directory Pointers / L4.
906 * @{
907 */
908
909/** Page table/directory entry as an unsigned integer. */
910typedef uint32_t X86PGUINT;
911/** Pointer to a page table/directory table entry as an unsigned integer. */
912typedef X86PGUINT *PX86PGUINT;
913
914/** Number of entries in a 32-bit PT/PD. */
915#define X86_PG_ENTRIES 1024
916
917
918/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
919typedef uint64_t X86PGPAEUINT;
920/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
921typedef X86PGPAEUINT *PX86PGPAEUINT;
922
923/** Number of entries in a PAE PT/PD. */
924#define X86_PG_PAE_ENTRIES 512
925/** Number of entries in a PAE PDPT. */
926#define X86_PG_PAE_PDPE_ENTRIES 4
927
928/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
929#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
930/** Number of entries in an AMD64 PDPT.
931 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
932#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
933
934/** The size of a 4KB page. */
935#define X86_PAGE_4K_SIZE _4K
936/** The page shift of a 4KB page. */
937#define X86_PAGE_4K_SHIFT 12
938/** The 4KB page offset mask. */
939#define X86_PAGE_4K_OFFSET_MASK 0xfff
940/** The 4KB page base mask for virtual addresses. */
941#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
942/** The 4KB page base mask for virtual addresses - 32bit version. */
943#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
944
945/** The size of a 2MB page. */
946#define X86_PAGE_2M_SIZE _2M
947/** The page shift of a 2MB page. */
948#define X86_PAGE_2M_SHIFT 21
949/** The 2MB page offset mask. */
950#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
951/** The 2MB page base mask for virtual addresses. */
952#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
953/** The 2MB page base mask for virtual addresses - 32bit version. */
954#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
955
956/** The size of a 4MB page. */
957#define X86_PAGE_4M_SIZE _4M
958/** The page shift of a 4MB page. */
959#define X86_PAGE_4M_SHIFT 22
960/** The 4MB page offset mask. */
961#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
962/** The 4MB page base mask for virtual addresses. */
963#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
964/** The 4MB page base mask for virtual addresses - 32bit version. */
965#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
966
967
968
969/** @name Page Table Entry
970 * @{
971 */
972/** Bit 0 - P - Present bit. */
973#define X86_PTE_P RT_BIT(0)
974/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
975#define X86_PTE_RW RT_BIT(1)
976/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
977#define X86_PTE_US RT_BIT(2)
978/** Bit 3 - PWT - Page level write thru bit. */
979#define X86_PTE_PWT RT_BIT(3)
980/** Bit 4 - PCD - Page level cache disable bit. */
981#define X86_PTE_PCD RT_BIT(4)
982/** Bit 5 - A - Access bit. */
983#define X86_PTE_A RT_BIT(5)
984/** Bit 6 - D - Dirty bit. */
985#define X86_PTE_D RT_BIT(6)
986/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
987#define X86_PTE_PAT RT_BIT(7)
988/** Bit 8 - G - Global flag. */
989#define X86_PTE_G RT_BIT(8)
990/** Bits 9-11 - - Available for use to system software. */
991#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
992/** Bits 12-31 - - Physical Page number of the next level. */
993#define X86_PTE_PG_MASK ( 0xfffff000 )
994
995/** Bits 12-51 - - PAE - Physical Page number of the next level. */
996#if 1 /* we're using this internally and have to mask of the top 16-bit. */
997#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
998/** @todo Get rid of the above hack; makes code unreadable. */
999#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1000#else
1001#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1002#endif
1003/** Bits 63 - NX - PAE - No execution flag. */
1004#define X86_PTE_PAE_NX RT_BIT_64(63)
1005
1006/**
1007 * Page table entry.
1008 */
1009typedef struct X86PTEBITS
1010{
1011 /** Flags whether(=1) or not the page is present. */
1012 unsigned u1Present : 1;
1013 /** Read(=0) / Write(=1) flag. */
1014 unsigned u1Write : 1;
1015 /** User(=1) / Supervisor (=0) flag. */
1016 unsigned u1User : 1;
1017 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1018 unsigned u1WriteThru : 1;
1019 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1020 unsigned u1CacheDisable : 1;
1021 /** Accessed flag.
1022 * Indicates that the page have been read or written to. */
1023 unsigned u1Accessed : 1;
1024 /** Dirty flag.
1025 * Indicates that the page have been written to. */
1026 unsigned u1Dirty : 1;
1027 /** Reserved / If PAT enabled, bit 2 of the index. */
1028 unsigned u1PAT : 1;
1029 /** Global flag. (Ignored in all but final level.) */
1030 unsigned u1Global : 1;
1031 /** Available for use to system software. */
1032 unsigned u3Available : 3;
1033 /** Physical Page number of the next level. */
1034 unsigned u20PageNo : 20;
1035} X86PTEBITS;
1036/** Pointer to a page table entry. */
1037typedef X86PTEBITS *PX86PTEBITS;
1038/** Pointer to a const page table entry. */
1039typedef const X86PTEBITS *PCX86PTEBITS;
1040
1041/**
1042 * Page table entry.
1043 */
1044typedef union X86PTE
1045{
1046 /** Bit field view. */
1047 X86PTEBITS n;
1048 /** Unsigned integer view */
1049 X86PGUINT u;
1050 /** 32-bit view. */
1051 uint32_t au32[1];
1052 /** 16-bit view. */
1053 uint16_t au16[2];
1054 /** 8-bit view. */
1055 uint8_t au8[4];
1056} X86PTE;
1057/** Pointer to a page table entry. */
1058typedef X86PTE *PX86PTE;
1059/** Pointer to a const page table entry. */
1060typedef const X86PTE *PCX86PTE;
1061
1062
1063/**
1064 * PAE page table entry.
1065 */
1066typedef struct X86PTEPAEBITS
1067{
1068 /** Flags whether(=1) or not the page is present. */
1069 uint32_t u1Present : 1;
1070 /** Read(=0) / Write(=1) flag. */
1071 uint32_t u1Write : 1;
1072 /** User(=1) / Supervisor(=0) flag. */
1073 uint32_t u1User : 1;
1074 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1075 uint32_t u1WriteThru : 1;
1076 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1077 uint32_t u1CacheDisable : 1;
1078 /** Accessed flag.
1079 * Indicates that the page have been read or written to. */
1080 uint32_t u1Accessed : 1;
1081 /** Dirty flag.
1082 * Indicates that the page have been written to. */
1083 uint32_t u1Dirty : 1;
1084 /** Reserved / If PAT enabled, bit 2 of the index. */
1085 uint32_t u1PAT : 1;
1086 /** Global flag. (Ignored in all but final level.) */
1087 uint32_t u1Global : 1;
1088 /** Available for use to system software. */
1089 uint32_t u3Available : 3;
1090 /** Physical Page number of the next level - Low Part. Don't use this. */
1091 uint32_t u20PageNoLow : 20;
1092 /** Physical Page number of the next level - High Part. Don't use this. */
1093 uint32_t u20PageNoHigh : 20;
1094 /** MBZ bits */
1095 uint32_t u11Reserved : 11;
1096 /** No Execute flag. */
1097 uint32_t u1NoExecute : 1;
1098} X86PTEPAEBITS;
1099/** Pointer to a page table entry. */
1100typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1101/** Pointer to a page table entry. */
1102typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1103
1104/**
1105 * PAE Page table entry.
1106 */
1107typedef union X86PTEPAE
1108{
1109 /** Bit field view. */
1110 X86PTEPAEBITS n;
1111 /** Unsigned integer view */
1112 X86PGPAEUINT u;
1113 /** 32-bit view. */
1114 uint32_t au32[2];
1115 /** 16-bit view. */
1116 uint16_t au16[4];
1117 /** 8-bit view. */
1118 uint8_t au8[8];
1119} X86PTEPAE;
1120/** Pointer to a PAE page table entry. */
1121typedef X86PTEPAE *PX86PTEPAE;
1122/** Pointer to a const PAE page table entry. */
1123typedef const X86PTEPAE *PCX86PTEPAE;
1124/** @} */
1125
1126/**
1127 * Page table.
1128 */
1129typedef struct X86PT
1130{
1131 /** PTE Array. */
1132 X86PTE a[X86_PG_ENTRIES];
1133} X86PT;
1134/** Pointer to a page table. */
1135typedef X86PT *PX86PT;
1136/** Pointer to a const page table. */
1137typedef const X86PT *PCX86PT;
1138
1139/** The page shift to get the PT index. */
1140#define X86_PT_SHIFT 12
1141/** The PT index mask (apply to a shifted page address). */
1142#define X86_PT_MASK 0x3ff
1143
1144
1145/**
1146 * Page directory.
1147 */
1148typedef struct X86PTPAE
1149{
1150 /** PTE Array. */
1151 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1152} X86PTPAE;
1153/** Pointer to a page table. */
1154typedef X86PTPAE *PX86PTPAE;
1155/** Pointer to a const page table. */
1156typedef const X86PTPAE *PCX86PTPAE;
1157
1158/** The page shift to get the PA PTE index. */
1159#define X86_PT_PAE_SHIFT 12
1160/** The PAE PT index mask (apply to a shifted page address). */
1161#define X86_PT_PAE_MASK 0x1ff
1162
1163
1164/** @name 4KB Page Directory Entry
1165 * @{
1166 */
1167/** Bit 0 - P - Present bit. */
1168#define X86_PDE_P RT_BIT(0)
1169/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1170#define X86_PDE_RW RT_BIT(1)
1171/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1172#define X86_PDE_US RT_BIT(2)
1173/** Bit 3 - PWT - Page level write thru bit. */
1174#define X86_PDE_PWT RT_BIT(3)
1175/** Bit 4 - PCD - Page level cache disable bit. */
1176#define X86_PDE_PCD RT_BIT(4)
1177/** Bit 5 - A - Access bit. */
1178#define X86_PDE_A RT_BIT(5)
1179/** Bit 7 - PS - Page size attribute.
1180 * Clear mean 4KB pages, set means large pages (2/4MB). */
1181#define X86_PDE_PS RT_BIT(7)
1182/** Bits 9-11 - - Available for use to system software. */
1183#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1184/** Bits 12-31 - - Physical Page number of the next level. */
1185#define X86_PDE_PG_MASK ( 0xfffff000 )
1186
1187/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1188#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1189/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1190 * we partly or that part into shadow page table entries. Will be corrected
1191 * soon.
1192 */
1193#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1194#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1195#else
1196#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1197#endif
1198/** Bits 63 - NX - PAE - No execution flag. */
1199#define X86_PDE_PAE_NX RT_BIT_64(63)
1200
1201/**
1202 * Page directory entry.
1203 */
1204typedef struct X86PDEBITS
1205{
1206 /** Flags whether(=1) or not the page is present. */
1207 unsigned u1Present : 1;
1208 /** Read(=0) / Write(=1) flag. */
1209 unsigned u1Write : 1;
1210 /** User(=1) / Supervisor (=0) flag. */
1211 unsigned u1User : 1;
1212 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1213 unsigned u1WriteThru : 1;
1214 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1215 unsigned u1CacheDisable : 1;
1216 /** Accessed flag.
1217 * Indicates that the page have been read or written to. */
1218 unsigned u1Accessed : 1;
1219 /** Reserved / Ignored (dirty bit). */
1220 unsigned u1Reserved0 : 1;
1221 /** Size bit if PSE is enabled - in any event it's 0. */
1222 unsigned u1Size : 1;
1223 /** Reserved / Ignored (global bit). */
1224 unsigned u1Reserved1 : 1;
1225 /** Available for use to system software. */
1226 unsigned u3Available : 3;
1227 /** Physical Page number of the next level. */
1228 unsigned u20PageNo : 20;
1229} X86PDEBITS;
1230/** Pointer to a page directory entry. */
1231typedef X86PDEBITS *PX86PDEBITS;
1232/** Pointer to a const page directory entry. */
1233typedef const X86PDEBITS *PCX86PDEBITS;
1234
1235
1236/**
1237 * PAE page directory entry.
1238 */
1239typedef struct X86PDEPAEBITS
1240{
1241 /** Flags whether(=1) or not the page is present. */
1242 uint32_t u1Present : 1;
1243 /** Read(=0) / Write(=1) flag. */
1244 uint32_t u1Write : 1;
1245 /** User(=1) / Supervisor (=0) flag. */
1246 uint32_t u1User : 1;
1247 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1248 uint32_t u1WriteThru : 1;
1249 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1250 uint32_t u1CacheDisable : 1;
1251 /** Accessed flag.
1252 * Indicates that the page have been read or written to. */
1253 uint32_t u1Accessed : 1;
1254 /** Reserved / Ignored (dirty bit). */
1255 uint32_t u1Reserved0 : 1;
1256 /** Size bit if PSE is enabled - in any event it's 0. */
1257 uint32_t u1Size : 1;
1258 /** Reserved / Ignored (global bit). / */
1259 uint32_t u1Reserved1 : 1;
1260 /** Available for use to system software. */
1261 uint32_t u3Available : 3;
1262 /** Physical Page number of the next level - Low Part. Don't use! */
1263 uint32_t u20PageNoLow : 20;
1264 /** Physical Page number of the next level - High Part. Don't use! */
1265 uint32_t u20PageNoHigh : 20;
1266 /** MBZ bits */
1267 uint32_t u11Reserved : 11;
1268 /** No Execute flag. */
1269 uint32_t u1NoExecute : 1;
1270} X86PDEPAEBITS;
1271/** Pointer to a page directory entry. */
1272typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1273/** Pointer to a const page directory entry. */
1274typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1275
1276/** @} */
1277
1278
1279/** @name 2/4MB Page Directory Entry
1280 * @{
1281 */
1282/** Bit 0 - P - Present bit. */
1283#define X86_PDE4M_P RT_BIT(0)
1284/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1285#define X86_PDE4M_RW RT_BIT(1)
1286/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1287#define X86_PDE4M_US RT_BIT(2)
1288/** Bit 3 - PWT - Page level write thru bit. */
1289#define X86_PDE4M_PWT RT_BIT(3)
1290/** Bit 4 - PCD - Page level cache disable bit. */
1291#define X86_PDE4M_PCD RT_BIT(4)
1292/** Bit 5 - A - Access bit. */
1293#define X86_PDE4M_A RT_BIT(5)
1294/** Bit 6 - D - Dirty bit. */
1295#define X86_PDE4M_D RT_BIT(6)
1296/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1297#define X86_PDE4M_PS RT_BIT(7)
1298/** Bit 8 - G - Global flag. */
1299#define X86_PDE4M_G RT_BIT(8)
1300/** Bits 9-11 - AVL - Available for use to system software. */
1301#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1302/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1303#define X86_PDE4M_PAT RT_BIT(12)
1304/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1305#define X86_PDE4M_PAT_SHIFT (12 - 7)
1306/** Bits 22-31 - - Physical Page number. */
1307#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1308/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1309#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1310/** The number of bits to the high part of the page number. */
1311#define X86_PDE4M_PG_HIGH_SHIFT 19
1312
1313/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1314 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1315#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1316/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1317#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1318
1319/**
1320 * 4MB page directory entry.
1321 */
1322typedef struct X86PDE4MBITS
1323{
1324 /** Flags whether(=1) or not the page is present. */
1325 unsigned u1Present : 1;
1326 /** Read(=0) / Write(=1) flag. */
1327 unsigned u1Write : 1;
1328 /** User(=1) / Supervisor (=0) flag. */
1329 unsigned u1User : 1;
1330 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1331 unsigned u1WriteThru : 1;
1332 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1333 unsigned u1CacheDisable : 1;
1334 /** Accessed flag.
1335 * Indicates that the page have been read or written to. */
1336 unsigned u1Accessed : 1;
1337 /** Dirty flag.
1338 * Indicates that the page have been written to. */
1339 unsigned u1Dirty : 1;
1340 /** Page size flag - always 1 for 4MB entries. */
1341 unsigned u1Size : 1;
1342 /** Global flag. */
1343 unsigned u1Global : 1;
1344 /** Available for use to system software. */
1345 unsigned u3Available : 3;
1346 /** Reserved / If PAT enabled, bit 2 of the index. */
1347 unsigned u1PAT : 1;
1348 /** Bits 32-39 of the page number on AMD64.
1349 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1350 unsigned u8PageNoHigh : 8;
1351 /** Reserved. */
1352 unsigned u1Reserved : 1;
1353 /** Physical Page number of the page. */
1354 unsigned u10PageNo : 10;
1355} X86PDE4MBITS;
1356/** Pointer to a page table entry. */
1357typedef X86PDE4MBITS *PX86PDE4MBITS;
1358/** Pointer to a const page table entry. */
1359typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1360
1361
1362/**
1363 * 2MB PAE page directory entry.
1364 */
1365typedef struct X86PDE2MPAEBITS
1366{
1367 /** Flags whether(=1) or not the page is present. */
1368 uint32_t u1Present : 1;
1369 /** Read(=0) / Write(=1) flag. */
1370 uint32_t u1Write : 1;
1371 /** User(=1) / Supervisor(=0) flag. */
1372 uint32_t u1User : 1;
1373 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1374 uint32_t u1WriteThru : 1;
1375 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1376 uint32_t u1CacheDisable : 1;
1377 /** Accessed flag.
1378 * Indicates that the page have been read or written to. */
1379 uint32_t u1Accessed : 1;
1380 /** Dirty flag.
1381 * Indicates that the page have been written to. */
1382 uint32_t u1Dirty : 1;
1383 /** Page size flag - always 1 for 2MB entries. */
1384 uint32_t u1Size : 1;
1385 /** Global flag. */
1386 uint32_t u1Global : 1;
1387 /** Available for use to system software. */
1388 uint32_t u3Available : 3;
1389 /** Reserved / If PAT enabled, bit 2 of the index. */
1390 uint32_t u1PAT : 1;
1391 /** Reserved. */
1392 uint32_t u9Reserved : 9;
1393 /** Physical Page number of the next level - Low part. Don't use! */
1394 uint32_t u10PageNoLow : 10;
1395 /** Physical Page number of the next level - High part. Don't use! */
1396 uint32_t u20PageNoHigh : 20;
1397 /** MBZ bits */
1398 uint32_t u11Reserved : 11;
1399 /** No Execute flag. */
1400 uint32_t u1NoExecute : 1;
1401} X86PDE2MPAEBITS;
1402/** Pointer to a 4MB PAE page table entry. */
1403typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1404/** Pointer to a 4MB PAE page table entry. */
1405typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1406
1407/** @} */
1408
1409/**
1410 * Page directory entry.
1411 */
1412typedef union X86PDE
1413{
1414 /** Normal view. */
1415 X86PDEBITS n;
1416 /** 4MB view (big). */
1417 X86PDE4MBITS b;
1418 /** Unsigned integer view. */
1419 X86PGUINT u;
1420 /** 8 bit unsigned integer view. */
1421 uint8_t au8[4];
1422 /** 16 bit unsigned integer view. */
1423 uint16_t au16[2];
1424 /** 32 bit unsigned integer view. */
1425 uint32_t au32[1];
1426} X86PDE;
1427/** Pointer to a page directory entry. */
1428typedef X86PDE *PX86PDE;
1429/** Pointer to a const page directory entry. */
1430typedef const X86PDE *PCX86PDE;
1431
1432/**
1433 * PAE page directory entry.
1434 */
1435typedef union X86PDEPAE
1436{
1437 /** Normal view. */
1438 X86PDEPAEBITS n;
1439 /** 2MB page view (big). */
1440 X86PDE2MPAEBITS b;
1441 /** Unsigned integer view. */
1442 X86PGPAEUINT u;
1443 /** 8 bit unsigned integer view. */
1444 uint8_t au8[8];
1445 /** 16 bit unsigned integer view. */
1446 uint16_t au16[4];
1447 /** 32 bit unsigned integer view. */
1448 uint32_t au32[2];
1449} X86PDEPAE;
1450/** Pointer to a page directory entry. */
1451typedef X86PDEPAE *PX86PDEPAE;
1452/** Pointer to a const page directory entry. */
1453typedef const X86PDEPAE *PCX86PDEPAE;
1454
1455/**
1456 * Page directory.
1457 */
1458typedef struct X86PD
1459{
1460 /** PDE Array. */
1461 X86PDE a[X86_PG_ENTRIES];
1462} X86PD;
1463/** Pointer to a page directory. */
1464typedef X86PD *PX86PD;
1465/** Pointer to a const page directory. */
1466typedef const X86PD *PCX86PD;
1467
1468/** The page shift to get the PD index. */
1469#define X86_PD_SHIFT 22
1470/** The PD index mask (apply to a shifted page address). */
1471#define X86_PD_MASK 0x3ff
1472
1473
1474/**
1475 * PAE page directory.
1476 */
1477typedef struct X86PDPAE
1478{
1479 /** PDE Array. */
1480 X86PDEPAE a[X86_PG_PAE_ENTRIES];
1481} X86PDPAE;
1482/** Pointer to a PAE page directory. */
1483typedef X86PDPAE *PX86PDPAE;
1484/** Pointer to a const PAE page directory. */
1485typedef const X86PDPAE *PCX86PDPAE;
1486
1487/** The page shift to get the PAE PD index. */
1488#define X86_PD_PAE_SHIFT 21
1489/** The PAE PD index mask (apply to a shifted page address). */
1490#define X86_PD_PAE_MASK 0x1ff
1491
1492
1493/** @name Page Directory Pointer Table Entry (PAE)
1494 * @{
1495 */
1496/** Bit 0 - P - Present bit. */
1497#define X86_PDPE_P RT_BIT(0)
1498/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1499#define X86_PDPE_RW RT_BIT(1)
1500/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1501#define X86_PDPE_US RT_BIT(2)
1502/** Bit 3 - PWT - Page level write thru bit. */
1503#define X86_PDPE_PWT RT_BIT(3)
1504/** Bit 4 - PCD - Page level cache disable bit. */
1505#define X86_PDPE_PCD RT_BIT(4)
1506/** Bit 5 - A - Access bit. Long Mode only. */
1507#define X86_PDPE_A RT_BIT(5)
1508/** Bits 9-11 - - Available for use to system software. */
1509#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1510/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1511#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1512#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1513/** @todo Get rid of the above hack; makes code unreadable. */
1514#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1515#else
1516#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1517#endif
1518/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1519#define X86_PDPE_NX RT_BIT_64(63)
1520
1521/**
1522 * Page directory pointer table entry.
1523 */
1524typedef struct X86PDPEBITS
1525{
1526 /** Flags whether(=1) or not the page is present. */
1527 uint32_t u1Present : 1;
1528 /** Chunk of reserved bits. */
1529 uint32_t u2Reserved : 2;
1530 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1531 uint32_t u1WriteThru : 1;
1532 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1533 uint32_t u1CacheDisable : 1;
1534 /** Chunk of reserved bits. */
1535 uint32_t u4Reserved : 4;
1536 /** Available for use to system software. */
1537 uint32_t u3Available : 3;
1538 /** Physical Page number of the next level - Low Part. Don't use! */
1539 uint32_t u20PageNoLow : 20;
1540 /** Physical Page number of the next level - High Part. Don't use! */
1541 uint32_t u20PageNoHigh : 20;
1542 /** MBZ bits */
1543 uint32_t u12Reserved : 12;
1544} X86PDPEBITS;
1545/** Pointer to a page directory pointer table entry. */
1546typedef X86PDPEBITS *PX86PTPEBITS;
1547/** Pointer to a const page directory pointer table entry. */
1548typedef const X86PDPEBITS *PCX86PTPEBITS;
1549
1550/**
1551 * Page directory pointer table entry. AMD64 version
1552 */
1553typedef struct X86PDPEAMD64BITS
1554{
1555 /** Flags whether(=1) or not the page is present. */
1556 uint32_t u1Present : 1;
1557 /** Read(=0) / Write(=1) flag. */
1558 uint32_t u1Write : 1;
1559 /** User(=1) / Supervisor (=0) flag. */
1560 uint32_t u1User : 1;
1561 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1562 uint32_t u1WriteThru : 1;
1563 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1564 uint32_t u1CacheDisable : 1;
1565 /** Accessed flag.
1566 * Indicates that the page have been read or written to. */
1567 uint32_t u1Accessed : 1;
1568 /** Chunk of reserved bits. */
1569 uint32_t u3Reserved : 3;
1570 /** Available for use to system software. */
1571 uint32_t u3Available : 3;
1572 /** Physical Page number of the next level - Low Part. Don't use! */
1573 uint32_t u20PageNoLow : 20;
1574 /** Physical Page number of the next level - High Part. Don't use! */
1575 uint32_t u20PageNoHigh : 20;
1576 /** MBZ bits */
1577 uint32_t u11Reserved : 11;
1578 /** No Execute flag. */
1579 uint32_t u1NoExecute : 1;
1580} X86PDPEAMD64BITS;
1581/** Pointer to a page directory pointer table entry. */
1582typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1583/** Pointer to a const page directory pointer table entry. */
1584typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1585
1586/**
1587 * Page directory pointer table entry.
1588 */
1589typedef union X86PDPE
1590{
1591 /** Normal view. */
1592 X86PDPEBITS n;
1593 /** AMD64 view. */
1594 X86PDPEAMD64BITS lm;
1595 /** Unsigned integer view. */
1596 X86PGPAEUINT u;
1597 /** 8 bit unsigned integer view. */
1598 uint8_t au8[8];
1599 /** 16 bit unsigned integer view. */
1600 uint16_t au16[4];
1601 /** 32 bit unsigned integer view. */
1602 uint32_t au32[2];
1603} X86PDPE;
1604/** Pointer to a page directory pointer table entry. */
1605typedef X86PDPE *PX86PDPE;
1606/** Pointer to a const page directory pointer table entry. */
1607typedef const X86PDPE *PCX86PDPE;
1608
1609
1610/**
1611 * Page directory pointer table.
1612 */
1613typedef struct X86PDPT
1614{
1615 /** PDE Array. */
1616 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1617} X86PDPT;
1618/** Pointer to a page directory pointer table. */
1619typedef X86PDPT *PX86PDPT;
1620/** Pointer to a const page directory pointer table. */
1621typedef const X86PDPT *PCX86PDPT;
1622
1623/** The page shift to get the PDPT index. */
1624#define X86_PDPT_SHIFT 30
1625/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1626#define X86_PDPT_MASK_PAE 0x3
1627/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1628#define X86_PDPT_MASK_AMD64 0x1ff
1629
1630/** @} */
1631
1632
1633/** @name Page Map Level-4 Entry (Long Mode PAE)
1634 * @{
1635 */
1636/** Bit 0 - P - Present bit. */
1637#define X86_PML4E_P RT_BIT(0)
1638/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1639#define X86_PML4E_RW RT_BIT(1)
1640/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1641#define X86_PML4E_US RT_BIT(2)
1642/** Bit 3 - PWT - Page level write thru bit. */
1643#define X86_PML4E_PWT RT_BIT(3)
1644/** Bit 4 - PCD - Page level cache disable bit. */
1645#define X86_PML4E_PCD RT_BIT(4)
1646/** Bit 5 - A - Access bit. */
1647#define X86_PML4E_A RT_BIT(5)
1648/** Bits 9-11 - - Available for use to system software. */
1649#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1650/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1651#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1652#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1653#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1654#else
1655#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1656#endif
1657/** Bits 63 - NX - PAE - No execution flag. */
1658#define X86_PML4E_NX RT_BIT_64(63)
1659
1660/**
1661 * Page Map Level-4 Entry
1662 */
1663typedef struct X86PML4EBITS
1664{
1665 /** Flags whether(=1) or not the page is present. */
1666 uint32_t u1Present : 1;
1667 /** Read(=0) / Write(=1) flag. */
1668 uint32_t u1Write : 1;
1669 /** User(=1) / Supervisor (=0) flag. */
1670 uint32_t u1User : 1;
1671 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1672 uint32_t u1WriteThru : 1;
1673 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1674 uint32_t u1CacheDisable : 1;
1675 /** Accessed flag.
1676 * Indicates that the page have been read or written to. */
1677 uint32_t u1Accessed : 1;
1678 /** Chunk of reserved bits. */
1679 uint32_t u3Reserved : 3;
1680 /** Available for use to system software. */
1681 uint32_t u3Available : 3;
1682 /** Physical Page number of the next level - Low Part. Don't use! */
1683 uint32_t u20PageNoLow : 20;
1684 /** Physical Page number of the next level - High Part. Don't use! */
1685 uint32_t u20PageNoHigh : 20;
1686 /** MBZ bits */
1687 uint32_t u11Reserved : 11;
1688 /** No Execute flag. */
1689 uint32_t u1NoExecute : 1;
1690} X86PML4EBITS;
1691/** Pointer to a page map level-4 entry. */
1692typedef X86PML4EBITS *PX86PML4EBITS;
1693/** Pointer to a const page map level-4 entry. */
1694typedef const X86PML4EBITS *PCX86PML4EBITS;
1695
1696/**
1697 * Page Map Level-4 Entry.
1698 */
1699typedef union X86PML4E
1700{
1701 /** Normal view. */
1702 X86PML4EBITS n;
1703 /** Unsigned integer view. */
1704 X86PGPAEUINT u;
1705 /** 8 bit unsigned integer view. */
1706 uint8_t au8[8];
1707 /** 16 bit unsigned integer view. */
1708 uint16_t au16[4];
1709 /** 32 bit unsigned integer view. */
1710 uint32_t au32[2];
1711} X86PML4E;
1712/** Pointer to a page map level-4 entry. */
1713typedef X86PML4E *PX86PML4E;
1714/** Pointer to a const page map level-4 entry. */
1715typedef const X86PML4E *PCX86PML4E;
1716
1717
1718/**
1719 * Page Map Level-4.
1720 */
1721typedef struct X86PML4
1722{
1723 /** PDE Array. */
1724 X86PML4E a[X86_PG_PAE_ENTRIES];
1725} X86PML4;
1726/** Pointer to a page map level-4. */
1727typedef X86PML4 *PX86PML4;
1728/** Pointer to a const page map level-4. */
1729typedef const X86PML4 *PCX86PML4;
1730
1731/** The page shift to get the PML4 index. */
1732#define X86_PML4_SHIFT 39
1733/** The PML4 index mask (apply to a shifted page address). */
1734#define X86_PML4_MASK 0x1ff
1735
1736/** @} */
1737
1738/** @} */
1739
1740
1741/**
1742 * 80-bit MMX/FPU register type.
1743 */
1744typedef struct X86FPUMMX
1745{
1746 uint8_t reg[10];
1747} X86FPUMMX;
1748/** Pointer to a 80-bit MMX/FPU register type. */
1749typedef X86FPUMMX *PX86FPUMMX;
1750/** Pointer to a const 80-bit MMX/FPU register type. */
1751typedef const X86FPUMMX *PCX86FPUMMX;
1752
1753/**
1754 * FPU state (aka FSAVE/FRSTOR Memory Region).
1755 */
1756#pragma pack(1)
1757typedef struct X86FPUSTATE
1758{
1759 /** Control word. */
1760 uint16_t FCW;
1761 /** Alignment word */
1762 uint16_t Dummy1;
1763 /** Status word. */
1764 uint16_t FSW;
1765 /** Alignment word */
1766 uint16_t Dummy2;
1767 /** Tag word */
1768 uint16_t FTW;
1769 /** Alignment word */
1770 uint16_t Dummy3;
1771
1772 /** Instruction pointer. */
1773 uint32_t FPUIP;
1774 /** Code selector. */
1775 uint16_t CS;
1776 /** Opcode. */
1777 uint16_t FOP;
1778 /** FOO. */
1779 uint32_t FPUOO;
1780 /** FOS. */
1781 uint32_t FPUOS;
1782 /** FPU view - todo. */
1783 X86FPUMMX regs[8];
1784} X86FPUSTATE;
1785#pragma pack()
1786/** Pointer to a FPU state. */
1787typedef X86FPUSTATE *PX86FPUSTATE;
1788/** Pointer to a const FPU state. */
1789typedef const X86FPUSTATE *PCX86FPUSTATE;
1790
1791/**
1792 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1793 */
1794#pragma pack(1)
1795typedef struct X86FXSTATE
1796{
1797 /** Control word. */
1798 uint16_t FCW;
1799 /** Status word. */
1800 uint16_t FSW;
1801 /** Tag word (it's a byte actually). */
1802 uint8_t FTW;
1803 uint8_t huh1;
1804 /** Opcode. */
1805 uint16_t FOP;
1806 /** Instruction pointer. */
1807 uint32_t FPUIP;
1808 /** Code selector. */
1809 uint16_t CS;
1810 uint16_t Rsvrd1;
1811 /* - offset 16 - */
1812 /** Data pointer. */
1813 uint32_t FPUDP;
1814 /** Data segment */
1815 uint16_t DS;
1816 uint16_t Rsrvd2;
1817 uint32_t MXCSR;
1818 uint32_t MXCSR_MASK;
1819 /* - offset 32 - */
1820 union
1821 {
1822 /** MMX view. */
1823 uint64_t mmx;
1824 /** FPU view - todo. */
1825 X86FPUMMX fpu;
1826 /** 8-bit view. */
1827 uint8_t au8[16];
1828 /** 16-bit view. */
1829 uint16_t au16[8];
1830 /** 32-bit view. */
1831 uint32_t au32[4];
1832 /** 64-bit view. */
1833 uint64_t au64[2];
1834 /** 128-bit view. (yeah, very helpful) */
1835 uint128_t au128[1];
1836 } aRegs[8];
1837 /* - offset 160 - */
1838 union
1839 {
1840 /** XMM Register view *. */
1841 uint128_t xmm;
1842 /** 8-bit view. */
1843 uint8_t au8[16];
1844 /** 16-bit view. */
1845 uint16_t au16[8];
1846 /** 32-bit view. */
1847 uint32_t au32[4];
1848 /** 64-bit view. */
1849 uint64_t au64[2];
1850 /** 128-bit view. (yeah, very helpful) */
1851 uint128_t au128[1];
1852 } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1853 /* - offset 416 - */
1854 uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1855} X86FXSTATE;
1856#pragma pack()
1857/** Pointer to a FPU Extended state. */
1858typedef X86FXSTATE *PX86FXSTATE;
1859/** Pointer to a const FPU Extended state. */
1860typedef const X86FXSTATE *PCX86FXSTATE;
1861
1862
1863/** @name Selector Descriptor
1864 * @{
1865 */
1866
1867/**
1868 * Generic descriptor table entry
1869 */
1870#pragma pack(1)
1871typedef struct X86DESCGENERIC
1872{
1873 /** Limit - Low word. */
1874 unsigned u16LimitLow : 16;
1875 /** Base address - lowe word.
1876 * Don't try set this to 24 because MSC is doing studing things then. */
1877 unsigned u16BaseLow : 16;
1878 /** Base address - first 8 bits of high word. */
1879 unsigned u8BaseHigh1 : 8;
1880 /** Segment Type. */
1881 unsigned u4Type : 4;
1882 /** Descriptor Type. System(=0) or code/data selector */
1883 unsigned u1DescType : 1;
1884 /** Descriptor Privelege level. */
1885 unsigned u2Dpl : 2;
1886 /** Flags selector present(=1) or not. */
1887 unsigned u1Present : 1;
1888 /** Segment limit 16-19. */
1889 unsigned u4LimitHigh : 4;
1890 /** Available for system software. */
1891 unsigned u1Available : 1;
1892 /** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1893 unsigned u1Long : 1;
1894 /** This flags meaning depends on the segment type. Try make sense out
1895 * of the intel manual yourself. */
1896 unsigned u1DefBig : 1;
1897 /** Granularity of the limit. If set 4KB granularity is used, if
1898 * clear byte. */
1899 unsigned u1Granularity : 1;
1900 /** Base address - highest 8 bits. */
1901 unsigned u8BaseHigh2 : 8;
1902} X86DESCGENERIC;
1903#pragma pack()
1904/** Pointer to a generic descriptor entry. */
1905typedef X86DESCGENERIC *PX86DESCGENERIC;
1906/** Pointer to a const generic descriptor entry. */
1907typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1908
1909
1910/**
1911 * Descriptor attributes.
1912 */
1913typedef struct X86DESCATTRBITS
1914{
1915 /** Segment Type. */
1916 unsigned u4Type : 4;
1917 /** Descriptor Type. System(=0) or code/data selector */
1918 unsigned u1DescType : 1;
1919 /** Descriptor Privelege level. */
1920 unsigned u2Dpl : 2;
1921 /** Flags selector present(=1) or not. */
1922 unsigned u1Present : 1;
1923 /** Segment limit 16-19. */
1924 unsigned u4LimitHigh : 4;
1925 /** Available for system software. */
1926 unsigned u1Available : 1;
1927 /** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1928 unsigned u1Long : 1;
1929 /** This flags meaning depends on the segment type. Try make sense out
1930 * of the intel manual yourself. */
1931 unsigned u1DefBig : 1;
1932 /** Granularity of the limit. If set 4KB granularity is used, if
1933 * clear byte. */
1934 unsigned u1Granularity : 1;
1935} X86DESCATTRBITS;
1936
1937
1938#pragma pack(1)
1939typedef union X86DESCATTR
1940{
1941 /** Normal view. */
1942 X86DESCATTRBITS n;
1943 /** Unsigned integer view. */
1944 uint32_t u;
1945} X86DESCATTR;
1946#pragma pack()
1947
1948/** Pointer to descriptor attributes. */
1949typedef X86DESCATTR *PX86DESCATTR;
1950/** Pointer to const descriptor attributes. */
1951typedef const X86DESCATTR *PCX86DESCATTR;
1952
1953
1954/**
1955 * Descriptor table entry.
1956 */
1957#pragma pack(1)
1958typedef union X86DESC
1959{
1960 /** Generic descriptor view. */
1961 X86DESCGENERIC Gen;
1962#if 0
1963 /** IDT view. */
1964 VBOXIDTE Idt;
1965#endif
1966
1967 /** 8 bit unsigned interger view. */
1968 uint8_t au8[8];
1969 /** 16 bit unsigned interger view. */
1970 uint16_t au16[4];
1971 /** 32 bit unsigned interger view. */
1972 uint32_t au32[2];
1973} X86DESC;
1974#pragma pack()
1975/** Pointer to descriptor table entry. */
1976typedef X86DESC *PX86DESC;
1977/** Pointer to const descriptor table entry. */
1978typedef const X86DESC *PCX86DESC;
1979
1980
1981/** @def X86DESC_BASE
1982 * Return the base address of a descriptor.
1983 */
1984#define X86DESC_BASE(desc) \
1985 ( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
1986 | ( (desc).Gen.u8BaseHigh1 << 16) \
1987 | ( (desc).Gen.u16BaseLow ) )
1988
1989/** @def X86DESC_LIMIT
1990 * Return the limit of a descriptor.
1991 */
1992#define X86DESC_LIMIT(desc) \
1993 ( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
1994 | ( (desc).Gen.u16LimitLow ) )
1995
1996/**
1997 * 64 bits generic descriptor table entry
1998 * Note: most of these bits have no meaning in long mode.
1999 */
2000#pragma pack(1)
2001typedef struct X86DESC64GENERIC
2002{
2003 /** Limit - Low word - *IGNORED*. */
2004 unsigned u16LimitLow : 16;
2005 /** Base address - lowe word. - *IGNORED*
2006 * Don't try set this to 24 because MSC is doing studing things then. */
2007 unsigned u16BaseLow : 16;
2008 /** Base address - first 8 bits of high word. - *IGNORED* */
2009 unsigned u8BaseHigh1 : 8;
2010 /** Segment Type. */
2011 unsigned u4Type : 4;
2012 /** Descriptor Type. System(=0) or code/data selector */
2013 unsigned u1DescType : 1;
2014 /** Descriptor Privelege level. */
2015 unsigned u2Dpl : 2;
2016 /** Flags selector present(=1) or not. */
2017 unsigned u1Present : 1;
2018 /** Segment limit 16-19. - *IGNORED* */
2019 unsigned u4LimitHigh : 4;
2020 /** Available for system software. - *IGNORED* */
2021 unsigned u1Available : 1;
2022 /** Long mode flag. */
2023 unsigned u1Long : 1;
2024 /** This flags meaning depends on the segment type. Try make sense out
2025 * of the intel manual yourself. */
2026 unsigned u1DefBig : 1;
2027 /** Granularity of the limit. If set 4KB granularity is used, if
2028 * clear byte. - *IGNORED* */
2029 unsigned u1Granularity : 1;
2030 /** Base address - highest 8 bits. - *IGNORED* */
2031 unsigned u8BaseHigh2 : 8;
2032 /** Base address - bits 63-32. */
2033 unsigned u32BaseHigh3 : 32;
2034 unsigned u8Reserved : 8;
2035 unsigned u5Zeros : 5;
2036 unsigned u19Reserved : 19;
2037} X86DESC64GENERIC;
2038#pragma pack()
2039/** Pointer to a generic descriptor entry. */
2040typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2041/** Pointer to a const generic descriptor entry. */
2042typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2043
2044/**
2045 * System descriptor table entry (64 bits)
2046 */
2047#pragma pack(1)
2048typedef struct X86DESC64SYSTEM
2049{
2050 /** Limit - Low word. */
2051 unsigned u16LimitLow : 16;
2052 /** Base address - lowe word.
2053 * Don't try set this to 24 because MSC is doing studing things then. */
2054 unsigned u16BaseLow : 16;
2055 /** Base address - first 8 bits of high word. */
2056 unsigned u8BaseHigh1 : 8;
2057 /** Segment Type. */
2058 unsigned u4Type : 4;
2059 /** Descriptor Type. System(=0) or code/data selector */
2060 unsigned u1DescType : 1;
2061 /** Descriptor Privelege level. */
2062 unsigned u2Dpl : 2;
2063 /** Flags selector present(=1) or not. */
2064 unsigned u1Present : 1;
2065 /** Segment limit 16-19. */
2066 unsigned u4LimitHigh : 4;
2067 /** Available for system software. */
2068 unsigned u1Available : 1;
2069 /** Reserved - 0. */
2070 unsigned u1Reserved : 1;
2071 /** This flags meaning depends on the segment type. Try make sense out
2072 * of the intel manual yourself. */
2073 unsigned u1DefBig : 1;
2074 /** Granularity of the limit. If set 4KB granularity is used, if
2075 * clear byte. */
2076 unsigned u1Granularity : 1;
2077 /** Base address - bits 31-24. */
2078 unsigned u8BaseHigh2 : 8;
2079 /** Base address - bits 63-32. */
2080 unsigned u32BaseHigh3 : 32;
2081 unsigned u8Reserved : 8;
2082 unsigned u5Zeros : 5;
2083 unsigned u19Reserved : 19;
2084} X86DESC64SYSTEM;
2085#pragma pack()
2086/** Pointer to a generic descriptor entry. */
2087typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2088/** Pointer to a const generic descriptor entry. */
2089typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2090
2091
2092/**
2093 * Descriptor table entry.
2094 */
2095#pragma pack(1)
2096typedef union X86DESC64
2097{
2098 /** Generic descriptor view. */
2099 X86DESC64GENERIC Gen;
2100 /** System descriptor view. */
2101 X86DESC64SYSTEM System;
2102#if 0
2103 X86DESC64GATE Gate;
2104#endif
2105
2106 /** 8 bit unsigned interger view. */
2107 uint8_t au8[16];
2108 /** 16 bit unsigned interger view. */
2109 uint16_t au16[8];
2110 /** 32 bit unsigned interger view. */
2111 uint32_t au32[4];
2112 /** 64 bit unsigned interger view. */
2113 uint64_t au64[2];
2114} X86DESC64;
2115#pragma pack()
2116/** Pointer to descriptor table entry. */
2117typedef X86DESC64 *PX86DESC64;
2118/** Pointer to const descriptor table entry. */
2119typedef const X86DESC64 *PCX86DESC64;
2120
2121#if HC_ARCH_BITS == 64
2122typedef X86DESC64 X86DESCHC;
2123typedef X86DESC64 *PX86DESCHC;
2124#else
2125typedef X86DESC X86DESCHC;
2126typedef X86DESC *PX86DESCHC;
2127#endif
2128
2129/** @def X86DESC_LIMIT
2130 * Return the base of a 64-bit descriptor.
2131 */
2132#define X86DESC64_BASE(desc) \
2133 ( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2134 | ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2135 | ( (desc).Gen.u8BaseHigh1 << 16) \
2136 | ( (desc).Gen.u16BaseLow ) )
2137
2138
2139/** @name Selector Descriptor Types.
2140 * @{
2141 */
2142
2143/** @name Non-System Selector Types.
2144 * @{ */
2145/** Code(=set)/Data(=clear) bit. */
2146#define X86_SEL_TYPE_CODE 8
2147/** Memory(=set)/System(=clear) bit. */
2148#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2149/** Accessed bit. */
2150#define X86_SEL_TYPE_ACCESSED 1
2151/** Expand down bit (for data selectors only). */
2152#define X86_SEL_TYPE_DOWN 4
2153/** Conforming bit (for code selectors only). */
2154#define X86_SEL_TYPE_CONF 4
2155/** Write bit (for data selectors only). */
2156#define X86_SEL_TYPE_WRITE 2
2157/** Read bit (for code selectors only). */
2158#define X86_SEL_TYPE_READ 2
2159
2160/** Read only selector type. */
2161#define X86_SEL_TYPE_RO 0
2162/** Accessed read only selector type. */
2163#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
2164/** Read write selector type. */
2165#define X86_SEL_TYPE_RW 2
2166/** Accessed read write selector type. */
2167#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
2168/** Expand down read only selector type. */
2169#define X86_SEL_TYPE_RO_DOWN 4
2170/** Accessed expand down read only selector type. */
2171#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
2172/** Expand down read write selector type. */
2173#define X86_SEL_TYPE_RW_DOWN 6
2174/** Accessed expand down read write selector type. */
2175#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
2176/** Execute only selector type. */
2177#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
2178/** Accessed execute only selector type. */
2179#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2180/** Execute and read selector type. */
2181#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
2182/** Accessed execute and read selector type. */
2183#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2184/** Conforming execute only selector type. */
2185#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
2186/** Accessed Conforming execute only selector type. */
2187#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2188/** Conforming execute and write selector type. */
2189#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
2190/** Accessed Conforming execute and write selector type. */
2191#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2192/** @} */
2193
2194
2195/** @name System Selector Types.
2196 * @{ */
2197/** Undefined system selector type. */
2198#define X86_SEL_TYPE_SYS_UNDEFINED 0
2199/** 286 TSS selector. */
2200#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2201/** LDT selector. */
2202#define X86_SEL_TYPE_SYS_LDT 2
2203/** 286 TSS selector - Busy. */
2204#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2205/** 286 Callgate selector. */
2206#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2207/** Taskgate selector. */
2208#define X86_SEL_TYPE_SYS_TASK_GATE 5
2209/** 286 Interrupt gate selector. */
2210#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2211/** 286 Trapgate selector. */
2212#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2213/** Undefined system selector. */
2214#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2215/** 386 TSS selector. */
2216#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2217/** Undefined system selector. */
2218#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2219/** 386 TSS selector - Busy. */
2220#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2221/** 386 Callgate selector. */
2222#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2223/** Undefined system selector. */
2224#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2225/** 386 Interruptgate selector. */
2226#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2227/** 386 Trapgate selector. */
2228#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2229/** @} */
2230
2231/** @name AMD64 System Selector Types.
2232 * @{ */
2233#define AMD64_SEL_TYPE_SYS_LDT 2
2234/** 286 TSS selector - Busy. */
2235#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2236/** 386 TSS selector - Busy. */
2237#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2238/** 386 Callgate selector. */
2239#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2240/** 386 Interruptgate selector. */
2241#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2242/** 386 Trapgate selector. */
2243#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2244/** @} */
2245
2246/** @} */
2247
2248
2249/** @name Descriptor Table Entry Flag Masks.
2250 * These are for the 2nd 32-bit word of a descriptor.
2251 * @{ */
2252/** Bits 8-11 - TYPE - Descriptor type mask. */
2253#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
2254/** Bit 12 - S - System (=0) or Code/Data (=1). */
2255#define X86_DESC_S RT_BIT(12)
2256/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2257#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
2258/** Bit 15 - P - Present. */
2259#define X86_DESC_P RT_BIT(15)
2260/** Bit 20 - AVL - Available for system software. */
2261#define X86_DESC_AVL RT_BIT(20)
2262/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2263#define X86_DESC_DB RT_BIT(22)
2264/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2265 * used, if clear byte. */
2266#define X86_DESC_G RT_BIT(23)
2267/** @} */
2268
2269/** @} */
2270
2271
2272/** @name Selectors.
2273 * @{
2274 */
2275
2276/**
2277 * The shift used to convert a selector from and to index an index (C).
2278 */
2279#define X86_SEL_SHIFT 3
2280
2281/**
2282 * The shift used to convert a selector from and to index an index (C).
2283 */
2284#define AMD64_SEL_SHIFT 4
2285
2286#if HC_ARCH_BITS == 64
2287#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2288#else
2289#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2290#endif
2291
2292/**
2293 * The mask used to mask off the table indicator and CPL of an selector.
2294 */
2295#define X86_SEL_MASK 0xfff8
2296
2297/**
2298 * The bit indicating that a selector is in the LDT and not in the GDT.
2299 */
2300#define X86_SEL_LDT 0x0004
2301/**
2302 * The bit mask for getting the RPL of a selector.
2303 */
2304#define X86_SEL_RPL 0x0003
2305
2306/** @} */
2307
2308
2309/**
2310 * x86 Exceptions/Faults/Traps.
2311 */
2312typedef enum X86XCPT
2313{
2314 /** \#DE - Divide error. */
2315 X86_XCPT_DE = 0x00,
2316 /** \#DB - Debug event (single step, DRx, ..) */
2317 X86_XCPT_DB = 0x01,
2318 /** NMI - Non-Maskable Interrupt */
2319 X86_XCPT_NMI = 0x02,
2320 /** \#BP - Breakpoint (INT3). */
2321 X86_XCPT_BP = 0x03,
2322 /** \#OF - Overflow (INTO). */
2323 X86_XCPT_OF = 0x04,
2324 /** \#BR - Bound range exceeded (BOUND). */
2325 X86_XCPT_BR = 0x05,
2326 /** \#UD - Undefined opcode. */
2327 X86_XCPT_UD = 0x06,
2328 /** \#NM - Device not available (math coprocessor device). */
2329 X86_XCPT_NM = 0x07,
2330 /** \#DF - Double fault. */
2331 X86_XCPT_DF = 0x08,
2332 /** ??? - Coprocessor segment overrun (obsolete). */
2333 X86_XCPT_CO_SEG_OVERRUN = 0x09,
2334 /** \#TS - Taskswitch (TSS). */
2335 X86_XCPT_TS = 0x0a,
2336 /** \#NP - Segment no present. */
2337 X86_XCPT_NP = 0x0b,
2338 /** \#SS - Stack segment fault. */
2339 X86_XCPT_SS = 0x0c,
2340 /** \#GP - General protection fault. */
2341 X86_XCPT_GP = 0x0d,
2342 /** \#PF - Page fault. */
2343 X86_XCPT_PF = 0x0e,
2344 /* 0x0f is reserved. */
2345 /** \#MF - Math fault (FPU). */
2346 X86_XCPT_MF = 0x10,
2347 /** \#AC - Alignment check. */
2348 X86_XCPT_AC = 0x11,
2349 /** \#MC - Machine check. */
2350 X86_XCPT_MC = 0x12,
2351 /** \#XF - SIMD Floating-Pointer Exception. */
2352 X86_XCPT_XF = 0x13
2353} X86XCPT;
2354/** Pointer to a x86 exception code. */
2355typedef X86XCPT *PX86XCPT;
2356/** Pointer to a const x86 exception code. */
2357typedef const X86XCPT *PCX86XCPT;
2358
2359
2360/** @name Trap Error Codes
2361 * @{
2362 */
2363/** External indicator. */
2364#define X86_TRAP_ERR_EXTERNAL 1
2365/** IDT indicator. */
2366#define X86_TRAP_ERR_IDT 2
2367/** Descriptor table indicator - If set LDT, if clear GDT. */
2368#define X86_TRAP_ERR_TI 4
2369/** Mask for getting the selector. */
2370#define X86_TRAP_ERR_SEL_MASK 0xfff8
2371/** Shift for getting the selector table index (C type index). */
2372#define X86_TRAP_ERR_SEL_SHIFT 3
2373/** @} */
2374
2375
2376/** @name \#PF Trap Error Codes
2377 * @{
2378 */
2379/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2380#define X86_TRAP_PF_P RT_BIT(0)
2381/** Bit 1 - R/W - Read (clear) or write (set) access. */
2382#define X86_TRAP_PF_RW RT_BIT(1)
2383/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2384#define X86_TRAP_PF_US RT_BIT(2)
2385/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2386#define X86_TRAP_PF_RSVD RT_BIT(3)
2387/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2388#define X86_TRAP_PF_ID RT_BIT(4)
2389/** @} */
2390
2391#pragma pack(1)
2392/**
2393 * 32-bit IDTR/GDTR.
2394 */
2395typedef struct X86XDTR32
2396{
2397 /** Size of the descriptor table. */
2398 uint16_t cb;
2399 /** Address of the descriptor table. */
2400 uint32_t uAddr;
2401} X86XDTR32, *PX86XDTR32;
2402#pragma pack()
2403
2404#pragma pack(1)
2405/**
2406 * 64-bit IDTR/GDTR.
2407 */
2408typedef struct X86XDTR64
2409{
2410 /** Size of the descriptor table. */
2411 uint16_t cb;
2412 /** Address of the descriptor table. */
2413 uint64_t uAddr;
2414} X86XDTR64, *PX86XDTR64;
2415#pragma pack()
2416
2417/** @} */
2418
2419#endif
2420
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