x86.h@ 12971

Last change on this file since 12971 was 12971, checked in by vboxsync, 16 years ago
x2APIC bits definitions
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1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39
40	/* Workaround for Solaris sys/regset.h defining CS, DS */
41	#if defined(RT_OS_SOLARIS)
42	# undef CS
43	# undef DS
44	#endif
45
46	/** @defgroup grp_x86 x86 Types and Definitions
47	* @{
48	*/
49
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105	/**
106	* EFLAGS.
107	*/
108	typedef union X86EFLAGS
109	{
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	/** The plain unsigned view. */
121	uint32_t u;
122	} X86EFLAGS;
123	/** Pointer to EFLAGS. */
124	typedef X86EFLAGS *PX86EFLAGS;
125	/** Pointer to const EFLAGS. */
126	typedef const X86EFLAGS *PCX86EFLAGS;
127
128	/**
129	* RFLAGS (32 upper bits are reserved).
130	*/
131	typedef union X86RFLAGS
132	{
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	/** The plain unsigned view. */
146	uint64_t u;
147	} X86RFLAGS;
148	/** Pointer to RFLAGS. */
149	typedef X86RFLAGS *PX86RFLAGS;
150	/** Pointer to const RFLAGS. */
151	typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154	/** @name EFLAGS
155	* @{
156	*/
157	/** Bit 0 - CF - Carry flag - Status flag. */
158	#define X86_EFL_CF RT_BIT(0)
159	/** Bit 2 - PF - Parity flag - Status flag. */
160	#define X86_EFL_PF RT_BIT(2)
161	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162	#define X86_EFL_AF RT_BIT(4)
163	/** Bit 6 - ZF - Zero flag - Status flag. */
164	#define X86_EFL_ZF RT_BIT(6)
165	/** Bit 7 - SF - Signed flag - Status flag. */
166	#define X86_EFL_SF RT_BIT(7)
167	/** Bit 8 - TF - Trap flag - System flag. */
168	#define X86_EFL_TF RT_BIT(8)
169	/** Bit 9 - IF - Interrupt flag - System flag. */
170	#define X86_EFL_IF RT_BIT(9)
171	/** Bit 10 - DF - Direction flag - Control flag. */
172	#define X86_EFL_DF RT_BIT(10)
173	/** Bit 11 - OF - Overflow flag - Status flag. */
174	#define X86_EFL_OF RT_BIT(11)
175	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
177	/** Bit 14 - NT - Nested task flag - System flag. */
178	#define X86_EFL_NT RT_BIT(14)
179	/** Bit 16 - RF - Resume flag - System flag. */
180	#define X86_EFL_RF RT_BIT(16)
181	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182	#define X86_EFL_VM RT_BIT(17)
183	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184	#define X86_EFL_AC RT_BIT(18)
185	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186	#define X86_EFL_VIF RT_BIT(19)
187	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188	#define X86_EFL_VIP RT_BIT(20)
189	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190	#define X86_EFL_ID RT_BIT(21)
191	/** IOPL shift. */
192	#define X86_EFL_IOPL_SHIFT 12
193	/** The the IOPL level from the flags. */
194	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chip. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 21 - x2APIC support. */
353	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
354	/** ECX Bit 23 - POPCOUNT instruction. */
355	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
356
357
358	/** Bit 0 - FPU - x87 FPU on Chip. */
359	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
360	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
361	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
362	/** Bit 2 - DE - Debugging extensions. */
363	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
364	/** Bit 3 - PSE - Page Size Extension. */
365	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
366	/** Bit 4 - TSC - Time Stamp Counter. */
367	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
368	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
369	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
370	/** Bit 6 - PAE - Physical Address Extension. */
371	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
372	/** Bit 7 - MCE - Machine Check Exception. */
373	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
374	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
375	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
376	/** Bit 9 - APIC - APIC On-Chip. */
377	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
378	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
379	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
380	/** Bit 12 - MTRR - Memory Type Range Registers. */
381	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
382	/** Bit 13 - PGE - PTE Global Bit. */
383	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
384	/** Bit 14 - MCA - Machine Check Architecture. */
385	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
386	/** Bit 15 - CMOV - Conditional Move Instructions. */
387	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
388	/** Bit 16 - PAT - Page Attribute Table. */
389	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
390	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
391	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
392	/** Bit 18 - PSN - Processor Serial Number. */
393	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
394	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
395	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
396	/** Bit 21 - DS - Debug Store. */
397	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
398	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
399	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
400	/** Bit 23 - MMX - Intel MMX Technology. */
401	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
402	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
403	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
404	/** Bit 25 - SSE - SSE Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
406	/** Bit 26 - SSE2 - SSE2 Support. */
407	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
408	/** Bit 27 - SS - Self Snoop. */
409	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
410	/** Bit 28 - HTT - Hyper-Threading Technology. */
411	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
412	/** Bit 29 - TM - Therm. Monitor. */
413	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
414	/** Bit 31 - PBE - Pending Break Enabled. */
415	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
416	/** @} */
417
418
419	/** @name CPUID AMD Feature information.
420	* CPUID query with EAX=0x80000001.
421	* @{
422	*/
423	/** Bit 0 - FPU - x87 FPU on Chip. */
424	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
425	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
426	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
427	/** Bit 2 - DE - Debugging extensions. */
428	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
429	/** Bit 3 - PSE - Page Size Extension. */
430	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
431	/** Bit 4 - TSC - Time Stamp Counter. */
432	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
433	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
434	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
435	/** Bit 6 - PAE - Physical Address Extension. */
436	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
437	/** Bit 7 - MCE - Machine Check Exception. */
438	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
439	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
440	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
441	/** Bit 9 - APIC - APIC On-Chip. */
442	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
443	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
444	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
445	/** Bit 12 - MTRR - Memory Type Range Registers. */
446	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
447	/** Bit 13 - PGE - PTE Global Bit. */
448	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
449	/** Bit 14 - MCA - Machine Check Architecture. */
450	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
451	/** Bit 15 - CMOV - Conditional Move Instructions. */
452	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
453	/** Bit 16 - PAT - Page Attribute Table. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
455	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
456	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
457	/** Bit 20 - NX - AMD No-Execute Page Protection. */
458	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
459	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
460	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
461	/** Bit 23 - MMX - Intel MMX Technology. */
462	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
463	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
465	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
466	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
467	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
468	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
469	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
470	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
471	/** Bit 29 - LM - AMD Long Mode. */
472	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
473	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
475	/** Bit 31 - 3DNOW - AMD 3DNow. */
476	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
477
478	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
480	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
481	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
482	/** Bit 2 - SVM - AMD VM extensions. */
483	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
484	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
485	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
486	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
487	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
488	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
490	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
491	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
492	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
493	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
494	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
495	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
496	/** Bit 9 - OSVW - AMD OS visible workaround. */
497	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
498	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
500	/** Bit 13 - WDT - AMD Watchdog timer support. */
501	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
502
503	/** @} */
504
505
506	/** @name CPUID AMD Feature information.
507	* CPUID query with EAX=0x80000007.
508	* @{
509	*/
510	/** Bit 0 - TS - Temperature Sensor. */
511	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
512	/** Bit 1 - FID - Frequency ID Control. */
513	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
514	/** Bit 2 - VID - Voltage ID Control. */
515	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
516	/** Bit 3 - TTP - THERMTRIP. */
517	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
518	/** Bit 4 - TM - Hardware Thermal Control. */
519	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
520	/** Bit 5 - STC - Software Thermal Control. */
521	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
522	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
523	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
524	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
525	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
526	/** Bit 8 - TSCINVAR - TSC Invariant. */
527	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
528	/** @} */
529
530
531	/** @name CR0
532	* @{ */
533	/** Bit 0 - PE - Protection Enabled */
534	#define X86_CR0_PE RT_BIT(0)
535	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
536	/** Bit 1 - MP - Monitor Coprocessor */
537	#define X86_CR0_MP RT_BIT(1)
538	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
539	/** Bit 2 - EM - Emulation. */
540	#define X86_CR0_EM RT_BIT(2)
541	#define X86_CR0_EMULATE_FPU RT_BIT(2)
542	/** Bit 3 - TS - Task Switch. */
543	#define X86_CR0_TS RT_BIT(3)
544	#define X86_CR0_TASK_SWITCH RT_BIT(3)
545	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
546	#define X86_CR0_ET RT_BIT(4)
547	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
548	/** Bit 5 - NE - Numeric error. */
549	#define X86_CR0_NE RT_BIT(5)
550	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
551	/** Bit 16 - WP - Write Protect. */
552	#define X86_CR0_WP RT_BIT(16)
553	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
554	/** Bit 18 - AM - Alignment Mask. */
555	#define X86_CR0_AM RT_BIT(18)
556	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
557	/** Bit 29 - NW - Not Write-though. */
558	#define X86_CR0_NW RT_BIT(29)
559	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
560	/** Bit 30 - WP - Cache Disable. */
561	#define X86_CR0_CD RT_BIT(30)
562	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
563	/** Bit 31 - PG - Paging. */
564	#define X86_CR0_PG RT_BIT(31)
565	#define X86_CR0_PAGING RT_BIT(31)
566	/** @} */
567
568
569	/** @name CR3
570	* @{ */
571	/** Bit 3 - PWT - Page-level Writes Transparent. */
572	#define X86_CR3_PWT RT_BIT(3)
573	/** Bit 4 - PCD - Page-level Cache Disable. */
574	#define X86_CR3_PCD RT_BIT(4)
575	/** Bits 12-31 - - Page directory page number. */
576	#define X86_CR3_PAGE_MASK (0xfffff000)
577	/** Bits 5-31 - - PAE Page directory page number. */
578	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
579	/** Bits 12-51 - - AMD64 Page directory page number. */
580	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
581	/** @} */
582
583
584	/** @name CR4
585	* @{ */
586	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
587	#define X86_CR4_VME RT_BIT(0)
588	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
589	#define X86_CR4_PVI RT_BIT(1)
590	/** Bit 2 - TSD - Time Stamp Disable. */
591	#define X86_CR4_TSD RT_BIT(2)
592	/** Bit 3 - DE - Debugging Extensions. */
593	#define X86_CR4_DE RT_BIT(3)
594	/** Bit 4 - PSE - Page Size Extension. */
595	#define X86_CR4_PSE RT_BIT(4)
596	/** Bit 5 - PAE - Physical Address Extension. */
597	#define X86_CR4_PAE RT_BIT(5)
598	/** Bit 6 - MCE - Machine-Check Enable. */
599	#define X86_CR4_MCE RT_BIT(6)
600	/** Bit 7 - PGE - Page Global Enable. */
601	#define X86_CR4_PGE RT_BIT(7)
602	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
603	#define X86_CR4_PCE RT_BIT(8)
604	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
605	#define X86_CR4_OSFSXR RT_BIT(9)
606	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
607	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
608	/** Bit 13 - VMXE - VMX mode is enabled. */
609	#define X86_CR4_VMXE RT_BIT(13)
610	/** @} */
611
612
613	/** @name DR6
614	* @{ */
615	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
616	#define X86_DR6_B0 RT_BIT(0)
617	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
618	#define X86_DR6_B1 RT_BIT(1)
619	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
620	#define X86_DR6_B2 RT_BIT(2)
621	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
622	#define X86_DR6_B3 RT_BIT(3)
623	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
624	#define X86_DR6_BD RT_BIT(13)
625	/** Bit 14 - BS - Single step */
626	#define X86_DR6_BS RT_BIT(14)
627	/** Bit 15 - BT - Task switch. (TSS T bit.) */
628	#define X86_DR6_BT RT_BIT(15)
629	/** Value of DR6 after powerup/reset. */
630	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
631	/** @} */
632
633
634	/** @name DR7
635	* @{ */
636	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
637	#define X86_DR7_L0 RT_BIT(0)
638	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
639	#define X86_DR7_G0 RT_BIT(1)
640	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
641	#define X86_DR7_L1 RT_BIT(2)
642	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
643	#define X86_DR7_G1 RT_BIT(3)
644	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
645	#define X86_DR7_L2 RT_BIT(4)
646	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
647	#define X86_DR7_G2 RT_BIT(5)
648	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
649	#define X86_DR7_L3 RT_BIT(6)
650	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
651	#define X86_DR7_G3 RT_BIT(7)
652	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
653	#define X86_DR7_LE RT_BIT(8)
654	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
655	#define X86_DR7_GE RT_BIT(9)
656
657	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
658	* any DR register is accessed. */
659	#define X86_DR7_GD RT_BIT(13)
660	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
661	#define X86_DR7_RW0_MASK (3 << 16)
662	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
663	#define X86_DR7_LEN0_MASK (3 << 18)
664	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
665	#define X86_DR7_RW1_MASK (3 << 20)
666	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
667	#define X86_DR7_LEN1_MASK (3 << 22)
668	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
669	#define X86_DR7_RW2_MASK (3 << 24)
670	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
671	#define X86_DR7_LEN2_MASK (3 << 26)
672	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
673	#define X86_DR7_RW3_MASK (3 << 28)
674	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
675	#define X86_DR7_LEN3_MASK (3 << 30)
676
677	/** Bits which must be 1s. */
678	#define X86_DR7_MB1_MASK (RT_BIT(10))
679
680	/** Calcs the L bit of Nth breakpoint.
681	* @param iBp The breakpoint number [0..3].
682	*/
683	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
684
685	/** Calcs the G bit of Nth breakpoint.
686	* @param iBp The breakpoint number [0..3].
687	*/
688	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
689
690	/** @name Read/Write values.
691	* @{ */
692	/** Break on instruction fetch only. */
693	#define X86_DR7_RW_EO 0U
694	/** Break on write only. */
695	#define X86_DR7_RW_WO 1U
696	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
697	#define X86_DR7_RW_IO 2U
698	/** Break on read or write (but not instruction fetches). */
699	#define X86_DR7_RW_RW 3U
700	/** @} */
701
702	/** Shifts a X86_DR7_RW_* value to its right place.
703	* @param iBp The breakpoint number [0..3].
704	* @param fRw One of the X86_DR7_RW_* value.
705	*/
706	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
707
708	/** @name Length values.
709	* @{ */
710	#define X86_DR7_LEN_BYTE 0U
711	#define X86_DR7_LEN_WORD 1U
712	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
713	#define X86_DR7_LEN_DWORD 3U
714	/** @} */
715
716	/** Shifts a X86_DR7_LEN_* value to its right place.
717	* @param iBp The breakpoint number [0..3].
718	* @param cb One of the X86_DR7_LEN_* values.
719	*/
720	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
721
722	/** Fetch the breakpoint length bits from the DR7 value.
723	* @param uDR7 DR7 value
724	* @param iBp The breakpoint number [0..3].
725	*/
726	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
727
728	/** Mask used to check if any breakpoints are enabled. */
729	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
730
731	/** Mask used to check if any io breakpoints are set. */
732	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
733
734	/** Value of DR7 after powerup/reset. */
735	#define X86_DR7_INIT_VAL 0x400
736	/** @} */
737
738
739	/** @name Machine Specific Registers
740	* @{
741	*/
742
743	/** Time Stamp Counter. */
744	#define MSR_IA32_TSC 0x10
745
746	#define MSR_IA32_PLATFORM_ID 0x17
747
748	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
749	#define MSR_IA32_APICBASE 0x1b
750	#endif
751
752	/** CPU Feature control. */
753	#define MSR_IA32_FEATURE_CONTROL 0x3A
754	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
755	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
756
757	/** BIOS update trigger (microcode update). */
758	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
759
760	/** BIOS update signature (microcode). */
761	#define MSR_IA32_BIOS_SIGN_ID 0x8B
762
763	/** MTRR Capabilities. */
764	#define MSR_IA32_MTRR_CAP 0xFE
765
766
767	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
768	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
769	* R0 SS == CS + 8
770	* R3 CS == CS + 16
771	* R3 SS == CS + 24
772	*/
773	#define MSR_IA32_SYSENTER_CS 0x174
774	/** SYSENTER_ESP - the R0 ESP. */
775	#define MSR_IA32_SYSENTER_ESP 0x175
776	/** SYSENTER_EIP - the R0 EIP. */
777	#define MSR_IA32_SYSENTER_EIP 0x176
778	#endif
779
780	/** Machine Check Global Capabilities Register. */
781	#define MSR_IA32_MCP_CAP 0x179
782	/** Machine Check Global Status Register. */
783	#define MSR_IA32_MCP_STATUS 0x17A
784	/** Machine Check Global Control Register. */
785	#define MSR_IA32_MCP_CTRL 0x17B
786
787	/* Page Attribute Table. */
788	#define MSR_IA32_CR_PAT 0x277
789
790	/** MTRR Default Range. */
791	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
792
793	#define MSR_IA32_MC0_CTL 0x400
794	#define MSR_IA32_MC0_STATUS 0x401
795
796	/** Basic VMX information. */
797	#define MSR_IA32_VMX_BASIC_INFO 0x480
798	/** Allowed settings for pin-based VM execution controls */
799	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
800	/** Allowed settings for proc-based VM execution controls */
801	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
802	/** Allowed settings for the VMX exit controls. */
803	#define MSR_IA32_VMX_EXIT_CTLS 0x483
804	/** Allowed settings for the VMX entry controls. */
805	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
806	/** Misc VMX info. */
807	#define MSR_IA32_VMX_MISC 0x485
808	/** Fixed cleared bits in CR0. */
809	#define MSR_IA32_VMX_CR0_FIXED0 0x486
810	/** Fixed set bits in CR0. */
811	#define MSR_IA32_VMX_CR0_FIXED1 0x487
812	/** Fixed cleared bits in CR4. */
813	#define MSR_IA32_VMX_CR4_FIXED0 0x488
814	/** Fixed set bits in CR4. */
815	#define MSR_IA32_VMX_CR4_FIXED1 0x489
816	/** Information for enumerating fields in the VMCS. */
817	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
818	/** Allowed settings for secondary proc-based VM execution controls */
819	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
820	/** EPT capabilities. */
821	#define MSR_IA32_VMX_EPT_CAPS 0x48C
822
823	/** K6 EFER - Extended Feature Enable Register. */
824	#define MSR_K6_EFER 0xc0000080
825	/** @todo document EFER */
826	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
827	#define MSR_K6_EFER_SCE RT_BIT(0)
828	/** Bit 8 - LME - Long mode enabled. (R/W) */
829	#define MSR_K6_EFER_LME RT_BIT(8)
830	/** Bit 10 - LMA - Long mode active. (R) */
831	#define MSR_K6_EFER_LMA RT_BIT(10)
832	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
833	#define MSR_K6_EFER_NXE RT_BIT(11)
834	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
835	#define MSR_K6_EFER_SVME RT_BIT(12)
836	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
837	#define MSR_K6_EFER_LMSLE RT_BIT(13)
838	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
839	#define MSR_K6_EFER_FFXSR RT_BIT(14)
840	/** K6 STAR - SYSCALL/RET targets. */
841	#define MSR_K6_STAR 0xc0000081
842	/** Shift value for getting the SYSRET CS and SS value. */
843	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
844	/** Shift value for getting the SYSCALL CS and SS value. */
845	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
846	/** Selector mask for use after shifting. */
847	#define MSR_K6_STAR_SEL_MASK 0xffff
848	/** The mask which give the SYSCALL EIP. */
849	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
850	/** K6 WHCR - Write Handling Control Register. */
851	#define MSR_K6_WHCR 0xc0000082
852	/** K6 UWCCR - UC/WC Cacheability Control Register. */
853	#define MSR_K6_UWCCR 0xc0000085
854	/** K6 PSOR - Processor State Observability Register. */
855	#define MSR_K6_PSOR 0xc0000087
856	/** K6 PFIR - Page Flush/Invalidate Register. */
857	#define MSR_K6_PFIR 0xc0000088
858
859	#define MSR_K7_EVNTSEL0 0xc0010000
860	#define MSR_K7_EVNTSEL1 0xc0010001
861	#define MSR_K7_EVNTSEL2 0xc0010002
862	#define MSR_K7_EVNTSEL3 0xc0010003
863	#define MSR_K7_PERFCTR0 0xc0010004
864	#define MSR_K7_PERFCTR1 0xc0010005
865	#define MSR_K7_PERFCTR2 0xc0010006
866	#define MSR_K7_PERFCTR3 0xc0010007
867
868	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
869	#define MSR_K8_LSTAR 0xc0000082
870	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
871	#define MSR_K8_CSTAR 0xc0000083
872	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
873	#define MSR_K8_SF_MASK 0xc0000084
874	/** K8 FS.base - The 64-bit base FS register. */
875	#define MSR_K8_FS_BASE 0xc0000100
876	/** K8 GS.base - The 64-bit base GS register. */
877	#define MSR_K8_GS_BASE 0xc0000101
878	/** K8 KernelGSbase - Used with SWAPGS. */
879	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
880	#define MSR_K8_TSC_AUX 0xc0000103
881	#define MSR_K8_SYSCFG 0xc0010010
882	#define MSR_K8_HWCR 0xc0010015
883	#define MSR_K8_IORRBASE0 0xc0010016
884	#define MSR_K8_IORRMASK0 0xc0010017
885	#define MSR_K8_IORRBASE1 0xc0010018
886	#define MSR_K8_IORRMASK1 0xc0010019
887	#define MSR_K8_TOP_MEM1 0xc001001a
888	#define MSR_K8_TOP_MEM2 0xc001001d
889	#define MSR_K8_VM_CR 0xc0010114
890	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
891
892	#define MSR_K8_IGNNE 0xc0010115
893	#define MSR_K8_SMM_CTL 0xc0010116
894	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
895	* host state during world switch.
896	*/
897	#define MSR_K8_VM_HSAVE_PA 0xc0010117
898
899	/** @} */
900
901
902	/** @name Page Table / Directory / Directory Pointers / L4.
903	* @{
904	*/
905
906	/** Page table/directory entry as an unsigned integer. */
907	typedef uint32_t X86PGUINT;
908	/** Pointer to a page table/directory table entry as an unsigned integer. */
909	typedef X86PGUINT *PX86PGUINT;
910
911	/** Number of entries in a 32-bit PT/PD. */
912	#define X86_PG_ENTRIES 1024
913
914
915	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
916	typedef uint64_t X86PGPAEUINT;
917	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
918	typedef X86PGPAEUINT *PX86PGPAEUINT;
919
920	/** Number of entries in a PAE PT/PD. */
921	#define X86_PG_PAE_ENTRIES 512
922	/** Number of entries in a PAE PDPT. */
923	#define X86_PG_PAE_PDPE_ENTRIES 4
924
925	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
926	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
927	/** Number of entries in an AMD64 PDPT.
928	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
929	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
930
931	/** The size of a 4KB page. */
932	#define X86_PAGE_4K_SIZE _4K
933	/** The page shift of a 4KB page. */
934	#define X86_PAGE_4K_SHIFT 12
935	/** The 4KB page offset mask. */
936	#define X86_PAGE_4K_OFFSET_MASK 0xfff
937	/** The 4KB page base mask for virtual addresses. */
938	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
939	/** The 4KB page base mask for virtual addresses - 32bit version. */
940	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
941
942	/** The size of a 2MB page. */
943	#define X86_PAGE_2M_SIZE _2M
944	/** The page shift of a 2MB page. */
945	#define X86_PAGE_2M_SHIFT 21
946	/** The 2MB page offset mask. */
947	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
948	/** The 2MB page base mask for virtual addresses. */
949	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
950	/** The 2MB page base mask for virtual addresses - 32bit version. */
951	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
952
953	/** The size of a 4MB page. */
954	#define X86_PAGE_4M_SIZE _4M
955	/** The page shift of a 4MB page. */
956	#define X86_PAGE_4M_SHIFT 22
957	/** The 4MB page offset mask. */
958	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
959	/** The 4MB page base mask for virtual addresses. */
960	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
961	/** The 4MB page base mask for virtual addresses - 32bit version. */
962	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
963
964
965
966	/** @name Page Table Entry
967	* @{
968	*/
969	/** Bit 0 - P - Present bit. */
970	#define X86_PTE_P RT_BIT(0)
971	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
972	#define X86_PTE_RW RT_BIT(1)
973	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
974	#define X86_PTE_US RT_BIT(2)
975	/** Bit 3 - PWT - Page level write thru bit. */
976	#define X86_PTE_PWT RT_BIT(3)
977	/** Bit 4 - PCD - Page level cache disable bit. */
978	#define X86_PTE_PCD RT_BIT(4)
979	/** Bit 5 - A - Access bit. */
980	#define X86_PTE_A RT_BIT(5)
981	/** Bit 6 - D - Dirty bit. */
982	#define X86_PTE_D RT_BIT(6)
983	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
984	#define X86_PTE_PAT RT_BIT(7)
985	/** Bit 8 - G - Global flag. */
986	#define X86_PTE_G RT_BIT(8)
987	/** Bits 9-11 - - Available for use to system software. */
988	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
989	/** Bits 12-31 - - Physical Page number of the next level. */
990	#define X86_PTE_PG_MASK ( 0xfffff000 )
991
992	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
993	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
994	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
995	/** @todo Get rid of the above hack; makes code unreadable. */
996	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
997	#else
998	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
999	#endif
1000	/** Bits 63 - NX - PAE - No execution flag. */
1001	#define X86_PTE_PAE_NX RT_BIT_64(63)
1002
1003	/**
1004	* Page table entry.
1005	*/
1006	typedef struct X86PTEBITS
1007	{
1008	/** Flags whether(=1) or not the page is present. */
1009	unsigned u1Present : 1;
1010	/** Read(=0) / Write(=1) flag. */
1011	unsigned u1Write : 1;
1012	/** User(=1) / Supervisor (=0) flag. */
1013	unsigned u1User : 1;
1014	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1015	unsigned u1WriteThru : 1;
1016	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1017	unsigned u1CacheDisable : 1;
1018	/** Accessed flag.
1019	* Indicates that the page have been read or written to. */
1020	unsigned u1Accessed : 1;
1021	/** Dirty flag.
1022	* Indicates that the page have been written to. */
1023	unsigned u1Dirty : 1;
1024	/** Reserved / If PAT enabled, bit 2 of the index. */
1025	unsigned u1PAT : 1;
1026	/** Global flag. (Ignored in all but final level.) */
1027	unsigned u1Global : 1;
1028	/** Available for use to system software. */
1029	unsigned u3Available : 3;
1030	/** Physical Page number of the next level. */
1031	unsigned u20PageNo : 20;
1032	} X86PTEBITS;
1033	/** Pointer to a page table entry. */
1034	typedef X86PTEBITS *PX86PTEBITS;
1035	/** Pointer to a const page table entry. */
1036	typedef const X86PTEBITS *PCX86PTEBITS;
1037
1038	/**
1039	* Page table entry.
1040	*/
1041	typedef union X86PTE
1042	{
1043	/** Bit field view. */
1044	X86PTEBITS n;
1045	/** Unsigned integer view */
1046	X86PGUINT u;
1047	/** 32-bit view. */
1048	uint32_t au32[1];
1049	/** 16-bit view. */
1050	uint16_t au16[2];
1051	/** 8-bit view. */
1052	uint8_t au8[4];
1053	} X86PTE;
1054	/** Pointer to a page table entry. */
1055	typedef X86PTE *PX86PTE;
1056	/** Pointer to a const page table entry. */
1057	typedef const X86PTE *PCX86PTE;
1058
1059
1060	/**
1061	* PAE page table entry.
1062	*/
1063	typedef struct X86PTEPAEBITS
1064	{
1065	/** Flags whether(=1) or not the page is present. */
1066	uint32_t u1Present : 1;
1067	/** Read(=0) / Write(=1) flag. */
1068	uint32_t u1Write : 1;
1069	/** User(=1) / Supervisor(=0) flag. */
1070	uint32_t u1User : 1;
1071	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1072	uint32_t u1WriteThru : 1;
1073	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1074	uint32_t u1CacheDisable : 1;
1075	/** Accessed flag.
1076	* Indicates that the page have been read or written to. */
1077	uint32_t u1Accessed : 1;
1078	/** Dirty flag.
1079	* Indicates that the page have been written to. */
1080	uint32_t u1Dirty : 1;
1081	/** Reserved / If PAT enabled, bit 2 of the index. */
1082	uint32_t u1PAT : 1;
1083	/** Global flag. (Ignored in all but final level.) */
1084	uint32_t u1Global : 1;
1085	/** Available for use to system software. */
1086	uint32_t u3Available : 3;
1087	/** Physical Page number of the next level - Low Part. Don't use this. */
1088	uint32_t u20PageNoLow : 20;
1089	/** Physical Page number of the next level - High Part. Don't use this. */
1090	uint32_t u20PageNoHigh : 20;
1091	/** MBZ bits */
1092	uint32_t u11Reserved : 11;
1093	/** No Execute flag. */
1094	uint32_t u1NoExecute : 1;
1095	} X86PTEPAEBITS;
1096	/** Pointer to a page table entry. */
1097	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1098	/** Pointer to a page table entry. */
1099	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1100
1101	/**
1102	* PAE Page table entry.
1103	*/
1104	typedef union X86PTEPAE
1105	{
1106	/** Bit field view. */
1107	X86PTEPAEBITS n;
1108	/** Unsigned integer view */
1109	X86PGPAEUINT u;
1110	/** 32-bit view. */
1111	uint32_t au32[2];
1112	/** 16-bit view. */
1113	uint16_t au16[4];
1114	/** 8-bit view. */
1115	uint8_t au8[8];
1116	} X86PTEPAE;
1117	/** Pointer to a PAE page table entry. */
1118	typedef X86PTEPAE *PX86PTEPAE;
1119	/** Pointer to a const PAE page table entry. */
1120	typedef const X86PTEPAE *PCX86PTEPAE;
1121	/** @} */
1122
1123	/**
1124	* Page table.
1125	*/
1126	typedef struct X86PT
1127	{
1128	/** PTE Array. */
1129	X86PTE a[X86_PG_ENTRIES];
1130	} X86PT;
1131	/** Pointer to a page table. */
1132	typedef X86PT *PX86PT;
1133	/** Pointer to a const page table. */
1134	typedef const X86PT *PCX86PT;
1135
1136	/** The page shift to get the PT index. */
1137	#define X86_PT_SHIFT 12
1138	/** The PT index mask (apply to a shifted page address). */
1139	#define X86_PT_MASK 0x3ff
1140
1141
1142	/**
1143	* Page directory.
1144	*/
1145	typedef struct X86PTPAE
1146	{
1147	/** PTE Array. */
1148	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1149	} X86PTPAE;
1150	/** Pointer to a page table. */
1151	typedef X86PTPAE *PX86PTPAE;
1152	/** Pointer to a const page table. */
1153	typedef const X86PTPAE *PCX86PTPAE;
1154
1155	/** The page shift to get the PA PTE index. */
1156	#define X86_PT_PAE_SHIFT 12
1157	/** The PAE PT index mask (apply to a shifted page address). */
1158	#define X86_PT_PAE_MASK 0x1ff
1159
1160
1161	/** @name 4KB Page Directory Entry
1162	* @{
1163	*/
1164	/** Bit 0 - P - Present bit. */
1165	#define X86_PDE_P RT_BIT(0)
1166	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1167	#define X86_PDE_RW RT_BIT(1)
1168	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1169	#define X86_PDE_US RT_BIT(2)
1170	/** Bit 3 - PWT - Page level write thru bit. */
1171	#define X86_PDE_PWT RT_BIT(3)
1172	/** Bit 4 - PCD - Page level cache disable bit. */
1173	#define X86_PDE_PCD RT_BIT(4)
1174	/** Bit 5 - A - Access bit. */
1175	#define X86_PDE_A RT_BIT(5)
1176	/** Bit 7 - PS - Page size attribute.
1177	* Clear mean 4KB pages, set means large pages (2/4MB). */
1178	#define X86_PDE_PS RT_BIT(7)
1179	/** Bits 9-11 - - Available for use to system software. */
1180	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1181	/** Bits 12-31 - - Physical Page number of the next level. */
1182	#define X86_PDE_PG_MASK ( 0xfffff000 )
1183
1184	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1185	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1186	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1187	* we partly or that part into shadow page table entries. Will be corrected
1188	* soon.
1189	*/
1190	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1191	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1192	#else
1193	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1194	#endif
1195	/** Bits 63 - NX - PAE - No execution flag. */
1196	#define X86_PDE_PAE_NX RT_BIT_64(63)
1197
1198	/**
1199	* Page directory entry.
1200	*/
1201	typedef struct X86PDEBITS
1202	{
1203	/** Flags whether(=1) or not the page is present. */
1204	unsigned u1Present : 1;
1205	/** Read(=0) / Write(=1) flag. */
1206	unsigned u1Write : 1;
1207	/** User(=1) / Supervisor (=0) flag. */
1208	unsigned u1User : 1;
1209	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1210	unsigned u1WriteThru : 1;
1211	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1212	unsigned u1CacheDisable : 1;
1213	/** Accessed flag.
1214	* Indicates that the page have been read or written to. */
1215	unsigned u1Accessed : 1;
1216	/** Reserved / Ignored (dirty bit). */
1217	unsigned u1Reserved0 : 1;
1218	/** Size bit if PSE is enabled - in any event it's 0. */
1219	unsigned u1Size : 1;
1220	/** Reserved / Ignored (global bit). */
1221	unsigned u1Reserved1 : 1;
1222	/** Available for use to system software. */
1223	unsigned u3Available : 3;
1224	/** Physical Page number of the next level. */
1225	unsigned u20PageNo : 20;
1226	} X86PDEBITS;
1227	/** Pointer to a page directory entry. */
1228	typedef X86PDEBITS *PX86PDEBITS;
1229	/** Pointer to a const page directory entry. */
1230	typedef const X86PDEBITS *PCX86PDEBITS;
1231
1232
1233	/**
1234	* PAE page directory entry.
1235	*/
1236	typedef struct X86PDEPAEBITS
1237	{
1238	/** Flags whether(=1) or not the page is present. */
1239	uint32_t u1Present : 1;
1240	/** Read(=0) / Write(=1) flag. */
1241	uint32_t u1Write : 1;
1242	/** User(=1) / Supervisor (=0) flag. */
1243	uint32_t u1User : 1;
1244	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1245	uint32_t u1WriteThru : 1;
1246	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1247	uint32_t u1CacheDisable : 1;
1248	/** Accessed flag.
1249	* Indicates that the page have been read or written to. */
1250	uint32_t u1Accessed : 1;
1251	/** Reserved / Ignored (dirty bit). */
1252	uint32_t u1Reserved0 : 1;
1253	/** Size bit if PSE is enabled - in any event it's 0. */
1254	uint32_t u1Size : 1;
1255	/** Reserved / Ignored (global bit). / */
1256	uint32_t u1Reserved1 : 1;
1257	/** Available for use to system software. */
1258	uint32_t u3Available : 3;
1259	/** Physical Page number of the next level - Low Part. Don't use! */
1260	uint32_t u20PageNoLow : 20;
1261	/** Physical Page number of the next level - High Part. Don't use! */
1262	uint32_t u20PageNoHigh : 20;
1263	/** MBZ bits */
1264	uint32_t u11Reserved : 11;
1265	/** No Execute flag. */
1266	uint32_t u1NoExecute : 1;
1267	} X86PDEPAEBITS;
1268	/** Pointer to a page directory entry. */
1269	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1270	/** Pointer to a const page directory entry. */
1271	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1272
1273	/** @} */
1274
1275
1276	/** @name 2/4MB Page Directory Entry
1277	* @{
1278	*/
1279	/** Bit 0 - P - Present bit. */
1280	#define X86_PDE4M_P RT_BIT(0)
1281	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1282	#define X86_PDE4M_RW RT_BIT(1)
1283	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1284	#define X86_PDE4M_US RT_BIT(2)
1285	/** Bit 3 - PWT - Page level write thru bit. */
1286	#define X86_PDE4M_PWT RT_BIT(3)
1287	/** Bit 4 - PCD - Page level cache disable bit. */
1288	#define X86_PDE4M_PCD RT_BIT(4)
1289	/** Bit 5 - A - Access bit. */
1290	#define X86_PDE4M_A RT_BIT(5)
1291	/** Bit 6 - D - Dirty bit. */
1292	#define X86_PDE4M_D RT_BIT(6)
1293	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1294	#define X86_PDE4M_PS RT_BIT(7)
1295	/** Bit 8 - G - Global flag. */
1296	#define X86_PDE4M_G RT_BIT(8)
1297	/** Bits 9-11 - AVL - Available for use to system software. */
1298	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1299	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1300	#define X86_PDE4M_PAT RT_BIT(12)
1301	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1302	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1303	/** Bits 22-31 - - Physical Page number. */
1304	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1305	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1306	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1307	/** The number of bits to the high part of the page number. */
1308	#define X86_PDE4M_PG_HIGH_SHIFT 19
1309
1310	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1311	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1312	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1313	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1314	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1315
1316	/**
1317	* 4MB page directory entry.
1318	*/
1319	typedef struct X86PDE4MBITS
1320	{
1321	/** Flags whether(=1) or not the page is present. */
1322	unsigned u1Present : 1;
1323	/** Read(=0) / Write(=1) flag. */
1324	unsigned u1Write : 1;
1325	/** User(=1) / Supervisor (=0) flag. */
1326	unsigned u1User : 1;
1327	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1328	unsigned u1WriteThru : 1;
1329	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1330	unsigned u1CacheDisable : 1;
1331	/** Accessed flag.
1332	* Indicates that the page have been read or written to. */
1333	unsigned u1Accessed : 1;
1334	/** Dirty flag.
1335	* Indicates that the page have been written to. */
1336	unsigned u1Dirty : 1;
1337	/** Page size flag - always 1 for 4MB entries. */
1338	unsigned u1Size : 1;
1339	/** Global flag. */
1340	unsigned u1Global : 1;
1341	/** Available for use to system software. */
1342	unsigned u3Available : 3;
1343	/** Reserved / If PAT enabled, bit 2 of the index. */
1344	unsigned u1PAT : 1;
1345	/** Bits 32-39 of the page number on AMD64.
1346	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1347	unsigned u8PageNoHigh : 8;
1348	/** Reserved. */
1349	unsigned u1Reserved : 1;
1350	/** Physical Page number of the page. */
1351	unsigned u10PageNo : 10;
1352	} X86PDE4MBITS;
1353	/** Pointer to a page table entry. */
1354	typedef X86PDE4MBITS *PX86PDE4MBITS;
1355	/** Pointer to a const page table entry. */
1356	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1357
1358
1359	/**
1360	* 2MB PAE page directory entry.
1361	*/
1362	typedef struct X86PDE2MPAEBITS
1363	{
1364	/** Flags whether(=1) or not the page is present. */
1365	uint32_t u1Present : 1;
1366	/** Read(=0) / Write(=1) flag. */
1367	uint32_t u1Write : 1;
1368	/** User(=1) / Supervisor(=0) flag. */
1369	uint32_t u1User : 1;
1370	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1371	uint32_t u1WriteThru : 1;
1372	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1373	uint32_t u1CacheDisable : 1;
1374	/** Accessed flag.
1375	* Indicates that the page have been read or written to. */
1376	uint32_t u1Accessed : 1;
1377	/** Dirty flag.
1378	* Indicates that the page have been written to. */
1379	uint32_t u1Dirty : 1;
1380	/** Page size flag - always 1 for 2MB entries. */
1381	uint32_t u1Size : 1;
1382	/** Global flag. */
1383	uint32_t u1Global : 1;
1384	/** Available for use to system software. */
1385	uint32_t u3Available : 3;
1386	/** Reserved / If PAT enabled, bit 2 of the index. */
1387	uint32_t u1PAT : 1;
1388	/** Reserved. */
1389	uint32_t u9Reserved : 9;
1390	/** Physical Page number of the next level - Low part. Don't use! */
1391	uint32_t u10PageNoLow : 10;
1392	/** Physical Page number of the next level - High part. Don't use! */
1393	uint32_t u20PageNoHigh : 20;
1394	/** MBZ bits */
1395	uint32_t u11Reserved : 11;
1396	/** No Execute flag. */
1397	uint32_t u1NoExecute : 1;
1398	} X86PDE2MPAEBITS;
1399	/** Pointer to a 4MB PAE page table entry. */
1400	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1401	/** Pointer to a 4MB PAE page table entry. */
1402	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1403
1404	/** @} */
1405
1406	/**
1407	* Page directory entry.
1408	*/
1409	typedef union X86PDE
1410	{
1411	/** Normal view. */
1412	X86PDEBITS n;
1413	/** 4MB view (big). */
1414	X86PDE4MBITS b;
1415	/** Unsigned integer view. */
1416	X86PGUINT u;
1417	/** 8 bit unsigned integer view. */
1418	uint8_t au8[4];
1419	/** 16 bit unsigned integer view. */
1420	uint16_t au16[2];
1421	/** 32 bit unsigned integer view. */
1422	uint32_t au32[1];
1423	} X86PDE;
1424	/** Pointer to a page directory entry. */
1425	typedef X86PDE *PX86PDE;
1426	/** Pointer to a const page directory entry. */
1427	typedef const X86PDE *PCX86PDE;
1428
1429	/**
1430	* PAE page directory entry.
1431	*/
1432	typedef union X86PDEPAE
1433	{
1434	/** Normal view. */
1435	X86PDEPAEBITS n;
1436	/** 2MB page view (big). */
1437	X86PDE2MPAEBITS b;
1438	/** Unsigned integer view. */
1439	X86PGPAEUINT u;
1440	/** 8 bit unsigned integer view. */
1441	uint8_t au8[8];
1442	/** 16 bit unsigned integer view. */
1443	uint16_t au16[4];
1444	/** 32 bit unsigned integer view. */
1445	uint32_t au32[2];
1446	} X86PDEPAE;
1447	/** Pointer to a page directory entry. */
1448	typedef X86PDEPAE *PX86PDEPAE;
1449	/** Pointer to a const page directory entry. */
1450	typedef const X86PDEPAE *PCX86PDEPAE;
1451
1452	/**
1453	* Page directory.
1454	*/
1455	typedef struct X86PD
1456	{
1457	/** PDE Array. */
1458	X86PDE a[X86_PG_ENTRIES];
1459	} X86PD;
1460	/** Pointer to a page directory. */
1461	typedef X86PD *PX86PD;
1462	/** Pointer to a const page directory. */
1463	typedef const X86PD *PCX86PD;
1464
1465	/** The page shift to get the PD index. */
1466	#define X86_PD_SHIFT 22
1467	/** The PD index mask (apply to a shifted page address). */
1468	#define X86_PD_MASK 0x3ff
1469
1470
1471	/**
1472	* PAE page directory.
1473	*/
1474	typedef struct X86PDPAE
1475	{
1476	/** PDE Array. */
1477	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1478	} X86PDPAE;
1479	/** Pointer to a PAE page directory. */
1480	typedef X86PDPAE *PX86PDPAE;
1481	/** Pointer to a const PAE page directory. */
1482	typedef const X86PDPAE *PCX86PDPAE;
1483
1484	/** The page shift to get the PAE PD index. */
1485	#define X86_PD_PAE_SHIFT 21
1486	/** The PAE PD index mask (apply to a shifted page address). */
1487	#define X86_PD_PAE_MASK 0x1ff
1488
1489
1490	/** @name Page Directory Pointer Table Entry (PAE)
1491	* @{
1492	*/
1493	/** Bit 0 - P - Present bit. */
1494	#define X86_PDPE_P RT_BIT(0)
1495	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1496	#define X86_PDPE_RW RT_BIT(1)
1497	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1498	#define X86_PDPE_US RT_BIT(2)
1499	/** Bit 3 - PWT - Page level write thru bit. */
1500	#define X86_PDPE_PWT RT_BIT(3)
1501	/** Bit 4 - PCD - Page level cache disable bit. */
1502	#define X86_PDPE_PCD RT_BIT(4)
1503	/** Bit 5 - A - Access bit. Long Mode only. */
1504	#define X86_PDPE_A RT_BIT(5)
1505	/** Bits 9-11 - - Available for use to system software. */
1506	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1507	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1508	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1509	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1510	/** @todo Get rid of the above hack; makes code unreadable. */
1511	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1512	#else
1513	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1514	#endif
1515	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1516	#define X86_PDPE_NX RT_BIT_64(63)
1517
1518	/**
1519	* Page directory pointer table entry.
1520	*/
1521	typedef struct X86PDPEBITS
1522	{
1523	/** Flags whether(=1) or not the page is present. */
1524	uint32_t u1Present : 1;
1525	/** Chunk of reserved bits. */
1526	uint32_t u2Reserved : 2;
1527	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1528	uint32_t u1WriteThru : 1;
1529	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1530	uint32_t u1CacheDisable : 1;
1531	/** Chunk of reserved bits. */
1532	uint32_t u4Reserved : 4;
1533	/** Available for use to system software. */
1534	uint32_t u3Available : 3;
1535	/** Physical Page number of the next level - Low Part. Don't use! */
1536	uint32_t u20PageNoLow : 20;
1537	/** Physical Page number of the next level - High Part. Don't use! */
1538	uint32_t u20PageNoHigh : 20;
1539	/** MBZ bits */
1540	uint32_t u12Reserved : 12;
1541	} X86PDPEBITS;
1542	/** Pointer to a page directory pointer table entry. */
1543	typedef X86PDPEBITS *PX86PTPEBITS;
1544	/** Pointer to a const page directory pointer table entry. */
1545	typedef const X86PDPEBITS *PCX86PTPEBITS;
1546
1547	/**
1548	* Page directory pointer table entry. AMD64 version
1549	*/
1550	typedef struct X86PDPEAMD64BITS
1551	{
1552	/** Flags whether(=1) or not the page is present. */
1553	uint32_t u1Present : 1;
1554	/** Read(=0) / Write(=1) flag. */
1555	uint32_t u1Write : 1;
1556	/** User(=1) / Supervisor (=0) flag. */
1557	uint32_t u1User : 1;
1558	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1559	uint32_t u1WriteThru : 1;
1560	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1561	uint32_t u1CacheDisable : 1;
1562	/** Accessed flag.
1563	* Indicates that the page have been read or written to. */
1564	uint32_t u1Accessed : 1;
1565	/** Chunk of reserved bits. */
1566	uint32_t u3Reserved : 3;
1567	/** Available for use to system software. */
1568	uint32_t u3Available : 3;
1569	/** Physical Page number of the next level - Low Part. Don't use! */
1570	uint32_t u20PageNoLow : 20;
1571	/** Physical Page number of the next level - High Part. Don't use! */
1572	uint32_t u20PageNoHigh : 20;
1573	/** MBZ bits */
1574	uint32_t u11Reserved : 11;
1575	/** No Execute flag. */
1576	uint32_t u1NoExecute : 1;
1577	} X86PDPEAMD64BITS;
1578	/** Pointer to a page directory pointer table entry. */
1579	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1580	/** Pointer to a const page directory pointer table entry. */
1581	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1582
1583	/**
1584	* Page directory pointer table entry.
1585	*/
1586	typedef union X86PDPE
1587	{
1588	/** Normal view. */
1589	X86PDPEBITS n;
1590	/** AMD64 view. */
1591	X86PDPEAMD64BITS lm;
1592	/** Unsigned integer view. */
1593	X86PGPAEUINT u;
1594	/** 8 bit unsigned integer view. */
1595	uint8_t au8[8];
1596	/** 16 bit unsigned integer view. */
1597	uint16_t au16[4];
1598	/** 32 bit unsigned integer view. */
1599	uint32_t au32[2];
1600	} X86PDPE;
1601	/** Pointer to a page directory pointer table entry. */
1602	typedef X86PDPE *PX86PDPE;
1603	/** Pointer to a const page directory pointer table entry. */
1604	typedef const X86PDPE *PCX86PDPE;
1605
1606
1607	/**
1608	* Page directory pointer table.
1609	*/
1610	typedef struct X86PDPT
1611	{
1612	/** PDE Array. */
1613	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1614	} X86PDPT;
1615	/** Pointer to a page directory pointer table. */
1616	typedef X86PDPT *PX86PDPT;
1617	/** Pointer to a const page directory pointer table. */
1618	typedef const X86PDPT *PCX86PDPT;
1619
1620	/** The page shift to get the PDPT index. */
1621	#define X86_PDPT_SHIFT 30
1622	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1623	#define X86_PDPT_MASK_PAE 0x3
1624	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1625	#define X86_PDPT_MASK_AMD64 0x1ff
1626
1627	/** @} */
1628
1629
1630	/** @name Page Map Level-4 Entry (Long Mode PAE)
1631	* @{
1632	*/
1633	/** Bit 0 - P - Present bit. */
1634	#define X86_PML4E_P RT_BIT(0)
1635	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1636	#define X86_PML4E_RW RT_BIT(1)
1637	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1638	#define X86_PML4E_US RT_BIT(2)
1639	/** Bit 3 - PWT - Page level write thru bit. */
1640	#define X86_PML4E_PWT RT_BIT(3)
1641	/** Bit 4 - PCD - Page level cache disable bit. */
1642	#define X86_PML4E_PCD RT_BIT(4)
1643	/** Bit 5 - A - Access bit. */
1644	#define X86_PML4E_A RT_BIT(5)
1645	/** Bits 9-11 - - Available for use to system software. */
1646	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1647	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1648	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1649	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1650	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1651	#else
1652	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1653	#endif
1654	/** Bits 63 - NX - PAE - No execution flag. */
1655	#define X86_PML4E_NX RT_BIT_64(63)
1656
1657	/**
1658	* Page Map Level-4 Entry
1659	*/
1660	typedef struct X86PML4EBITS
1661	{
1662	/** Flags whether(=1) or not the page is present. */
1663	uint32_t u1Present : 1;
1664	/** Read(=0) / Write(=1) flag. */
1665	uint32_t u1Write : 1;
1666	/** User(=1) / Supervisor (=0) flag. */
1667	uint32_t u1User : 1;
1668	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1669	uint32_t u1WriteThru : 1;
1670	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1671	uint32_t u1CacheDisable : 1;
1672	/** Accessed flag.
1673	* Indicates that the page have been read or written to. */
1674	uint32_t u1Accessed : 1;
1675	/** Chunk of reserved bits. */
1676	uint32_t u3Reserved : 3;
1677	/** Available for use to system software. */
1678	uint32_t u3Available : 3;
1679	/** Physical Page number of the next level - Low Part. Don't use! */
1680	uint32_t u20PageNoLow : 20;
1681	/** Physical Page number of the next level - High Part. Don't use! */
1682	uint32_t u20PageNoHigh : 20;
1683	/** MBZ bits */
1684	uint32_t u11Reserved : 11;
1685	/** No Execute flag. */
1686	uint32_t u1NoExecute : 1;
1687	} X86PML4EBITS;
1688	/** Pointer to a page map level-4 entry. */
1689	typedef X86PML4EBITS *PX86PML4EBITS;
1690	/** Pointer to a const page map level-4 entry. */
1691	typedef const X86PML4EBITS *PCX86PML4EBITS;
1692
1693	/**
1694	* Page Map Level-4 Entry.
1695	*/
1696	typedef union X86PML4E
1697	{
1698	/** Normal view. */
1699	X86PML4EBITS n;
1700	/** Unsigned integer view. */
1701	X86PGPAEUINT u;
1702	/** 8 bit unsigned integer view. */
1703	uint8_t au8[8];
1704	/** 16 bit unsigned integer view. */
1705	uint16_t au16[4];
1706	/** 32 bit unsigned integer view. */
1707	uint32_t au32[2];
1708	} X86PML4E;
1709	/** Pointer to a page map level-4 entry. */
1710	typedef X86PML4E *PX86PML4E;
1711	/** Pointer to a const page map level-4 entry. */
1712	typedef const X86PML4E *PCX86PML4E;
1713
1714
1715	/**
1716	* Page Map Level-4.
1717	*/
1718	typedef struct X86PML4
1719	{
1720	/** PDE Array. */
1721	X86PML4E a[X86_PG_PAE_ENTRIES];
1722	} X86PML4;
1723	/** Pointer to a page map level-4. */
1724	typedef X86PML4 *PX86PML4;
1725	/** Pointer to a const page map level-4. */
1726	typedef const X86PML4 *PCX86PML4;
1727
1728	/** The page shift to get the PML4 index. */
1729	#define X86_PML4_SHIFT 39
1730	/** The PML4 index mask (apply to a shifted page address). */
1731	#define X86_PML4_MASK 0x1ff
1732
1733	/** @} */
1734
1735	/** @} */
1736
1737
1738	/**
1739	* 80-bit MMX/FPU register type.
1740	*/
1741	typedef struct X86FPUMMX
1742	{
1743	uint8_t reg[10];
1744	} X86FPUMMX;
1745	/** Pointer to a 80-bit MMX/FPU register type. */
1746	typedef X86FPUMMX *PX86FPUMMX;
1747	/** Pointer to a const 80-bit MMX/FPU register type. */
1748	typedef const X86FPUMMX *PCX86FPUMMX;
1749
1750	/**
1751	* FPU state (aka FSAVE/FRSTOR Memory Region).
1752	*/
1753	#pragma pack(1)
1754	typedef struct X86FPUSTATE
1755	{
1756	/** Control word. */
1757	uint16_t FCW;
1758	/** Alignment word */
1759	uint16_t Dummy1;
1760	/** Status word. */
1761	uint16_t FSW;
1762	/** Alignment word */
1763	uint16_t Dummy2;
1764	/** Tag word */
1765	uint16_t FTW;
1766	/** Alignment word */
1767	uint16_t Dummy3;
1768
1769	/** Instruction pointer. */
1770	uint32_t FPUIP;
1771	/** Code selector. */
1772	uint16_t CS;
1773	/** Opcode. */
1774	uint16_t FOP;
1775	/** FOO. */
1776	uint32_t FPUOO;
1777	/** FOS. */
1778	uint32_t FPUOS;
1779	/** FPU view - todo. */
1780	X86FPUMMX regs[8];
1781	} X86FPUSTATE;
1782	#pragma pack()
1783	/** Pointer to a FPU state. */
1784	typedef X86FPUSTATE *PX86FPUSTATE;
1785	/** Pointer to a const FPU state. */
1786	typedef const X86FPUSTATE *PCX86FPUSTATE;
1787
1788	/**
1789	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1790	*/
1791	#pragma pack(1)
1792	typedef struct X86FXSTATE
1793	{
1794	/** Control word. */
1795	uint16_t FCW;
1796	/** Status word. */
1797	uint16_t FSW;
1798	/** Tag word (it's a byte actually). */
1799	uint8_t FTW;
1800	uint8_t huh1;
1801	/** Opcode. */
1802	uint16_t FOP;
1803	/** Instruction pointer. */
1804	uint32_t FPUIP;
1805	/** Code selector. */
1806	uint16_t CS;
1807	uint16_t Rsvrd1;
1808	/* - offset 16 - */
1809	/** Data pointer. */
1810	uint32_t FPUDP;
1811	/** Data segment */
1812	uint16_t DS;
1813	uint16_t Rsrvd2;
1814	uint32_t MXCSR;
1815	uint32_t MXCSR_MASK;
1816	/* - offset 32 - */
1817	union
1818	{
1819	/** MMX view. */
1820	uint64_t mmx;
1821	/** FPU view - todo. */
1822	X86FPUMMX fpu;
1823	/** 8-bit view. */
1824	uint8_t au8[16];
1825	/** 16-bit view. */
1826	uint16_t au16[8];
1827	/** 32-bit view. */
1828	uint32_t au32[4];
1829	/** 64-bit view. */
1830	uint64_t au64[2];
1831	/** 128-bit view. (yeah, very helpful) */
1832	uint128_t au128[1];
1833	} aRegs[8];
1834	/* - offset 160 - */
1835	union
1836	{
1837	/** XMM Register view . /
1838	uint128_t xmm;
1839	/** 8-bit view. */
1840	uint8_t au8[16];
1841	/** 16-bit view. */
1842	uint16_t au16[8];
1843	/** 32-bit view. */
1844	uint32_t au32[4];
1845	/** 64-bit view. */
1846	uint64_t au64[2];
1847	/** 128-bit view. (yeah, very helpful) */
1848	uint128_t au128[1];
1849	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1850	/* - offset 416 - */
1851	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1852	} X86FXSTATE;
1853	#pragma pack()
1854	/** Pointer to a FPU Extended state. */
1855	typedef X86FXSTATE *PX86FXSTATE;
1856	/** Pointer to a const FPU Extended state. */
1857	typedef const X86FXSTATE *PCX86FXSTATE;
1858
1859
1860	/** @name Selector Descriptor
1861	* @{
1862	*/
1863
1864	/**
1865	* Generic descriptor table entry
1866	*/
1867	#pragma pack(1)
1868	typedef struct X86DESCGENERIC
1869	{
1870	/** Limit - Low word. */
1871	unsigned u16LimitLow : 16;
1872	/** Base address - lowe word.
1873	* Don't try set this to 24 because MSC is doing studing things then. */
1874	unsigned u16BaseLow : 16;
1875	/** Base address - first 8 bits of high word. */
1876	unsigned u8BaseHigh1 : 8;
1877	/** Segment Type. */
1878	unsigned u4Type : 4;
1879	/** Descriptor Type. System(=0) or code/data selector */
1880	unsigned u1DescType : 1;
1881	/** Descriptor Privelege level. */
1882	unsigned u2Dpl : 2;
1883	/** Flags selector present(=1) or not. */
1884	unsigned u1Present : 1;
1885	/** Segment limit 16-19. */
1886	unsigned u4LimitHigh : 4;
1887	/** Available for system software. */
1888	unsigned u1Available : 1;
1889	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1890	unsigned u1Long : 1;
1891	/** This flags meaning depends on the segment type. Try make sense out
1892	* of the intel manual yourself. */
1893	unsigned u1DefBig : 1;
1894	/** Granularity of the limit. If set 4KB granularity is used, if
1895	* clear byte. */
1896	unsigned u1Granularity : 1;
1897	/** Base address - highest 8 bits. */
1898	unsigned u8BaseHigh2 : 8;
1899	} X86DESCGENERIC;
1900	#pragma pack()
1901	/** Pointer to a generic descriptor entry. */
1902	typedef X86DESCGENERIC *PX86DESCGENERIC;
1903	/** Pointer to a const generic descriptor entry. */
1904	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1905
1906
1907	/**
1908	* Descriptor attributes.
1909	*/
1910	typedef struct X86DESCATTRBITS
1911	{
1912	/** Segment Type. */
1913	unsigned u4Type : 4;
1914	/** Descriptor Type. System(=0) or code/data selector */
1915	unsigned u1DescType : 1;
1916	/** Descriptor Privelege level. */
1917	unsigned u2Dpl : 2;
1918	/** Flags selector present(=1) or not. */
1919	unsigned u1Present : 1;
1920	/** Segment limit 16-19. */
1921	unsigned u4LimitHigh : 4;
1922	/** Available for system software. */
1923	unsigned u1Available : 1;
1924	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1925	unsigned u1Long : 1;
1926	/** This flags meaning depends on the segment type. Try make sense out
1927	* of the intel manual yourself. */
1928	unsigned u1DefBig : 1;
1929	/** Granularity of the limit. If set 4KB granularity is used, if
1930	* clear byte. */
1931	unsigned u1Granularity : 1;
1932	} X86DESCATTRBITS;
1933
1934
1935	#pragma pack(1)
1936	typedef union X86DESCATTR
1937	{
1938	/** Normal view. */
1939	X86DESCATTRBITS n;
1940	/** Unsigned integer view. */
1941	uint32_t u;
1942	} X86DESCATTR;
1943	#pragma pack()
1944
1945	/** Pointer to descriptor attributes. */
1946	typedef X86DESCATTR *PX86DESCATTR;
1947	/** Pointer to const descriptor attributes. */
1948	typedef const X86DESCATTR *PCX86DESCATTR;
1949
1950
1951	/**
1952	* Descriptor table entry.
1953	*/
1954	#pragma pack(1)
1955	typedef union X86DESC
1956	{
1957	/** Generic descriptor view. */
1958	X86DESCGENERIC Gen;
1959	#if 0
1960	/** IDT view. */
1961	VBOXIDTE Idt;
1962	#endif
1963
1964	/** 8 bit unsigned interger view. */
1965	uint8_t au8[8];
1966	/** 16 bit unsigned interger view. */
1967	uint16_t au16[4];
1968	/** 32 bit unsigned interger view. */
1969	uint32_t au32[2];
1970	} X86DESC;
1971	#pragma pack()
1972	/** Pointer to descriptor table entry. */
1973	typedef X86DESC *PX86DESC;
1974	/** Pointer to const descriptor table entry. */
1975	typedef const X86DESC *PCX86DESC;
1976
1977
1978	/** @def X86DESC_BASE
1979	* Return the base address of a descriptor.
1980	*/
1981	#define X86DESC_BASE(desc) \
1982	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
1983	\| ( (desc).Gen.u8BaseHigh1 << 16) \
1984	\| ( (desc).Gen.u16BaseLow ) )
1985
1986	/** @def X86DESC_LIMIT
1987	* Return the limit of a descriptor.
1988	*/
1989	#define X86DESC_LIMIT(desc) \
1990	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
1991	\| ( (desc).Gen.u16LimitLow ) )
1992
1993	/**
1994	* 64 bits generic descriptor table entry
1995	* Note: most of these bits have no meaning in long mode.
1996	*/
1997	#pragma pack(1)
1998	typedef struct X86DESC64GENERIC
1999	{
2000	/** Limit - Low word - IGNORED. */
2001	unsigned u16LimitLow : 16;
2002	/** Base address - lowe word. - IGNORED
2003	* Don't try set this to 24 because MSC is doing studing things then. */
2004	unsigned u16BaseLow : 16;
2005	/** Base address - first 8 bits of high word. - IGNORED */
2006	unsigned u8BaseHigh1 : 8;
2007	/** Segment Type. */
2008	unsigned u4Type : 4;
2009	/** Descriptor Type. System(=0) or code/data selector */
2010	unsigned u1DescType : 1;
2011	/** Descriptor Privelege level. */
2012	unsigned u2Dpl : 2;
2013	/** Flags selector present(=1) or not. */
2014	unsigned u1Present : 1;
2015	/** Segment limit 16-19. - IGNORED */
2016	unsigned u4LimitHigh : 4;
2017	/** Available for system software. - IGNORED */
2018	unsigned u1Available : 1;
2019	/** Long mode flag. */
2020	unsigned u1Long : 1;
2021	/** This flags meaning depends on the segment type. Try make sense out
2022	* of the intel manual yourself. */
2023	unsigned u1DefBig : 1;
2024	/** Granularity of the limit. If set 4KB granularity is used, if
2025	* clear byte. - IGNORED */
2026	unsigned u1Granularity : 1;
2027	/** Base address - highest 8 bits. - IGNORED */
2028	unsigned u8BaseHigh2 : 8;
2029	/** Base address - bits 63-32. */
2030	unsigned u32BaseHigh3 : 32;
2031	unsigned u8Reserved : 8;
2032	unsigned u5Zeros : 5;
2033	unsigned u19Reserved : 19;
2034	} X86DESC64GENERIC;
2035	#pragma pack()
2036	/** Pointer to a generic descriptor entry. */
2037	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2038	/** Pointer to a const generic descriptor entry. */
2039	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2040
2041	/**
2042	* System descriptor table entry (64 bits)
2043	*/
2044	#pragma pack(1)
2045	typedef struct X86DESC64SYSTEM
2046	{
2047	/** Limit - Low word. */
2048	unsigned u16LimitLow : 16;
2049	/** Base address - lowe word.
2050	* Don't try set this to 24 because MSC is doing studing things then. */
2051	unsigned u16BaseLow : 16;
2052	/** Base address - first 8 bits of high word. */
2053	unsigned u8BaseHigh1 : 8;
2054	/** Segment Type. */
2055	unsigned u4Type : 4;
2056	/** Descriptor Type. System(=0) or code/data selector */
2057	unsigned u1DescType : 1;
2058	/** Descriptor Privelege level. */
2059	unsigned u2Dpl : 2;
2060	/** Flags selector present(=1) or not. */
2061	unsigned u1Present : 1;
2062	/** Segment limit 16-19. */
2063	unsigned u4LimitHigh : 4;
2064	/** Available for system software. */
2065	unsigned u1Available : 1;
2066	/** Reserved - 0. */
2067	unsigned u1Reserved : 1;
2068	/** This flags meaning depends on the segment type. Try make sense out
2069	* of the intel manual yourself. */
2070	unsigned u1DefBig : 1;
2071	/** Granularity of the limit. If set 4KB granularity is used, if
2072	* clear byte. */
2073	unsigned u1Granularity : 1;
2074	/** Base address - bits 31-24. */
2075	unsigned u8BaseHigh2 : 8;
2076	/** Base address - bits 63-32. */
2077	unsigned u32BaseHigh3 : 32;
2078	unsigned u8Reserved : 8;
2079	unsigned u5Zeros : 5;
2080	unsigned u19Reserved : 19;
2081	} X86DESC64SYSTEM;
2082	#pragma pack()
2083	/** Pointer to a generic descriptor entry. */
2084	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2085	/** Pointer to a const generic descriptor entry. */
2086	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2087
2088
2089	/**
2090	* Descriptor table entry.
2091	*/
2092	#pragma pack(1)
2093	typedef union X86DESC64
2094	{
2095	/** Generic descriptor view. */
2096	X86DESC64GENERIC Gen;
2097	/** System descriptor view. */
2098	X86DESC64SYSTEM System;
2099	#if 0
2100	X86DESC64GATE Gate;
2101	#endif
2102
2103	/** 8 bit unsigned interger view. */
2104	uint8_t au8[16];
2105	/** 16 bit unsigned interger view. */
2106	uint16_t au16[8];
2107	/** 32 bit unsigned interger view. */
2108	uint32_t au32[4];
2109	/** 64 bit unsigned interger view. */
2110	uint64_t au64[2];
2111	} X86DESC64;
2112	#pragma pack()
2113	/** Pointer to descriptor table entry. */
2114	typedef X86DESC64 *PX86DESC64;
2115	/** Pointer to const descriptor table entry. */
2116	typedef const X86DESC64 *PCX86DESC64;
2117
2118	#if HC_ARCH_BITS == 64
2119	typedef X86DESC64 X86DESCHC;
2120	typedef X86DESC64 *PX86DESCHC;
2121	#else
2122	typedef X86DESC X86DESCHC;
2123	typedef X86DESC *PX86DESCHC;
2124	#endif
2125
2126	/** @def X86DESC_LIMIT
2127	* Return the base of a 64-bit descriptor.
2128	*/
2129	#define X86DESC64_BASE(desc) \
2130	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2131	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2132	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2133	\| ( (desc).Gen.u16BaseLow ) )
2134
2135
2136	/** @name Selector Descriptor Types.
2137	* @{
2138	*/
2139
2140	/** @name Non-System Selector Types.
2141	* @{ */
2142	/** Code(=set)/Data(=clear) bit. */
2143	#define X86_SEL_TYPE_CODE 8
2144	/** Memory(=set)/System(=clear) bit. */
2145	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2146	/** Accessed bit. */
2147	#define X86_SEL_TYPE_ACCESSED 1
2148	/** Expand down bit (for data selectors only). */
2149	#define X86_SEL_TYPE_DOWN 4
2150	/** Conforming bit (for code selectors only). */
2151	#define X86_SEL_TYPE_CONF 4
2152	/** Write bit (for data selectors only). */
2153	#define X86_SEL_TYPE_WRITE 2
2154	/** Read bit (for code selectors only). */
2155	#define X86_SEL_TYPE_READ 2
2156
2157	/** Read only selector type. */
2158	#define X86_SEL_TYPE_RO 0
2159	/** Accessed read only selector type. */
2160	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2161	/** Read write selector type. */
2162	#define X86_SEL_TYPE_RW 2
2163	/** Accessed read write selector type. */
2164	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2165	/** Expand down read only selector type. */
2166	#define X86_SEL_TYPE_RO_DOWN 4
2167	/** Accessed expand down read only selector type. */
2168	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2169	/** Expand down read write selector type. */
2170	#define X86_SEL_TYPE_RW_DOWN 6
2171	/** Accessed expand down read write selector type. */
2172	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2173	/** Execute only selector type. */
2174	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2175	/** Accessed execute only selector type. */
2176	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2177	/** Execute and read selector type. */
2178	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2179	/** Accessed execute and read selector type. */
2180	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2181	/** Conforming execute only selector type. */
2182	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2183	/** Accessed Conforming execute only selector type. */
2184	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2185	/** Conforming execute and write selector type. */
2186	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2187	/** Accessed Conforming execute and write selector type. */
2188	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2189	/** @} */
2190
2191
2192	/** @name System Selector Types.
2193	* @{ */
2194	/** Undefined system selector type. */
2195	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2196	/** 286 TSS selector. */
2197	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2198	/** LDT selector. */
2199	#define X86_SEL_TYPE_SYS_LDT 2
2200	/** 286 TSS selector - Busy. */
2201	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2202	/** 286 Callgate selector. */
2203	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2204	/** Taskgate selector. */
2205	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2206	/** 286 Interrupt gate selector. */
2207	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2208	/** 286 Trapgate selector. */
2209	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2210	/** Undefined system selector. */
2211	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2212	/** 386 TSS selector. */
2213	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2214	/** Undefined system selector. */
2215	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2216	/** 386 TSS selector - Busy. */
2217	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2218	/** 386 Callgate selector. */
2219	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2220	/** Undefined system selector. */
2221	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2222	/** 386 Interruptgate selector. */
2223	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2224	/** 386 Trapgate selector. */
2225	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2226	/** @} */
2227
2228	/** @name AMD64 System Selector Types.
2229	* @{ */
2230	#define AMD64_SEL_TYPE_SYS_LDT 2
2231	/** 286 TSS selector - Busy. */
2232	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2233	/** 386 TSS selector - Busy. */
2234	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2235	/** 386 Callgate selector. */
2236	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2237	/** 386 Interruptgate selector. */
2238	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2239	/** 386 Trapgate selector. */
2240	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2241	/** @} */
2242
2243	/** @} */
2244
2245
2246	/** @name Descriptor Table Entry Flag Masks.
2247	* These are for the 2nd 32-bit word of a descriptor.
2248	* @{ */
2249	/** Bits 8-11 - TYPE - Descriptor type mask. */
2250	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2251	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2252	#define X86_DESC_S RT_BIT(12)
2253	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2254	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2255	/** Bit 15 - P - Present. */
2256	#define X86_DESC_P RT_BIT(15)
2257	/** Bit 20 - AVL - Available for system software. */
2258	#define X86_DESC_AVL RT_BIT(20)
2259	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2260	#define X86_DESC_DB RT_BIT(22)
2261	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2262	* used, if clear byte. */
2263	#define X86_DESC_G RT_BIT(23)
2264	/** @} */
2265
2266	/** @} */
2267
2268
2269	/** @name Selectors.
2270	* @{
2271	*/
2272
2273	/**
2274	* The shift used to convert a selector from and to index an index (C).
2275	*/
2276	#define X86_SEL_SHIFT 3
2277
2278	/**
2279	* The shift used to convert a selector from and to index an index (C).
2280	*/
2281	#define AMD64_SEL_SHIFT 4
2282
2283	#if HC_ARCH_BITS == 64
2284	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2285	#else
2286	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2287	#endif
2288
2289	/**
2290	* The mask used to mask off the table indicator and CPL of an selector.
2291	*/
2292	#define X86_SEL_MASK 0xfff8
2293
2294	/**
2295	* The bit indicating that a selector is in the LDT and not in the GDT.
2296	*/
2297	#define X86_SEL_LDT 0x0004
2298	/**
2299	* The bit mask for getting the RPL of a selector.
2300	*/
2301	#define X86_SEL_RPL 0x0003
2302
2303	/** @} */
2304
2305
2306	/**
2307	* x86 Exceptions/Faults/Traps.
2308	*/
2309	typedef enum X86XCPT
2310	{
2311	/** \#DE - Divide error. */
2312	X86_XCPT_DE = 0x00,
2313	/** \#DB - Debug event (single step, DRx, ..) */
2314	X86_XCPT_DB = 0x01,
2315	/** NMI - Non-Maskable Interrupt */
2316	X86_XCPT_NMI = 0x02,
2317	/** \#BP - Breakpoint (INT3). */
2318	X86_XCPT_BP = 0x03,
2319	/** \#OF - Overflow (INTO). */
2320	X86_XCPT_OF = 0x04,
2321	/** \#BR - Bound range exceeded (BOUND). */
2322	X86_XCPT_BR = 0x05,
2323	/** \#UD - Undefined opcode. */
2324	X86_XCPT_UD = 0x06,
2325	/** \#NM - Device not available (math coprocessor device). */
2326	X86_XCPT_NM = 0x07,
2327	/** \#DF - Double fault. */
2328	X86_XCPT_DF = 0x08,
2329	/** ??? - Coprocessor segment overrun (obsolete). */
2330	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2331	/** \#TS - Taskswitch (TSS). */
2332	X86_XCPT_TS = 0x0a,
2333	/** \#NP - Segment no present. */
2334	X86_XCPT_NP = 0x0b,
2335	/** \#SS - Stack segment fault. */
2336	X86_XCPT_SS = 0x0c,
2337	/** \#GP - General protection fault. */
2338	X86_XCPT_GP = 0x0d,
2339	/** \#PF - Page fault. */
2340	X86_XCPT_PF = 0x0e,
2341	/* 0x0f is reserved. */
2342	/** \#MF - Math fault (FPU). */
2343	X86_XCPT_MF = 0x10,
2344	/** \#AC - Alignment check. */
2345	X86_XCPT_AC = 0x11,
2346	/** \#MC - Machine check. */
2347	X86_XCPT_MC = 0x12,
2348	/** \#XF - SIMD Floating-Pointer Exception. */
2349	X86_XCPT_XF = 0x13
2350	} X86XCPT;
2351	/** Pointer to a x86 exception code. */
2352	typedef X86XCPT *PX86XCPT;
2353	/** Pointer to a const x86 exception code. */
2354	typedef const X86XCPT *PCX86XCPT;
2355
2356
2357	/** @name Trap Error Codes
2358	* @{
2359	*/
2360	/** External indicator. */
2361	#define X86_TRAP_ERR_EXTERNAL 1
2362	/** IDT indicator. */
2363	#define X86_TRAP_ERR_IDT 2
2364	/** Descriptor table indicator - If set LDT, if clear GDT. */
2365	#define X86_TRAP_ERR_TI 4
2366	/** Mask for getting the selector. */
2367	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2368	/** Shift for getting the selector table index (C type index). */
2369	#define X86_TRAP_ERR_SEL_SHIFT 3
2370	/** @} */
2371
2372
2373	/** @name \#PF Trap Error Codes
2374	* @{
2375	*/
2376	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2377	#define X86_TRAP_PF_P RT_BIT(0)
2378	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2379	#define X86_TRAP_PF_RW RT_BIT(1)
2380	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2381	#define X86_TRAP_PF_US RT_BIT(2)
2382	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2383	#define X86_TRAP_PF_RSVD RT_BIT(3)
2384	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2385	#define X86_TRAP_PF_ID RT_BIT(4)
2386	/** @} */
2387
2388	#pragma pack(1)
2389	/**
2390	* 32-bit IDTR/GDTR.
2391	*/
2392	typedef struct X86XDTR32
2393	{
2394	/** Size of the descriptor table. */
2395	uint16_t cb;
2396	/** Address of the descriptor table. */
2397	uint32_t uAddr;
2398	} X86XDTR32, *PX86XDTR32;
2399	#pragma pack()
2400
2401	#pragma pack(1)
2402	/**
2403	* 64-bit IDTR/GDTR.
2404	*/
2405	typedef struct X86XDTR64
2406	{
2407	/** Size of the descriptor table. */
2408	uint16_t cb;
2409	/** Address of the descriptor table. */
2410	uint64_t uAddr;
2411	} X86XDTR64, *PX86XDTR64;
2412	#pragma pack()
2413
2414	/** @} */
2415
2416	#endif
2417

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source: vbox/trunk/include/VBox/x86.h@ 12971

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