x86.h@ 27084

Last change on this file since 27084 was 26993, checked in by vboxsync, 15 years ago
VMM: implement some Nehalem MSRs
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1	/** @file
2	* X86 (and AMD64) Structures and Definitions (VMM,++).
3	*
4	* x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*
27	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
28	* Clara, CA 95054 USA or visit http://www.sun.com if you need
29	* additional information or have any questions.
30	*/
31
32	#ifndef ___VBox_x86_h
33	#define ___VBox_x86_h
34
35	#include <VBox/types.h>
36	#include <iprt/assert.h>
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_x86 x86 Types and Definitions
45	* @{
46	*/
47
48	/**
49	* EFLAGS Bits.
50	*/
51	typedef struct X86EFLAGSBITS
52	{
53	/** Bit 0 - CF - Carry flag - Status flag. */
54	unsigned u1CF : 1;
55	/** Bit 1 - 1 - Reserved flag. */
56	unsigned u1Reserved0 : 1;
57	/** Bit 2 - PF - Parity flag - Status flag. */
58	unsigned u1PF : 1;
59	/** Bit 3 - 0 - Reserved flag. */
60	unsigned u1Reserved1 : 1;
61	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
62	unsigned u1AF : 1;
63	/** Bit 5 - 0 - Reserved flag. */
64	unsigned u1Reserved2 : 1;
65	/** Bit 6 - ZF - Zero flag - Status flag. */
66	unsigned u1ZF : 1;
67	/** Bit 7 - SF - Signed flag - Status flag. */
68	unsigned u1SF : 1;
69	/** Bit 8 - TF - Trap flag - System flag. */
70	unsigned u1TF : 1;
71	/** Bit 9 - IF - Interrupt flag - System flag. */
72	unsigned u1IF : 1;
73	/** Bit 10 - DF - Direction flag - Control flag. */
74	unsigned u1DF : 1;
75	/** Bit 11 - OF - Overflow flag - Status flag. */
76	unsigned u1OF : 1;
77	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
78	unsigned u2IOPL : 2;
79	/** Bit 14 - NT - Nested task flag - System flag. */
80	unsigned u1NT : 1;
81	/** Bit 15 - 0 - Reserved flag. */
82	unsigned u1Reserved3 : 1;
83	/** Bit 16 - RF - Resume flag - System flag. */
84	unsigned u1RF : 1;
85	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
86	unsigned u1VM : 1;
87	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
88	unsigned u1AC : 1;
89	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
90	unsigned u1VIF : 1;
91	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
92	unsigned u1VIP : 1;
93	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
94	unsigned u1ID : 1;
95	/** Bit 22-31 - 0 - Reserved flag. */
96	unsigned u10Reserved4 : 10;
97	} X86EFLAGSBITS;
98	/** Pointer to EFLAGS bits. */
99	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
100	/** Pointer to const EFLAGS bits. */
101	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
102
103	/**
104	* EFLAGS.
105	*/
106	typedef union X86EFLAGS
107	{
108	/** The plain unsigned view. */
109	uint32_t u;
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	} X86EFLAGS;
121	/** Pointer to EFLAGS. */
122	typedef X86EFLAGS *PX86EFLAGS;
123	/** Pointer to const EFLAGS. */
124	typedef const X86EFLAGS *PCX86EFLAGS;
125
126	/**
127	* RFLAGS (32 upper bits are reserved).
128	*/
129	typedef union X86RFLAGS
130	{
131	/** The plain unsigned view. */
132	uint64_t u;
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	} X86RFLAGS;
146	/** Pointer to RFLAGS. */
147	typedef X86RFLAGS *PX86RFLAGS;
148	/** Pointer to const RFLAGS. */
149	typedef const X86RFLAGS *PCX86RFLAGS;
150
151
152	/** @name EFLAGS
153	* @{
154	*/
155	/** Bit 0 - CF - Carry flag - Status flag. */
156	#define X86_EFL_CF RT_BIT(0)
157	/** Bit 2 - PF - Parity flag - Status flag. */
158	#define X86_EFL_PF RT_BIT(2)
159	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
160	#define X86_EFL_AF RT_BIT(4)
161	/** Bit 6 - ZF - Zero flag - Status flag. */
162	#define X86_EFL_ZF RT_BIT(6)
163	/** Bit 7 - SF - Signed flag - Status flag. */
164	#define X86_EFL_SF RT_BIT(7)
165	/** Bit 8 - TF - Trap flag - System flag. */
166	#define X86_EFL_TF RT_BIT(8)
167	/** Bit 9 - IF - Interrupt flag - System flag. */
168	#define X86_EFL_IF RT_BIT(9)
169	/** Bit 10 - DF - Direction flag - Control flag. */
170	#define X86_EFL_DF RT_BIT(10)
171	/** Bit 11 - OF - Overflow flag - Status flag. */
172	#define X86_EFL_OF RT_BIT(11)
173	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
174	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
175	/** Bit 14 - NT - Nested task flag - System flag. */
176	#define X86_EFL_NT RT_BIT(14)
177	/** Bit 16 - RF - Resume flag - System flag. */
178	#define X86_EFL_RF RT_BIT(16)
179	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
180	#define X86_EFL_VM RT_BIT(17)
181	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
182	#define X86_EFL_AC RT_BIT(18)
183	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
184	#define X86_EFL_VIF RT_BIT(19)
185	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
186	#define X86_EFL_VIP RT_BIT(20)
187	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
188	#define X86_EFL_ID RT_BIT(21)
189	/** IOPL shift. */
190	#define X86_EFL_IOPL_SHIFT 12
191	/** The the IOPL level from the flags. */
192	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
193	/** Bits restored by popf */
194	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u1Reserved1 : 1;
207	/** Bit 2 - DS Area 64-bit layout. */
208	unsigned u1DTE64 : 1;
209	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
210	unsigned u1Monitor : 1;
211	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
212	unsigned u1CPLDS : 1;
213	/** Bit 5 - VMX - Virtual Machine Technology. */
214	unsigned u1VMX : 1;
215	/** Bit 6 - SMX: Safer Mode Extensions. */
216	unsigned u1SMX : 1;
217	/** Bit 7 - EST - Enh. SpeedStep Tech. */
218	unsigned u1EST : 1;
219	/** Bit 8 - TM2 - Terminal Monitor 2. */
220	unsigned u1TM2 : 1;
221	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
222	unsigned u1SSSE3 : 1;
223	/** Bit 10 - CNTX-ID - L1 Context ID. */
224	unsigned u1CNTXID : 1;
225	/** Bit 11 - FMA. */
226	unsigned u1FMA : 1;
227	/** Bit 12 - Reserved. */
228	unsigned u1Reserved2 : 1;
229	/** Bit 13 - CX16 - CMPXCHG16B. */
230	unsigned u1CX16 : 1;
231	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
232	unsigned u1TPRUpdate : 1;
233	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
234	unsigned u1PDCM : 1;
235	/** Reserved. */
236	unsigned u2Reserved3 : 2;
237	/** Bit 18 - Direct Cache Access. */
238	unsigned u1DCA : 1;
239	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
240	unsigned u1SSE4_1 : 1;
241	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
242	unsigned u1SSE4_2 : 1;
243	/** Bit 21 - x2APIC. */
244	unsigned u1x2APIC : 1;
245	/** Bit 22 - MOVBE - Supports MOVBE. */
246	unsigned u1MOVBE : 1;
247	/** Bit 23 - POPCNT - Supports POPCNT. */
248	unsigned u1POPCNT : 1;
249	/** Bit 24 - Reserved. */
250	unsigned u1Reserved4 : 1;
251	/** Bit 25 - AES. */
252	unsigned u1AES : 1;
253	/** Bit 26 - XSAVE - Supports XSAVE. */
254	unsigned u1XSAVE : 1;
255	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
256	unsigned u1OSXSAVE : 1;
257	/** Reserved. */
258	unsigned u4Reserved5 : 4;
259	} X86CPUIDFEATECX;
260	/** Pointer to CPUID Feature Information - ECX. */
261	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
262	/** Pointer to const CPUID Feature Information - ECX. */
263	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
264
265
266	/** CPUID Feature Information - EDX.
267	* CPUID query with EAX=1.
268	*/
269	typedef struct X86CPUIDFEATEDX
270	{
271	/** Bit 0 - FPU - x87 FPU on Chip. */
272	unsigned u1FPU : 1;
273	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
274	unsigned u1VME : 1;
275	/** Bit 2 - DE - Debugging extensions. */
276	unsigned u1DE : 1;
277	/** Bit 3 - PSE - Page Size Extension. */
278	unsigned u1PSE : 1;
279	/** Bit 4 - TSC - Time Stamp Counter. */
280	unsigned u1TSC : 1;
281	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
282	unsigned u1MSR : 1;
283	/** Bit 6 - PAE - Physical Address Extension. */
284	unsigned u1PAE : 1;
285	/** Bit 7 - MCE - Machine Check Exception. */
286	unsigned u1MCE : 1;
287	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
288	unsigned u1CX8 : 1;
289	/** Bit 9 - APIC - APIC On-Chip. */
290	unsigned u1APIC : 1;
291	/** Bit 10 - Reserved. */
292	unsigned u1Reserved1 : 1;
293	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
294	unsigned u1SEP : 1;
295	/** Bit 12 - MTRR - Memory Type Range Registers. */
296	unsigned u1MTRR : 1;
297	/** Bit 13 - PGE - PTE Global Bit. */
298	unsigned u1PGE : 1;
299	/** Bit 14 - MCA - Machine Check Architecture. */
300	unsigned u1MCA : 1;
301	/** Bit 15 - CMOV - Conditional Move Instructions. */
302	unsigned u1CMOV : 1;
303	/** Bit 16 - PAT - Page Attribute Table. */
304	unsigned u1PAT : 1;
305	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
306	unsigned u1PSE36 : 1;
307	/** Bit 18 - PSN - Processor Serial Number. */
308	unsigned u1PSN : 1;
309	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
310	unsigned u1CLFSH : 1;
311	/** Bit 20 - Reserved. */
312	unsigned u1Reserved2 : 1;
313	/** Bit 21 - DS - Debug Store. */
314	unsigned u1DS : 1;
315	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
316	unsigned u1ACPI : 1;
317	/** Bit 23 - MMX - Intel MMX 'Technology'. */
318	unsigned u1MMX : 1;
319	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
320	unsigned u1FXSR : 1;
321	/** Bit 25 - SSE - SSE Support. */
322	unsigned u1SSE : 1;
323	/** Bit 26 - SSE2 - SSE2 Support. */
324	unsigned u1SSE2 : 1;
325	/** Bit 27 - SS - Self Snoop. */
326	unsigned u1SS : 1;
327	/** Bit 28 - HTT - Hyper-Threading Technology. */
328	unsigned u1HTT : 1;
329	/** Bit 29 - TM - Thermal Monitor. */
330	unsigned u1TM : 1;
331	/** Bit 30 - Reserved - . */
332	unsigned u1Reserved3 : 1;
333	/** Bit 31 - PBE - Pending Break Enabled. */
334	unsigned u1PBE : 1;
335	} X86CPUIDFEATEDX;
336	/** Pointer to CPUID Feature Information - EDX. */
337	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
338	/** Pointer to const CPUID Feature Information - EDX. */
339	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
340
341	/** @name CPUID Vendor information.
342	* CPUID query with EAX=0.
343	* @{
344	*/
345	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
346	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
347	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
348
349	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
350	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
351	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
352	/** @} */
353
354
355	/** @name CPUID Feature information.
356	* CPUID query with EAX=1.
357	* @{
358	*/
359	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
360	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
361	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
362	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
363	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
364	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
365	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
366	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
367	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
368	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
369	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
370	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
371	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
372	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
373	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
374	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
375	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
376	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
377	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
378	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
379	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
380	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
381	/** ECX Bit 12 - FMA. */
382	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
383	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
384	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
385	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
386	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
387	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
388	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
389	/** ECX Bit 18 - DCA - Direct Cache Access. */
390	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
391	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
392	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
393	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
394	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
395	/** ECX Bit 21 - x2APIC support. */
396	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
397	/** ECX Bit 22 - MOVBE instruction. */
398	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
399	/** ECX Bit 23 - POPCNT instruction. */
400	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
401	/** ECX Bit 25 - AES instructions. */
402	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
403	/** ECX Bit 26 - XSAVE instruction. */
404	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
405	/** ECX Bit 27 - OSXSAVE instruction. */
406	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
407	/** ECX Bit 28 - AVX. */
408	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
409
410
411	/** Bit 0 - FPU - x87 FPU on Chip. */
412	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
413	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
414	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
415	/** Bit 2 - DE - Debugging extensions. */
416	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
417	/** Bit 3 - PSE - Page Size Extension. */
418	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
419	/** Bit 4 - TSC - Time Stamp Counter. */
420	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
421	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
422	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
423	/** Bit 6 - PAE - Physical Address Extension. */
424	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
425	/** Bit 7 - MCE - Machine Check Exception. */
426	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
427	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
428	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
429	/** Bit 9 - APIC - APIC On-Chip. */
430	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
431	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
432	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
433	/** Bit 12 - MTRR - Memory Type Range Registers. */
434	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
435	/** Bit 13 - PGE - PTE Global Bit. */
436	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
437	/** Bit 14 - MCA - Machine Check Architecture. */
438	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
439	/** Bit 15 - CMOV - Conditional Move Instructions. */
440	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
441	/** Bit 16 - PAT - Page Attribute Table. */
442	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
443	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
444	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
445	/** Bit 18 - PSN - Processor Serial Number. */
446	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
447	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
448	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
449	/** Bit 21 - DS - Debug Store. */
450	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
451	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
452	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
453	/** Bit 23 - MMX - Intel MMX Technology. */
454	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
455	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
456	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
457	/** Bit 25 - SSE - SSE Support. */
458	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
459	/** Bit 26 - SSE2 - SSE2 Support. */
460	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
461	/** Bit 27 - SS - Self Snoop. */
462	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
463	/** Bit 28 - HTT - Hyper-Threading Technology. */
464	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
465	/** Bit 29 - TM - Therm. Monitor. */
466	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
467	/** Bit 31 - PBE - Pending Break Enabled. */
468	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
469	/** @} */
470
471	/** @name CPUID mwait/monitor information.
472	* CPUID query with EAX=5.
473	* @{
474	*/
475	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
476	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
477	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
478	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
479	/** @} */
480
481
482	/** @name CPUID AMD Feature information.
483	* CPUID query with EAX=0x80000001.
484	* @{
485	*/
486	/** Bit 0 - FPU - x87 FPU on Chip. */
487	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
488	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
489	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
490	/** Bit 2 - DE - Debugging extensions. */
491	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
492	/** Bit 3 - PSE - Page Size Extension. */
493	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
494	/** Bit 4 - TSC - Time Stamp Counter. */
495	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
496	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
497	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
498	/** Bit 6 - PAE - Physical Address Extension. */
499	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
500	/** Bit 7 - MCE - Machine Check Exception. */
501	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
502	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
503	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
504	/** Bit 9 - APIC - APIC On-Chip. */
505	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
506	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
507	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
508	/** Bit 12 - MTRR - Memory Type Range Registers. */
509	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
510	/** Bit 13 - PGE - PTE Global Bit. */
511	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
512	/** Bit 14 - MCA - Machine Check Architecture. */
513	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
514	/** Bit 15 - CMOV - Conditional Move Instructions. */
515	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
516	/** Bit 16 - PAT - Page Attribute Table. */
517	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
518	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
519	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
520	/** Bit 20 - NX - AMD No-Execute Page Protection. */
521	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
522	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
523	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
524	/** Bit 23 - MMX - Intel MMX Technology. */
525	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
526	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
527	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
528	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
529	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
530	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
531	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
532	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
533	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
534	/** Bit 29 - LM - AMD Long Mode. */
535	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
536	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
537	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
538	/** Bit 31 - 3DNOW - AMD 3DNow. */
539	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
540
541	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
542	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
543	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
544	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
545	/** Bit 2 - SVM - AMD VM extensions. */
546	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
547	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
548	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
549	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
550	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
551	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
552	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
553	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
554	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
555	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
556	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
557	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
558	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
559	/** Bit 9 - OSVW - AMD OS visible workaround. */
560	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
561	/** Bit 10 - IBS - Instruct based sampling. */
562	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
563	/** Bit 11 - SSE5 - SSE5 instruction support. */
564	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
565	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
566	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
567	/** Bit 13 - WDT - AMD Watchdog timer support. */
568	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
569
570	/** @} */
571
572
573	/** @name CPUID AMD Feature information.
574	* CPUID query with EAX=0x80000007.
575	* @{
576	*/
577	/** Bit 0 - TS - Temperature Sensor. */
578	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
579	/** Bit 1 - FID - Frequency ID Control. */
580	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
581	/** Bit 2 - VID - Voltage ID Control. */
582	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
583	/** Bit 3 - TTP - THERMTRIP. */
584	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
585	/** Bit 4 - TM - Hardware Thermal Control. */
586	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
587	/** Bit 5 - STC - Software Thermal Control. */
588	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
589	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
590	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
591	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
592	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
593	/** Bit 8 - TSCINVAR - TSC Invariant. */
594	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
595	/** @} */
596
597
598	/** @name CR0
599	* @{ */
600	/** Bit 0 - PE - Protection Enabled */
601	#define X86_CR0_PE RT_BIT(0)
602	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
603	/** Bit 1 - MP - Monitor Coprocessor */
604	#define X86_CR0_MP RT_BIT(1)
605	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
606	/** Bit 2 - EM - Emulation. */
607	#define X86_CR0_EM RT_BIT(2)
608	#define X86_CR0_EMULATE_FPU RT_BIT(2)
609	/** Bit 3 - TS - Task Switch. */
610	#define X86_CR0_TS RT_BIT(3)
611	#define X86_CR0_TASK_SWITCH RT_BIT(3)
612	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
613	#define X86_CR0_ET RT_BIT(4)
614	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
615	/** Bit 5 - NE - Numeric error. */
616	#define X86_CR0_NE RT_BIT(5)
617	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
618	/** Bit 16 - WP - Write Protect. */
619	#define X86_CR0_WP RT_BIT(16)
620	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
621	/** Bit 18 - AM - Alignment Mask. */
622	#define X86_CR0_AM RT_BIT(18)
623	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
624	/** Bit 29 - NW - Not Write-though. */
625	#define X86_CR0_NW RT_BIT(29)
626	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
627	/** Bit 30 - WP - Cache Disable. */
628	#define X86_CR0_CD RT_BIT(30)
629	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
630	/** Bit 31 - PG - Paging. */
631	#define X86_CR0_PG RT_BIT(31)
632	#define X86_CR0_PAGING RT_BIT(31)
633	/** @} */
634
635
636	/** @name CR3
637	* @{ */
638	/** Bit 3 - PWT - Page-level Writes Transparent. */
639	#define X86_CR3_PWT RT_BIT(3)
640	/** Bit 4 - PCD - Page-level Cache Disable. */
641	#define X86_CR3_PCD RT_BIT(4)
642	/** Bits 12-31 - - Page directory page number. */
643	#define X86_CR3_PAGE_MASK (0xfffff000)
644	/** Bits 5-31 - - PAE Page directory page number. */
645	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
646	/** Bits 12-51 - - AMD64 Page directory page number. */
647	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
648	/** @} */
649
650
651	/** @name CR4
652	* @{ */
653	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
654	#define X86_CR4_VME RT_BIT(0)
655	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
656	#define X86_CR4_PVI RT_BIT(1)
657	/** Bit 2 - TSD - Time Stamp Disable. */
658	#define X86_CR4_TSD RT_BIT(2)
659	/** Bit 3 - DE - Debugging Extensions. */
660	#define X86_CR4_DE RT_BIT(3)
661	/** Bit 4 - PSE - Page Size Extension. */
662	#define X86_CR4_PSE RT_BIT(4)
663	/** Bit 5 - PAE - Physical Address Extension. */
664	#define X86_CR4_PAE RT_BIT(5)
665	/** Bit 6 - MCE - Machine-Check Enable. */
666	#define X86_CR4_MCE RT_BIT(6)
667	/** Bit 7 - PGE - Page Global Enable. */
668	#define X86_CR4_PGE RT_BIT(7)
669	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
670	#define X86_CR4_PCE RT_BIT(8)
671	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
672	#define X86_CR4_OSFSXR RT_BIT(9)
673	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
674	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
675	/** Bit 13 - VMXE - VMX mode is enabled. */
676	#define X86_CR4_VMXE RT_BIT(13)
677	/** @} */
678
679
680	/** @name DR6
681	* @{ */
682	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
683	#define X86_DR6_B0 RT_BIT(0)
684	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
685	#define X86_DR6_B1 RT_BIT(1)
686	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
687	#define X86_DR6_B2 RT_BIT(2)
688	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
689	#define X86_DR6_B3 RT_BIT(3)
690	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
691	#define X86_DR6_BD RT_BIT(13)
692	/** Bit 14 - BS - Single step */
693	#define X86_DR6_BS RT_BIT(14)
694	/** Bit 15 - BT - Task switch. (TSS T bit.) */
695	#define X86_DR6_BT RT_BIT(15)
696	/** Value of DR6 after powerup/reset. */
697	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
698	/** @} */
699
700
701	/** @name DR7
702	* @{ */
703	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
704	#define X86_DR7_L0 RT_BIT(0)
705	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
706	#define X86_DR7_G0 RT_BIT(1)
707	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
708	#define X86_DR7_L1 RT_BIT(2)
709	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
710	#define X86_DR7_G1 RT_BIT(3)
711	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
712	#define X86_DR7_L2 RT_BIT(4)
713	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
714	#define X86_DR7_G2 RT_BIT(5)
715	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
716	#define X86_DR7_L3 RT_BIT(6)
717	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
718	#define X86_DR7_G3 RT_BIT(7)
719	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
720	#define X86_DR7_LE RT_BIT(8)
721	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
722	#define X86_DR7_GE RT_BIT(9)
723
724	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
725	* any DR register is accessed. */
726	#define X86_DR7_GD RT_BIT(13)
727	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
728	#define X86_DR7_RW0_MASK (3 << 16)
729	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
730	#define X86_DR7_LEN0_MASK (3 << 18)
731	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
732	#define X86_DR7_RW1_MASK (3 << 20)
733	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
734	#define X86_DR7_LEN1_MASK (3 << 22)
735	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
736	#define X86_DR7_RW2_MASK (3 << 24)
737	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
738	#define X86_DR7_LEN2_MASK (3 << 26)
739	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
740	#define X86_DR7_RW3_MASK (3 << 28)
741	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
742	#define X86_DR7_LEN3_MASK (3 << 30)
743
744	/** Bits which must be 1s. */
745	#define X86_DR7_MB1_MASK (RT_BIT(10))
746
747	/** Calcs the L bit of Nth breakpoint.
748	* @param iBp The breakpoint number [0..3].
749	*/
750	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
751
752	/** Calcs the G bit of Nth breakpoint.
753	* @param iBp The breakpoint number [0..3].
754	*/
755	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
756
757	/** @name Read/Write values.
758	* @{ */
759	/** Break on instruction fetch only. */
760	#define X86_DR7_RW_EO 0U
761	/** Break on write only. */
762	#define X86_DR7_RW_WO 1U
763	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
764	#define X86_DR7_RW_IO 2U
765	/** Break on read or write (but not instruction fetches). */
766	#define X86_DR7_RW_RW 3U
767	/** @} */
768
769	/** Shifts a X86_DR7_RW_* value to its right place.
770	* @param iBp The breakpoint number [0..3].
771	* @param fRw One of the X86_DR7_RW_* value.
772	*/
773	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
774
775	/** @name Length values.
776	* @{ */
777	#define X86_DR7_LEN_BYTE 0U
778	#define X86_DR7_LEN_WORD 1U
779	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
780	#define X86_DR7_LEN_DWORD 3U
781	/** @} */
782
783	/** Shifts a X86_DR7_LEN_* value to its right place.
784	* @param iBp The breakpoint number [0..3].
785	* @param cb One of the X86_DR7_LEN_* values.
786	*/
787	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
788
789	/** Fetch the breakpoint length bits from the DR7 value.
790	* @param uDR7 DR7 value
791	* @param iBp The breakpoint number [0..3].
792	*/
793	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
794
795	/** Mask used to check if any breakpoints are enabled. */
796	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
797
798	/** Mask used to check if any io breakpoints are set. */
799	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
800
801	/** Value of DR7 after powerup/reset. */
802	#define X86_DR7_INIT_VAL 0x400
803	/** @} */
804
805
806	/** @name Machine Specific Registers
807	* @{
808	*/
809
810	/** Time Stamp Counter. */
811	#define MSR_IA32_TSC 0x10
812
813	#define MSR_IA32_PLATFORM_ID 0x17
814
815	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
816	#define MSR_IA32_APICBASE 0x1b
817	#endif
818
819	/** CPU Feature control. */
820	#define MSR_IA32_FEATURE_CONTROL 0x3A
821	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
822	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
823
824	/** BIOS update trigger (microcode update). */
825	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
826
827	/** BIOS update signature (microcode). */
828	#define MSR_IA32_BIOS_SIGN_ID 0x8B
829
830	/* Nehalem power control */
831	#define MSR_IA32_PLATFORM_INFO 0xCE
832
833	/** MTRR Capabilities. */
834	#define MSR_IA32_MTRR_CAP 0xFE
835
836
837	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
838	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
839	* R0 SS == CS + 8
840	* R3 CS == CS + 16
841	* R3 SS == CS + 24
842	*/
843	#define MSR_IA32_SYSENTER_CS 0x174
844	/** SYSENTER_ESP - the R0 ESP. */
845	#define MSR_IA32_SYSENTER_ESP 0x175
846	/** SYSENTER_EIP - the R0 EIP. */
847	#define MSR_IA32_SYSENTER_EIP 0x176
848	#endif
849
850	/** Machine Check Global Capabilities Register. */
851	#define MSR_IA32_MCP_CAP 0x179
852	/** Machine Check Global Status Register. */
853	#define MSR_IA32_MCP_STATUS 0x17A
854	/** Machine Check Global Control Register. */
855	#define MSR_IA32_MCP_CTRL 0x17B
856
857	/** Trace/Profile Resource Control (R/W) */
858	#define MSR_IA32_DEBUGCTL 0x1D9
859
860	/* Page Attribute Table. */
861	#define MSR_IA32_CR_PAT 0x277
862
863	/** Performance counter MSRs. (Intel only) */
864	#define MSR_IA32_PERFEVTSEL0 0x186
865	#define MSR_IA32_PERFEVTSEL1 0x187
866	#define MSR_IA32_FLEX_RATIO 0x194
867	#define MSR_IA32_PERF_STATUS 0x198
868	#define MSR_IA32_PERF_CTL 0x199
869
870	/** MTRR Default Range. */
871	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
872
873	#define MSR_IA32_MC0_CTL 0x400
874	#define MSR_IA32_MC0_STATUS 0x401
875
876	/** Basic VMX information. */
877	#define MSR_IA32_VMX_BASIC_INFO 0x480
878	/** Allowed settings for pin-based VM execution controls */
879	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
880	/** Allowed settings for proc-based VM execution controls */
881	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
882	/** Allowed settings for the VMX exit controls. */
883	#define MSR_IA32_VMX_EXIT_CTLS 0x483
884	/** Allowed settings for the VMX entry controls. */
885	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
886	/** Misc VMX info. */
887	#define MSR_IA32_VMX_MISC 0x485
888	/** Fixed cleared bits in CR0. */
889	#define MSR_IA32_VMX_CR0_FIXED0 0x486
890	/** Fixed set bits in CR0. */
891	#define MSR_IA32_VMX_CR0_FIXED1 0x487
892	/** Fixed cleared bits in CR4. */
893	#define MSR_IA32_VMX_CR4_FIXED0 0x488
894	/** Fixed set bits in CR4. */
895	#define MSR_IA32_VMX_CR4_FIXED1 0x489
896	/** Information for enumerating fields in the VMCS. */
897	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
898	/** Allowed settings for secondary proc-based VM execution controls */
899	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
900	/** EPT capabilities. */
901	#define MSR_IA32_VMX_EPT_CAPS 0x48C
902	/** DS Save Area (R/W). */
903	#define MSR_IA32_DS_AREA 0x600
904	/** X2APIC MSR ranges. */
905	#define MSR_IA32_APIC_START 0x800
906	#define MSR_IA32_APIC_END 0x900
907
908	/** K6 EFER - Extended Feature Enable Register. */
909	#define MSR_K6_EFER 0xc0000080
910	/** @todo document EFER */
911	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
912	#define MSR_K6_EFER_SCE RT_BIT(0)
913	/** Bit 8 - LME - Long mode enabled. (R/W) */
914	#define MSR_K6_EFER_LME RT_BIT(8)
915	/** Bit 10 - LMA - Long mode active. (R) */
916	#define MSR_K6_EFER_LMA RT_BIT(10)
917	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
918	#define MSR_K6_EFER_NXE RT_BIT(11)
919	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
920	#define MSR_K6_EFER_SVME RT_BIT(12)
921	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
922	#define MSR_K6_EFER_LMSLE RT_BIT(13)
923	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
924	#define MSR_K6_EFER_FFXSR RT_BIT(14)
925	/** K6 STAR - SYSCALL/RET targets. */
926	#define MSR_K6_STAR 0xc0000081
927	/** Shift value for getting the SYSRET CS and SS value. */
928	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
929	/** Shift value for getting the SYSCALL CS and SS value. */
930	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
931	/** Selector mask for use after shifting. */
932	#define MSR_K6_STAR_SEL_MASK 0xffff
933	/** The mask which give the SYSCALL EIP. */
934	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
935	/** K6 WHCR - Write Handling Control Register. */
936	#define MSR_K6_WHCR 0xc0000082
937	/** K6 UWCCR - UC/WC Cacheability Control Register. */
938	#define MSR_K6_UWCCR 0xc0000085
939	/** K6 PSOR - Processor State Observability Register. */
940	#define MSR_K6_PSOR 0xc0000087
941	/** K6 PFIR - Page Flush/Invalidate Register. */
942	#define MSR_K6_PFIR 0xc0000088
943
944	/** Performance counter MSRs. (AMD only) */
945	#define MSR_K7_EVNTSEL0 0xc0010000
946	#define MSR_K7_EVNTSEL1 0xc0010001
947	#define MSR_K7_EVNTSEL2 0xc0010002
948	#define MSR_K7_EVNTSEL3 0xc0010003
949	#define MSR_K7_PERFCTR0 0xc0010004
950	#define MSR_K7_PERFCTR1 0xc0010005
951	#define MSR_K7_PERFCTR2 0xc0010006
952	#define MSR_K7_PERFCTR3 0xc0010007
953
954	#define MSR_K8_HWCR 0xc0010015
955
956	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
957	#define MSR_K8_LSTAR 0xc0000082
958	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
959	#define MSR_K8_CSTAR 0xc0000083
960	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
961	#define MSR_K8_SF_MASK 0xc0000084
962	/** K8 FS.base - The 64-bit base FS register. */
963	#define MSR_K8_FS_BASE 0xc0000100
964	/** K8 GS.base - The 64-bit base GS register. */
965	#define MSR_K8_GS_BASE 0xc0000101
966	/** K8 KernelGSbase - Used with SWAPGS. */
967	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
968	#define MSR_K8_TSC_AUX 0xc0000103
969	#define MSR_K8_SYSCFG 0xc0010010
970	#define MSR_K8_HWCR 0xc0010015
971	#define MSR_K8_IORRBASE0 0xc0010016
972	#define MSR_K8_IORRMASK0 0xc0010017
973	#define MSR_K8_IORRBASE1 0xc0010018
974	#define MSR_K8_IORRMASK1 0xc0010019
975	#define MSR_K8_TOP_MEM1 0xc001001a
976	#define MSR_K8_TOP_MEM2 0xc001001d
977	#define MSR_K8_VM_CR 0xc0010114
978	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
979
980	#define MSR_K8_IGNNE 0xc0010115
981	#define MSR_K8_SMM_CTL 0xc0010116
982	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
983	* host state during world switch.
984	*/
985	#define MSR_K8_VM_HSAVE_PA 0xc0010117
986
987	/** @} */
988
989
990	/** @name Page Table / Directory / Directory Pointers / L4.
991	* @{
992	*/
993
994	/** Page table/directory entry as an unsigned integer. */
995	typedef uint32_t X86PGUINT;
996	/** Pointer to a page table/directory table entry as an unsigned integer. */
997	typedef X86PGUINT *PX86PGUINT;
998	/** Pointer to an const page table/directory table entry as an unsigned integer. */
999	typedef X86PGUINT const *PCX86PGUINT;
1000
1001	/** Number of entries in a 32-bit PT/PD. */
1002	#define X86_PG_ENTRIES 1024
1003
1004
1005	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1006	typedef uint64_t X86PGPAEUINT;
1007	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1008	typedef X86PGPAEUINT *PX86PGPAEUINT;
1009	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1010	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1011
1012	/** Number of entries in a PAE PT/PD. */
1013	#define X86_PG_PAE_ENTRIES 512
1014	/** Number of entries in a PAE PDPT. */
1015	#define X86_PG_PAE_PDPE_ENTRIES 4
1016
1017	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1018	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1019	/** Number of entries in an AMD64 PDPT.
1020	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1021	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1022
1023	/** The size of a 4KB page. */
1024	#define X86_PAGE_4K_SIZE _4K
1025	/** The page shift of a 4KB page. */
1026	#define X86_PAGE_4K_SHIFT 12
1027	/** The 4KB page offset mask. */
1028	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1029	/** The 4KB page base mask for virtual addresses. */
1030	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1031	/** The 4KB page base mask for virtual addresses - 32bit version. */
1032	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1033
1034	/** The size of a 2MB page. */
1035	#define X86_PAGE_2M_SIZE _2M
1036	/** The page shift of a 2MB page. */
1037	#define X86_PAGE_2M_SHIFT 21
1038	/** The 2MB page offset mask. */
1039	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1040	/** The 2MB page base mask for virtual addresses. */
1041	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1042	/** The 2MB page base mask for virtual addresses - 32bit version. */
1043	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1044
1045	/** The size of a 4MB page. */
1046	#define X86_PAGE_4M_SIZE _4M
1047	/** The page shift of a 4MB page. */
1048	#define X86_PAGE_4M_SHIFT 22
1049	/** The 4MB page offset mask. */
1050	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1051	/** The 4MB page base mask for virtual addresses. */
1052	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1053	/** The 4MB page base mask for virtual addresses - 32bit version. */
1054	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1055
1056
1057
1058	/** @name Page Table Entry
1059	* @{
1060	*/
1061	/** Bit 0 - P - Present bit. */
1062	#define X86_PTE_BIT_P 0
1063	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1064	#define X86_PTE_BIT_RW 1
1065	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1066	#define X86_PTE_BIT_US 2
1067	/** Bit 3 - PWT - Page level write thru bit. */
1068	#define X86_PTE_BIT_PWT 3
1069	/** Bit 4 - PCD - Page level cache disable bit. */
1070	#define X86_PTE_BIT_PCD 4
1071	/** Bit 5 - A - Access bit. */
1072	#define X86_PTE_BIT_A 5
1073	/** Bit 6 - D - Dirty bit. */
1074	#define X86_PTE_BIT_D 6
1075	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1076	#define X86_PTE_BIT_PAT 7
1077	/** Bit 8 - G - Global flag. */
1078	#define X86_PTE_BIT_G 8
1079
1080	/** Bit 0 - P - Present bit mask. */
1081	#define X86_PTE_P RT_BIT(0)
1082	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1083	#define X86_PTE_RW RT_BIT(1)
1084	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1085	#define X86_PTE_US RT_BIT(2)
1086	/** Bit 3 - PWT - Page level write thru bit mask. */
1087	#define X86_PTE_PWT RT_BIT(3)
1088	/** Bit 4 - PCD - Page level cache disable bit mask. */
1089	#define X86_PTE_PCD RT_BIT(4)
1090	/** Bit 5 - A - Access bit mask. */
1091	#define X86_PTE_A RT_BIT(5)
1092	/** Bit 6 - D - Dirty bit mask. */
1093	#define X86_PTE_D RT_BIT(6)
1094	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1095	#define X86_PTE_PAT RT_BIT(7)
1096	/** Bit 8 - G - Global bit mask. */
1097	#define X86_PTE_G RT_BIT(8)
1098
1099	/** Bits 9-11 - - Available for use to system software. */
1100	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1101	/** Bits 12-31 - - Physical Page number of the next level. */
1102	#define X86_PTE_PG_MASK ( 0xfffff000 )
1103
1104	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1105	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1106	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1107	/** @todo Get rid of the above hack; makes code unreadable. */
1108	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1109	#else
1110	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1111	#endif
1112	/** Bits 63 - NX - PAE - No execution flag. */
1113	#define X86_PTE_PAE_NX RT_BIT_64(63)
1114
1115	/**
1116	* Page table entry.
1117	*/
1118	typedef struct X86PTEBITS
1119	{
1120	/** Flags whether(=1) or not the page is present. */
1121	unsigned u1Present : 1;
1122	/** Read(=0) / Write(=1) flag. */
1123	unsigned u1Write : 1;
1124	/** User(=1) / Supervisor (=0) flag. */
1125	unsigned u1User : 1;
1126	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1127	unsigned u1WriteThru : 1;
1128	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1129	unsigned u1CacheDisable : 1;
1130	/** Accessed flag.
1131	* Indicates that the page have been read or written to. */
1132	unsigned u1Accessed : 1;
1133	/** Dirty flag.
1134	* Indicates that the page have been written to. */
1135	unsigned u1Dirty : 1;
1136	/** Reserved / If PAT enabled, bit 2 of the index. */
1137	unsigned u1PAT : 1;
1138	/** Global flag. (Ignored in all but final level.) */
1139	unsigned u1Global : 1;
1140	/** Available for use to system software. */
1141	unsigned u3Available : 3;
1142	/** Physical Page number of the next level. */
1143	unsigned u20PageNo : 20;
1144	} X86PTEBITS;
1145	/** Pointer to a page table entry. */
1146	typedef X86PTEBITS *PX86PTEBITS;
1147	/** Pointer to a const page table entry. */
1148	typedef const X86PTEBITS *PCX86PTEBITS;
1149
1150	/**
1151	* Page table entry.
1152	*/
1153	typedef union X86PTE
1154	{
1155	/** Unsigned integer view */
1156	X86PGUINT u;
1157	/** Bit field view. */
1158	X86PTEBITS n;
1159	/** 32-bit view. */
1160	uint32_t au32[1];
1161	/** 16-bit view. */
1162	uint16_t au16[2];
1163	/** 8-bit view. */
1164	uint8_t au8[4];
1165	} X86PTE;
1166	/** Pointer to a page table entry. */
1167	typedef X86PTE *PX86PTE;
1168	/** Pointer to a const page table entry. */
1169	typedef const X86PTE *PCX86PTE;
1170
1171
1172	/**
1173	* PAE page table entry.
1174	*/
1175	typedef struct X86PTEPAEBITS
1176	{
1177	/** Flags whether(=1) or not the page is present. */
1178	uint32_t u1Present : 1;
1179	/** Read(=0) / Write(=1) flag. */
1180	uint32_t u1Write : 1;
1181	/** User(=1) / Supervisor(=0) flag. */
1182	uint32_t u1User : 1;
1183	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1184	uint32_t u1WriteThru : 1;
1185	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1186	uint32_t u1CacheDisable : 1;
1187	/** Accessed flag.
1188	* Indicates that the page have been read or written to. */
1189	uint32_t u1Accessed : 1;
1190	/** Dirty flag.
1191	* Indicates that the page have been written to. */
1192	uint32_t u1Dirty : 1;
1193	/** Reserved / If PAT enabled, bit 2 of the index. */
1194	uint32_t u1PAT : 1;
1195	/** Global flag. (Ignored in all but final level.) */
1196	uint32_t u1Global : 1;
1197	/** Available for use to system software. */
1198	uint32_t u3Available : 3;
1199	/** Physical Page number of the next level - Low Part. Don't use this. */
1200	uint32_t u20PageNoLow : 20;
1201	/** Physical Page number of the next level - High Part. Don't use this. */
1202	uint32_t u20PageNoHigh : 20;
1203	/** MBZ bits */
1204	uint32_t u11Reserved : 11;
1205	/** No Execute flag. */
1206	uint32_t u1NoExecute : 1;
1207	} X86PTEPAEBITS;
1208	/** Pointer to a page table entry. */
1209	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1210	/** Pointer to a page table entry. */
1211	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1212
1213	/**
1214	* PAE Page table entry.
1215	*/
1216	typedef union X86PTEPAE
1217	{
1218	/** Unsigned integer view */
1219	X86PGPAEUINT u;
1220	/** Bit field view. */
1221	X86PTEPAEBITS n;
1222	/** 32-bit view. */
1223	uint32_t au32[2];
1224	/** 16-bit view. */
1225	uint16_t au16[4];
1226	/** 8-bit view. */
1227	uint8_t au8[8];
1228	} X86PTEPAE;
1229	/** Pointer to a PAE page table entry. */
1230	typedef X86PTEPAE *PX86PTEPAE;
1231	/** Pointer to a const PAE page table entry. */
1232	typedef const X86PTEPAE *PCX86PTEPAE;
1233	/** @} */
1234
1235	/**
1236	* Page table.
1237	*/
1238	typedef struct X86PT
1239	{
1240	/** PTE Array. */
1241	X86PTE a[X86_PG_ENTRIES];
1242	} X86PT;
1243	/** Pointer to a page table. */
1244	typedef X86PT *PX86PT;
1245	/** Pointer to a const page table. */
1246	typedef const X86PT *PCX86PT;
1247
1248	/** The page shift to get the PT index. */
1249	#define X86_PT_SHIFT 12
1250	/** The PT index mask (apply to a shifted page address). */
1251	#define X86_PT_MASK 0x3ff
1252
1253
1254	/**
1255	* Page directory.
1256	*/
1257	typedef struct X86PTPAE
1258	{
1259	/** PTE Array. */
1260	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1261	} X86PTPAE;
1262	/** Pointer to a page table. */
1263	typedef X86PTPAE *PX86PTPAE;
1264	/** Pointer to a const page table. */
1265	typedef const X86PTPAE *PCX86PTPAE;
1266
1267	/** The page shift to get the PA PTE index. */
1268	#define X86_PT_PAE_SHIFT 12
1269	/** The PAE PT index mask (apply to a shifted page address). */
1270	#define X86_PT_PAE_MASK 0x1ff
1271
1272
1273	/** @name 4KB Page Directory Entry
1274	* @{
1275	*/
1276	/** Bit 0 - P - Present bit. */
1277	#define X86_PDE_P RT_BIT(0)
1278	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1279	#define X86_PDE_RW RT_BIT(1)
1280	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1281	#define X86_PDE_US RT_BIT(2)
1282	/** Bit 3 - PWT - Page level write thru bit. */
1283	#define X86_PDE_PWT RT_BIT(3)
1284	/** Bit 4 - PCD - Page level cache disable bit. */
1285	#define X86_PDE_PCD RT_BIT(4)
1286	/** Bit 5 - A - Access bit. */
1287	#define X86_PDE_A RT_BIT(5)
1288	/** Bit 7 - PS - Page size attribute.
1289	* Clear mean 4KB pages, set means large pages (2/4MB). */
1290	#define X86_PDE_PS RT_BIT(7)
1291	/** Bits 9-11 - - Available for use to system software. */
1292	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1293	/** Bits 12-31 - - Physical Page number of the next level. */
1294	#define X86_PDE_PG_MASK ( 0xfffff000 )
1295
1296	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1297	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1298	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1299	* we partly or that part into shadow page table entries. Will be corrected
1300	* soon.
1301	*/
1302	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1303	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1304	#else
1305	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1306	#endif
1307	/** Bits 63 - NX - PAE - No execution flag. */
1308	#define X86_PDE_PAE_NX RT_BIT_64(63)
1309
1310	/**
1311	* Page directory entry.
1312	*/
1313	typedef struct X86PDEBITS
1314	{
1315	/** Flags whether(=1) or not the page is present. */
1316	unsigned u1Present : 1;
1317	/** Read(=0) / Write(=1) flag. */
1318	unsigned u1Write : 1;
1319	/** User(=1) / Supervisor (=0) flag. */
1320	unsigned u1User : 1;
1321	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1322	unsigned u1WriteThru : 1;
1323	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1324	unsigned u1CacheDisable : 1;
1325	/** Accessed flag.
1326	* Indicates that the page have been read or written to. */
1327	unsigned u1Accessed : 1;
1328	/** Reserved / Ignored (dirty bit). */
1329	unsigned u1Reserved0 : 1;
1330	/** Size bit if PSE is enabled - in any event it's 0. */
1331	unsigned u1Size : 1;
1332	/** Reserved / Ignored (global bit). */
1333	unsigned u1Reserved1 : 1;
1334	/** Available for use to system software. */
1335	unsigned u3Available : 3;
1336	/** Physical Page number of the next level. */
1337	unsigned u20PageNo : 20;
1338	} X86PDEBITS;
1339	/** Pointer to a page directory entry. */
1340	typedef X86PDEBITS *PX86PDEBITS;
1341	/** Pointer to a const page directory entry. */
1342	typedef const X86PDEBITS *PCX86PDEBITS;
1343
1344
1345	/**
1346	* PAE page directory entry.
1347	*/
1348	typedef struct X86PDEPAEBITS
1349	{
1350	/** Flags whether(=1) or not the page is present. */
1351	uint32_t u1Present : 1;
1352	/** Read(=0) / Write(=1) flag. */
1353	uint32_t u1Write : 1;
1354	/** User(=1) / Supervisor (=0) flag. */
1355	uint32_t u1User : 1;
1356	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1357	uint32_t u1WriteThru : 1;
1358	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1359	uint32_t u1CacheDisable : 1;
1360	/** Accessed flag.
1361	* Indicates that the page have been read or written to. */
1362	uint32_t u1Accessed : 1;
1363	/** Reserved / Ignored (dirty bit). */
1364	uint32_t u1Reserved0 : 1;
1365	/** Size bit if PSE is enabled - in any event it's 0. */
1366	uint32_t u1Size : 1;
1367	/** Reserved / Ignored (global bit). / */
1368	uint32_t u1Reserved1 : 1;
1369	/** Available for use to system software. */
1370	uint32_t u3Available : 3;
1371	/** Physical Page number of the next level - Low Part. Don't use! */
1372	uint32_t u20PageNoLow : 20;
1373	/** Physical Page number of the next level - High Part. Don't use! */
1374	uint32_t u20PageNoHigh : 20;
1375	/** MBZ bits */
1376	uint32_t u11Reserved : 11;
1377	/** No Execute flag. */
1378	uint32_t u1NoExecute : 1;
1379	} X86PDEPAEBITS;
1380	/** Pointer to a page directory entry. */
1381	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1382	/** Pointer to a const page directory entry. */
1383	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1384
1385	/** @} */
1386
1387
1388	/** @name 2/4MB Page Directory Entry
1389	* @{
1390	*/
1391	/** Bit 0 - P - Present bit. */
1392	#define X86_PDE4M_P RT_BIT(0)
1393	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1394	#define X86_PDE4M_RW RT_BIT(1)
1395	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1396	#define X86_PDE4M_US RT_BIT(2)
1397	/** Bit 3 - PWT - Page level write thru bit. */
1398	#define X86_PDE4M_PWT RT_BIT(3)
1399	/** Bit 4 - PCD - Page level cache disable bit. */
1400	#define X86_PDE4M_PCD RT_BIT(4)
1401	/** Bit 5 - A - Access bit. */
1402	#define X86_PDE4M_A RT_BIT(5)
1403	/** Bit 6 - D - Dirty bit. */
1404	#define X86_PDE4M_D RT_BIT(6)
1405	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1406	#define X86_PDE4M_PS RT_BIT(7)
1407	/** Bit 8 - G - Global flag. */
1408	#define X86_PDE4M_G RT_BIT(8)
1409	/** Bits 9-11 - AVL - Available for use to system software. */
1410	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1411	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1412	#define X86_PDE4M_PAT RT_BIT(12)
1413	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1414	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1415	/** Bits 22-31 - - Physical Page number. */
1416	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1417	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1418	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1419	/** The number of bits to the high part of the page number. */
1420	#define X86_PDE4M_PG_HIGH_SHIFT 19
1421
1422	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1423	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1424	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1425	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1426	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1427
1428	/**
1429	* 4MB page directory entry.
1430	*/
1431	typedef struct X86PDE4MBITS
1432	{
1433	/** Flags whether(=1) or not the page is present. */
1434	unsigned u1Present : 1;
1435	/** Read(=0) / Write(=1) flag. */
1436	unsigned u1Write : 1;
1437	/** User(=1) / Supervisor (=0) flag. */
1438	unsigned u1User : 1;
1439	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1440	unsigned u1WriteThru : 1;
1441	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1442	unsigned u1CacheDisable : 1;
1443	/** Accessed flag.
1444	* Indicates that the page have been read or written to. */
1445	unsigned u1Accessed : 1;
1446	/** Dirty flag.
1447	* Indicates that the page have been written to. */
1448	unsigned u1Dirty : 1;
1449	/** Page size flag - always 1 for 4MB entries. */
1450	unsigned u1Size : 1;
1451	/** Global flag. */
1452	unsigned u1Global : 1;
1453	/** Available for use to system software. */
1454	unsigned u3Available : 3;
1455	/** Reserved / If PAT enabled, bit 2 of the index. */
1456	unsigned u1PAT : 1;
1457	/** Bits 32-39 of the page number on AMD64.
1458	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1459	unsigned u8PageNoHigh : 8;
1460	/** Reserved. */
1461	unsigned u1Reserved : 1;
1462	/** Physical Page number of the page. */
1463	unsigned u10PageNo : 10;
1464	} X86PDE4MBITS;
1465	/** Pointer to a page table entry. */
1466	typedef X86PDE4MBITS *PX86PDE4MBITS;
1467	/** Pointer to a const page table entry. */
1468	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1469
1470
1471	/**
1472	* 2MB PAE page directory entry.
1473	*/
1474	typedef struct X86PDE2MPAEBITS
1475	{
1476	/** Flags whether(=1) or not the page is present. */
1477	uint32_t u1Present : 1;
1478	/** Read(=0) / Write(=1) flag. */
1479	uint32_t u1Write : 1;
1480	/** User(=1) / Supervisor(=0) flag. */
1481	uint32_t u1User : 1;
1482	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1483	uint32_t u1WriteThru : 1;
1484	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1485	uint32_t u1CacheDisable : 1;
1486	/** Accessed flag.
1487	* Indicates that the page have been read or written to. */
1488	uint32_t u1Accessed : 1;
1489	/** Dirty flag.
1490	* Indicates that the page have been written to. */
1491	uint32_t u1Dirty : 1;
1492	/** Page size flag - always 1 for 2MB entries. */
1493	uint32_t u1Size : 1;
1494	/** Global flag. */
1495	uint32_t u1Global : 1;
1496	/** Available for use to system software. */
1497	uint32_t u3Available : 3;
1498	/** Reserved / If PAT enabled, bit 2 of the index. */
1499	uint32_t u1PAT : 1;
1500	/** Reserved. */
1501	uint32_t u9Reserved : 9;
1502	/** Physical Page number of the next level - Low part. Don't use! */
1503	uint32_t u10PageNoLow : 10;
1504	/** Physical Page number of the next level - High part. Don't use! */
1505	uint32_t u20PageNoHigh : 20;
1506	/** MBZ bits */
1507	uint32_t u11Reserved : 11;
1508	/** No Execute flag. */
1509	uint32_t u1NoExecute : 1;
1510	} X86PDE2MPAEBITS;
1511	/** Pointer to a 2MB PAE page table entry. */
1512	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1513	/** Pointer to a 2MB PAE page table entry. */
1514	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1515
1516	/** @} */
1517
1518	/**
1519	* Page directory entry.
1520	*/
1521	typedef union X86PDE
1522	{
1523	/** Unsigned integer view. */
1524	X86PGUINT u;
1525	/** Normal view. */
1526	X86PDEBITS n;
1527	/** 4MB view (big). */
1528	X86PDE4MBITS b;
1529	/** 8 bit unsigned integer view. */
1530	uint8_t au8[4];
1531	/** 16 bit unsigned integer view. */
1532	uint16_t au16[2];
1533	/** 32 bit unsigned integer view. */
1534	uint32_t au32[1];
1535	} X86PDE;
1536	/** Pointer to a page directory entry. */
1537	typedef X86PDE *PX86PDE;
1538	/** Pointer to a const page directory entry. */
1539	typedef const X86PDE *PCX86PDE;
1540
1541	/**
1542	* PAE page directory entry.
1543	*/
1544	typedef union X86PDEPAE
1545	{
1546	/** Unsigned integer view. */
1547	X86PGPAEUINT u;
1548	/** Normal view. */
1549	X86PDEPAEBITS n;
1550	/** 2MB page view (big). */
1551	X86PDE2MPAEBITS b;
1552	/** 8 bit unsigned integer view. */
1553	uint8_t au8[8];
1554	/** 16 bit unsigned integer view. */
1555	uint16_t au16[4];
1556	/** 32 bit unsigned integer view. */
1557	uint32_t au32[2];
1558	} X86PDEPAE;
1559	/** Pointer to a page directory entry. */
1560	typedef X86PDEPAE *PX86PDEPAE;
1561	/** Pointer to a const page directory entry. */
1562	typedef const X86PDEPAE *PCX86PDEPAE;
1563
1564	/**
1565	* Page directory.
1566	*/
1567	typedef struct X86PD
1568	{
1569	/** PDE Array. */
1570	X86PDE a[X86_PG_ENTRIES];
1571	} X86PD;
1572	/** Pointer to a page directory. */
1573	typedef X86PD *PX86PD;
1574	/** Pointer to a const page directory. */
1575	typedef const X86PD *PCX86PD;
1576
1577	/** The page shift to get the PD index. */
1578	#define X86_PD_SHIFT 22
1579	/** The PD index mask (apply to a shifted page address). */
1580	#define X86_PD_MASK 0x3ff
1581
1582
1583	/**
1584	* PAE page directory.
1585	*/
1586	typedef struct X86PDPAE
1587	{
1588	/** PDE Array. */
1589	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1590	} X86PDPAE;
1591	/** Pointer to a PAE page directory. */
1592	typedef X86PDPAE *PX86PDPAE;
1593	/** Pointer to a const PAE page directory. */
1594	typedef const X86PDPAE *PCX86PDPAE;
1595
1596	/** The page shift to get the PAE PD index. */
1597	#define X86_PD_PAE_SHIFT 21
1598	/** The PAE PD index mask (apply to a shifted page address). */
1599	#define X86_PD_PAE_MASK 0x1ff
1600
1601
1602	/** @name Page Directory Pointer Table Entry (PAE)
1603	* @{
1604	*/
1605	/** Bit 0 - P - Present bit. */
1606	#define X86_PDPE_P RT_BIT(0)
1607	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1608	#define X86_PDPE_RW RT_BIT(1)
1609	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1610	#define X86_PDPE_US RT_BIT(2)
1611	/** Bit 3 - PWT - Page level write thru bit. */
1612	#define X86_PDPE_PWT RT_BIT(3)
1613	/** Bit 4 - PCD - Page level cache disable bit. */
1614	#define X86_PDPE_PCD RT_BIT(4)
1615	/** Bit 5 - A - Access bit. Long Mode only. */
1616	#define X86_PDPE_A RT_BIT(5)
1617	/** Bits 9-11 - - Available for use to system software. */
1618	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1619	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1620	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1621	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1622	/** @todo Get rid of the above hack; makes code unreadable. */
1623	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1624	#else
1625	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1626	#endif
1627	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1628	#define X86_PDPE_NX RT_BIT_64(63)
1629
1630	/**
1631	* Page directory pointer table entry.
1632	*/
1633	typedef struct X86PDPEBITS
1634	{
1635	/** Flags whether(=1) or not the page is present. */
1636	uint32_t u1Present : 1;
1637	/** Chunk of reserved bits. */
1638	uint32_t u2Reserved : 2;
1639	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1640	uint32_t u1WriteThru : 1;
1641	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1642	uint32_t u1CacheDisable : 1;
1643	/** Chunk of reserved bits. */
1644	uint32_t u4Reserved : 4;
1645	/** Available for use to system software. */
1646	uint32_t u3Available : 3;
1647	/** Physical Page number of the next level - Low Part. Don't use! */
1648	uint32_t u20PageNoLow : 20;
1649	/** Physical Page number of the next level - High Part. Don't use! */
1650	uint32_t u20PageNoHigh : 20;
1651	/** MBZ bits */
1652	uint32_t u12Reserved : 12;
1653	} X86PDPEBITS;
1654	/** Pointer to a page directory pointer table entry. */
1655	typedef X86PDPEBITS *PX86PTPEBITS;
1656	/** Pointer to a const page directory pointer table entry. */
1657	typedef const X86PDPEBITS *PCX86PTPEBITS;
1658
1659	/**
1660	* Page directory pointer table entry. AMD64 version
1661	*/
1662	typedef struct X86PDPEAMD64BITS
1663	{
1664	/** Flags whether(=1) or not the page is present. */
1665	uint32_t u1Present : 1;
1666	/** Read(=0) / Write(=1) flag. */
1667	uint32_t u1Write : 1;
1668	/** User(=1) / Supervisor (=0) flag. */
1669	uint32_t u1User : 1;
1670	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1671	uint32_t u1WriteThru : 1;
1672	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1673	uint32_t u1CacheDisable : 1;
1674	/** Accessed flag.
1675	* Indicates that the page have been read or written to. */
1676	uint32_t u1Accessed : 1;
1677	/** Chunk of reserved bits. */
1678	uint32_t u3Reserved : 3;
1679	/** Available for use to system software. */
1680	uint32_t u3Available : 3;
1681	/** Physical Page number of the next level - Low Part. Don't use! */
1682	uint32_t u20PageNoLow : 20;
1683	/** Physical Page number of the next level - High Part. Don't use! */
1684	uint32_t u20PageNoHigh : 20;
1685	/** MBZ bits */
1686	uint32_t u11Reserved : 11;
1687	/** No Execute flag. */
1688	uint32_t u1NoExecute : 1;
1689	} X86PDPEAMD64BITS;
1690	/** Pointer to a page directory pointer table entry. */
1691	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1692	/** Pointer to a const page directory pointer table entry. */
1693	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1694
1695	/**
1696	* Page directory pointer table entry.
1697	*/
1698	typedef union X86PDPE
1699	{
1700	/** Unsigned integer view. */
1701	X86PGPAEUINT u;
1702	/** Normal view. */
1703	X86PDPEBITS n;
1704	/** AMD64 view. */
1705	X86PDPEAMD64BITS lm;
1706	/** 8 bit unsigned integer view. */
1707	uint8_t au8[8];
1708	/** 16 bit unsigned integer view. */
1709	uint16_t au16[4];
1710	/** 32 bit unsigned integer view. */
1711	uint32_t au32[2];
1712	} X86PDPE;
1713	/** Pointer to a page directory pointer table entry. */
1714	typedef X86PDPE *PX86PDPE;
1715	/** Pointer to a const page directory pointer table entry. */
1716	typedef const X86PDPE *PCX86PDPE;
1717
1718
1719	/**
1720	* Page directory pointer table.
1721	*/
1722	typedef struct X86PDPT
1723	{
1724	/** PDE Array. */
1725	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1726	} X86PDPT;
1727	/** Pointer to a page directory pointer table. */
1728	typedef X86PDPT *PX86PDPT;
1729	/** Pointer to a const page directory pointer table. */
1730	typedef const X86PDPT *PCX86PDPT;
1731
1732	/** The page shift to get the PDPT index. */
1733	#define X86_PDPT_SHIFT 30
1734	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1735	#define X86_PDPT_MASK_PAE 0x3
1736	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1737	#define X86_PDPT_MASK_AMD64 0x1ff
1738
1739	/** @} */
1740
1741
1742	/** @name Page Map Level-4 Entry (Long Mode PAE)
1743	* @{
1744	*/
1745	/** Bit 0 - P - Present bit. */
1746	#define X86_PML4E_P RT_BIT(0)
1747	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1748	#define X86_PML4E_RW RT_BIT(1)
1749	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1750	#define X86_PML4E_US RT_BIT(2)
1751	/** Bit 3 - PWT - Page level write thru bit. */
1752	#define X86_PML4E_PWT RT_BIT(3)
1753	/** Bit 4 - PCD - Page level cache disable bit. */
1754	#define X86_PML4E_PCD RT_BIT(4)
1755	/** Bit 5 - A - Access bit. */
1756	#define X86_PML4E_A RT_BIT(5)
1757	/** Bits 9-11 - - Available for use to system software. */
1758	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1759	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1760	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1761	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1762	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1763	#else
1764	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1765	#endif
1766	/** Bits 63 - NX - PAE - No execution flag. */
1767	#define X86_PML4E_NX RT_BIT_64(63)
1768
1769	/**
1770	* Page Map Level-4 Entry
1771	*/
1772	typedef struct X86PML4EBITS
1773	{
1774	/** Flags whether(=1) or not the page is present. */
1775	uint32_t u1Present : 1;
1776	/** Read(=0) / Write(=1) flag. */
1777	uint32_t u1Write : 1;
1778	/** User(=1) / Supervisor (=0) flag. */
1779	uint32_t u1User : 1;
1780	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1781	uint32_t u1WriteThru : 1;
1782	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1783	uint32_t u1CacheDisable : 1;
1784	/** Accessed flag.
1785	* Indicates that the page have been read or written to. */
1786	uint32_t u1Accessed : 1;
1787	/** Chunk of reserved bits. */
1788	uint32_t u3Reserved : 3;
1789	/** Available for use to system software. */
1790	uint32_t u3Available : 3;
1791	/** Physical Page number of the next level - Low Part. Don't use! */
1792	uint32_t u20PageNoLow : 20;
1793	/** Physical Page number of the next level - High Part. Don't use! */
1794	uint32_t u20PageNoHigh : 20;
1795	/** MBZ bits */
1796	uint32_t u11Reserved : 11;
1797	/** No Execute flag. */
1798	uint32_t u1NoExecute : 1;
1799	} X86PML4EBITS;
1800	/** Pointer to a page map level-4 entry. */
1801	typedef X86PML4EBITS *PX86PML4EBITS;
1802	/** Pointer to a const page map level-4 entry. */
1803	typedef const X86PML4EBITS *PCX86PML4EBITS;
1804
1805	/**
1806	* Page Map Level-4 Entry.
1807	*/
1808	typedef union X86PML4E
1809	{
1810	/** Unsigned integer view. */
1811	X86PGPAEUINT u;
1812	/** Normal view. */
1813	X86PML4EBITS n;
1814	/** 8 bit unsigned integer view. */
1815	uint8_t au8[8];
1816	/** 16 bit unsigned integer view. */
1817	uint16_t au16[4];
1818	/** 32 bit unsigned integer view. */
1819	uint32_t au32[2];
1820	} X86PML4E;
1821	/** Pointer to a page map level-4 entry. */
1822	typedef X86PML4E *PX86PML4E;
1823	/** Pointer to a const page map level-4 entry. */
1824	typedef const X86PML4E *PCX86PML4E;
1825
1826
1827	/**
1828	* Page Map Level-4.
1829	*/
1830	typedef struct X86PML4
1831	{
1832	/** PDE Array. */
1833	X86PML4E a[X86_PG_PAE_ENTRIES];
1834	} X86PML4;
1835	/** Pointer to a page map level-4. */
1836	typedef X86PML4 *PX86PML4;
1837	/** Pointer to a const page map level-4. */
1838	typedef const X86PML4 *PCX86PML4;
1839
1840	/** The page shift to get the PML4 index. */
1841	#define X86_PML4_SHIFT 39
1842	/** The PML4 index mask (apply to a shifted page address). */
1843	#define X86_PML4_MASK 0x1ff
1844
1845	/** @} */
1846
1847	/** @} */
1848
1849
1850	/**
1851	* 80-bit MMX/FPU register type.
1852	*/
1853	typedef struct X86FPUMMX
1854	{
1855	uint8_t reg[10];
1856	} X86FPUMMX;
1857	/** Pointer to a 80-bit MMX/FPU register type. */
1858	typedef X86FPUMMX *PX86FPUMMX;
1859	/** Pointer to a const 80-bit MMX/FPU register type. */
1860	typedef const X86FPUMMX *PCX86FPUMMX;
1861
1862	/**
1863	* FPU state (aka FSAVE/FRSTOR Memory Region).
1864	*/
1865	#pragma pack(1)
1866	typedef struct X86FPUSTATE
1867	{
1868	/** Control word. */
1869	uint16_t FCW;
1870	/** Alignment word */
1871	uint16_t Dummy1;
1872	/** Status word. */
1873	uint16_t FSW;
1874	/** Alignment word */
1875	uint16_t Dummy2;
1876	/** Tag word */
1877	uint16_t FTW;
1878	/** Alignment word */
1879	uint16_t Dummy3;
1880
1881	/** Instruction pointer. */
1882	uint32_t FPUIP;
1883	/** Code selector. */
1884	uint16_t CS;
1885	/** Opcode. */
1886	uint16_t FOP;
1887	/** FOO. */
1888	uint32_t FPUOO;
1889	/** FOS. */
1890	uint32_t FPUOS;
1891	/** FPU view - todo. */
1892	X86FPUMMX regs[8];
1893	} X86FPUSTATE;
1894	#pragma pack()
1895	/** Pointer to a FPU state. */
1896	typedef X86FPUSTATE *PX86FPUSTATE;
1897	/** Pointer to a const FPU state. */
1898	typedef const X86FPUSTATE *PCX86FPUSTATE;
1899
1900	/**
1901	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1902	*/
1903	#pragma pack(1)
1904	typedef struct X86FXSTATE
1905	{
1906	/** Control word. */
1907	uint16_t FCW;
1908	/** Status word. */
1909	uint16_t FSW;
1910	/** Tag word. (The upper byte is always zero.) */
1911	uint16_t FTW;
1912	/** Opcode. */
1913	uint16_t FOP;
1914	/** Instruction pointer. */
1915	uint32_t FPUIP;
1916	/** Code selector. */
1917	uint16_t CS;
1918	uint16_t Rsvrd1;
1919	/* - offset 16 - */
1920	/** Data pointer. */
1921	uint32_t FPUDP;
1922	/** Data segment */
1923	uint16_t DS;
1924	uint16_t Rsrvd2;
1925	uint32_t MXCSR;
1926	uint32_t MXCSR_MASK;
1927	/* - offset 32 - */
1928	union
1929	{
1930	/** MMX view. */
1931	uint64_t mmx;
1932	/** FPU view - todo. */
1933	X86FPUMMX fpu;
1934	/** 8-bit view. */
1935	uint8_t au8[16];
1936	/** 16-bit view. */
1937	uint16_t au16[8];
1938	/** 32-bit view. */
1939	uint32_t au32[4];
1940	/** 64-bit view. */
1941	uint64_t au64[2];
1942	/** 128-bit view. (yeah, very helpful) */
1943	uint128_t au128[1];
1944	} aRegs[8];
1945	/* - offset 160 - */
1946	union
1947	{
1948	/** XMM Register view . /
1949	uint128_t xmm;
1950	/** 8-bit view. */
1951	uint8_t au8[16];
1952	/** 16-bit view. */
1953	uint16_t au16[8];
1954	/** 32-bit view. */
1955	uint32_t au32[4];
1956	/** 64-bit view. */
1957	uint64_t au64[2];
1958	/** 128-bit view. (yeah, very helpful) */
1959	uint128_t au128[1];
1960	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1961	/* - offset 416 - */
1962	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1963	} X86FXSTATE;
1964	#pragma pack()
1965	/** Pointer to a FPU Extended state. */
1966	typedef X86FXSTATE *PX86FXSTATE;
1967	/** Pointer to a const FPU Extended state. */
1968	typedef const X86FXSTATE *PCX86FXSTATE;
1969
1970
1971	/** @name Selector Descriptor
1972	* @{
1973	*/
1974
1975	/**
1976	* Descriptor attributes.
1977	*/
1978	typedef struct X86DESCATTRBITS
1979	{
1980	/** 00 - Segment Type. */
1981	unsigned u4Type : 4;
1982	/** 04 - Descriptor Type. System(=0) or code/data selector */
1983	unsigned u1DescType : 1;
1984	/** 05 - Descriptor Privelege level. */
1985	unsigned u2Dpl : 2;
1986	/** 07 - Flags selector present(=1) or not. */
1987	unsigned u1Present : 1;
1988	/** 08 - Segment limit 16-19. */
1989	unsigned u4LimitHigh : 4;
1990	/** 0c - Available for system software. */
1991	unsigned u1Available : 1;
1992	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1993	unsigned u1Long : 1;
1994	/** 0e - This flags meaning depends on the segment type. Try make sense out
1995	* of the intel manual yourself. */
1996	unsigned u1DefBig : 1;
1997	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
1998	* clear byte. */
1999	unsigned u1Granularity : 1;
2000	} X86DESCATTRBITS;
2001
2002
2003	#pragma pack(1)
2004	typedef union X86DESCATTR
2005	{
2006	/** Unsigned integer view. */
2007	uint32_t u;
2008	/** Normal view. */
2009	X86DESCATTRBITS n;
2010	} X86DESCATTR;
2011	#pragma pack()
2012	/** Pointer to descriptor attributes. */
2013	typedef X86DESCATTR *PX86DESCATTR;
2014	/** Pointer to const descriptor attributes. */
2015	typedef const X86DESCATTR *PCX86DESCATTR;
2016
2017
2018	/**
2019	* Generic descriptor table entry
2020	*/
2021	#pragma pack(1)
2022	typedef struct X86DESCGENERIC
2023	{
2024	/** Limit - Low word. */
2025	unsigned u16LimitLow : 16;
2026	/** Base address - lowe word.
2027	* Don't try set this to 24 because MSC is doing stupid things then. */
2028	unsigned u16BaseLow : 16;
2029	/** Base address - first 8 bits of high word. */
2030	unsigned u8BaseHigh1 : 8;
2031	/** Segment Type. */
2032	unsigned u4Type : 4;
2033	/** Descriptor Type. System(=0) or code/data selector */
2034	unsigned u1DescType : 1;
2035	/** Descriptor Privelege level. */
2036	unsigned u2Dpl : 2;
2037	/** Flags selector present(=1) or not. */
2038	unsigned u1Present : 1;
2039	/** Segment limit 16-19. */
2040	unsigned u4LimitHigh : 4;
2041	/** Available for system software. */
2042	unsigned u1Available : 1;
2043	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2044	unsigned u1Long : 1;
2045	/** This flags meaning depends on the segment type. Try make sense out
2046	* of the intel manual yourself. */
2047	unsigned u1DefBig : 1;
2048	/** Granularity of the limit. If set 4KB granularity is used, if
2049	* clear byte. */
2050	unsigned u1Granularity : 1;
2051	/** Base address - highest 8 bits. */
2052	unsigned u8BaseHigh2 : 8;
2053	} X86DESCGENERIC;
2054	#pragma pack()
2055	/** Pointer to a generic descriptor entry. */
2056	typedef X86DESCGENERIC *PX86DESCGENERIC;
2057	/** Pointer to a const generic descriptor entry. */
2058	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2059
2060	/**
2061	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2062	*/
2063	typedef struct X86DESCGATE
2064	{
2065	/** Target code segment offset - Low word.
2066	* Ignored if task-gate. */
2067	unsigned u16OffsetLow : 16;
2068	/** Target code segment selector for call-, interrupt- and trap-gates,
2069	* TSS selector if task-gate. */
2070	unsigned u16Sel : 16;
2071	/** Number of parameters for a call-gate.
2072	* Ignored if interrupt-, trap- or task-gate. */
2073	unsigned u4ParmCount : 4;
2074	/** Reserved / ignored. */
2075	unsigned u4Reserved : 4;
2076	/** Segment Type. */
2077	unsigned u4Type : 4;
2078	/** Descriptor Type (0 = system). */
2079	unsigned u1DescType : 1;
2080	/** Descriptor Privelege level. */
2081	unsigned u2Dpl : 2;
2082	/** Flags selector present(=1) or not. */
2083	unsigned u1Present : 1;
2084	/** Target code segment offset - High word.
2085	* Ignored if task-gate. */
2086	unsigned u16OffsetHigh : 16;
2087	} X86DESCGATE;
2088	AssertCompileSize(X86DESCGATE, 8);
2089	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2090	typedef X86DESCGATE *PX86DESCGATE;
2091	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2092	typedef const X86DESCGATE *PCX86DESCGATE;
2093
2094	/**
2095	* Descriptor table entry.
2096	*/
2097	#pragma pack(1)
2098	typedef union X86DESC
2099	{
2100	/** Generic descriptor view. */
2101	X86DESCGENERIC Gen;
2102	/** Gate descriptor view. */
2103	X86DESCGATE Gate;
2104
2105	/** 8 bit unsigned interger view. */
2106	uint8_t au8[8];
2107	/** 16 bit unsigned interger view. */
2108	uint16_t au16[4];
2109	/** 32 bit unsigned interger view. */
2110	uint32_t au32[2];
2111	} X86DESC;
2112	AssertCompileSize(X86DESC, 8);
2113	#pragma pack()
2114	/** Pointer to descriptor table entry. */
2115	typedef X86DESC *PX86DESC;
2116	/** Pointer to const descriptor table entry. */
2117	typedef const X86DESC *PCX86DESC;
2118
2119	/** @def X86DESC_BASE
2120	* Return the base address of a descriptor.
2121	*/
2122	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2123	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2124	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2125	\| ( (desc).Gen.u16BaseLow ) )
2126
2127	/** @def X86DESC_LIMIT
2128	* Return the limit of a descriptor.
2129	*/
2130	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2131	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2132	\| ( (desc).Gen.u16LimitLow ) )
2133
2134	/**
2135	* 64 bits generic descriptor table entry
2136	* Note: most of these bits have no meaning in long mode.
2137	*/
2138	#pragma pack(1)
2139	typedef struct X86DESC64GENERIC
2140	{
2141	/** Limit - Low word - IGNORED. */
2142	unsigned u16LimitLow : 16;
2143	/** Base address - lowe word. - IGNORED
2144	* Don't try set this to 24 because MSC is doing stupid things then. */
2145	unsigned u16BaseLow : 16;
2146	/** Base address - first 8 bits of high word. - IGNORED */
2147	unsigned u8BaseHigh1 : 8;
2148	/** Segment Type. */
2149	unsigned u4Type : 4;
2150	/** Descriptor Type. System(=0) or code/data selector */
2151	unsigned u1DescType : 1;
2152	/** Descriptor Privelege level. */
2153	unsigned u2Dpl : 2;
2154	/** Flags selector present(=1) or not. */
2155	unsigned u1Present : 1;
2156	/** Segment limit 16-19. - IGNORED */
2157	unsigned u4LimitHigh : 4;
2158	/** Available for system software. - IGNORED */
2159	unsigned u1Available : 1;
2160	/** Long mode flag. */
2161	unsigned u1Long : 1;
2162	/** This flags meaning depends on the segment type. Try make sense out
2163	* of the intel manual yourself. */
2164	unsigned u1DefBig : 1;
2165	/** Granularity of the limit. If set 4KB granularity is used, if
2166	* clear byte. - IGNORED */
2167	unsigned u1Granularity : 1;
2168	/** Base address - highest 8 bits. - IGNORED */
2169	unsigned u8BaseHigh2 : 8;
2170	/** Base address - bits 63-32. */
2171	unsigned u32BaseHigh3 : 32;
2172	unsigned u8Reserved : 8;
2173	unsigned u5Zeros : 5;
2174	unsigned u19Reserved : 19;
2175	} X86DESC64GENERIC;
2176	#pragma pack()
2177	/** Pointer to a generic descriptor entry. */
2178	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2179	/** Pointer to a const generic descriptor entry. */
2180	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2181
2182	/**
2183	* System descriptor table entry (64 bits)
2184	*
2185	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2186	*/
2187	#pragma pack(1)
2188	typedef struct X86DESC64SYSTEM
2189	{
2190	/** Limit - Low word. */
2191	unsigned u16LimitLow : 16;
2192	/** Base address - lowe word.
2193	* Don't try set this to 24 because MSC is doing stupid things then. */
2194	unsigned u16BaseLow : 16;
2195	/** Base address - first 8 bits of high word. */
2196	unsigned u8BaseHigh1 : 8;
2197	/** Segment Type. */
2198	unsigned u4Type : 4;
2199	/** Descriptor Type. System(=0) or code/data selector */
2200	unsigned u1DescType : 1;
2201	/** Descriptor Privelege level. */
2202	unsigned u2Dpl : 2;
2203	/** Flags selector present(=1) or not. */
2204	unsigned u1Present : 1;
2205	/** Segment limit 16-19. */
2206	unsigned u4LimitHigh : 4;
2207	/** Available for system software. */
2208	unsigned u1Available : 1;
2209	/** Reserved - 0. */
2210	unsigned u1Reserved : 1;
2211	/** This flags meaning depends on the segment type. Try make sense out
2212	* of the intel manual yourself. */
2213	unsigned u1DefBig : 1;
2214	/** Granularity of the limit. If set 4KB granularity is used, if
2215	* clear byte. */
2216	unsigned u1Granularity : 1;
2217	/** Base address - bits 31-24. */
2218	unsigned u8BaseHigh2 : 8;
2219	/** Base address - bits 63-32. */
2220	unsigned u32BaseHigh3 : 32;
2221	unsigned u8Reserved : 8;
2222	unsigned u5Zeros : 5;
2223	unsigned u19Reserved : 19;
2224	} X86DESC64SYSTEM;
2225	#pragma pack()
2226	/** Pointer to a system descriptor entry. */
2227	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2228	/** Pointer to a const system descriptor entry. */
2229	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2230
2231	/**
2232	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2233	*/
2234	typedef struct X86DESC64GATE
2235	{
2236	/** Target code segment offset - Low word. */
2237	unsigned u16OffsetLow : 16;
2238	/** Target code segment selector. */
2239	unsigned u16Sel : 16;
2240	/** Interrupt stack table for interrupt- and trap-gates.
2241	* Ignored by call-gates. */
2242	unsigned u3IST : 3;
2243	/** Reserved / ignored. */
2244	unsigned u5Reserved : 5;
2245	/** Segment Type. */
2246	unsigned u4Type : 4;
2247	/** Descriptor Type (0 = system). */
2248	unsigned u1DescType : 1;
2249	/** Descriptor Privelege level. */
2250	unsigned u2Dpl : 2;
2251	/** Flags selector present(=1) or not. */
2252	unsigned u1Present : 1;
2253	/** Target code segment offset - High word.
2254	* Ignored if task-gate. */
2255	unsigned u16OffsetHigh : 16;
2256	/** Target code segment offset - Top dword.
2257	* Ignored if task-gate. */
2258	unsigned u32OffsetTop : 32;
2259	/** Reserved / ignored / must be zero.
2260	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2261	unsigned u32Reserved : 32;
2262	} X86DESC64GATE;
2263	AssertCompileSize(X86DESC64GATE, 16);
2264	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2265	typedef X86DESC64GATE *PX86DESC64GATE;
2266	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2267	typedef const X86DESC64GATE *PCX86DESC64GATE;
2268
2269
2270	/**
2271	* Descriptor table entry.
2272	*/
2273	#pragma pack(1)
2274	typedef union X86DESC64
2275	{
2276	/** Generic descriptor view. */
2277	X86DESC64GENERIC Gen;
2278	/** System descriptor view. */
2279	X86DESC64SYSTEM System;
2280	/** Gate descriptor view. */
2281	X86DESC64GATE Gate;
2282
2283	/** 8 bit unsigned interger view. */
2284	uint8_t au8[16];
2285	/** 16 bit unsigned interger view. */
2286	uint16_t au16[8];
2287	/** 32 bit unsigned interger view. */
2288	uint32_t au32[4];
2289	/** 64 bit unsigned interger view. */
2290	uint64_t au64[2];
2291	} X86DESC64;
2292	AssertCompileSize(X86DESC64, 16);
2293	#pragma pack()
2294	/** Pointer to descriptor table entry. */
2295	typedef X86DESC64 *PX86DESC64;
2296	/** Pointer to const descriptor table entry. */
2297	typedef const X86DESC64 *PCX86DESC64;
2298
2299	/** @def X86DESC64_BASE
2300	* Return the base of a 64-bit descriptor.
2301	*/
2302	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2303	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2304	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2305	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2306	\| ( (desc).Gen.u16BaseLow ) )
2307
2308
2309
2310	/** @name Host system descriptor table entry - Use with care!
2311	* @{ */
2312	/** Host system descriptor table entry. */
2313	#if HC_ARCH_BITS == 64
2314	typedef X86DESC64 X86DESCHC;
2315	#else
2316	typedef X86DESC X86DESCHC;
2317	#endif
2318	/** Pointer to a host system descriptor table entry. */
2319	#if HC_ARCH_BITS == 64
2320	typedef PX86DESC64 PX86DESCHC;
2321	#else
2322	typedef PX86DESC PX86DESCHC;
2323	#endif
2324	/** Pointer to a const host system descriptor table entry. */
2325	#if HC_ARCH_BITS == 64
2326	typedef PCX86DESC64 PCX86DESCHC;
2327	#else
2328	typedef PCX86DESC PCX86DESCHC;
2329	#endif
2330	/** @} */
2331
2332
2333	/** @name Selector Descriptor Types.
2334	* @{
2335	*/
2336
2337	/** @name Non-System Selector Types.
2338	* @{ */
2339	/** Code(=set)/Data(=clear) bit. */
2340	#define X86_SEL_TYPE_CODE 8
2341	/** Memory(=set)/System(=clear) bit. */
2342	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2343	/** Accessed bit. */
2344	#define X86_SEL_TYPE_ACCESSED 1
2345	/** Expand down bit (for data selectors only). */
2346	#define X86_SEL_TYPE_DOWN 4
2347	/** Conforming bit (for code selectors only). */
2348	#define X86_SEL_TYPE_CONF 4
2349	/** Write bit (for data selectors only). */
2350	#define X86_SEL_TYPE_WRITE 2
2351	/** Read bit (for code selectors only). */
2352	#define X86_SEL_TYPE_READ 2
2353
2354	/** Read only selector type. */
2355	#define X86_SEL_TYPE_RO 0
2356	/** Accessed read only selector type. */
2357	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2358	/** Read write selector type. */
2359	#define X86_SEL_TYPE_RW 2
2360	/** Accessed read write selector type. */
2361	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2362	/** Expand down read only selector type. */
2363	#define X86_SEL_TYPE_RO_DOWN 4
2364	/** Accessed expand down read only selector type. */
2365	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2366	/** Expand down read write selector type. */
2367	#define X86_SEL_TYPE_RW_DOWN 6
2368	/** Accessed expand down read write selector type. */
2369	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2370	/** Execute only selector type. */
2371	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2372	/** Accessed execute only selector type. */
2373	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2374	/** Execute and read selector type. */
2375	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2376	/** Accessed execute and read selector type. */
2377	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2378	/** Conforming execute only selector type. */
2379	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2380	/** Accessed Conforming execute only selector type. */
2381	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2382	/** Conforming execute and write selector type. */
2383	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2384	/** Accessed Conforming execute and write selector type. */
2385	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2386	/** @} */
2387
2388
2389	/** @name System Selector Types.
2390	* @{ */
2391	/** Undefined system selector type. */
2392	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2393	/** 286 TSS selector. */
2394	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2395	/** LDT selector. */
2396	#define X86_SEL_TYPE_SYS_LDT 2
2397	/** 286 TSS selector - Busy. */
2398	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2399	/** 286 Callgate selector. */
2400	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2401	/** Taskgate selector. */
2402	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2403	/** 286 Interrupt gate selector. */
2404	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2405	/** 286 Trapgate selector. */
2406	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2407	/** Undefined system selector. */
2408	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2409	/** 386 TSS selector. */
2410	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2411	/** Undefined system selector. */
2412	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2413	/** 386 TSS selector - Busy. */
2414	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2415	/** 386 Callgate selector. */
2416	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2417	/** Undefined system selector. */
2418	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2419	/** 386 Interruptgate selector. */
2420	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2421	/** 386 Trapgate selector. */
2422	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2423	/** @} */
2424
2425	/** @name AMD64 System Selector Types.
2426	* @{ */
2427	#define AMD64_SEL_TYPE_SYS_LDT 2
2428	/** 286 TSS selector - Busy. */
2429	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2430	/** 386 TSS selector - Busy. */
2431	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2432	/** 386 Callgate selector. */
2433	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2434	/** 386 Interruptgate selector. */
2435	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2436	/** 386 Trapgate selector. */
2437	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2438	/** @} */
2439
2440	/** @} */
2441
2442
2443	/** @name Descriptor Table Entry Flag Masks.
2444	* These are for the 2nd 32-bit word of a descriptor.
2445	* @{ */
2446	/** Bits 8-11 - TYPE - Descriptor type mask. */
2447	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2448	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2449	#define X86_DESC_S RT_BIT(12)
2450	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2451	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2452	/** Bit 15 - P - Present. */
2453	#define X86_DESC_P RT_BIT(15)
2454	/** Bit 20 - AVL - Available for system software. */
2455	#define X86_DESC_AVL RT_BIT(20)
2456	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2457	#define X86_DESC_DB RT_BIT(22)
2458	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2459	* used, if clear byte. */
2460	#define X86_DESC_G RT_BIT(23)
2461	/** @} */
2462
2463	/** @} */
2464
2465	/** @name Task segment.
2466	* @{
2467	*/
2468	#pragma pack(1)
2469	typedef struct X86TSS32
2470	{
2471	/** Back link to previous task. (static) */
2472	RTSEL selPrev;
2473	uint16_t padding1;
2474	/** Ring-0 stack pointer. (static) */
2475	uint32_t esp0;
2476	/** Ring-0 stack segment. (static) */
2477	RTSEL ss0;
2478	uint16_t padding_ss0;
2479	/** Ring-1 stack pointer. (static) */
2480	uint32_t esp1;
2481	/** Ring-1 stack segment. (static) */
2482	RTSEL ss1;
2483	uint16_t padding_ss1;
2484	/** Ring-2 stack pointer. (static) */
2485	uint32_t esp2;
2486	/** Ring-2 stack segment. (static) */
2487	RTSEL ss2;
2488	uint16_t padding_ss2;
2489	/** Page directory for the task. (static) */
2490	uint32_t cr3;
2491	/** EIP before task switch. */
2492	uint32_t eip;
2493	/** EFLAGS before task switch. */
2494	uint32_t eflags;
2495	/** EAX before task switch. */
2496	uint32_t eax;
2497	/** ECX before task switch. */
2498	uint32_t ecx;
2499	/** EDX before task switch. */
2500	uint32_t edx;
2501	/** EBX before task switch. */
2502	uint32_t ebx;
2503	/** ESP before task switch. */
2504	uint32_t esp;
2505	/** EBP before task switch. */
2506	uint32_t ebp;
2507	/** ESI before task switch. */
2508	uint32_t esi;
2509	/** EDI before task switch. */
2510	uint32_t edi;
2511	/** ES before task switch. */
2512	RTSEL es;
2513	uint16_t padding_es;
2514	/** CS before task switch. */
2515	RTSEL cs;
2516	uint16_t padding_cs;
2517	/** SS before task switch. */
2518	RTSEL ss;
2519	uint16_t padding_ss;
2520	/** DS before task switch. */
2521	RTSEL ds;
2522	uint16_t padding_ds;
2523	/** FS before task switch. */
2524	RTSEL fs;
2525	uint16_t padding_fs;
2526	/** GS before task switch. */
2527	RTSEL gs;
2528	uint16_t padding_gs;
2529	/** LDTR before task switch. */
2530	RTSEL selLdt;
2531	uint16_t padding_ldt;
2532	/** Debug trap flag */
2533	uint16_t fDebugTrap;
2534	/** Offset relative to the TSS of the start of the I/O Bitmap
2535	* and the end of the interrupt redirection bitmap. */
2536	uint16_t offIoBitmap;
2537	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2538	uint8_t IntRedirBitmap[32];
2539	} X86TSS32;
2540	#pragma pack()
2541	/** Pointer to task segment. */
2542	typedef X86TSS32 *PX86TSS32;
2543	/** Pointer to const task segment. */
2544	typedef const X86TSS32 *PCX86TSS32;
2545	/** @} */
2546
2547
2548	/** @name 64 bits Task segment.
2549	* @{
2550	*/
2551	#pragma pack(1)
2552	typedef struct X86TSS64
2553	{
2554	/** Reserved. */
2555	uint32_t u32Reserved;
2556	/** Ring-0 stack pointer. (static) */
2557	uint64_t rsp0;
2558	/** Ring-1 stack pointer. (static) */
2559	uint64_t rsp1;
2560	/** Ring-2 stack pointer. (static) */
2561	uint64_t rsp2;
2562	/** Reserved. */
2563	uint32_t u32Reserved2[2];
2564	/* IST */
2565	uint64_t ist1;
2566	uint64_t ist2;
2567	uint64_t ist3;
2568	uint64_t ist4;
2569	uint64_t ist5;
2570	uint64_t ist6;
2571	uint64_t ist7;
2572	/* Reserved. */
2573	uint16_t u16Reserved[5];
2574	/** Offset relative to the TSS of the start of the I/O Bitmap
2575	* and the end of the interrupt redirection bitmap. */
2576	uint16_t offIoBitmap;
2577	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2578	uint8_t IntRedirBitmap[32];
2579	} X86TSS64;
2580	#pragma pack()
2581	/** Pointer to task segment. */
2582	typedef X86TSS64 *PX86TSS64;
2583	/** Pointer to const task segment. */
2584	typedef const X86TSS64 *PCX86TSS64;
2585	AssertCompileSize(X86TSS64, 136);
2586
2587	/** @} */
2588
2589
2590	/** @name Selectors.
2591	* @{
2592	*/
2593
2594	/**
2595	* The shift used to convert a selector from and to index an index (C).
2596	*/
2597	#define X86_SEL_SHIFT 3
2598
2599	/**
2600	* The mask used to mask off the table indicator and CPL of an selector.
2601	*/
2602	#define X86_SEL_MASK 0xfff8
2603
2604	/**
2605	* The bit indicating that a selector is in the LDT and not in the GDT.
2606	*/
2607	#define X86_SEL_LDT 0x0004
2608	/**
2609	* The bit mask for getting the RPL of a selector.
2610	*/
2611	#define X86_SEL_RPL 0x0003
2612
2613	/** @} */
2614
2615
2616	/**
2617	* x86 Exceptions/Faults/Traps.
2618	*/
2619	typedef enum X86XCPT
2620	{
2621	/** \#DE - Divide error. */
2622	X86_XCPT_DE = 0x00,
2623	/** \#DB - Debug event (single step, DRx, ..) */
2624	X86_XCPT_DB = 0x01,
2625	/** NMI - Non-Maskable Interrupt */
2626	X86_XCPT_NMI = 0x02,
2627	/** \#BP - Breakpoint (INT3). */
2628	X86_XCPT_BP = 0x03,
2629	/** \#OF - Overflow (INTO). */
2630	X86_XCPT_OF = 0x04,
2631	/** \#BR - Bound range exceeded (BOUND). */
2632	X86_XCPT_BR = 0x05,
2633	/** \#UD - Undefined opcode. */
2634	X86_XCPT_UD = 0x06,
2635	/** \#NM - Device not available (math coprocessor device). */
2636	X86_XCPT_NM = 0x07,
2637	/** \#DF - Double fault. */
2638	X86_XCPT_DF = 0x08,
2639	/** ??? - Coprocessor segment overrun (obsolete). */
2640	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2641	/** \#TS - Taskswitch (TSS). */
2642	X86_XCPT_TS = 0x0a,
2643	/** \#NP - Segment no present. */
2644	X86_XCPT_NP = 0x0b,
2645	/** \#SS - Stack segment fault. */
2646	X86_XCPT_SS = 0x0c,
2647	/** \#GP - General protection fault. */
2648	X86_XCPT_GP = 0x0d,
2649	/** \#PF - Page fault. */
2650	X86_XCPT_PF = 0x0e,
2651	/* 0x0f is reserved. */
2652	/** \#MF - Math fault (FPU). */
2653	X86_XCPT_MF = 0x10,
2654	/** \#AC - Alignment check. */
2655	X86_XCPT_AC = 0x11,
2656	/** \#MC - Machine check. */
2657	X86_XCPT_MC = 0x12,
2658	/** \#XF - SIMD Floating-Pointer Exception. */
2659	X86_XCPT_XF = 0x13
2660	} X86XCPT;
2661	/** Pointer to a x86 exception code. */
2662	typedef X86XCPT *PX86XCPT;
2663	/** Pointer to a const x86 exception code. */
2664	typedef const X86XCPT *PCX86XCPT;
2665
2666
2667	/** @name Trap Error Codes
2668	* @{
2669	*/
2670	/** External indicator. */
2671	#define X86_TRAP_ERR_EXTERNAL 1
2672	/** IDT indicator. */
2673	#define X86_TRAP_ERR_IDT 2
2674	/** Descriptor table indicator - If set LDT, if clear GDT. */
2675	#define X86_TRAP_ERR_TI 4
2676	/** Mask for getting the selector. */
2677	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2678	/** Shift for getting the selector table index (C type index). */
2679	#define X86_TRAP_ERR_SEL_SHIFT 3
2680	/** @} */
2681
2682
2683	/** @name \#PF Trap Error Codes
2684	* @{
2685	*/
2686	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2687	#define X86_TRAP_PF_P RT_BIT(0)
2688	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2689	#define X86_TRAP_PF_RW RT_BIT(1)
2690	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2691	#define X86_TRAP_PF_US RT_BIT(2)
2692	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2693	#define X86_TRAP_PF_RSVD RT_BIT(3)
2694	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2695	#define X86_TRAP_PF_ID RT_BIT(4)
2696	/** @} */
2697
2698	#pragma pack(1)
2699	/**
2700	* 32-bit IDTR/GDTR.
2701	*/
2702	typedef struct X86XDTR32
2703	{
2704	/** Size of the descriptor table. */
2705	uint16_t cb;
2706	/** Address of the descriptor table. */
2707	uint32_t uAddr;
2708	} X86XDTR32, *PX86XDTR32;
2709	#pragma pack()
2710
2711	#pragma pack(1)
2712	/**
2713	* 64-bit IDTR/GDTR.
2714	*/
2715	typedef struct X86XDTR64
2716	{
2717	/** Size of the descriptor table. */
2718	uint16_t cb;
2719	/** Address of the descriptor table. */
2720	uint64_t uAddr;
2721	} X86XDTR64, *PX86XDTR64;
2722	#pragma pack()
2723
2724	/** @} */
2725
2726	#endif
2727

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source: vbox/trunk/include/VBox/x86.h@ 27084

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