x86.h@ 6000

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 innotek GmbH
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	/*
27	* x86.mac is generated from this file using:
28	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
29	*/
30
31	#ifndef ___VBox_x86_h
32	#define ___VBox_x86_h
33
34	#include <VBox/types.h>
35
36	/* Workaround for Solaris sys/regset.h defining CS, DS */
37	#if defined(RT_OS_SOLARIS)
38	# undef CS
39	# undef DS
40	#endif
41
42	/** @defgroup grp_x86 x86 Types and Definitions
43	* @{
44	*/
45
46	/**
47	* EFLAGS Bits.
48	*/
49	typedef struct X86EFLAGSBITS
50	{
51	/** Bit 0 - CF - Carry flag - Status flag. */
52	unsigned u1CF : 1;
53	/** Bit 1 - 1 - Reserved flag. */
54	unsigned u1Reserved0 : 1;
55	/** Bit 2 - PF - Parity flag - Status flag. */
56	unsigned u1PF : 1;
57	/** Bit 3 - 0 - Reserved flag. */
58	unsigned u1Reserved1 : 1;
59	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
60	unsigned u1AF : 1;
61	/** Bit 5 - 0 - Reserved flag. */
62	unsigned u1Reserved2 : 1;
63	/** Bit 6 - ZF - Zero flag - Status flag. */
64	unsigned u1ZF : 1;
65	/** Bit 7 - SF - Signed flag - Status flag. */
66	unsigned u1SF : 1;
67	/** Bit 8 - TF - Trap flag - System flag. */
68	unsigned u1TF : 1;
69	/** Bit 9 - IF - Interrupt flag - System flag. */
70	unsigned u1IF : 1;
71	/** Bit 10 - DF - Direction flag - Control flag. */
72	unsigned u1DF : 1;
73	/** Bit 11 - OF - Overflow flag - Status flag. */
74	unsigned u1OF : 1;
75	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
76	unsigned u2IOPL : 2;
77	/** Bit 14 - NT - Nested task flag - System flag. */
78	unsigned u1NT : 1;
79	/** Bit 15 - 0 - Reserved flag. */
80	unsigned u1Reserved3 : 1;
81	/** Bit 16 - RF - Resume flag - System flag. */
82	unsigned u1RF : 1;
83	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
84	unsigned u1VM : 1;
85	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
86	unsigned u1AC : 1;
87	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
88	unsigned u1VIF : 1;
89	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
90	unsigned u1VIP : 1;
91	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
92	unsigned u1ID : 1;
93	/** Bit 22-31 - 0 - Reserved flag. */
94	unsigned u10Reserved4 : 10;
95	} X86EFLAGSBITS;
96	/** Pointer to EFLAGS bits. */
97	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
98	/** Pointer to const EFLAGS bits. */
99	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
100
101	/**
102	* EFLAGS.
103	*/
104	typedef union X86EFLAGS
105	{
106	/** The bitfield view. */
107	X86EFLAGSBITS Bits;
108	/** The 8-bit view. */
109	uint8_t au8[4];
110	/** The 16-bit view. */
111	uint16_t au16[2];
112	/** The 32-bit view. */
113	uint32_t au32[1];
114	/** The 32-bit view. */
115	uint32_t u32;
116	} X86EFLAGS;
117	/** Pointer to EFLAGS. */
118	typedef X86EFLAGS *PX86EFLAGS;
119	/** Pointer to const EFLAGS. */
120	typedef const X86EFLAGS *PCX86EFLAGS;
121
122
123	/** @name EFLAGS
124	* @{
125	*/
126	/** Bit 0 - CF - Carry flag - Status flag. */
127	#define X86_EFL_CF RT_BIT(0)
128	/** Bit 2 - PF - Parity flag - Status flag. */
129	#define X86_EFL_PF RT_BIT(2)
130	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
131	#define X86_EFL_AF RT_BIT(4)
132	/** Bit 6 - ZF - Zero flag - Status flag. */
133	#define X86_EFL_ZF RT_BIT(6)
134	/** Bit 7 - SF - Signed flag - Status flag. */
135	#define X86_EFL_SF RT_BIT(7)
136	/** Bit 8 - TF - Trap flag - System flag. */
137	#define X86_EFL_TF RT_BIT(8)
138	/** Bit 9 - IF - Interrupt flag - System flag. */
139	#define X86_EFL_IF RT_BIT(9)
140	/** Bit 10 - DF - Direction flag - Control flag. */
141	#define X86_EFL_DF RT_BIT(10)
142	/** Bit 11 - OF - Overflow flag - Status flag. */
143	#define X86_EFL_OF RT_BIT(11)
144	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
145	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
146	/** Bit 14 - NT - Nested task flag - System flag. */
147	#define X86_EFL_NT RT_BIT(14)
148	/** Bit 16 - RF - Resume flag - System flag. */
149	#define X86_EFL_RF RT_BIT(16)
150	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
151	#define X86_EFL_VM RT_BIT(17)
152	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
153	#define X86_EFL_AC RT_BIT(18)
154	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
155	#define X86_EFL_VIF RT_BIT(19)
156	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
157	#define X86_EFL_VIP RT_BIT(20)
158	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
159	#define X86_EFL_ID RT_BIT(21)
160	/** IOPL shift. */
161	#define X86_EFL_IOPL_SHIFT 12
162	/** The the IOPL level from the flags. */
163	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
164	/** @} */
165
166
167	/** CPUID Feature information - ECX.
168	* CPUID query with EAX=1.
169	*/
170	typedef struct X86CPUIDFEATECX
171	{
172	/** Bit 0 - SSE3 - Supports SSE3 or not. */
173	unsigned u1SSE3 : 1;
174	/** Reserved. */
175	unsigned u2Reserved1 : 2;
176	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
177	unsigned u1Monitor : 1;
178	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
179	unsigned u1CPLDS : 1;
180	/** Bit 5 - VMX - Virtual Machine Technology. */
181	unsigned u1VMX : 1;
182	/** Reserved. */
183	unsigned u1Reserved2 : 1;
184	/** Bit 7 - EST - Enh. SpeedStep Tech. */
185	unsigned u1EST : 1;
186	/** Bit 8 - TM2 - Terminal Monitor 2. */
187	unsigned u1TM2 : 1;
188	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
189	unsigned u1SSSE3 : 1;
190	/** Bit 10 - CNTX-ID - L1 Context ID. */
191	unsigned u1CNTXID : 1;
192	/** Reserved. */
193	unsigned u2Reserved4 : 2;
194	/** Bit 13 - CX16 - CMPXCHG16B. */
195	unsigned u1CX16 : 1;
196	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
197	unsigned u1TPRUpdate : 1;
198	/** Reserved. */
199	unsigned u17Reserved5 : 17;
200
201	} X86CPUIDFEATECX;
202	/** Pointer to CPUID Feature Information - ECX. */
203	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
204	/** Pointer to const CPUID Feature Information - ECX. */
205	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
206
207
208	/** CPUID Feature Information - EDX.
209	* CPUID query with EAX=1.
210	*/
211	typedef struct X86CPUIDFEATEDX
212	{
213	/** Bit 0 - FPU - x87 FPU on Chip. */
214	unsigned u1FPU : 1;
215	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
216	unsigned u1VME : 1;
217	/** Bit 2 - DE - Debugging extensions. */
218	unsigned u1DE : 1;
219	/** Bit 3 - PSE - Page Size Extension. */
220	unsigned u1PSE : 1;
221	/** Bit 4 - TSC - Time Stamp Counter. */
222	unsigned u1TSC : 1;
223	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
224	unsigned u1MSR : 1;
225	/** Bit 6 - PAE - Physical Address Extension. */
226	unsigned u1PAE : 1;
227	/** Bit 7 - MCE - Machine Check Exception. */
228	unsigned u1MCE : 1;
229	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
230	unsigned u1CX8 : 1;
231	/** Bit 9 - APIC - APIC On-Chick. */
232	unsigned u1APIC : 1;
233	/** Bit 10 - Reserved. */
234	unsigned u1Reserved1 : 1;
235	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
236	unsigned u1SEP : 1;
237	/** Bit 12 - MTRR - Memory Type Range Registers. */
238	unsigned u1MTRR : 1;
239	/** Bit 13 - PGE - PTE Global Bit. */
240	unsigned u1PGE : 1;
241	/** Bit 14 - MCA - Machine Check Architecture. */
242	unsigned u1MCA : 1;
243	/** Bit 15 - CMOV - Conditional Move Instructions. */
244	unsigned u1CMOV : 1;
245	/** Bit 16 - PAT - Page Attribute Table. */
246	unsigned u1PAT : 1;
247	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
248	unsigned u1PSE36 : 1;
249	/** Bit 18 - PSN - Processor Serial Number. */
250	unsigned u1PSN : 1;
251	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
252	unsigned u1CLFSH : 1;
253	/** Bit 20 - Reserved. */
254	unsigned u1Reserved2 : 1;
255	/** Bit 21 - DS - Debug Store. */
256	unsigned u1DS : 1;
257	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
258	unsigned u1ACPI : 1;
259	/** Bit 23 - MMX - Intel MMX 'Technology'. */
260	unsigned u1MMX : 1;
261	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
262	unsigned u1FXSR : 1;
263	/** Bit 25 - SSE - SSE Support. */
264	unsigned u1SSE : 1;
265	/** Bit 26 - SSE2 - SSE2 Support. */
266	unsigned u1SSE2 : 1;
267	/** Bit 27 - SS - Self Snoop. */
268	unsigned u1SS : 1;
269	/** Bit 28 - HTT - Hyper-Threading Technology. */
270	unsigned u1HTT : 1;
271	/** Bit 29 - TM - Thermal Monitor. */
272	unsigned u1TM : 1;
273	/** Bit 30 - Reserved - . */
274	unsigned u1Reserved3 : 1;
275	/** Bit 31 - PBE - Pending Break Enabled. */
276	unsigned u1PBE : 1;
277	} X86CPUIDFEATEDX;
278	/** Pointer to CPUID Feature Information - EDX. */
279	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
280	/** Pointer to const CPUID Feature Information - EDX. */
281	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
282
283	/** @name CPUID Vendor information.
284	* CPUID query with EAX=0.
285	* @{
286	*/
287	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
288	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
289	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
290
291	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
292	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
293	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
294	/** @} */
295
296
297	/** @name CPUID Feature information.
298	* CPUID query with EAX=1.
299	* @{
300	*/
301	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
302	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
303	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
304	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
305	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
306	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
307	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
308	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
309	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
310	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
311	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
312	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
313	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
314	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
315	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
316	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
317	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
318	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
319	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
320	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
321	/** ECX Bit 23 - POPCOUNT instruction. */
322	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
323
324
325	/** Bit 0 - FPU - x87 FPU on Chip. */
326	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
327	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
328	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
329	/** Bit 2 - DE - Debugging extensions. */
330	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
331	/** Bit 3 - PSE - Page Size Extension. */
332	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
333	/** Bit 4 - TSC - Time Stamp Counter. */
334	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
335	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
336	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
337	/** Bit 6 - PAE - Physical Address Extension. */
338	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
339	/** Bit 7 - MCE - Machine Check Exception. */
340	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
341	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
342	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
343	/** Bit 9 - APIC - APIC On-Chip. */
344	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
345	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
346	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
347	/** Bit 12 - MTRR - Memory Type Range Registers. */
348	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
349	/** Bit 13 - PGE - PTE Global Bit. */
350	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
351	/** Bit 14 - MCA - Machine Check Architecture. */
352	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
353	/** Bit 15 - CMOV - Conditional Move Instructions. */
354	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
355	/** Bit 16 - PAT - Page Attribute Table. */
356	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
357	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
358	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
359	/** Bit 18 - PSN - Processor Serial Number. */
360	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
361	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
362	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
363	/** Bit 21 - DS - Debug Store. */
364	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
365	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
366	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
367	/** Bit 23 - MMX - Intel MMX Technology. */
368	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
369	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
370	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
371	/** Bit 25 - SSE - SSE Support. */
372	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
373	/** Bit 26 - SSE2 - SSE2 Support. */
374	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
375	/** Bit 27 - SS - Self Snoop. */
376	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
377	/** Bit 28 - HTT - Hyper-Threading Technology. */
378	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
379	/** Bit 29 - TM - Therm. Monitor. */
380	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
381	/** Bit 31 - PBE - Pending Break Enabled. */
382	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
383	/** @} */
384
385
386	/** @name CPUID AMD Feature information.
387	* CPUID query with EAX=0x80000001.
388	* @{
389	*/
390	/** Bit 0 - FPU - x87 FPU on Chip. */
391	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
392	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
393	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
394	/** Bit 2 - DE - Debugging extensions. */
395	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
396	/** Bit 3 - PSE - Page Size Extension. */
397	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
398	/** Bit 4 - TSC - Time Stamp Counter. */
399	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
400	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
401	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
402	/** Bit 6 - PAE - Physical Address Extension. */
403	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
404	/** Bit 7 - MCE - Machine Check Exception. */
405	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
406	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
407	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
408	/** Bit 9 - APIC - APIC On-Chip. */
409	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
410	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
411	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
412	/** Bit 12 - MTRR - Memory Type Range Registers. */
413	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
414	/** Bit 13 - PGE - PTE Global Bit. */
415	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
416	/** Bit 14 - MCA - Machine Check Architecture. */
417	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
418	/** Bit 15 - CMOV - Conditional Move Instructions. */
419	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
420	/** Bit 16 - PAT - Page Attribute Table. */
421	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
422	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
423	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
424	/** Bit 20 - NX - AMD No-Execute Page Protection. */
425	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
426	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
427	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
428	/** Bit 23 - MMX - Intel MMX Technology. */
429	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
430	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
431	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
432	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
433	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
434	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
435	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
436	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
437	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
438	/** Bit 29 - LM - AMD Long Mode. */
439	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
440	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
441	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
442	/** Bit 31 - 3DNOW - AMD 3DNow. */
443	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
444
445	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
446	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
447	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
448	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
449	/** Bit 2 - SVM - AMD VM extensions. */
450	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
451	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
452	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
453	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
454	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
455	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
456	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
457	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
458	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
459	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
460	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
461	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
462	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
463	/** Bit 9 - OSVW - AMD OS visible workaround. */
464	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
465	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
466	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
467	/** Bit 13 - WDT - AMD Watchdog timer support. */
468	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
469
470	/** @} */
471
472
473	/** @name CR0
474	* @{ */
475	/** Bit 0 - PE - Protection Enabled */
476	#define X86_CR0_PE RT_BIT(0)
477	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
478	/** Bit 1 - MP - Monitor Coprocessor */
479	#define X86_CR0_MP RT_BIT(1)
480	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
481	/** Bit 2 - EM - Emulation. */
482	#define X86_CR0_EM RT_BIT(2)
483	#define X86_CR0_EMULATE_FPU RT_BIT(2)
484	/** Bit 3 - TS - Task Switch. */
485	#define X86_CR0_TS RT_BIT(3)
486	#define X86_CR0_TASK_SWITCH RT_BIT(3)
487	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
488	#define X86_CR0_ET RT_BIT(4)
489	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
490	/** Bit 5 - NE - Numeric error. */
491	#define X86_CR0_NE RT_BIT(5)
492	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
493	/** Bit 16 - WP - Write Protect. */
494	#define X86_CR0_WP RT_BIT(16)
495	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
496	/** Bit 18 - AM - Alignment Mask. */
497	#define X86_CR0_AM RT_BIT(18)
498	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
499	/** Bit 29 - NW - Not Write-though. */
500	#define X86_CR0_NW RT_BIT(29)
501	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
502	/** Bit 30 - WP - Cache Disable. */
503	#define X86_CR0_CD RT_BIT(30)
504	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
505	/** Bit 31 - PG - Paging. */
506	#define X86_CR0_PG RT_BIT(31)
507	#define X86_CR0_PAGING RT_BIT(31)
508	/** @} */
509
510
511	/** @name CR3
512	* @{ */
513	/** Bit 3 - PWT - Page-level Writes Transparent. */
514	#define X86_CR3_PWT RT_BIT(3)
515	/** Bit 4 - PCD - Page-level Cache Disable. */
516	#define X86_CR3_PCD RT_BIT(4)
517	/** Bits 12-31 - - Page directory page number. */
518	#define X86_CR3_PAGE_MASK (0xfffff000)
519	/** Bits 5-31 - - PAE Page directory page number. */
520	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
521	/** @} */
522
523
524	/** @name CR4
525	* @{ */
526	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
527	#define X86_CR4_VME RT_BIT(0)
528	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
529	#define X86_CR4_PVI RT_BIT(1)
530	/** Bit 2 - TSD - Time Stamp Disable. */
531	#define X86_CR4_TSD RT_BIT(2)
532	/** Bit 3 - DE - Debugging Extensions. */
533	#define X86_CR4_DE RT_BIT(3)
534	/** Bit 4 - PSE - Page Size Extension. */
535	#define X86_CR4_PSE RT_BIT(4)
536	/** Bit 5 - PAE - Physical Address Extension. */
537	#define X86_CR4_PAE RT_BIT(5)
538	/** Bit 6 - MCE - Machine-Check Enable. */
539	#define X86_CR4_MCE RT_BIT(6)
540	/** Bit 7 - PGE - Page Global Enable. */
541	#define X86_CR4_PGE RT_BIT(7)
542	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
543	#define X86_CR4_PCE RT_BIT(8)
544	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
545	#define X86_CR4_OSFSXR RT_BIT(9)
546	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
547	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
548	/** Bit 13 - VMXE - VMX mode is enabled. */
549	#define X86_CR4_VMXE RT_BIT(13)
550	/** @} */
551
552
553	/** @name DR6
554	* @{ */
555	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
556	#define X86_DR6_B0 RT_BIT(0)
557	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
558	#define X86_DR6_B1 RT_BIT(1)
559	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
560	#define X86_DR6_B2 RT_BIT(2)
561	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
562	#define X86_DR6_B3 RT_BIT(3)
563	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
564	#define X86_DR6_BD RT_BIT(13)
565	/** Bit 14 - BS - Single step */
566	#define X86_DR6_BS RT_BIT(14)
567	/** Bit 15 - BT - Task switch. (TSS T bit.) */
568	#define X86_DR6_BT RT_BIT(15)
569	/** @} */
570
571
572	/** @name DR7
573	* @{ */
574	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
575	#define X86_DR7_L0 RT_BIT(0)
576	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
577	#define X86_DR7_G0 RT_BIT(1)
578	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
579	#define X86_DR7_L1 RT_BIT(2)
580	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
581	#define X86_DR7_G1 RT_BIT(3)
582	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
583	#define X86_DR7_L2 RT_BIT(4)
584	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
585	#define X86_DR7_G2 RT_BIT(5)
586	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
587	#define X86_DR7_L3 RT_BIT(6)
588	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
589	#define X86_DR7_G3 RT_BIT(7)
590	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
591	#define X86_DR7_LE RT_BIT(8)
592	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
593	#define X86_DR7_GE RT_BIT(9)
594
595	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
596	* any DR register is accessed. */
597	#define X86_DR7_GD RT_BIT(13)
598	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
599	#define X86_DR7_RW0_MASK (3 << 16)
600	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
601	#define X86_DR7_LEN0_MASK (3 << 18)
602	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
603	#define X86_DR7_RW1_MASK (3 << 20)
604	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
605	#define X86_DR7_LEN1_MASK (3 << 22)
606	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
607	#define X86_DR7_RW2_MASK (3 << 24)
608	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
609	#define X86_DR7_LEN2_MASK (3 << 26)
610	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
611	#define X86_DR7_RW3_MASK (3 << 28)
612	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
613	#define X86_DR7_LEN3_MASK (3 << 30)
614
615	/** Bits which must be 1s. */
616	#define X86_DR7_MB1_MASK (RT_BIT(10))
617
618	/** Calcs the L bit of Nth breakpoint.
619	* @param iBp The breakpoint number [0..3].
620	*/
621	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
622
623	/** Calcs the G bit of Nth breakpoint.
624	* @param iBp The breakpoint number [0..3].
625	*/
626	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
627
628	/** @name Read/Write values.
629	* @{ */
630	/** Break on instruction fetch only. */
631	#define X86_DR7_RW_EO 0
632	/** Break on write only. */
633	#define X86_DR7_RW_WO 1
634	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
635	#define X86_DR7_RW_IO 2
636	/** Break on read or write (but not instruction fetches). */
637	#define X86_DR7_RW_RW 3
638	/** @} */
639
640	/** Shifts a X86_DR7_RW_* value to its right place.
641	* @param iBp The breakpoint number [0..3].
642	* @param fRw One of the X86_DR7_RW_* value.
643	*/
644	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
645
646	/** @name Length values.
647	* @{ */
648	#define X86_DR7_LEN_BYTE 0
649	#define X86_DR7_LEN_WORD 1
650	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
651	#define X86_DR7_LEN_DWORD 3
652	/** @} */
653
654	/** Shifts a X86_DR7_LEN_* value to its right place.
655	* @param iBp The breakpoint number [0..3].
656	* @param cb One of the X86_DR7_LEN_* values.
657	*/
658	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
659
660	/** Mask used to check if any breakpoints are enabled. */
661	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(6) \| RT_BIT(7))
662
663	/** @} */
664
665
666	/** @name Machine Specific Registers
667	* @{
668	*/
669	/** CPU Feature control. */
670	#define MSR_IA32_FEATURE_CONTROL 0x3A
671	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
672	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
673
674
675	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
676	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
677	* R0 SS == CS + 8
678	* R3 CS == CS + 16
679	* R3 SS == CS + 24
680	*/
681	#define MSR_IA32_SYSENTER_CS 0x174
682	/** SYSENTER_ESP - the R0 ESP. */
683	#define MSR_IA32_SYSENTER_ESP 0x175
684	/** SYSENTER_EIP - the R0 EIP. */
685	#define MSR_IA32_SYSENTER_EIP 0x176
686	#endif
687
688	/** Basic VMX information. */
689	#define MSR_IA32_VMX_BASIC_INFO 0x480
690	/** Allowed settings for pin-based VM execution controls */
691	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
692	/** Allowed settings for proc-based VM execution controls */
693	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
694	/** Allowed settings for the VMX exit controls. */
695	#define MSR_IA32_VMX_EXIT_CTLS 0x483
696	/** Allowed settings for the VMX entry controls. */
697	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
698	/** Misc VMX info. */
699	#define MSR_IA32_VMX_MISC 0x485
700	/** Fixed cleared bits in CR0. */
701	#define MSR_IA32_VMX_CR0_FIXED0 0x486
702	/** Fixed set bits in CR0. */
703	#define MSR_IA32_VMX_CR0_FIXED1 0x487
704	/** Fixed cleared bits in CR4. */
705	#define MSR_IA32_VMX_CR4_FIXED0 0x488
706	/** Fixed set bits in CR4. */
707	#define MSR_IA32_VMX_CR4_FIXED1 0x489
708	/** Information for enumerating fields in the VMCS. */
709	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
710
711
712	/** K6 EFER - Extended Feature Enable Register. */
713	#define MSR_K6_EFER 0xc0000080
714	/** @todo document EFER */
715	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
716	#define MSR_K6_EFER_SCE RT_BIT(0)
717	/** Bit 8 - LME - Long mode enabled. (R/W) */
718	#define MSR_K6_EFER_LME RT_BIT(8)
719	/** Bit 10 - LMA - Long mode active. (R) */
720	#define MSR_K6_EFER_LMA RT_BIT(10)
721	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
722	#define MSR_K6_EFER_NXE RT_BIT(11)
723	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
724	#define MSR_K6_EFER_SVME RT_BIT(12)
725	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
726	#define MSR_K6_EFER_LMSLE RT_BIT(13)
727	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
728	#define MSR_K6_EFER_FFXSR RT_BIT(14)
729	/** K6 STAR - SYSCALL/RET targets. */
730	#define MSR_K6_STAR 0xc0000081
731	/** Shift value for getting the SYSRET CS and SS value. */
732	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
733	/** Shift value for getting the SYSCALL CS and SS value. */
734	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
735	/** Selector mask for use after shifting. */
736	#define MSR_K6_STAR_SEL_MASK 0xffff
737	/** The mask which give the SYSCALL EIP. */
738	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
739	/** K6 WHCR - Write Handling Control Register. */
740	#define MSR_K6_WHCR 0xc0000082
741	/** K6 UWCCR - UC/WC Cacheability Control Register. */
742	#define MSR_K6_UWCCR 0xc0000085
743	/** K6 PSOR - Processor State Observability Register. */
744	#define MSR_K6_PSOR 0xc0000087
745	/** K6 PFIR - Page Flush/Invalidate Register. */
746	#define MSR_K6_PFIR 0xc0000088
747
748	#define MSR_K7_EVNTSEL0 0xc0010000
749	#define MSR_K7_EVNTSEL1 0xc0010001
750	#define MSR_K7_EVNTSEL2 0xc0010002
751	#define MSR_K7_EVNTSEL3 0xc0010003
752	#define MSR_K7_PERFCTR0 0xc0010004
753	#define MSR_K7_PERFCTR1 0xc0010005
754	#define MSR_K7_PERFCTR2 0xc0010006
755	#define MSR_K7_PERFCTR3 0xc0010007
756
757	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
758	#define MSR_K8_LSTAR 0xc0000082
759	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
760	#define MSR_K8_CSTAR 0xc0000083
761	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
762	#define MSR_K8_SF_MASK 0xc0000084
763	/** K8 FS.base - The 64-bit base FS register. */
764	#define MSR_K8_FS_BASE 0xc0000100
765	/** K8 GS.base - The 64-bit base GS register. */
766	#define MSR_K8_GS_BASE 0xc0000101
767	/** K8 KernelGSbase - Used with SWAPGS. */
768	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
769	#define MSR_K8_TSC_AUX 0xc0000103
770	#define MSR_K8_SYSCFG 0xc0010010
771	#define MSR_K8_HWCR 0xc0010015
772	#define MSR_K8_IORRBASE0 0xc0010016
773	#define MSR_K8_IORRMASK0 0xc0010017
774	#define MSR_K8_IORRBASE1 0xc0010018
775	#define MSR_K8_IORRMASK1 0xc0010019
776	#define MSR_K8_TOP_MEM1 0xc001001a
777	#define MSR_K8_TOP_MEM2 0xc001001d
778	#define MSR_K8_VM_CR 0xc0010114
779	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
780
781	#define MSR_K8_IGNNE 0xc0010115
782	#define MSR_K8_SMM_CTL 0xc0010116
783	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
784	* host state during world switch.
785	*/
786	#define MSR_K8_VM_HSAVE_PA 0xc0010117
787
788	/** @} */
789
790
791	/** @name Page Table / Directory / Directory Pointers / L4.
792	* @{
793	*/
794
795	/** Page table/directory entry as an unsigned integer. */
796	typedef uint32_t X86PGUINT;
797	/** Pointer to a page table/directory table entry as an unsigned integer. */
798	typedef X86PGUINT *PX86PGUINT;
799
800	/** Number of entries in a 32-bit PT/PD. */
801	#define X86_PG_ENTRIES 1024
802
803
804	/** PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
805	typedef uint64_t X86PGPAEUINT;
806	/** Pointer to a PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
807	typedef X86PGPAEUINT *PX86PGPAEUINT;
808
809	/** Number of entries in a PAE PT/PD/PDPTR/L4/L5. */
810	#define X86_PG_PAE_ENTRIES 512
811
812
813	/** The size of a 4KB page. */
814	#define X86_PAGE_4K_SIZE _4K
815	/** The page shift of a 4KB page. */
816	#define X86_PAGE_4K_SHIFT 12
817	/** The 4KB page offset mask. */
818	#define X86_PAGE_4K_OFFSET_MASK 0xfff
819	/** The 4KB page base mask for virtual addresses. */
820	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
821	/** The 4KB page base mask for virtual addresses - 32bit version. */
822	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
823
824	/** The size of a 2MB page. */
825	#define X86_PAGE_2M_SIZE _2M
826	/** The page shift of a 2MB page. */
827	#define X86_PAGE_2M_SHIFT 21
828	/** The 2MB page offset mask. */
829	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
830	/** The 2MB page base mask for virtual addresses. */
831	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
832	/** The 2MB page base mask for virtual addresses - 32bit version. */
833	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
834
835	/** The size of a 4MB page. */
836	#define X86_PAGE_4M_SIZE _4M
837	/** The page shift of a 4MB page. */
838	#define X86_PAGE_4M_SHIFT 22
839	/** The 4MB page offset mask. */
840	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
841	/** The 4MB page base mask for virtual addresses. */
842	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
843	/** The 4MB page base mask for virtual addresses - 32bit version. */
844	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
845
846
847
848	/** @name Page Table Entry
849	* @{
850	*/
851	/** Bit 0 - P - Present bit. */
852	#define X86_PTE_P RT_BIT(0)
853	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
854	#define X86_PTE_RW RT_BIT(1)
855	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
856	#define X86_PTE_US RT_BIT(2)
857	/** Bit 3 - PWT - Page level write thru bit. */
858	#define X86_PTE_PWT RT_BIT(3)
859	/** Bit 4 - PCD - Page level cache disable bit. */
860	#define X86_PTE_PCD RT_BIT(4)
861	/** Bit 5 - A - Access bit. */
862	#define X86_PTE_A RT_BIT(5)
863	/** Bit 6 - D - Dirty bit. */
864	#define X86_PTE_D RT_BIT(6)
865	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
866	#define X86_PTE_PAT RT_BIT(7)
867	/** Bit 8 - G - Global flag. */
868	#define X86_PTE_G RT_BIT(8)
869	/** Bits 9-11 - - Available for use to system software. */
870	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
871	/** Bits 12-31 - - Physical Page number of the next level. */
872	#define X86_PTE_PG_MASK ( 0xfffff000 )
873
874	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
875	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
876	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
877	#else
878	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
879	#endif
880	/** Bits 63 - NX - PAE - No execution flag. */
881	#define X86_PTE_PAE_NX RT_BIT_64(63)
882
883	/**
884	* Page table entry.
885	*/
886	typedef struct X86PTEBITS
887	{
888	/** Flags whether(=1) or not the page is present. */
889	unsigned u1Present : 1;
890	/** Read(=0) / Write(=1) flag. */
891	unsigned u1Write : 1;
892	/** User(=1) / Supervisor (=0) flag. */
893	unsigned u1User : 1;
894	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
895	unsigned u1WriteThru : 1;
896	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
897	unsigned u1CacheDisable : 1;
898	/** Accessed flag.
899	* Indicates that the page have been read or written to. */
900	unsigned u1Accessed : 1;
901	/** Dirty flag.
902	* Indicates that the page have been written to. */
903	unsigned u1Dirty : 1;
904	/** Reserved / If PAT enabled, bit 2 of the index. */
905	unsigned u1PAT : 1;
906	/** Global flag. (Ignored in all but final level.) */
907	unsigned u1Global : 1;
908	/** Available for use to system software. */
909	unsigned u3Available : 3;
910	/** Physical Page number of the next level. */
911	unsigned u20PageNo : 20;
912	} X86PTEBITS;
913	/** Pointer to a page table entry. */
914	typedef X86PTEBITS *PX86PTEBITS;
915	/** Pointer to a const page table entry. */
916	typedef const X86PTEBITS *PCX86PTEBITS;
917
918	/**
919	* Page table entry.
920	*/
921	typedef union X86PTE
922	{
923	/** Bit field view. */
924	X86PTEBITS n;
925	/** Unsigned integer view */
926	X86PGUINT u;
927	/** 32-bit view. */
928	uint32_t au32[1];
929	/** 16-bit view. */
930	uint16_t au16[2];
931	/** 8-bit view. */
932	uint8_t au8[4];
933	} X86PTE;
934	/** Pointer to a page table entry. */
935	typedef X86PTE *PX86PTE;
936	/** Pointer to a const page table entry. */
937	typedef const X86PTE *PCX86PTE;
938
939
940	/**
941	* PAE page table entry.
942	*/
943	typedef struct X86PTEPAEBITS
944	{
945	/** Flags whether(=1) or not the page is present. */
946	uint32_t u1Present : 1;
947	/** Read(=0) / Write(=1) flag. */
948	uint32_t u1Write : 1;
949	/** User(=1) / Supervisor(=0) flag. */
950	uint32_t u1User : 1;
951	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
952	uint32_t u1WriteThru : 1;
953	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
954	uint32_t u1CacheDisable : 1;
955	/** Accessed flag.
956	* Indicates that the page have been read or written to. */
957	uint32_t u1Accessed : 1;
958	/** Dirty flag.
959	* Indicates that the page have been written to. */
960	uint32_t u1Dirty : 1;
961	/** Reserved / If PAT enabled, bit 2 of the index. */
962	uint32_t u1PAT : 1;
963	/** Global flag. (Ignored in all but final level.) */
964	uint32_t u1Global : 1;
965	/** Available for use to system software. */
966	uint32_t u3Available : 3;
967	/** Physical Page number of the next level - Low Part. Don't use this. */
968	uint32_t u20PageNoLow : 20;
969	/** Physical Page number of the next level - High Part. Don't use this. */
970	uint32_t u20PageNoHigh : 20;
971	/** MBZ bits */
972	uint32_t u11Reserved : 11;
973	/** No Execute flag. */
974	uint32_t u1NoExecute : 1;
975	} X86PTEPAEBITS;
976	/** Pointer to a page table entry. */
977	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
978	/** Pointer to a page table entry. */
979	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
980
981	/**
982	* PAE Page table entry.
983	*/
984	typedef union X86PTEPAE
985	{
986	/** Bit field view. */
987	X86PTEPAEBITS n;
988	/** Unsigned integer view */
989	X86PGPAEUINT u;
990	/** 32-bit view. */
991	uint32_t au32[2];
992	/** 16-bit view. */
993	uint16_t au16[4];
994	/** 8-bit view. */
995	uint8_t au8[8];
996	} X86PTEPAE;
997	/** Pointer to a PAE page table entry. */
998	typedef X86PTEPAE *PX86PTEPAE;
999	/** Pointer to a const PAE page table entry. */
1000	typedef const X86PTEPAE *PCX86PTEPAE;
1001	/** @} */
1002
1003	/**
1004	* Page table.
1005	*/
1006	typedef struct X86PT
1007	{
1008	/** PTE Array. */
1009	X86PTE a[X86_PG_ENTRIES];
1010	} X86PT;
1011	/** Pointer to a page table. */
1012	typedef X86PT *PX86PT;
1013	/** Pointer to a const page table. */
1014	typedef const X86PT *PCX86PT;
1015
1016	/** The page shift to get the PT index. */
1017	#define X86_PT_SHIFT 12
1018	/** The PT index mask (apply to a shifted page address). */
1019	#define X86_PT_MASK 0x3ff
1020
1021
1022	/**
1023	* Page directory.
1024	*/
1025	typedef struct X86PTPAE
1026	{
1027	/** PTE Array. */
1028	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1029	} X86PTPAE;
1030	/** Pointer to a page table. */
1031	typedef X86PTPAE *PX86PTPAE;
1032	/** Pointer to a const page table. */
1033	typedef const X86PTPAE *PCX86PTPAE;
1034
1035	/** The page shift to get the PA PTE index. */
1036	#define X86_PT_PAE_SHIFT 12
1037	/** The PAE PT index mask (apply to a shifted page address). */
1038	#define X86_PT_PAE_MASK 0x1ff
1039
1040
1041	/** @name 4KB Page Directory Entry
1042	* @{
1043	*/
1044	/** Bit 0 - P - Present bit. */
1045	#define X86_PDE_P RT_BIT(0)
1046	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1047	#define X86_PDE_RW RT_BIT(1)
1048	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1049	#define X86_PDE_US RT_BIT(2)
1050	/** Bit 3 - PWT - Page level write thru bit. */
1051	#define X86_PDE_PWT RT_BIT(3)
1052	/** Bit 4 - PCD - Page level cache disable bit. */
1053	#define X86_PDE_PCD RT_BIT(4)
1054	/** Bit 5 - A - Access bit. */
1055	#define X86_PDE_A RT_BIT(5)
1056	/** Bit 7 - PS - Page size attribute.
1057	* Clear mean 4KB pages, set means large pages (2/4MB). */
1058	#define X86_PDE_PS RT_BIT(7)
1059	/** Bits 9-11 - - Available for use to system software. */
1060	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1061	/** Bits 12-31 - - Physical Page number of the next level. */
1062	#define X86_PDE_PG_MASK ( 0xfffff000 )
1063
1064	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1065	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1066	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1067	#else
1068	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1069	#endif
1070	/** Bits 63 - NX - PAE - No execution flag. */
1071	#define X86_PDE_PAE_NX RT_BIT_64(63)
1072
1073	/**
1074	* Page directory entry.
1075	*/
1076	typedef struct X86PDEBITS
1077	{
1078	/** Flags whether(=1) or not the page is present. */
1079	unsigned u1Present : 1;
1080	/** Read(=0) / Write(=1) flag. */
1081	unsigned u1Write : 1;
1082	/** User(=1) / Supervisor (=0) flag. */
1083	unsigned u1User : 1;
1084	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1085	unsigned u1WriteThru : 1;
1086	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1087	unsigned u1CacheDisable : 1;
1088	/** Accessed flag.
1089	* Indicates that the page have been read or written to. */
1090	unsigned u1Accessed : 1;
1091	/** Reserved / Ignored (dirty bit). */
1092	unsigned u1Reserved0 : 1;
1093	/** Size bit if PSE is enabled - in any event it's 0. */
1094	unsigned u1Size : 1;
1095	/** Reserved / Ignored (global bit). */
1096	unsigned u1Reserved1 : 1;
1097	/** Available for use to system software. */
1098	unsigned u3Available : 3;
1099	/** Physical Page number of the next level. */
1100	unsigned u20PageNo : 20;
1101	} X86PDEBITS;
1102	/** Pointer to a page directory entry. */
1103	typedef X86PDEBITS *PX86PDEBITS;
1104	/** Pointer to a const page directory entry. */
1105	typedef const X86PDEBITS *PCX86PDEBITS;
1106
1107
1108	/**
1109	* PAE page directory entry.
1110	*/
1111	typedef struct X86PDEPAEBITS
1112	{
1113	/** Flags whether(=1) or not the page is present. */
1114	uint32_t u1Present : 1;
1115	/** Read(=0) / Write(=1) flag. */
1116	uint32_t u1Write : 1;
1117	/** User(=1) / Supervisor (=0) flag. */
1118	uint32_t u1User : 1;
1119	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1120	uint32_t u1WriteThru : 1;
1121	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1122	uint32_t u1CacheDisable : 1;
1123	/** Accessed flag.
1124	* Indicates that the page have been read or written to. */
1125	uint32_t u1Accessed : 1;
1126	/** Reserved / Ignored (dirty bit). */
1127	uint32_t u1Reserved0 : 1;
1128	/** Size bit if PSE is enabled - in any event it's 0. */
1129	uint32_t u1Size : 1;
1130	/** Reserved / Ignored (global bit). / */
1131	uint32_t u1Reserved1 : 1;
1132	/** Available for use to system software. */
1133	uint32_t u3Available : 3;
1134	/** Physical Page number of the next level - Low Part. Don't use! */
1135	uint32_t u20PageNoLow : 20;
1136	/** Physical Page number of the next level - High Part. Don't use! */
1137	uint32_t u20PageNoHigh : 20;
1138	/** MBZ bits */
1139	uint32_t u11Reserved : 11;
1140	/** No Execute flag. */
1141	uint32_t u1NoExecute : 1;
1142	} X86PDEPAEBITS;
1143	/** Pointer to a page directory entry. */
1144	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1145	/** Pointer to a const page directory entry. */
1146	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1147
1148	/** @} */
1149
1150
1151	/** @name 2/4MB Page Directory Entry
1152	* @{
1153	*/
1154	/** Bit 0 - P - Present bit. */
1155	#define X86_PDE4M_P RT_BIT(0)
1156	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1157	#define X86_PDE4M_RW RT_BIT(1)
1158	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1159	#define X86_PDE4M_US RT_BIT(2)
1160	/** Bit 3 - PWT - Page level write thru bit. */
1161	#define X86_PDE4M_PWT RT_BIT(3)
1162	/** Bit 4 - PCD - Page level cache disable bit. */
1163	#define X86_PDE4M_PCD RT_BIT(4)
1164	/** Bit 5 - A - Access bit. */
1165	#define X86_PDE4M_A RT_BIT(5)
1166	/** Bit 6 - D - Dirty bit. */
1167	#define X86_PDE4M_D RT_BIT(6)
1168	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1169	#define X86_PDE4M_PS RT_BIT(7)
1170	/** Bit 8 - G - Global flag. */
1171	#define X86_PDE4M_G RT_BIT(8)
1172	/** Bits 9-11 - AVL - Available for use to system software. */
1173	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1174	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1175	#define X86_PDE4M_PAT RT_BIT(12)
1176	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1177	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1178	/** Bits 22-31 - - Physical Page number. */
1179	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1180	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1181	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1182	/** The number of bits to the high part of the page number. */
1183	#define X86_PDE4M_PG_HIGH_SHIFT 19
1184
1185	/** Bits 12-51 - - PAE - Physical Page number. */
1186	#define X86_PDE4M_PAE_PG_MASK ( 0x000fffffffc00000ULL )
1187	/** Bits 63 - NX - PAE - No execution flag. */
1188	#define X86_PDE4M_PAE_NX RT_BIT_64(63)
1189
1190	/**
1191	* 4MB page directory entry.
1192	*/
1193	typedef struct X86PDE4MBITS
1194	{
1195	/** Flags whether(=1) or not the page is present. */
1196	unsigned u1Present : 1;
1197	/** Read(=0) / Write(=1) flag. */
1198	unsigned u1Write : 1;
1199	/** User(=1) / Supervisor (=0) flag. */
1200	unsigned u1User : 1;
1201	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1202	unsigned u1WriteThru : 1;
1203	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1204	unsigned u1CacheDisable : 1;
1205	/** Accessed flag.
1206	* Indicates that the page have been read or written to. */
1207	unsigned u1Accessed : 1;
1208	/** Dirty flag.
1209	* Indicates that the page have been written to. */
1210	unsigned u1Dirty : 1;
1211	/** Page size flag - always 1 for 4MB entries. */
1212	unsigned u1Size : 1;
1213	/** Global flag. */
1214	unsigned u1Global : 1;
1215	/** Available for use to system software. */
1216	unsigned u3Available : 3;
1217	/** Reserved / If PAT enabled, bit 2 of the index. */
1218	unsigned u1PAT : 1;
1219	/** Bits 32-39 of the page number on AMD64.
1220	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1221	unsigned u8PageNoHigh : 8;
1222	/** Reserved. */
1223	unsigned u1Reserved : 1;
1224	/** Physical Page number of the page. */
1225	unsigned u10PageNo : 10;
1226	} X86PDE4MBITS;
1227	/** Pointer to a page table entry. */
1228	typedef X86PDE4MBITS *PX86PDE4MBITS;
1229	/** Pointer to a const page table entry. */
1230	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1231
1232
1233	/**
1234	* 2MB PAE page directory entry.
1235	*/
1236	typedef struct X86PDE2MPAEBITS
1237	{
1238	/** Flags whether(=1) or not the page is present. */
1239	uint32_t u1Present : 1;
1240	/** Read(=0) / Write(=1) flag. */
1241	uint32_t u1Write : 1;
1242	/** User(=1) / Supervisor(=0) flag. */
1243	uint32_t u1User : 1;
1244	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1245	uint32_t u1WriteThru : 1;
1246	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1247	uint32_t u1CacheDisable : 1;
1248	/** Accessed flag.
1249	* Indicates that the page have been read or written to. */
1250	uint32_t u1Accessed : 1;
1251	/** Dirty flag.
1252	* Indicates that the page have been written to. */
1253	uint32_t u1Dirty : 1;
1254	/** Page size flag - always 1 for 2MB entries. */
1255	uint32_t u1Size : 1;
1256	/** Global flag. */
1257	uint32_t u1Global : 1;
1258	/** Available for use to system software. */
1259	uint32_t u3Available : 3;
1260	/** Reserved / If PAT enabled, bit 2 of the index. */
1261	uint32_t u1PAT : 1;
1262	/** Reserved. */
1263	uint32_t u9Reserved : 9;
1264	/** Physical Page number of the next level - Low part. Don't use! */
1265	uint32_t u10PageNoLow : 10;
1266	/** Physical Page number of the next level - High part. Don't use! */
1267	uint32_t u20PageNoHigh : 20;
1268	/** MBZ bits */
1269	uint32_t u11Reserved : 11;
1270	/** No Execute flag. */
1271	uint32_t u1NoExecute : 1;
1272	} X86PDE2MPAEBITS;
1273	/** Pointer to a 4MB PAE page table entry. */
1274	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1275	/** Pointer to a 4MB PAE page table entry. */
1276	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1277
1278	/** @} */
1279
1280	/**
1281	* Page directory entry.
1282	*/
1283	typedef union X86PDE
1284	{
1285	/** Normal view. */
1286	X86PDEBITS n;
1287	/** 4MB view (big). */
1288	X86PDE4MBITS b;
1289	/** Unsigned integer view. */
1290	X86PGUINT u;
1291	/** 8 bit unsigned integer view. */
1292	uint8_t au8[4];
1293	/** 16 bit unsigned integer view. */
1294	uint16_t au16[2];
1295	/** 32 bit unsigned integer view. */
1296	uint32_t au32[1];
1297	} X86PDE;
1298	/** Pointer to a page directory entry. */
1299	typedef X86PDE *PX86PDE;
1300	/** Pointer to a const page directory entry. */
1301	typedef const X86PDE *PCX86PDE;
1302
1303	/**
1304	* PAE page directory entry.
1305	*/
1306	typedef union X86PDEPAE
1307	{
1308	/** Normal view. */
1309	X86PDEPAEBITS n;
1310	/** 2MB page view (big). */
1311	X86PDE2MPAEBITS b;
1312	/** Unsigned integer view. */
1313	X86PGPAEUINT u;
1314	/** 8 bit unsigned integer view. */
1315	uint8_t au8[8];
1316	/** 16 bit unsigned integer view. */
1317	uint16_t au16[4];
1318	/** 32 bit unsigned integer view. */
1319	uint32_t au32[2];
1320	} X86PDEPAE;
1321	/** Pointer to a page directory entry. */
1322	typedef X86PDEPAE *PX86PDEPAE;
1323	/** Pointer to a const page directory entry. */
1324	typedef const X86PDEPAE *PCX86PDEPAE;
1325
1326	/**
1327	* Page directory.
1328	*/
1329	typedef struct X86PD
1330	{
1331	/** PDE Array. */
1332	X86PDE a[X86_PG_ENTRIES];
1333	} X86PD;
1334	/** Pointer to a page directory. */
1335	typedef X86PD *PX86PD;
1336	/** Pointer to a const page directory. */
1337	typedef const X86PD *PCX86PD;
1338
1339	/** The page shift to get the PD index. */
1340	#define X86_PD_SHIFT 22
1341	/** The PD index mask (apply to a shifted page address). */
1342	#define X86_PD_MASK 0x3ff
1343
1344
1345	/**
1346	* PAE page directory.
1347	*/
1348	typedef struct X86PDPAE
1349	{
1350	/** PDE Array. */
1351	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1352	} X86PDPAE;
1353	/** Pointer to a PAE page directory. */
1354	typedef X86PDPAE *PX86PDPAE;
1355	/** Pointer to a const PAE page directory. */
1356	typedef const X86PDPAE *PCX86PDPAE;
1357
1358	/** The page shift to get the PAE PD index. */
1359	#define X86_PD_PAE_SHIFT 21
1360	/** The PAE PD index mask (apply to a shifted page address). */
1361	#define X86_PD_PAE_MASK 0x1ff
1362
1363
1364	/** @name Page Directory Pointer Table Entry (PAE)
1365	* @{
1366	*/
1367	/** Bit 0 - P - Present bit. */
1368	#define X86_PDPE_P RT_BIT(0)
1369	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1370	#define X86_PDPE_RW RT_BIT(1)
1371	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1372	#define X86_PDPE_US RT_BIT(2)
1373	/** Bit 3 - PWT - Page level write thru bit. */
1374	#define X86_PDPE_PWT RT_BIT(3)
1375	/** Bit 4 - PCD - Page level cache disable bit. */
1376	#define X86_PDPE_PCD RT_BIT(4)
1377	/** Bit 5 - A - Access bit. Long Mode only. */
1378	#define X86_PDPE_A RT_BIT(5)
1379	/** Bits 9-11 - - Available for use to system software. */
1380	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1381	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1382	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1383	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1384	#else
1385	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1386	#endif
1387	/** Bits 63 - NX - PAE - No execution flag. */
1388	#define X86_PDPE_NX RT_BIT_64(63)
1389
1390	/**
1391	* Page directory pointer table entry.
1392	*/
1393	typedef struct X86PDPEBITS
1394	{
1395	/** Flags whether(=1) or not the page is present. */
1396	uint32_t u1Present : 1;
1397	/** Read(=0) / Write(=1) flag. */
1398	uint32_t u1Write : 1;
1399	/** User(=1) / Supervisor (=0) flag. */
1400	uint32_t u1User : 1;
1401	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1402	uint32_t u1WriteThru : 1;
1403	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1404	uint32_t u1CacheDisable : 1;
1405	/** Accessed flag.
1406	* Indicates that the page have been read or written to. */
1407	uint32_t u1Accessed : 1;
1408	/** Chunk of reserved bits. */
1409	uint32_t u3Reserved : 3;
1410	/** Available for use to system software. */
1411	uint32_t u3Available : 3;
1412	/** Physical Page number of the next level - Low Part. Don't use! */
1413	uint32_t u20PageNoLow : 20;
1414	/** Physical Page number of the next level - High Part. Don't use! */
1415	uint32_t u20PageNoHigh : 20;
1416	/** MBZ bits */
1417	uint32_t u11Reserved : 11;
1418	/** No Execute flag. */
1419	uint32_t u1NoExecute : 1;
1420	} X86PDPEBITS;
1421	/** Pointer to a page directory pointer table entry. */
1422	typedef X86PDPEBITS *PX86PTPEBITS;
1423	/** Pointer to a const page directory pointer table entry. */
1424	typedef const X86PDPEBITS *PCX86PTPEBITS;
1425
1426	/**
1427	* Page directory pointer table entry.
1428	*/
1429	typedef union X86PDPE
1430	{
1431	/** Normal view. */
1432	X86PDPEBITS n;
1433	/** Unsigned integer view. */
1434	X86PGPAEUINT u;
1435	/** 8 bit unsigned integer view. */
1436	uint8_t au8[8];
1437	/** 16 bit unsigned integer view. */
1438	uint16_t au16[4];
1439	/** 32 bit unsigned integer view. */
1440	uint32_t au32[2];
1441	} X86PDPE;
1442	/** Pointer to a page directory pointer table entry. */
1443	typedef X86PDPE *PX86PDPE;
1444	/** Pointer to a const page directory pointer table entry. */
1445	typedef const X86PDPE *PCX86PDPE;
1446
1447
1448	/**
1449	* Page directory pointer table.
1450	*/
1451	typedef struct X86PDPTR
1452	{
1453	/** PDE Array. */
1454	X86PDPE a[X86_PG_PAE_ENTRIES];
1455	} X86PDPTR;
1456	/** Pointer to a page directory pointer table. */
1457	typedef X86PDPTR *PX86PDPTR;
1458	/** Pointer to a const page directory pointer table. */
1459	typedef const X86PDPTR *PCX86PDPTR;
1460
1461	/** The page shift to get the PDPTR index. */
1462	#define X86_PDPTR_SHIFT 30
1463	/** The PDPTR index mask (apply to a shifted page address). (32 bits PAE) */
1464	#define X86_PDPTR_MASK_32 0x3
1465	/** The PDPTR index mask (apply to a shifted page address). (64 bits PAE)*/
1466	#define X86_PDPTR_MASK 0x1ff
1467
1468	/** @} */
1469
1470
1471	/** @name Page Map Level-4 Entry (Long Mode PAE)
1472	* @{
1473	*/
1474	/** Bit 0 - P - Present bit. */
1475	#define X86_PML4E_P RT_BIT(0)
1476	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1477	#define X86_PML4E_RW RT_BIT(1)
1478	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1479	#define X86_PML4E_US RT_BIT(2)
1480	/** Bit 3 - PWT - Page level write thru bit. */
1481	#define X86_PML4E_PWT RT_BIT(3)
1482	/** Bit 4 - PCD - Page level cache disable bit. */
1483	#define X86_PML4E_PCD RT_BIT(4)
1484	/** Bit 5 - A - Access bit. */
1485	#define X86_PML4E_A RT_BIT(5)
1486	/** Bits 9-11 - - Available for use to system software. */
1487	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1488	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1489	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1490	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1491	#else
1492	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1493	#endif
1494	/** Bits 63 - NX - PAE - No execution flag. */
1495	#define X86_PML4E_NX RT_BIT_64(63)
1496
1497	/**
1498	* Page Map Level-4 Entry
1499	*/
1500	typedef struct X86PML4EBITS
1501	{
1502	/** Flags whether(=1) or not the page is present. */
1503	uint32_t u1Present : 1;
1504	/** Read(=0) / Write(=1) flag. */
1505	uint32_t u1Write : 1;
1506	/** User(=1) / Supervisor (=0) flag. */
1507	uint32_t u1User : 1;
1508	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1509	uint32_t u1WriteThru : 1;
1510	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1511	uint32_t u1CacheDisable : 1;
1512	/** Accessed flag.
1513	* Indicates that the page have been read or written to. */
1514	uint32_t u1Accessed : 1;
1515	/** Chunk of reserved bits. */
1516	uint32_t u3Reserved : 3;
1517	/** Available for use to system software. */
1518	uint32_t u3Available : 3;
1519	/** Physical Page number of the next level - Low Part. Don't use! */
1520	uint32_t u20PageNoLow : 20;
1521	/** Physical Page number of the next level - High Part. Don't use! */
1522	uint32_t u20PageNoHigh : 20;
1523	/** MBZ bits */
1524	uint32_t u11Reserved : 11;
1525	/** No Execute flag. */
1526	uint32_t u1NoExecute : 1;
1527	} X86PML4EBITS;
1528	/** Pointer to a page map level-4 entry. */
1529	typedef X86PML4EBITS *PX86PML4EBITS;
1530	/** Pointer to a const page map level-4 entry. */
1531	typedef const X86PML4EBITS *PCX86PML4EBITS;
1532
1533	/**
1534	* Page Map Level-4 Entry.
1535	*/
1536	typedef union X86PML4E
1537	{
1538	/** Normal view. */
1539	X86PML4EBITS n;
1540	/** Unsigned integer view. */
1541	X86PGPAEUINT u;
1542	/** 8 bit unsigned integer view. */
1543	uint8_t au8[8];
1544	/** 16 bit unsigned integer view. */
1545	uint16_t au16[4];
1546	/** 32 bit unsigned integer view. */
1547	uint32_t au32[2];
1548	} X86PML4E;
1549	/** Pointer to a page map level-4 entry. */
1550	typedef X86PML4E *PX86PML4E;
1551	/** Pointer to a const page map level-4 entry. */
1552	typedef const X86PML4E *PCX86PML4E;
1553
1554
1555	/**
1556	* Page Map Level-4.
1557	*/
1558	typedef struct X86PML4
1559	{
1560	/** PDE Array. */
1561	X86PML4E a[X86_PG_PAE_ENTRIES];
1562	} X86PML4;
1563	/** Pointer to a page map level-4. */
1564	typedef X86PML4 *PX86PML4;
1565	/** Pointer to a const page map level-4. */
1566	typedef const X86PML4 *PCX86PML4;
1567
1568	/** The page shift to get the PML4 index. */
1569	#define X86_PML4_SHIFT 39
1570	/** The PML4 index mask (apply to a shifted page address). */
1571	#define X86_PML4_MASK 0x1ff
1572
1573	/** @} */
1574
1575	/** @} */
1576
1577
1578	/**
1579	* 80-bit MMX/FPU register type.
1580	*/
1581	typedef struct X86FPUMMX
1582	{
1583	uint8_t reg[10];
1584	} X86FPUMMX;
1585	/** Pointer to a 80-bit MMX/FPU register type. */
1586	typedef X86FPUMMX *PX86FPUMMX;
1587	/** Pointer to a const 80-bit MMX/FPU register type. */
1588	typedef const X86FPUMMX *PCX86FPUMMX;
1589
1590	/**
1591	* FPU state (aka FSAVE/FRSTOR Memory Region).
1592	*/
1593	#pragma pack(1)
1594	typedef struct X86FPUSTATE
1595	{
1596	/** Control word. */
1597	uint16_t FCW;
1598	/** Alignment word */
1599	uint16_t Dummy1;
1600	/** Status word. */
1601	uint16_t FSW;
1602	/** Alignment word */
1603	uint16_t Dummy2;
1604	/** Tag word */
1605	uint16_t FTW;
1606	/** Alignment word */
1607	uint16_t Dummy3;
1608
1609	/** Instruction pointer. */
1610	uint32_t FPUIP;
1611	/** Code selector. */
1612	uint16_t CS;
1613	/** Opcode. */
1614	uint16_t FOP;
1615	/** FOO. */
1616	uint32_t FPUOO;
1617	/** FOS. */
1618	uint32_t FPUOS;
1619	/** FPU view - todo. */
1620	X86FPUMMX regs[8];
1621	} X86FPUSTATE;
1622	#pragma pack()
1623	/** Pointer to a FPU state. */
1624	typedef X86FPUSTATE *PX86FPUSTATE;
1625	/** Pointer to a const FPU state. */
1626	typedef const X86FPUSTATE *PCX86FPUSTATE;
1627
1628	/**
1629	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1630	*/
1631	#pragma pack(1)
1632	typedef struct X86FXSTATE
1633	{
1634	/** Control word. */
1635	uint16_t FCW;
1636	/** Status word. */
1637	uint16_t FSW;
1638	/** Tag word (it's a byte actually). */
1639	uint8_t FTW;
1640	uint8_t huh1;
1641	/** Opcode. */
1642	uint16_t FOP;
1643	/** Instruction pointer. */
1644	uint32_t FPUIP;
1645	/** Code selector. */
1646	uint16_t CS;
1647	uint16_t Rsvrd1;
1648	/* - offset 16 - */
1649	/** Data pointer. */
1650	uint32_t FPUDP;
1651	/** Data segment */
1652	uint16_t DS;
1653	uint16_t Rsrvd2;
1654	uint32_t MXCSR;
1655	uint32_t MXCSR_MASK;
1656	/* - offset 32 - */
1657	union
1658	{
1659	/** MMX view. */
1660	uint64_t mmx;
1661	/** FPU view - todo. */
1662	X86FPUMMX fpu;
1663	/** 8-bit view. */
1664	uint8_t au8[16];
1665	/** 16-bit view. */
1666	uint16_t au16[8];
1667	/** 32-bit view. */
1668	uint32_t au32[4];
1669	/** 64-bit view. */
1670	uint64_t au64[2];
1671	/** 128-bit view. (yeah, very helpful) */
1672	uint128_t au128[1];
1673	} aRegs[8];
1674	/* - offset 160 - */
1675	union
1676	{
1677	/** XMM Register view . /
1678	uint128_t xmm;
1679	/** 8-bit view. */
1680	uint8_t au8[16];
1681	/** 16-bit view. */
1682	uint16_t au16[8];
1683	/** 32-bit view. */
1684	uint32_t au32[4];
1685	/** 64-bit view. */
1686	uint64_t au64[2];
1687	/** 128-bit view. (yeah, very helpful) */
1688	uint128_t au128[1];
1689	} aXMM[8];
1690	/* - offset 288 - */
1691	uint32_t au32RsrvdRest[(512 - 288) / sizeof(uint32_t)];
1692	} X86FXSTATE;
1693	#pragma pack()
1694	/** Pointer to a FPU Extended state. */
1695	typedef X86FXSTATE *PX86FXSTATE;
1696	/** Pointer to a const FPU Extended state. */
1697	typedef const X86FXSTATE *PCX86FXSTATE;
1698
1699
1700	/** @name Selector Descriptor
1701	* @{
1702	*/
1703
1704	/**
1705	* Generic descriptor table entry
1706	*/
1707	#pragma pack(1)
1708	typedef struct X86DESCGENERIC
1709	{
1710	/** Limit - Low word. */
1711	unsigned u16LimitLow : 16;
1712	/** Base address - lowe word.
1713	* Don't try set this to 24 because MSC is doing studing things then. */
1714	unsigned u16BaseLow : 16;
1715	/** Base address - first 8 bits of high word. */
1716	unsigned u8BaseHigh1 : 8;
1717	/** Segment Type. */
1718	unsigned u4Type : 4;
1719	/** Descriptor Type. System(=0) or code/data selector */
1720	unsigned u1DescType : 1;
1721	/** Descriptor Privelege level. */
1722	unsigned u2Dpl : 2;
1723	/** Flags selector present(=1) or not. */
1724	unsigned u1Present : 1;
1725	/** Segment limit 16-19. */
1726	unsigned u4LimitHigh : 4;
1727	/** Available for system software. */
1728	unsigned u1Available : 1;
1729	/** Reserved - 0. */
1730	unsigned u1Reserved : 1;
1731	/** This flags meaning depends on the segment type. Try make sense out
1732	* of the intel manual yourself. */
1733	unsigned u1DefBig : 1;
1734	/** Granularity of the limit. If set 4KB granularity is used, if
1735	* clear byte. */
1736	unsigned u1Granularity : 1;
1737	/** Base address - highest 8 bits. */
1738	unsigned u8BaseHigh2 : 8;
1739	} X86DESCGENERIC;
1740	#pragma pack()
1741	/** Pointer to a generic descriptor entry. */
1742	typedef X86DESCGENERIC *PX86DESCGENERIC;
1743	/** Pointer to a const generic descriptor entry. */
1744	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1745
1746
1747	/**
1748	* Descriptor attributes.
1749	*/
1750	typedef struct X86DESCATTRBITS
1751	{
1752	/** Segment Type. */
1753	unsigned u4Type : 4;
1754	/** Descriptor Type. System(=0) or code/data selector */
1755	unsigned u1DescType : 1;
1756	/** Descriptor Privelege level. */
1757	unsigned u2Dpl : 2;
1758	/** Flags selector present(=1) or not. */
1759	unsigned u1Present : 1;
1760	/** Segment limit 16-19. */
1761	unsigned u4LimitHigh : 4;
1762	/** Available for system software. */
1763	unsigned u1Available : 1;
1764	/** Reserved - 0. */
1765	unsigned u1Reserved : 1;
1766	/** This flags meaning depends on the segment type. Try make sense out
1767	* of the intel manual yourself. */
1768	unsigned u1DefBig : 1;
1769	/** Granularity of the limit. If set 4KB granularity is used, if
1770	* clear byte. */
1771	unsigned u1Granularity : 1;
1772	} X86DESCATTRBITS;
1773
1774
1775	#pragma pack(1)
1776	typedef union X86DESCATTR
1777	{
1778	/** Normal view. */
1779	X86DESCATTRBITS n;
1780	/** Unsigned integer view. */
1781	uint32_t u;
1782	} X86DESCATTR;
1783	#pragma pack()
1784
1785	/** Pointer to descriptor attributes. */
1786	typedef X86DESCATTR *PX86DESCATTR;
1787	/** Pointer to const descriptor attributes. */
1788	typedef const X86DESCATTR *PCX86DESCATTR;
1789
1790
1791	/**
1792	* Descriptor table entry.
1793	*/
1794	#pragma pack(1)
1795	typedef union X86DESC
1796	{
1797	/** Generic descriptor view. */
1798	X86DESCGENERIC Gen;
1799	#if 0
1800	/** IDT view. */
1801	VBOXIDTE Idt;
1802	#endif
1803
1804	/** 8 bit unsigned interger view. */
1805	uint8_t au8[8];
1806	/** 16 bit unsigned interger view. */
1807	uint16_t au16[4];
1808	/** 32 bit unsigned interger view. */
1809	uint32_t au32[2];
1810	} X86DESC;
1811	#pragma pack()
1812	/** Pointer to descriptor table entry. */
1813	typedef X86DESC *PX86DESC;
1814	/** Pointer to const descriptor table entry. */
1815	typedef const X86DESC *PCX86DESC;
1816
1817
1818	/**
1819	* 64 bits generic descriptor table entry
1820	* Note: most of these bits have no meaning in long mode.
1821	*/
1822	#pragma pack(1)
1823	typedef struct X86DESC64GENERIC
1824	{
1825	/** Limit - Low word - IGNORED. */
1826	unsigned u16LimitLow : 16;
1827	/** Base address - lowe word. - IGNORED
1828	* Don't try set this to 24 because MSC is doing studing things then. */
1829	unsigned u16BaseLow : 16;
1830	/** Base address - first 8 bits of high word. - IGNORED */
1831	unsigned u8BaseHigh1 : 8;
1832	/** Segment Type. */
1833	unsigned u4Type : 4;
1834	/** Descriptor Type. System(=0) or code/data selector */
1835	unsigned u1DescType : 1;
1836	/** Descriptor Privelege level. */
1837	unsigned u2Dpl : 2;
1838	/** Flags selector present(=1) or not. */
1839	unsigned u1Present : 1;
1840	/** Segment limit 16-19. - IGNORED */
1841	unsigned u4LimitHigh : 4;
1842	/** Available for system software. - IGNORED */
1843	unsigned u1Available : 1;
1844	/** Long mode flag. */
1845	unsigned u1Long : 1;
1846	/** This flags meaning depends on the segment type. Try make sense out
1847	* of the intel manual yourself. */
1848	unsigned u1DefBig : 1;
1849	/** Granularity of the limit. If set 4KB granularity is used, if
1850	* clear byte. - IGNORED */
1851	unsigned u1Granularity : 1;
1852	/** Base address - highest 8 bits. - IGNORED */
1853	unsigned u8BaseHigh2 : 8;
1854	/** Base address - bits 63-32. */
1855	unsigned u32BaseHigh3 : 32;
1856	unsigned u8Reserved : 8;
1857	unsigned u5Zeros : 5;
1858	unsigned u19Reserved : 19;
1859	} X86DESC64GENERIC;
1860	#pragma pack()
1861	/** Pointer to a generic descriptor entry. */
1862	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1863	/** Pointer to a const generic descriptor entry. */
1864	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1865
1866	/**
1867	* System descriptor table entry (64 bits)
1868	*/
1869	#pragma pack(1)
1870	typedef struct X86DESC64SYSTEM
1871	{
1872	/** Limit - Low word. */
1873	unsigned u16LimitLow : 16;
1874	/** Base address - lowe word.
1875	* Don't try set this to 24 because MSC is doing studing things then. */
1876	unsigned u16BaseLow : 16;
1877	/** Base address - first 8 bits of high word. */
1878	unsigned u8BaseHigh1 : 8;
1879	/** Segment Type. */
1880	unsigned u4Type : 4;
1881	/** Descriptor Type. System(=0) or code/data selector */
1882	unsigned u1DescType : 1;
1883	/** Descriptor Privelege level. */
1884	unsigned u2Dpl : 2;
1885	/** Flags selector present(=1) or not. */
1886	unsigned u1Present : 1;
1887	/** Segment limit 16-19. */
1888	unsigned u4LimitHigh : 4;
1889	/** Available for system software. */
1890	unsigned u1Available : 1;
1891	/** Reserved - 0. */
1892	unsigned u1Reserved : 1;
1893	/** This flags meaning depends on the segment type. Try make sense out
1894	* of the intel manual yourself. */
1895	unsigned u1DefBig : 1;
1896	/** Granularity of the limit. If set 4KB granularity is used, if
1897	* clear byte. */
1898	unsigned u1Granularity : 1;
1899	/** Base address - bits 31-24. */
1900	unsigned u8BaseHigh2 : 8;
1901	/** Base address - bits 63-32. */
1902	unsigned u32BaseHigh3 : 32;
1903	unsigned u8Reserved : 8;
1904	unsigned u5Zeros : 5;
1905	unsigned u19Reserved : 19;
1906	} X86DESC64SYSTEM;
1907	#pragma pack()
1908	/** Pointer to a generic descriptor entry. */
1909	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
1910	/** Pointer to a const generic descriptor entry. */
1911	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
1912
1913
1914	/**
1915	* Descriptor table entry.
1916	*/
1917	#pragma pack(1)
1918	typedef union X86DESC64
1919	{
1920	/** Generic descriptor view. */
1921	X86DESC64GENERIC Gen;
1922	/** System descriptor view. */
1923	X86DESC64SYSTEM System;
1924	#if 0
1925	X86DESC64GATE Gate;
1926	#endif
1927
1928	/** 8 bit unsigned interger view. */
1929	uint8_t au8[16];
1930	/** 16 bit unsigned interger view. */
1931	uint16_t au16[8];
1932	/** 32 bit unsigned interger view. */
1933	uint32_t au32[4];
1934	/** 64 bit unsigned interger view. */
1935	uint64_t au64[2];
1936	} X86DESC64;
1937	#pragma pack()
1938	/** Pointer to descriptor table entry. */
1939	typedef X86DESC64 *PX86DESC64;
1940	/** Pointer to const descriptor table entry. */
1941	typedef const X86DESC64 *PCX86DESC64;
1942
1943	#if HC_ARCH_BITS == 64
1944	typedef X86DESC64 X86DESCHC;
1945	typedef X86DESC64 *PX86DESCHC;
1946	#else
1947	typedef X86DESC X86DESCHC;
1948	typedef X86DESC *PX86DESCHC;
1949	#endif
1950
1951	/** @name Selector Descriptor Types.
1952	* @{
1953	*/
1954
1955	/** @name Non-System Selector Types.
1956	* @{ */
1957	/** Code(=set)/Data(=clear) bit. */
1958	#define X86_SEL_TYPE_CODE 8
1959	/** Memory(=set)/System(=clear) bit. */
1960	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
1961	/** Accessed bit. */
1962	#define X86_SEL_TYPE_ACCESSED 1
1963	/** Expand down bit (for data selectors only). */
1964	#define X86_SEL_TYPE_DOWN 4
1965	/** Conforming bit (for code selectors only). */
1966	#define X86_SEL_TYPE_CONF 4
1967	/** Write bit (for data selectors only). */
1968	#define X86_SEL_TYPE_WRITE 2
1969	/** Read bit (for code selectors only). */
1970	#define X86_SEL_TYPE_READ 2
1971
1972	/** Read only selector type. */
1973	#define X86_SEL_TYPE_RO 0
1974	/** Accessed read only selector type. */
1975	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
1976	/** Read write selector type. */
1977	#define X86_SEL_TYPE_RW 2
1978	/** Accessed read write selector type. */
1979	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
1980	/** Expand down read only selector type. */
1981	#define X86_SEL_TYPE_RO_DOWN 4
1982	/** Accessed expand down read only selector type. */
1983	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
1984	/** Expand down read write selector type. */
1985	#define X86_SEL_TYPE_RW_DOWN 6
1986	/** Accessed expand down read write selector type. */
1987	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
1988	/** Execute only selector type. */
1989	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
1990	/** Accessed execute only selector type. */
1991	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1992	/** Execute and read selector type. */
1993	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
1994	/** Accessed execute and read selector type. */
1995	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1996	/** Conforming execute only selector type. */
1997	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
1998	/** Accessed Conforming execute only selector type. */
1999	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2000	/** Conforming execute and write selector type. */
2001	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2002	/** Accessed Conforming execute and write selector type. */
2003	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2004	/** @} */
2005
2006
2007	/** @name System Selector Types.
2008	* @{ */
2009	/** Undefined system selector type. */
2010	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2011	/** 286 TSS selector. */
2012	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2013	/** LDT selector. */
2014	#define X86_SEL_TYPE_SYS_LDT 2
2015	/** 286 TSS selector - Busy. */
2016	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2017	/** 286 Callgate selector. */
2018	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2019	/** Taskgate selector. */
2020	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2021	/** 286 Interrupt gate selector. */
2022	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2023	/** 286 Trapgate selector. */
2024	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2025	/** Undefined system selector. */
2026	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2027	/** 386 TSS selector. */
2028	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2029	/** Undefined system selector. */
2030	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2031	/** 386 TSS selector - Busy. */
2032	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2033	/** 386 Callgate selector. */
2034	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2035	/** Undefined system selector. */
2036	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2037	/** 386 Interruptgate selector. */
2038	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2039	/** 386 Trapgate selector. */
2040	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2041	/** @} */
2042
2043	/** @name AMD64 System Selector Types.
2044	* @{ */
2045	#define AMD64_SEL_TYPE_SYS_LDT 2
2046	/** 286 TSS selector - Busy. */
2047	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2048	/** 386 TSS selector - Busy. */
2049	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2050	/** 386 Callgate selector. */
2051	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2052	/** 386 Interruptgate selector. */
2053	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2054	/** 386 Trapgate selector. */
2055	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2056	/** @} */
2057
2058	/** @} */
2059
2060
2061	/** @name Descriptor Table Entry Flag Masks.
2062	* These are for the 2nd 32-bit word of a descriptor.
2063	* @{ */
2064	/** Bits 8-11 - TYPE - Descriptor type mask. */
2065	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2066	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2067	#define X86_DESC_S RT_BIT(12)
2068	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2069	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2070	/** Bit 15 - P - Present. */
2071	#define X86_DESC_P RT_BIT(15)
2072	/** Bit 20 - AVL - Available for system software. */
2073	#define X86_DESC_AVL RT_BIT(20)
2074	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2075	#define X86_DESC_DB RT_BIT(22)
2076	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2077	* used, if clear byte. */
2078	#define X86_DESC_G RT_BIT(23)
2079	/** @} */
2080
2081	/** @} */
2082
2083
2084	/** @name Selectors.
2085	* @{
2086	*/
2087
2088	/**
2089	* The shift used to convert a selector from and to index an index (C).
2090	*/
2091	#define X86_SEL_SHIFT 3
2092
2093	/**
2094	* The shift used to convert a selector from and to index an index (C).
2095	*/
2096	#define AMD64_SEL_SHIFT 4
2097
2098	#if HC_ARCH_BITS == 64
2099	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2100	#else
2101	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2102	#endif
2103
2104	/**
2105	* The mask used to mask off the table indicator and CPL of an selector.
2106	*/
2107	#define X86_SEL_MASK 0xfff8
2108
2109	/**
2110	* The bit indicating that a selector is in the LDT and not in the GDT.
2111	*/
2112	#define X86_SEL_LDT 0x0004
2113	/**
2114	* The bit mask for getting the RPL of a selector.
2115	*/
2116	#define X86_SEL_RPL 0x0003
2117
2118	/** @} */
2119
2120
2121	/**
2122	* x86 Exceptions/Faults/Traps.
2123	*/
2124	typedef enum X86XCPT
2125	{
2126	/** \#DE - Divide error. */
2127	X86_XCPT_DE = 0x00,
2128	/** \#DB - Debug event (single step, DRx, ..) */
2129	X86_XCPT_DB = 0x01,
2130	/** NMI - Non-Maskable Interrupt */
2131	X86_XCPT_NMI = 0x02,
2132	/** \#BP - Breakpoint (INT3). */
2133	X86_XCPT_BP = 0x03,
2134	/** \#OF - Overflow (INTO). */
2135	X86_XCPT_OF = 0x04,
2136	/** \#BR - Bound range exceeded (BOUND). */
2137	X86_XCPT_BR = 0x05,
2138	/** \#UD - Undefined opcode. */
2139	X86_XCPT_UD = 0x06,
2140	/** \#NM - Device not available (math coprocessor device). */
2141	X86_XCPT_NM = 0x07,
2142	/** \#DF - Double fault. */
2143	X86_XCPT_DF = 0x08,
2144	/** ??? - Coprocessor segment overrun (obsolete). */
2145	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2146	/** \#TS - Taskswitch (TSS). */
2147	X86_XCPT_TS = 0x0a,
2148	/** \#NP - Segment no present. */
2149	X86_XCPT_NP = 0x0b,
2150	/** \#SS - Stack segment fault. */
2151	X86_XCPT_SS = 0x0c,
2152	/** \#GP - General protection fault. */
2153	X86_XCPT_GP = 0x0d,
2154	/** \#PF - Page fault. */
2155	X86_XCPT_PF = 0x0e,
2156	/* 0x0f is reserved. */
2157	/** \#MF - Math fault (FPU). */
2158	X86_XCPT_MF = 0x10,
2159	/** \#AC - Alignment check. */
2160	X86_XCPT_AC = 0x11,
2161	/** \#MC - Machine check. */
2162	X86_XCPT_MC = 0x12,
2163	/** \#XF - SIMD Floating-Pointer Exception. */
2164	X86_XCPT_XF = 0x13
2165	} X86XCPT;
2166	/** Pointer to a x86 exception code. */
2167	typedef X86XCPT *PX86XCPT;
2168	/** Pointer to a const x86 exception code. */
2169	typedef const X86XCPT *PCX86XCPT;
2170
2171
2172	/** @name Trap Error Codes
2173	* @{
2174	*/
2175	/** External indicator. */
2176	#define X86_TRAP_ERR_EXTERNAL 1
2177	/** IDT indicator. */
2178	#define X86_TRAP_ERR_IDT 2
2179	/** Descriptor table indicator - If set LDT, if clear GDT. */
2180	#define X86_TRAP_ERR_TI 4
2181	/** Mask for getting the selector. */
2182	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2183	/** Shift for getting the selector table index (C type index). */
2184	#define X86_TRAP_ERR_SEL_SHIFT 3
2185	/** @} */
2186
2187
2188	/** @name \#PF Trap Error Codes
2189	* @{
2190	*/
2191	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2192	#define X86_TRAP_PF_P RT_BIT(0)
2193	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2194	#define X86_TRAP_PF_RW RT_BIT(1)
2195	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2196	#define X86_TRAP_PF_US RT_BIT(2)
2197	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2198	#define X86_TRAP_PF_RSVD RT_BIT(3)
2199	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2200	#define X86_TRAP_PF_ID RT_BIT(4)
2201	/** @} */
2202
2203	#pragma pack(1)
2204	/**
2205	* 32-bit IDTR/GDTR.
2206	*/
2207	typedef struct X86XDTR32
2208	{
2209	/** Size of the descriptor table. */
2210	uint16_t cb;
2211	/** Address of the descriptor table. */
2212	uint32_t uAddr;
2213	} X86XDTR32, *PX86XDTR32;
2214	#pragma pack()
2215
2216	#pragma pack(1)
2217	/**
2218	* 64-bit IDTR/GDTR.
2219	*/
2220	typedef struct X86XDTR64
2221	{
2222	/** Size of the descriptor table. */
2223	uint16_t cb;
2224	/** Address of the descriptor table. */
2225	uint64_t uAddr;
2226	} X86XDTR64, *PX86XDTR64;
2227	#pragma pack()
2228
2229	/** @} */
2230
2231	#endif
2232

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source: vbox/trunk/include/VBox/x86.h@ 6000

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