x86.h@ 12936

Last change on this file since 12936 was 12795, checked in by vboxsync, 16 years ago
HWACCM: fixed unsigned/signed compare warning (x86.h), use const and g_.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
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Line
1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39
40	/* Workaround for Solaris sys/regset.h defining CS, DS */
41	#if defined(RT_OS_SOLARIS)
42	# undef CS
43	# undef DS
44	#endif
45
46	/** @defgroup grp_x86 x86 Types and Definitions
47	* @{
48	*/
49
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105	/**
106	* EFLAGS.
107	*/
108	typedef union X86EFLAGS
109	{
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	/** The plain unsigned view. */
121	uint32_t u;
122	} X86EFLAGS;
123	/** Pointer to EFLAGS. */
124	typedef X86EFLAGS *PX86EFLAGS;
125	/** Pointer to const EFLAGS. */
126	typedef const X86EFLAGS *PCX86EFLAGS;
127
128	/**
129	* RFLAGS (32 upper bits are reserved).
130	*/
131	typedef union X86RFLAGS
132	{
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	/** The plain unsigned view. */
146	uint64_t u;
147	} X86RFLAGS;
148	/** Pointer to RFLAGS. */
149	typedef X86RFLAGS *PX86RFLAGS;
150	/** Pointer to const RFLAGS. */
151	typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154	/** @name EFLAGS
155	* @{
156	*/
157	/** Bit 0 - CF - Carry flag - Status flag. */
158	#define X86_EFL_CF RT_BIT(0)
159	/** Bit 2 - PF - Parity flag - Status flag. */
160	#define X86_EFL_PF RT_BIT(2)
161	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162	#define X86_EFL_AF RT_BIT(4)
163	/** Bit 6 - ZF - Zero flag - Status flag. */
164	#define X86_EFL_ZF RT_BIT(6)
165	/** Bit 7 - SF - Signed flag - Status flag. */
166	#define X86_EFL_SF RT_BIT(7)
167	/** Bit 8 - TF - Trap flag - System flag. */
168	#define X86_EFL_TF RT_BIT(8)
169	/** Bit 9 - IF - Interrupt flag - System flag. */
170	#define X86_EFL_IF RT_BIT(9)
171	/** Bit 10 - DF - Direction flag - Control flag. */
172	#define X86_EFL_DF RT_BIT(10)
173	/** Bit 11 - OF - Overflow flag - Status flag. */
174	#define X86_EFL_OF RT_BIT(11)
175	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
177	/** Bit 14 - NT - Nested task flag - System flag. */
178	#define X86_EFL_NT RT_BIT(14)
179	/** Bit 16 - RF - Resume flag - System flag. */
180	#define X86_EFL_RF RT_BIT(16)
181	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182	#define X86_EFL_VM RT_BIT(17)
183	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184	#define X86_EFL_AC RT_BIT(18)
185	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186	#define X86_EFL_VIF RT_BIT(19)
187	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188	#define X86_EFL_VIP RT_BIT(20)
189	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190	#define X86_EFL_ID RT_BIT(21)
191	/** IOPL shift. */
192	#define X86_EFL_IOPL_SHIFT 12
193	/** The the IOPL level from the flags. */
194	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chip. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 23 - POPCOUNT instruction. */
353	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
354
355
356	/** Bit 0 - FPU - x87 FPU on Chip. */
357	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
358	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
359	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
360	/** Bit 2 - DE - Debugging extensions. */
361	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
362	/** Bit 3 - PSE - Page Size Extension. */
363	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
364	/** Bit 4 - TSC - Time Stamp Counter. */
365	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
366	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
367	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
368	/** Bit 6 - PAE - Physical Address Extension. */
369	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
370	/** Bit 7 - MCE - Machine Check Exception. */
371	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
372	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
373	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
374	/** Bit 9 - APIC - APIC On-Chip. */
375	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
376	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
377	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
378	/** Bit 12 - MTRR - Memory Type Range Registers. */
379	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
380	/** Bit 13 - PGE - PTE Global Bit. */
381	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
382	/** Bit 14 - MCA - Machine Check Architecture. */
383	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
384	/** Bit 15 - CMOV - Conditional Move Instructions. */
385	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
386	/** Bit 16 - PAT - Page Attribute Table. */
387	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
388	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
389	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
390	/** Bit 18 - PSN - Processor Serial Number. */
391	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
392	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
393	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
394	/** Bit 21 - DS - Debug Store. */
395	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
396	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
397	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
398	/** Bit 23 - MMX - Intel MMX Technology. */
399	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
402	/** Bit 25 - SSE - SSE Support. */
403	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
406	/** Bit 27 - SS - Self Snoop. */
407	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
410	/** Bit 29 - TM - Therm. Monitor. */
411	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
412	/** Bit 31 - PBE - Pending Break Enabled. */
413	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
414	/** @} */
415
416
417	/** @name CPUID AMD Feature information.
418	* CPUID query with EAX=0x80000001.
419	* @{
420	*/
421	/** Bit 0 - FPU - x87 FPU on Chip. */
422	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
423	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
424	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
425	/** Bit 2 - DE - Debugging extensions. */
426	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
427	/** Bit 3 - PSE - Page Size Extension. */
428	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
429	/** Bit 4 - TSC - Time Stamp Counter. */
430	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
431	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
432	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
433	/** Bit 6 - PAE - Physical Address Extension. */
434	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
435	/** Bit 7 - MCE - Machine Check Exception. */
436	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
437	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
438	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
439	/** Bit 9 - APIC - APIC On-Chip. */
440	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
441	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
442	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
443	/** Bit 12 - MTRR - Memory Type Range Registers. */
444	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
445	/** Bit 13 - PGE - PTE Global Bit. */
446	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
447	/** Bit 14 - MCA - Machine Check Architecture. */
448	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
449	/** Bit 15 - CMOV - Conditional Move Instructions. */
450	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
451	/** Bit 16 - PAT - Page Attribute Table. */
452	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
453	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
455	/** Bit 20 - NX - AMD No-Execute Page Protection. */
456	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
457	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
458	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
459	/** Bit 23 - MMX - Intel MMX Technology. */
460	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
461	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
462	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
463	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
465	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
466	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
467	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
468	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
469	/** Bit 29 - LM - AMD Long Mode. */
470	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
471	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
472	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
473	/** Bit 31 - 3DNOW - AMD 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
475
476	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
477	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
478	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
480	/** Bit 2 - SVM - AMD VM extensions. */
481	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
482	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
483	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
484	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
485	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
486	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
487	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
488	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
490	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
491	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
492	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
493	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
494	/** Bit 9 - OSVW - AMD OS visible workaround. */
495	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
496	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
497	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
498	/** Bit 13 - WDT - AMD Watchdog timer support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
500
501	/** @} */
502
503
504	/** @name CPUID AMD Feature information.
505	* CPUID query with EAX=0x80000007.
506	* @{
507	*/
508	/** Bit 0 - TS - Temperature Sensor. */
509	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
510	/** Bit 1 - FID - Frequency ID Control. */
511	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
512	/** Bit 2 - VID - Voltage ID Control. */
513	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
514	/** Bit 3 - TTP - THERMTRIP. */
515	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
516	/** Bit 4 - TM - Hardware Thermal Control. */
517	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
518	/** Bit 5 - STC - Software Thermal Control. */
519	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
520	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
521	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
522	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
523	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
524	/** Bit 8 - TSCINVAR - TSC Invariant. */
525	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
526	/** @} */
527
528
529	/** @name CR0
530	* @{ */
531	/** Bit 0 - PE - Protection Enabled */
532	#define X86_CR0_PE RT_BIT(0)
533	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
534	/** Bit 1 - MP - Monitor Coprocessor */
535	#define X86_CR0_MP RT_BIT(1)
536	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
537	/** Bit 2 - EM - Emulation. */
538	#define X86_CR0_EM RT_BIT(2)
539	#define X86_CR0_EMULATE_FPU RT_BIT(2)
540	/** Bit 3 - TS - Task Switch. */
541	#define X86_CR0_TS RT_BIT(3)
542	#define X86_CR0_TASK_SWITCH RT_BIT(3)
543	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
544	#define X86_CR0_ET RT_BIT(4)
545	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
546	/** Bit 5 - NE - Numeric error. */
547	#define X86_CR0_NE RT_BIT(5)
548	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
549	/** Bit 16 - WP - Write Protect. */
550	#define X86_CR0_WP RT_BIT(16)
551	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
552	/** Bit 18 - AM - Alignment Mask. */
553	#define X86_CR0_AM RT_BIT(18)
554	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
555	/** Bit 29 - NW - Not Write-though. */
556	#define X86_CR0_NW RT_BIT(29)
557	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
558	/** Bit 30 - WP - Cache Disable. */
559	#define X86_CR0_CD RT_BIT(30)
560	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
561	/** Bit 31 - PG - Paging. */
562	#define X86_CR0_PG RT_BIT(31)
563	#define X86_CR0_PAGING RT_BIT(31)
564	/** @} */
565
566
567	/** @name CR3
568	* @{ */
569	/** Bit 3 - PWT - Page-level Writes Transparent. */
570	#define X86_CR3_PWT RT_BIT(3)
571	/** Bit 4 - PCD - Page-level Cache Disable. */
572	#define X86_CR3_PCD RT_BIT(4)
573	/** Bits 12-31 - - Page directory page number. */
574	#define X86_CR3_PAGE_MASK (0xfffff000)
575	/** Bits 5-31 - - PAE Page directory page number. */
576	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
577	/** Bits 12-51 - - AMD64 Page directory page number. */
578	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
579	/** @} */
580
581
582	/** @name CR4
583	* @{ */
584	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
585	#define X86_CR4_VME RT_BIT(0)
586	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
587	#define X86_CR4_PVI RT_BIT(1)
588	/** Bit 2 - TSD - Time Stamp Disable. */
589	#define X86_CR4_TSD RT_BIT(2)
590	/** Bit 3 - DE - Debugging Extensions. */
591	#define X86_CR4_DE RT_BIT(3)
592	/** Bit 4 - PSE - Page Size Extension. */
593	#define X86_CR4_PSE RT_BIT(4)
594	/** Bit 5 - PAE - Physical Address Extension. */
595	#define X86_CR4_PAE RT_BIT(5)
596	/** Bit 6 - MCE - Machine-Check Enable. */
597	#define X86_CR4_MCE RT_BIT(6)
598	/** Bit 7 - PGE - Page Global Enable. */
599	#define X86_CR4_PGE RT_BIT(7)
600	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
601	#define X86_CR4_PCE RT_BIT(8)
602	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
603	#define X86_CR4_OSFSXR RT_BIT(9)
604	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
605	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
606	/** Bit 13 - VMXE - VMX mode is enabled. */
607	#define X86_CR4_VMXE RT_BIT(13)
608	/** @} */
609
610
611	/** @name DR6
612	* @{ */
613	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
614	#define X86_DR6_B0 RT_BIT(0)
615	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
616	#define X86_DR6_B1 RT_BIT(1)
617	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
618	#define X86_DR6_B2 RT_BIT(2)
619	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
620	#define X86_DR6_B3 RT_BIT(3)
621	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
622	#define X86_DR6_BD RT_BIT(13)
623	/** Bit 14 - BS - Single step */
624	#define X86_DR6_BS RT_BIT(14)
625	/** Bit 15 - BT - Task switch. (TSS T bit.) */
626	#define X86_DR6_BT RT_BIT(15)
627	/** Value of DR6 after powerup/reset. */
628	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
629	/** @} */
630
631
632	/** @name DR7
633	* @{ */
634	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
635	#define X86_DR7_L0 RT_BIT(0)
636	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
637	#define X86_DR7_G0 RT_BIT(1)
638	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
639	#define X86_DR7_L1 RT_BIT(2)
640	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
641	#define X86_DR7_G1 RT_BIT(3)
642	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
643	#define X86_DR7_L2 RT_BIT(4)
644	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
645	#define X86_DR7_G2 RT_BIT(5)
646	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
647	#define X86_DR7_L3 RT_BIT(6)
648	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
649	#define X86_DR7_G3 RT_BIT(7)
650	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
651	#define X86_DR7_LE RT_BIT(8)
652	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
653	#define X86_DR7_GE RT_BIT(9)
654
655	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
656	* any DR register is accessed. */
657	#define X86_DR7_GD RT_BIT(13)
658	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
659	#define X86_DR7_RW0_MASK (3 << 16)
660	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
661	#define X86_DR7_LEN0_MASK (3 << 18)
662	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
663	#define X86_DR7_RW1_MASK (3 << 20)
664	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
665	#define X86_DR7_LEN1_MASK (3 << 22)
666	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
667	#define X86_DR7_RW2_MASK (3 << 24)
668	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
669	#define X86_DR7_LEN2_MASK (3 << 26)
670	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
671	#define X86_DR7_RW3_MASK (3 << 28)
672	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
673	#define X86_DR7_LEN3_MASK (3 << 30)
674
675	/** Bits which must be 1s. */
676	#define X86_DR7_MB1_MASK (RT_BIT(10))
677
678	/** Calcs the L bit of Nth breakpoint.
679	* @param iBp The breakpoint number [0..3].
680	*/
681	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
682
683	/** Calcs the G bit of Nth breakpoint.
684	* @param iBp The breakpoint number [0..3].
685	*/
686	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
687
688	/** @name Read/Write values.
689	* @{ */
690	/** Break on instruction fetch only. */
691	#define X86_DR7_RW_EO 0U
692	/** Break on write only. */
693	#define X86_DR7_RW_WO 1U
694	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
695	#define X86_DR7_RW_IO 2U
696	/** Break on read or write (but not instruction fetches). */
697	#define X86_DR7_RW_RW 3U
698	/** @} */
699
700	/** Shifts a X86_DR7_RW_* value to its right place.
701	* @param iBp The breakpoint number [0..3].
702	* @param fRw One of the X86_DR7_RW_* value.
703	*/
704	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
705
706	/** @name Length values.
707	* @{ */
708	#define X86_DR7_LEN_BYTE 0U
709	#define X86_DR7_LEN_WORD 1U
710	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
711	#define X86_DR7_LEN_DWORD 3U
712	/** @} */
713
714	/** Shifts a X86_DR7_LEN_* value to its right place.
715	* @param iBp The breakpoint number [0..3].
716	* @param cb One of the X86_DR7_LEN_* values.
717	*/
718	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
719
720	/** Fetch the breakpoint length bits from the DR7 value.
721	* @param uDR7 DR7 value
722	* @param iBp The breakpoint number [0..3].
723	*/
724	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
725
726	/** Mask used to check if any breakpoints are enabled. */
727	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
728
729	/** Mask used to check if any io breakpoints are set. */
730	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
731
732	/** Value of DR7 after powerup/reset. */
733	#define X86_DR7_INIT_VAL 0x400
734	/** @} */
735
736
737	/** @name Machine Specific Registers
738	* @{
739	*/
740
741	/** Time Stamp Counter. */
742	#define MSR_IA32_TSC 0x10
743
744	#define MSR_IA32_PLATFORM_ID 0x17
745
746	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
747	#define MSR_IA32_APICBASE 0x1b
748	#endif
749
750	/** CPU Feature control. */
751	#define MSR_IA32_FEATURE_CONTROL 0x3A
752	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
753	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
754
755	/** BIOS update trigger (microcode update). */
756	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
757
758	/** BIOS update signature (microcode). */
759	#define MSR_IA32_BIOS_SIGN_ID 0x8B
760
761	/** MTRR Capabilities. */
762	#define MSR_IA32_MTRR_CAP 0xFE
763
764
765	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
766	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
767	* R0 SS == CS + 8
768	* R3 CS == CS + 16
769	* R3 SS == CS + 24
770	*/
771	#define MSR_IA32_SYSENTER_CS 0x174
772	/** SYSENTER_ESP - the R0 ESP. */
773	#define MSR_IA32_SYSENTER_ESP 0x175
774	/** SYSENTER_EIP - the R0 EIP. */
775	#define MSR_IA32_SYSENTER_EIP 0x176
776	#endif
777
778	/** Machine Check Global Capabilities Register. */
779	#define MSR_IA32_MCP_CAP 0x179
780	/** Machine Check Global Status Register. */
781	#define MSR_IA32_MCP_STATUS 0x17A
782	/** Machine Check Global Control Register. */
783	#define MSR_IA32_MCP_CTRL 0x17B
784
785	/* Page Attribute Table. */
786	#define MSR_IA32_CR_PAT 0x277
787
788	/** MTRR Default Range. */
789	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
790
791	#define MSR_IA32_MC0_CTL 0x400
792	#define MSR_IA32_MC0_STATUS 0x401
793
794	/** Basic VMX information. */
795	#define MSR_IA32_VMX_BASIC_INFO 0x480
796	/** Allowed settings for pin-based VM execution controls */
797	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
798	/** Allowed settings for proc-based VM execution controls */
799	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
800	/** Allowed settings for the VMX exit controls. */
801	#define MSR_IA32_VMX_EXIT_CTLS 0x483
802	/** Allowed settings for the VMX entry controls. */
803	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
804	/** Misc VMX info. */
805	#define MSR_IA32_VMX_MISC 0x485
806	/** Fixed cleared bits in CR0. */
807	#define MSR_IA32_VMX_CR0_FIXED0 0x486
808	/** Fixed set bits in CR0. */
809	#define MSR_IA32_VMX_CR0_FIXED1 0x487
810	/** Fixed cleared bits in CR4. */
811	#define MSR_IA32_VMX_CR4_FIXED0 0x488
812	/** Fixed set bits in CR4. */
813	#define MSR_IA32_VMX_CR4_FIXED1 0x489
814	/** Information for enumerating fields in the VMCS. */
815	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
816	/** Allowed settings for secondary proc-based VM execution controls */
817	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
818	/** EPT capabilities. */
819	#define MSR_IA32_VMX_EPT_CAPS 0x48C
820
821	/** K6 EFER - Extended Feature Enable Register. */
822	#define MSR_K6_EFER 0xc0000080
823	/** @todo document EFER */
824	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
825	#define MSR_K6_EFER_SCE RT_BIT(0)
826	/** Bit 8 - LME - Long mode enabled. (R/W) */
827	#define MSR_K6_EFER_LME RT_BIT(8)
828	/** Bit 10 - LMA - Long mode active. (R) */
829	#define MSR_K6_EFER_LMA RT_BIT(10)
830	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
831	#define MSR_K6_EFER_NXE RT_BIT(11)
832	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
833	#define MSR_K6_EFER_SVME RT_BIT(12)
834	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
835	#define MSR_K6_EFER_LMSLE RT_BIT(13)
836	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
837	#define MSR_K6_EFER_FFXSR RT_BIT(14)
838	/** K6 STAR - SYSCALL/RET targets. */
839	#define MSR_K6_STAR 0xc0000081
840	/** Shift value for getting the SYSRET CS and SS value. */
841	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
842	/** Shift value for getting the SYSCALL CS and SS value. */
843	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
844	/** Selector mask for use after shifting. */
845	#define MSR_K6_STAR_SEL_MASK 0xffff
846	/** The mask which give the SYSCALL EIP. */
847	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
848	/** K6 WHCR - Write Handling Control Register. */
849	#define MSR_K6_WHCR 0xc0000082
850	/** K6 UWCCR - UC/WC Cacheability Control Register. */
851	#define MSR_K6_UWCCR 0xc0000085
852	/** K6 PSOR - Processor State Observability Register. */
853	#define MSR_K6_PSOR 0xc0000087
854	/** K6 PFIR - Page Flush/Invalidate Register. */
855	#define MSR_K6_PFIR 0xc0000088
856
857	#define MSR_K7_EVNTSEL0 0xc0010000
858	#define MSR_K7_EVNTSEL1 0xc0010001
859	#define MSR_K7_EVNTSEL2 0xc0010002
860	#define MSR_K7_EVNTSEL3 0xc0010003
861	#define MSR_K7_PERFCTR0 0xc0010004
862	#define MSR_K7_PERFCTR1 0xc0010005
863	#define MSR_K7_PERFCTR2 0xc0010006
864	#define MSR_K7_PERFCTR3 0xc0010007
865
866	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
867	#define MSR_K8_LSTAR 0xc0000082
868	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
869	#define MSR_K8_CSTAR 0xc0000083
870	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
871	#define MSR_K8_SF_MASK 0xc0000084
872	/** K8 FS.base - The 64-bit base FS register. */
873	#define MSR_K8_FS_BASE 0xc0000100
874	/** K8 GS.base - The 64-bit base GS register. */
875	#define MSR_K8_GS_BASE 0xc0000101
876	/** K8 KernelGSbase - Used with SWAPGS. */
877	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
878	#define MSR_K8_TSC_AUX 0xc0000103
879	#define MSR_K8_SYSCFG 0xc0010010
880	#define MSR_K8_HWCR 0xc0010015
881	#define MSR_K8_IORRBASE0 0xc0010016
882	#define MSR_K8_IORRMASK0 0xc0010017
883	#define MSR_K8_IORRBASE1 0xc0010018
884	#define MSR_K8_IORRMASK1 0xc0010019
885	#define MSR_K8_TOP_MEM1 0xc001001a
886	#define MSR_K8_TOP_MEM2 0xc001001d
887	#define MSR_K8_VM_CR 0xc0010114
888	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
889
890	#define MSR_K8_IGNNE 0xc0010115
891	#define MSR_K8_SMM_CTL 0xc0010116
892	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
893	* host state during world switch.
894	*/
895	#define MSR_K8_VM_HSAVE_PA 0xc0010117
896
897	/** @} */
898
899
900	/** @name Page Table / Directory / Directory Pointers / L4.
901	* @{
902	*/
903
904	/** Page table/directory entry as an unsigned integer. */
905	typedef uint32_t X86PGUINT;
906	/** Pointer to a page table/directory table entry as an unsigned integer. */
907	typedef X86PGUINT *PX86PGUINT;
908
909	/** Number of entries in a 32-bit PT/PD. */
910	#define X86_PG_ENTRIES 1024
911
912
913	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
914	typedef uint64_t X86PGPAEUINT;
915	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
916	typedef X86PGPAEUINT *PX86PGPAEUINT;
917
918	/** Number of entries in a PAE PT/PD. */
919	#define X86_PG_PAE_ENTRIES 512
920	/** Number of entries in a PAE PDPT. */
921	#define X86_PG_PAE_PDPE_ENTRIES 4
922
923	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
924	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
925	/** Number of entries in an AMD64 PDPT.
926	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
927	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
928
929	/** The size of a 4KB page. */
930	#define X86_PAGE_4K_SIZE _4K
931	/** The page shift of a 4KB page. */
932	#define X86_PAGE_4K_SHIFT 12
933	/** The 4KB page offset mask. */
934	#define X86_PAGE_4K_OFFSET_MASK 0xfff
935	/** The 4KB page base mask for virtual addresses. */
936	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
937	/** The 4KB page base mask for virtual addresses - 32bit version. */
938	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
939
940	/** The size of a 2MB page. */
941	#define X86_PAGE_2M_SIZE _2M
942	/** The page shift of a 2MB page. */
943	#define X86_PAGE_2M_SHIFT 21
944	/** The 2MB page offset mask. */
945	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
946	/** The 2MB page base mask for virtual addresses. */
947	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
948	/** The 2MB page base mask for virtual addresses - 32bit version. */
949	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
950
951	/** The size of a 4MB page. */
952	#define X86_PAGE_4M_SIZE _4M
953	/** The page shift of a 4MB page. */
954	#define X86_PAGE_4M_SHIFT 22
955	/** The 4MB page offset mask. */
956	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
957	/** The 4MB page base mask for virtual addresses. */
958	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
959	/** The 4MB page base mask for virtual addresses - 32bit version. */
960	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
961
962
963
964	/** @name Page Table Entry
965	* @{
966	*/
967	/** Bit 0 - P - Present bit. */
968	#define X86_PTE_P RT_BIT(0)
969	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
970	#define X86_PTE_RW RT_BIT(1)
971	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
972	#define X86_PTE_US RT_BIT(2)
973	/** Bit 3 - PWT - Page level write thru bit. */
974	#define X86_PTE_PWT RT_BIT(3)
975	/** Bit 4 - PCD - Page level cache disable bit. */
976	#define X86_PTE_PCD RT_BIT(4)
977	/** Bit 5 - A - Access bit. */
978	#define X86_PTE_A RT_BIT(5)
979	/** Bit 6 - D - Dirty bit. */
980	#define X86_PTE_D RT_BIT(6)
981	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
982	#define X86_PTE_PAT RT_BIT(7)
983	/** Bit 8 - G - Global flag. */
984	#define X86_PTE_G RT_BIT(8)
985	/** Bits 9-11 - - Available for use to system software. */
986	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
987	/** Bits 12-31 - - Physical Page number of the next level. */
988	#define X86_PTE_PG_MASK ( 0xfffff000 )
989
990	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
991	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
992	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
993	/** @todo Get rid of the above hack; makes code unreadable. */
994	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
995	#else
996	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
997	#endif
998	/** Bits 63 - NX - PAE - No execution flag. */
999	#define X86_PTE_PAE_NX RT_BIT_64(63)
1000
1001	/**
1002	* Page table entry.
1003	*/
1004	typedef struct X86PTEBITS
1005	{
1006	/** Flags whether(=1) or not the page is present. */
1007	unsigned u1Present : 1;
1008	/** Read(=0) / Write(=1) flag. */
1009	unsigned u1Write : 1;
1010	/** User(=1) / Supervisor (=0) flag. */
1011	unsigned u1User : 1;
1012	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1013	unsigned u1WriteThru : 1;
1014	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1015	unsigned u1CacheDisable : 1;
1016	/** Accessed flag.
1017	* Indicates that the page have been read or written to. */
1018	unsigned u1Accessed : 1;
1019	/** Dirty flag.
1020	* Indicates that the page have been written to. */
1021	unsigned u1Dirty : 1;
1022	/** Reserved / If PAT enabled, bit 2 of the index. */
1023	unsigned u1PAT : 1;
1024	/** Global flag. (Ignored in all but final level.) */
1025	unsigned u1Global : 1;
1026	/** Available for use to system software. */
1027	unsigned u3Available : 3;
1028	/** Physical Page number of the next level. */
1029	unsigned u20PageNo : 20;
1030	} X86PTEBITS;
1031	/** Pointer to a page table entry. */
1032	typedef X86PTEBITS *PX86PTEBITS;
1033	/** Pointer to a const page table entry. */
1034	typedef const X86PTEBITS *PCX86PTEBITS;
1035
1036	/**
1037	* Page table entry.
1038	*/
1039	typedef union X86PTE
1040	{
1041	/** Bit field view. */
1042	X86PTEBITS n;
1043	/** Unsigned integer view */
1044	X86PGUINT u;
1045	/** 32-bit view. */
1046	uint32_t au32[1];
1047	/** 16-bit view. */
1048	uint16_t au16[2];
1049	/** 8-bit view. */
1050	uint8_t au8[4];
1051	} X86PTE;
1052	/** Pointer to a page table entry. */
1053	typedef X86PTE *PX86PTE;
1054	/** Pointer to a const page table entry. */
1055	typedef const X86PTE *PCX86PTE;
1056
1057
1058	/**
1059	* PAE page table entry.
1060	*/
1061	typedef struct X86PTEPAEBITS
1062	{
1063	/** Flags whether(=1) or not the page is present. */
1064	uint32_t u1Present : 1;
1065	/** Read(=0) / Write(=1) flag. */
1066	uint32_t u1Write : 1;
1067	/** User(=1) / Supervisor(=0) flag. */
1068	uint32_t u1User : 1;
1069	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1070	uint32_t u1WriteThru : 1;
1071	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1072	uint32_t u1CacheDisable : 1;
1073	/** Accessed flag.
1074	* Indicates that the page have been read or written to. */
1075	uint32_t u1Accessed : 1;
1076	/** Dirty flag.
1077	* Indicates that the page have been written to. */
1078	uint32_t u1Dirty : 1;
1079	/** Reserved / If PAT enabled, bit 2 of the index. */
1080	uint32_t u1PAT : 1;
1081	/** Global flag. (Ignored in all but final level.) */
1082	uint32_t u1Global : 1;
1083	/** Available for use to system software. */
1084	uint32_t u3Available : 3;
1085	/** Physical Page number of the next level - Low Part. Don't use this. */
1086	uint32_t u20PageNoLow : 20;
1087	/** Physical Page number of the next level - High Part. Don't use this. */
1088	uint32_t u20PageNoHigh : 20;
1089	/** MBZ bits */
1090	uint32_t u11Reserved : 11;
1091	/** No Execute flag. */
1092	uint32_t u1NoExecute : 1;
1093	} X86PTEPAEBITS;
1094	/** Pointer to a page table entry. */
1095	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1096	/** Pointer to a page table entry. */
1097	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1098
1099	/**
1100	* PAE Page table entry.
1101	*/
1102	typedef union X86PTEPAE
1103	{
1104	/** Bit field view. */
1105	X86PTEPAEBITS n;
1106	/** Unsigned integer view */
1107	X86PGPAEUINT u;
1108	/** 32-bit view. */
1109	uint32_t au32[2];
1110	/** 16-bit view. */
1111	uint16_t au16[4];
1112	/** 8-bit view. */
1113	uint8_t au8[8];
1114	} X86PTEPAE;
1115	/** Pointer to a PAE page table entry. */
1116	typedef X86PTEPAE *PX86PTEPAE;
1117	/** Pointer to a const PAE page table entry. */
1118	typedef const X86PTEPAE *PCX86PTEPAE;
1119	/** @} */
1120
1121	/**
1122	* Page table.
1123	*/
1124	typedef struct X86PT
1125	{
1126	/** PTE Array. */
1127	X86PTE a[X86_PG_ENTRIES];
1128	} X86PT;
1129	/** Pointer to a page table. */
1130	typedef X86PT *PX86PT;
1131	/** Pointer to a const page table. */
1132	typedef const X86PT *PCX86PT;
1133
1134	/** The page shift to get the PT index. */
1135	#define X86_PT_SHIFT 12
1136	/** The PT index mask (apply to a shifted page address). */
1137	#define X86_PT_MASK 0x3ff
1138
1139
1140	/**
1141	* Page directory.
1142	*/
1143	typedef struct X86PTPAE
1144	{
1145	/** PTE Array. */
1146	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1147	} X86PTPAE;
1148	/** Pointer to a page table. */
1149	typedef X86PTPAE *PX86PTPAE;
1150	/** Pointer to a const page table. */
1151	typedef const X86PTPAE *PCX86PTPAE;
1152
1153	/** The page shift to get the PA PTE index. */
1154	#define X86_PT_PAE_SHIFT 12
1155	/** The PAE PT index mask (apply to a shifted page address). */
1156	#define X86_PT_PAE_MASK 0x1ff
1157
1158
1159	/** @name 4KB Page Directory Entry
1160	* @{
1161	*/
1162	/** Bit 0 - P - Present bit. */
1163	#define X86_PDE_P RT_BIT(0)
1164	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1165	#define X86_PDE_RW RT_BIT(1)
1166	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1167	#define X86_PDE_US RT_BIT(2)
1168	/** Bit 3 - PWT - Page level write thru bit. */
1169	#define X86_PDE_PWT RT_BIT(3)
1170	/** Bit 4 - PCD - Page level cache disable bit. */
1171	#define X86_PDE_PCD RT_BIT(4)
1172	/** Bit 5 - A - Access bit. */
1173	#define X86_PDE_A RT_BIT(5)
1174	/** Bit 7 - PS - Page size attribute.
1175	* Clear mean 4KB pages, set means large pages (2/4MB). */
1176	#define X86_PDE_PS RT_BIT(7)
1177	/** Bits 9-11 - - Available for use to system software. */
1178	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1179	/** Bits 12-31 - - Physical Page number of the next level. */
1180	#define X86_PDE_PG_MASK ( 0xfffff000 )
1181
1182	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1183	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1184	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1185	* we partly or that part into shadow page table entries. Will be corrected
1186	* soon.
1187	*/
1188	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1189	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1190	#else
1191	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1192	#endif
1193	/** Bits 63 - NX - PAE - No execution flag. */
1194	#define X86_PDE_PAE_NX RT_BIT_64(63)
1195
1196	/**
1197	* Page directory entry.
1198	*/
1199	typedef struct X86PDEBITS
1200	{
1201	/** Flags whether(=1) or not the page is present. */
1202	unsigned u1Present : 1;
1203	/** Read(=0) / Write(=1) flag. */
1204	unsigned u1Write : 1;
1205	/** User(=1) / Supervisor (=0) flag. */
1206	unsigned u1User : 1;
1207	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1208	unsigned u1WriteThru : 1;
1209	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1210	unsigned u1CacheDisable : 1;
1211	/** Accessed flag.
1212	* Indicates that the page have been read or written to. */
1213	unsigned u1Accessed : 1;
1214	/** Reserved / Ignored (dirty bit). */
1215	unsigned u1Reserved0 : 1;
1216	/** Size bit if PSE is enabled - in any event it's 0. */
1217	unsigned u1Size : 1;
1218	/** Reserved / Ignored (global bit). */
1219	unsigned u1Reserved1 : 1;
1220	/** Available for use to system software. */
1221	unsigned u3Available : 3;
1222	/** Physical Page number of the next level. */
1223	unsigned u20PageNo : 20;
1224	} X86PDEBITS;
1225	/** Pointer to a page directory entry. */
1226	typedef X86PDEBITS *PX86PDEBITS;
1227	/** Pointer to a const page directory entry. */
1228	typedef const X86PDEBITS *PCX86PDEBITS;
1229
1230
1231	/**
1232	* PAE page directory entry.
1233	*/
1234	typedef struct X86PDEPAEBITS
1235	{
1236	/** Flags whether(=1) or not the page is present. */
1237	uint32_t u1Present : 1;
1238	/** Read(=0) / Write(=1) flag. */
1239	uint32_t u1Write : 1;
1240	/** User(=1) / Supervisor (=0) flag. */
1241	uint32_t u1User : 1;
1242	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1243	uint32_t u1WriteThru : 1;
1244	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1245	uint32_t u1CacheDisable : 1;
1246	/** Accessed flag.
1247	* Indicates that the page have been read or written to. */
1248	uint32_t u1Accessed : 1;
1249	/** Reserved / Ignored (dirty bit). */
1250	uint32_t u1Reserved0 : 1;
1251	/** Size bit if PSE is enabled - in any event it's 0. */
1252	uint32_t u1Size : 1;
1253	/** Reserved / Ignored (global bit). / */
1254	uint32_t u1Reserved1 : 1;
1255	/** Available for use to system software. */
1256	uint32_t u3Available : 3;
1257	/** Physical Page number of the next level - Low Part. Don't use! */
1258	uint32_t u20PageNoLow : 20;
1259	/** Physical Page number of the next level - High Part. Don't use! */
1260	uint32_t u20PageNoHigh : 20;
1261	/** MBZ bits */
1262	uint32_t u11Reserved : 11;
1263	/** No Execute flag. */
1264	uint32_t u1NoExecute : 1;
1265	} X86PDEPAEBITS;
1266	/** Pointer to a page directory entry. */
1267	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1268	/** Pointer to a const page directory entry. */
1269	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1270
1271	/** @} */
1272
1273
1274	/** @name 2/4MB Page Directory Entry
1275	* @{
1276	*/
1277	/** Bit 0 - P - Present bit. */
1278	#define X86_PDE4M_P RT_BIT(0)
1279	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1280	#define X86_PDE4M_RW RT_BIT(1)
1281	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1282	#define X86_PDE4M_US RT_BIT(2)
1283	/** Bit 3 - PWT - Page level write thru bit. */
1284	#define X86_PDE4M_PWT RT_BIT(3)
1285	/** Bit 4 - PCD - Page level cache disable bit. */
1286	#define X86_PDE4M_PCD RT_BIT(4)
1287	/** Bit 5 - A - Access bit. */
1288	#define X86_PDE4M_A RT_BIT(5)
1289	/** Bit 6 - D - Dirty bit. */
1290	#define X86_PDE4M_D RT_BIT(6)
1291	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1292	#define X86_PDE4M_PS RT_BIT(7)
1293	/** Bit 8 - G - Global flag. */
1294	#define X86_PDE4M_G RT_BIT(8)
1295	/** Bits 9-11 - AVL - Available for use to system software. */
1296	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1297	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1298	#define X86_PDE4M_PAT RT_BIT(12)
1299	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1300	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1301	/** Bits 22-31 - - Physical Page number. */
1302	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1303	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1304	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1305	/** The number of bits to the high part of the page number. */
1306	#define X86_PDE4M_PG_HIGH_SHIFT 19
1307
1308	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1309	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1310	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1311	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1312	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1313
1314	/**
1315	* 4MB page directory entry.
1316	*/
1317	typedef struct X86PDE4MBITS
1318	{
1319	/** Flags whether(=1) or not the page is present. */
1320	unsigned u1Present : 1;
1321	/** Read(=0) / Write(=1) flag. */
1322	unsigned u1Write : 1;
1323	/** User(=1) / Supervisor (=0) flag. */
1324	unsigned u1User : 1;
1325	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1326	unsigned u1WriteThru : 1;
1327	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1328	unsigned u1CacheDisable : 1;
1329	/** Accessed flag.
1330	* Indicates that the page have been read or written to. */
1331	unsigned u1Accessed : 1;
1332	/** Dirty flag.
1333	* Indicates that the page have been written to. */
1334	unsigned u1Dirty : 1;
1335	/** Page size flag - always 1 for 4MB entries. */
1336	unsigned u1Size : 1;
1337	/** Global flag. */
1338	unsigned u1Global : 1;
1339	/** Available for use to system software. */
1340	unsigned u3Available : 3;
1341	/** Reserved / If PAT enabled, bit 2 of the index. */
1342	unsigned u1PAT : 1;
1343	/** Bits 32-39 of the page number on AMD64.
1344	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1345	unsigned u8PageNoHigh : 8;
1346	/** Reserved. */
1347	unsigned u1Reserved : 1;
1348	/** Physical Page number of the page. */
1349	unsigned u10PageNo : 10;
1350	} X86PDE4MBITS;
1351	/** Pointer to a page table entry. */
1352	typedef X86PDE4MBITS *PX86PDE4MBITS;
1353	/** Pointer to a const page table entry. */
1354	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1355
1356
1357	/**
1358	* 2MB PAE page directory entry.
1359	*/
1360	typedef struct X86PDE2MPAEBITS
1361	{
1362	/** Flags whether(=1) or not the page is present. */
1363	uint32_t u1Present : 1;
1364	/** Read(=0) / Write(=1) flag. */
1365	uint32_t u1Write : 1;
1366	/** User(=1) / Supervisor(=0) flag. */
1367	uint32_t u1User : 1;
1368	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1369	uint32_t u1WriteThru : 1;
1370	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1371	uint32_t u1CacheDisable : 1;
1372	/** Accessed flag.
1373	* Indicates that the page have been read or written to. */
1374	uint32_t u1Accessed : 1;
1375	/** Dirty flag.
1376	* Indicates that the page have been written to. */
1377	uint32_t u1Dirty : 1;
1378	/** Page size flag - always 1 for 2MB entries. */
1379	uint32_t u1Size : 1;
1380	/** Global flag. */
1381	uint32_t u1Global : 1;
1382	/** Available for use to system software. */
1383	uint32_t u3Available : 3;
1384	/** Reserved / If PAT enabled, bit 2 of the index. */
1385	uint32_t u1PAT : 1;
1386	/** Reserved. */
1387	uint32_t u9Reserved : 9;
1388	/** Physical Page number of the next level - Low part. Don't use! */
1389	uint32_t u10PageNoLow : 10;
1390	/** Physical Page number of the next level - High part. Don't use! */
1391	uint32_t u20PageNoHigh : 20;
1392	/** MBZ bits */
1393	uint32_t u11Reserved : 11;
1394	/** No Execute flag. */
1395	uint32_t u1NoExecute : 1;
1396	} X86PDE2MPAEBITS;
1397	/** Pointer to a 4MB PAE page table entry. */
1398	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1399	/** Pointer to a 4MB PAE page table entry. */
1400	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1401
1402	/** @} */
1403
1404	/**
1405	* Page directory entry.
1406	*/
1407	typedef union X86PDE
1408	{
1409	/** Normal view. */
1410	X86PDEBITS n;
1411	/** 4MB view (big). */
1412	X86PDE4MBITS b;
1413	/** Unsigned integer view. */
1414	X86PGUINT u;
1415	/** 8 bit unsigned integer view. */
1416	uint8_t au8[4];
1417	/** 16 bit unsigned integer view. */
1418	uint16_t au16[2];
1419	/** 32 bit unsigned integer view. */
1420	uint32_t au32[1];
1421	} X86PDE;
1422	/** Pointer to a page directory entry. */
1423	typedef X86PDE *PX86PDE;
1424	/** Pointer to a const page directory entry. */
1425	typedef const X86PDE *PCX86PDE;
1426
1427	/**
1428	* PAE page directory entry.
1429	*/
1430	typedef union X86PDEPAE
1431	{
1432	/** Normal view. */
1433	X86PDEPAEBITS n;
1434	/** 2MB page view (big). */
1435	X86PDE2MPAEBITS b;
1436	/** Unsigned integer view. */
1437	X86PGPAEUINT u;
1438	/** 8 bit unsigned integer view. */
1439	uint8_t au8[8];
1440	/** 16 bit unsigned integer view. */
1441	uint16_t au16[4];
1442	/** 32 bit unsigned integer view. */
1443	uint32_t au32[2];
1444	} X86PDEPAE;
1445	/** Pointer to a page directory entry. */
1446	typedef X86PDEPAE *PX86PDEPAE;
1447	/** Pointer to a const page directory entry. */
1448	typedef const X86PDEPAE *PCX86PDEPAE;
1449
1450	/**
1451	* Page directory.
1452	*/
1453	typedef struct X86PD
1454	{
1455	/** PDE Array. */
1456	X86PDE a[X86_PG_ENTRIES];
1457	} X86PD;
1458	/** Pointer to a page directory. */
1459	typedef X86PD *PX86PD;
1460	/** Pointer to a const page directory. */
1461	typedef const X86PD *PCX86PD;
1462
1463	/** The page shift to get the PD index. */
1464	#define X86_PD_SHIFT 22
1465	/** The PD index mask (apply to a shifted page address). */
1466	#define X86_PD_MASK 0x3ff
1467
1468
1469	/**
1470	* PAE page directory.
1471	*/
1472	typedef struct X86PDPAE
1473	{
1474	/** PDE Array. */
1475	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1476	} X86PDPAE;
1477	/** Pointer to a PAE page directory. */
1478	typedef X86PDPAE *PX86PDPAE;
1479	/** Pointer to a const PAE page directory. */
1480	typedef const X86PDPAE *PCX86PDPAE;
1481
1482	/** The page shift to get the PAE PD index. */
1483	#define X86_PD_PAE_SHIFT 21
1484	/** The PAE PD index mask (apply to a shifted page address). */
1485	#define X86_PD_PAE_MASK 0x1ff
1486
1487
1488	/** @name Page Directory Pointer Table Entry (PAE)
1489	* @{
1490	*/
1491	/** Bit 0 - P - Present bit. */
1492	#define X86_PDPE_P RT_BIT(0)
1493	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1494	#define X86_PDPE_RW RT_BIT(1)
1495	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1496	#define X86_PDPE_US RT_BIT(2)
1497	/** Bit 3 - PWT - Page level write thru bit. */
1498	#define X86_PDPE_PWT RT_BIT(3)
1499	/** Bit 4 - PCD - Page level cache disable bit. */
1500	#define X86_PDPE_PCD RT_BIT(4)
1501	/** Bit 5 - A - Access bit. Long Mode only. */
1502	#define X86_PDPE_A RT_BIT(5)
1503	/** Bits 9-11 - - Available for use to system software. */
1504	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1505	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1506	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1507	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1508	/** @todo Get rid of the above hack; makes code unreadable. */
1509	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1510	#else
1511	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1512	#endif
1513	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1514	#define X86_PDPE_NX RT_BIT_64(63)
1515
1516	/**
1517	* Page directory pointer table entry.
1518	*/
1519	typedef struct X86PDPEBITS
1520	{
1521	/** Flags whether(=1) or not the page is present. */
1522	uint32_t u1Present : 1;
1523	/** Chunk of reserved bits. */
1524	uint32_t u2Reserved : 2;
1525	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1526	uint32_t u1WriteThru : 1;
1527	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1528	uint32_t u1CacheDisable : 1;
1529	/** Chunk of reserved bits. */
1530	uint32_t u4Reserved : 4;
1531	/** Available for use to system software. */
1532	uint32_t u3Available : 3;
1533	/** Physical Page number of the next level - Low Part. Don't use! */
1534	uint32_t u20PageNoLow : 20;
1535	/** Physical Page number of the next level - High Part. Don't use! */
1536	uint32_t u20PageNoHigh : 20;
1537	/** MBZ bits */
1538	uint32_t u12Reserved : 12;
1539	} X86PDPEBITS;
1540	/** Pointer to a page directory pointer table entry. */
1541	typedef X86PDPEBITS *PX86PTPEBITS;
1542	/** Pointer to a const page directory pointer table entry. */
1543	typedef const X86PDPEBITS *PCX86PTPEBITS;
1544
1545	/**
1546	* Page directory pointer table entry. AMD64 version
1547	*/
1548	typedef struct X86PDPEAMD64BITS
1549	{
1550	/** Flags whether(=1) or not the page is present. */
1551	uint32_t u1Present : 1;
1552	/** Read(=0) / Write(=1) flag. */
1553	uint32_t u1Write : 1;
1554	/** User(=1) / Supervisor (=0) flag. */
1555	uint32_t u1User : 1;
1556	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1557	uint32_t u1WriteThru : 1;
1558	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1559	uint32_t u1CacheDisable : 1;
1560	/** Accessed flag.
1561	* Indicates that the page have been read or written to. */
1562	uint32_t u1Accessed : 1;
1563	/** Chunk of reserved bits. */
1564	uint32_t u3Reserved : 3;
1565	/** Available for use to system software. */
1566	uint32_t u3Available : 3;
1567	/** Physical Page number of the next level - Low Part. Don't use! */
1568	uint32_t u20PageNoLow : 20;
1569	/** Physical Page number of the next level - High Part. Don't use! */
1570	uint32_t u20PageNoHigh : 20;
1571	/** MBZ bits */
1572	uint32_t u11Reserved : 11;
1573	/** No Execute flag. */
1574	uint32_t u1NoExecute : 1;
1575	} X86PDPEAMD64BITS;
1576	/** Pointer to a page directory pointer table entry. */
1577	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1578	/** Pointer to a const page directory pointer table entry. */
1579	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1580
1581	/**
1582	* Page directory pointer table entry.
1583	*/
1584	typedef union X86PDPE
1585	{
1586	/** Normal view. */
1587	X86PDPEBITS n;
1588	/** AMD64 view. */
1589	X86PDPEAMD64BITS lm;
1590	/** Unsigned integer view. */
1591	X86PGPAEUINT u;
1592	/** 8 bit unsigned integer view. */
1593	uint8_t au8[8];
1594	/** 16 bit unsigned integer view. */
1595	uint16_t au16[4];
1596	/** 32 bit unsigned integer view. */
1597	uint32_t au32[2];
1598	} X86PDPE;
1599	/** Pointer to a page directory pointer table entry. */
1600	typedef X86PDPE *PX86PDPE;
1601	/** Pointer to a const page directory pointer table entry. */
1602	typedef const X86PDPE *PCX86PDPE;
1603
1604
1605	/**
1606	* Page directory pointer table.
1607	*/
1608	typedef struct X86PDPT
1609	{
1610	/** PDE Array. */
1611	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1612	} X86PDPT;
1613	/** Pointer to a page directory pointer table. */
1614	typedef X86PDPT *PX86PDPT;
1615	/** Pointer to a const page directory pointer table. */
1616	typedef const X86PDPT *PCX86PDPT;
1617
1618	/** The page shift to get the PDPT index. */
1619	#define X86_PDPT_SHIFT 30
1620	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1621	#define X86_PDPT_MASK_PAE 0x3
1622	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1623	#define X86_PDPT_MASK_AMD64 0x1ff
1624
1625	/** @} */
1626
1627
1628	/** @name Page Map Level-4 Entry (Long Mode PAE)
1629	* @{
1630	*/
1631	/** Bit 0 - P - Present bit. */
1632	#define X86_PML4E_P RT_BIT(0)
1633	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1634	#define X86_PML4E_RW RT_BIT(1)
1635	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1636	#define X86_PML4E_US RT_BIT(2)
1637	/** Bit 3 - PWT - Page level write thru bit. */
1638	#define X86_PML4E_PWT RT_BIT(3)
1639	/** Bit 4 - PCD - Page level cache disable bit. */
1640	#define X86_PML4E_PCD RT_BIT(4)
1641	/** Bit 5 - A - Access bit. */
1642	#define X86_PML4E_A RT_BIT(5)
1643	/** Bits 9-11 - - Available for use to system software. */
1644	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1645	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1646	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1647	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1648	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1649	#else
1650	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1651	#endif
1652	/** Bits 63 - NX - PAE - No execution flag. */
1653	#define X86_PML4E_NX RT_BIT_64(63)
1654
1655	/**
1656	* Page Map Level-4 Entry
1657	*/
1658	typedef struct X86PML4EBITS
1659	{
1660	/** Flags whether(=1) or not the page is present. */
1661	uint32_t u1Present : 1;
1662	/** Read(=0) / Write(=1) flag. */
1663	uint32_t u1Write : 1;
1664	/** User(=1) / Supervisor (=0) flag. */
1665	uint32_t u1User : 1;
1666	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1667	uint32_t u1WriteThru : 1;
1668	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1669	uint32_t u1CacheDisable : 1;
1670	/** Accessed flag.
1671	* Indicates that the page have been read or written to. */
1672	uint32_t u1Accessed : 1;
1673	/** Chunk of reserved bits. */
1674	uint32_t u3Reserved : 3;
1675	/** Available for use to system software. */
1676	uint32_t u3Available : 3;
1677	/** Physical Page number of the next level - Low Part. Don't use! */
1678	uint32_t u20PageNoLow : 20;
1679	/** Physical Page number of the next level - High Part. Don't use! */
1680	uint32_t u20PageNoHigh : 20;
1681	/** MBZ bits */
1682	uint32_t u11Reserved : 11;
1683	/** No Execute flag. */
1684	uint32_t u1NoExecute : 1;
1685	} X86PML4EBITS;
1686	/** Pointer to a page map level-4 entry. */
1687	typedef X86PML4EBITS *PX86PML4EBITS;
1688	/** Pointer to a const page map level-4 entry. */
1689	typedef const X86PML4EBITS *PCX86PML4EBITS;
1690
1691	/**
1692	* Page Map Level-4 Entry.
1693	*/
1694	typedef union X86PML4E
1695	{
1696	/** Normal view. */
1697	X86PML4EBITS n;
1698	/** Unsigned integer view. */
1699	X86PGPAEUINT u;
1700	/** 8 bit unsigned integer view. */
1701	uint8_t au8[8];
1702	/** 16 bit unsigned integer view. */
1703	uint16_t au16[4];
1704	/** 32 bit unsigned integer view. */
1705	uint32_t au32[2];
1706	} X86PML4E;
1707	/** Pointer to a page map level-4 entry. */
1708	typedef X86PML4E *PX86PML4E;
1709	/** Pointer to a const page map level-4 entry. */
1710	typedef const X86PML4E *PCX86PML4E;
1711
1712
1713	/**
1714	* Page Map Level-4.
1715	*/
1716	typedef struct X86PML4
1717	{
1718	/** PDE Array. */
1719	X86PML4E a[X86_PG_PAE_ENTRIES];
1720	} X86PML4;
1721	/** Pointer to a page map level-4. */
1722	typedef X86PML4 *PX86PML4;
1723	/** Pointer to a const page map level-4. */
1724	typedef const X86PML4 *PCX86PML4;
1725
1726	/** The page shift to get the PML4 index. */
1727	#define X86_PML4_SHIFT 39
1728	/** The PML4 index mask (apply to a shifted page address). */
1729	#define X86_PML4_MASK 0x1ff
1730
1731	/** @} */
1732
1733	/** @} */
1734
1735
1736	/**
1737	* 80-bit MMX/FPU register type.
1738	*/
1739	typedef struct X86FPUMMX
1740	{
1741	uint8_t reg[10];
1742	} X86FPUMMX;
1743	/** Pointer to a 80-bit MMX/FPU register type. */
1744	typedef X86FPUMMX *PX86FPUMMX;
1745	/** Pointer to a const 80-bit MMX/FPU register type. */
1746	typedef const X86FPUMMX *PCX86FPUMMX;
1747
1748	/**
1749	* FPU state (aka FSAVE/FRSTOR Memory Region).
1750	*/
1751	#pragma pack(1)
1752	typedef struct X86FPUSTATE
1753	{
1754	/** Control word. */
1755	uint16_t FCW;
1756	/** Alignment word */
1757	uint16_t Dummy1;
1758	/** Status word. */
1759	uint16_t FSW;
1760	/** Alignment word */
1761	uint16_t Dummy2;
1762	/** Tag word */
1763	uint16_t FTW;
1764	/** Alignment word */
1765	uint16_t Dummy3;
1766
1767	/** Instruction pointer. */
1768	uint32_t FPUIP;
1769	/** Code selector. */
1770	uint16_t CS;
1771	/** Opcode. */
1772	uint16_t FOP;
1773	/** FOO. */
1774	uint32_t FPUOO;
1775	/** FOS. */
1776	uint32_t FPUOS;
1777	/** FPU view - todo. */
1778	X86FPUMMX regs[8];
1779	} X86FPUSTATE;
1780	#pragma pack()
1781	/** Pointer to a FPU state. */
1782	typedef X86FPUSTATE *PX86FPUSTATE;
1783	/** Pointer to a const FPU state. */
1784	typedef const X86FPUSTATE *PCX86FPUSTATE;
1785
1786	/**
1787	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1788	*/
1789	#pragma pack(1)
1790	typedef struct X86FXSTATE
1791	{
1792	/** Control word. */
1793	uint16_t FCW;
1794	/** Status word. */
1795	uint16_t FSW;
1796	/** Tag word (it's a byte actually). */
1797	uint8_t FTW;
1798	uint8_t huh1;
1799	/** Opcode. */
1800	uint16_t FOP;
1801	/** Instruction pointer. */
1802	uint32_t FPUIP;
1803	/** Code selector. */
1804	uint16_t CS;
1805	uint16_t Rsvrd1;
1806	/* - offset 16 - */
1807	/** Data pointer. */
1808	uint32_t FPUDP;
1809	/** Data segment */
1810	uint16_t DS;
1811	uint16_t Rsrvd2;
1812	uint32_t MXCSR;
1813	uint32_t MXCSR_MASK;
1814	/* - offset 32 - */
1815	union
1816	{
1817	/** MMX view. */
1818	uint64_t mmx;
1819	/** FPU view - todo. */
1820	X86FPUMMX fpu;
1821	/** 8-bit view. */
1822	uint8_t au8[16];
1823	/** 16-bit view. */
1824	uint16_t au16[8];
1825	/** 32-bit view. */
1826	uint32_t au32[4];
1827	/** 64-bit view. */
1828	uint64_t au64[2];
1829	/** 128-bit view. (yeah, very helpful) */
1830	uint128_t au128[1];
1831	} aRegs[8];
1832	/* - offset 160 - */
1833	union
1834	{
1835	/** XMM Register view . /
1836	uint128_t xmm;
1837	/** 8-bit view. */
1838	uint8_t au8[16];
1839	/** 16-bit view. */
1840	uint16_t au16[8];
1841	/** 32-bit view. */
1842	uint32_t au32[4];
1843	/** 64-bit view. */
1844	uint64_t au64[2];
1845	/** 128-bit view. (yeah, very helpful) */
1846	uint128_t au128[1];
1847	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1848	/* - offset 416 - */
1849	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1850	} X86FXSTATE;
1851	#pragma pack()
1852	/** Pointer to a FPU Extended state. */
1853	typedef X86FXSTATE *PX86FXSTATE;
1854	/** Pointer to a const FPU Extended state. */
1855	typedef const X86FXSTATE *PCX86FXSTATE;
1856
1857
1858	/** @name Selector Descriptor
1859	* @{
1860	*/
1861
1862	/**
1863	* Generic descriptor table entry
1864	*/
1865	#pragma pack(1)
1866	typedef struct X86DESCGENERIC
1867	{
1868	/** Limit - Low word. */
1869	unsigned u16LimitLow : 16;
1870	/** Base address - lowe word.
1871	* Don't try set this to 24 because MSC is doing studing things then. */
1872	unsigned u16BaseLow : 16;
1873	/** Base address - first 8 bits of high word. */
1874	unsigned u8BaseHigh1 : 8;
1875	/** Segment Type. */
1876	unsigned u4Type : 4;
1877	/** Descriptor Type. System(=0) or code/data selector */
1878	unsigned u1DescType : 1;
1879	/** Descriptor Privelege level. */
1880	unsigned u2Dpl : 2;
1881	/** Flags selector present(=1) or not. */
1882	unsigned u1Present : 1;
1883	/** Segment limit 16-19. */
1884	unsigned u4LimitHigh : 4;
1885	/** Available for system software. */
1886	unsigned u1Available : 1;
1887	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1888	unsigned u1Long : 1;
1889	/** This flags meaning depends on the segment type. Try make sense out
1890	* of the intel manual yourself. */
1891	unsigned u1DefBig : 1;
1892	/** Granularity of the limit. If set 4KB granularity is used, if
1893	* clear byte. */
1894	unsigned u1Granularity : 1;
1895	/** Base address - highest 8 bits. */
1896	unsigned u8BaseHigh2 : 8;
1897	} X86DESCGENERIC;
1898	#pragma pack()
1899	/** Pointer to a generic descriptor entry. */
1900	typedef X86DESCGENERIC *PX86DESCGENERIC;
1901	/** Pointer to a const generic descriptor entry. */
1902	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1903
1904
1905	/**
1906	* Descriptor attributes.
1907	*/
1908	typedef struct X86DESCATTRBITS
1909	{
1910	/** Segment Type. */
1911	unsigned u4Type : 4;
1912	/** Descriptor Type. System(=0) or code/data selector */
1913	unsigned u1DescType : 1;
1914	/** Descriptor Privelege level. */
1915	unsigned u2Dpl : 2;
1916	/** Flags selector present(=1) or not. */
1917	unsigned u1Present : 1;
1918	/** Segment limit 16-19. */
1919	unsigned u4LimitHigh : 4;
1920	/** Available for system software. */
1921	unsigned u1Available : 1;
1922	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1923	unsigned u1Long : 1;
1924	/** This flags meaning depends on the segment type. Try make sense out
1925	* of the intel manual yourself. */
1926	unsigned u1DefBig : 1;
1927	/** Granularity of the limit. If set 4KB granularity is used, if
1928	* clear byte. */
1929	unsigned u1Granularity : 1;
1930	} X86DESCATTRBITS;
1931
1932
1933	#pragma pack(1)
1934	typedef union X86DESCATTR
1935	{
1936	/** Normal view. */
1937	X86DESCATTRBITS n;
1938	/** Unsigned integer view. */
1939	uint32_t u;
1940	} X86DESCATTR;
1941	#pragma pack()
1942
1943	/** Pointer to descriptor attributes. */
1944	typedef X86DESCATTR *PX86DESCATTR;
1945	/** Pointer to const descriptor attributes. */
1946	typedef const X86DESCATTR *PCX86DESCATTR;
1947
1948
1949	/**
1950	* Descriptor table entry.
1951	*/
1952	#pragma pack(1)
1953	typedef union X86DESC
1954	{
1955	/** Generic descriptor view. */
1956	X86DESCGENERIC Gen;
1957	#if 0
1958	/** IDT view. */
1959	VBOXIDTE Idt;
1960	#endif
1961
1962	/** 8 bit unsigned interger view. */
1963	uint8_t au8[8];
1964	/** 16 bit unsigned interger view. */
1965	uint16_t au16[4];
1966	/** 32 bit unsigned interger view. */
1967	uint32_t au32[2];
1968	} X86DESC;
1969	#pragma pack()
1970	/** Pointer to descriptor table entry. */
1971	typedef X86DESC *PX86DESC;
1972	/** Pointer to const descriptor table entry. */
1973	typedef const X86DESC *PCX86DESC;
1974
1975
1976	/** @def X86DESC_BASE
1977	* Return the base address of a descriptor.
1978	*/
1979	#define X86DESC_BASE(desc) \
1980	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
1981	\| ( (desc).Gen.u8BaseHigh1 << 16) \
1982	\| ( (desc).Gen.u16BaseLow ) )
1983
1984	/** @def X86DESC_LIMIT
1985	* Return the limit of a descriptor.
1986	*/
1987	#define X86DESC_LIMIT(desc) \
1988	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
1989	\| ( (desc).Gen.u16LimitLow ) )
1990
1991	/**
1992	* 64 bits generic descriptor table entry
1993	* Note: most of these bits have no meaning in long mode.
1994	*/
1995	#pragma pack(1)
1996	typedef struct X86DESC64GENERIC
1997	{
1998	/** Limit - Low word - IGNORED. */
1999	unsigned u16LimitLow : 16;
2000	/** Base address - lowe word. - IGNORED
2001	* Don't try set this to 24 because MSC is doing studing things then. */
2002	unsigned u16BaseLow : 16;
2003	/** Base address - first 8 bits of high word. - IGNORED */
2004	unsigned u8BaseHigh1 : 8;
2005	/** Segment Type. */
2006	unsigned u4Type : 4;
2007	/** Descriptor Type. System(=0) or code/data selector */
2008	unsigned u1DescType : 1;
2009	/** Descriptor Privelege level. */
2010	unsigned u2Dpl : 2;
2011	/** Flags selector present(=1) or not. */
2012	unsigned u1Present : 1;
2013	/** Segment limit 16-19. - IGNORED */
2014	unsigned u4LimitHigh : 4;
2015	/** Available for system software. - IGNORED */
2016	unsigned u1Available : 1;
2017	/** Long mode flag. */
2018	unsigned u1Long : 1;
2019	/** This flags meaning depends on the segment type. Try make sense out
2020	* of the intel manual yourself. */
2021	unsigned u1DefBig : 1;
2022	/** Granularity of the limit. If set 4KB granularity is used, if
2023	* clear byte. - IGNORED */
2024	unsigned u1Granularity : 1;
2025	/** Base address - highest 8 bits. - IGNORED */
2026	unsigned u8BaseHigh2 : 8;
2027	/** Base address - bits 63-32. */
2028	unsigned u32BaseHigh3 : 32;
2029	unsigned u8Reserved : 8;
2030	unsigned u5Zeros : 5;
2031	unsigned u19Reserved : 19;
2032	} X86DESC64GENERIC;
2033	#pragma pack()
2034	/** Pointer to a generic descriptor entry. */
2035	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2036	/** Pointer to a const generic descriptor entry. */
2037	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2038
2039	/**
2040	* System descriptor table entry (64 bits)
2041	*/
2042	#pragma pack(1)
2043	typedef struct X86DESC64SYSTEM
2044	{
2045	/** Limit - Low word. */
2046	unsigned u16LimitLow : 16;
2047	/** Base address - lowe word.
2048	* Don't try set this to 24 because MSC is doing studing things then. */
2049	unsigned u16BaseLow : 16;
2050	/** Base address - first 8 bits of high word. */
2051	unsigned u8BaseHigh1 : 8;
2052	/** Segment Type. */
2053	unsigned u4Type : 4;
2054	/** Descriptor Type. System(=0) or code/data selector */
2055	unsigned u1DescType : 1;
2056	/** Descriptor Privelege level. */
2057	unsigned u2Dpl : 2;
2058	/** Flags selector present(=1) or not. */
2059	unsigned u1Present : 1;
2060	/** Segment limit 16-19. */
2061	unsigned u4LimitHigh : 4;
2062	/** Available for system software. */
2063	unsigned u1Available : 1;
2064	/** Reserved - 0. */
2065	unsigned u1Reserved : 1;
2066	/** This flags meaning depends on the segment type. Try make sense out
2067	* of the intel manual yourself. */
2068	unsigned u1DefBig : 1;
2069	/** Granularity of the limit. If set 4KB granularity is used, if
2070	* clear byte. */
2071	unsigned u1Granularity : 1;
2072	/** Base address - bits 31-24. */
2073	unsigned u8BaseHigh2 : 8;
2074	/** Base address - bits 63-32. */
2075	unsigned u32BaseHigh3 : 32;
2076	unsigned u8Reserved : 8;
2077	unsigned u5Zeros : 5;
2078	unsigned u19Reserved : 19;
2079	} X86DESC64SYSTEM;
2080	#pragma pack()
2081	/** Pointer to a generic descriptor entry. */
2082	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2083	/** Pointer to a const generic descriptor entry. */
2084	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2085
2086
2087	/**
2088	* Descriptor table entry.
2089	*/
2090	#pragma pack(1)
2091	typedef union X86DESC64
2092	{
2093	/** Generic descriptor view. */
2094	X86DESC64GENERIC Gen;
2095	/** System descriptor view. */
2096	X86DESC64SYSTEM System;
2097	#if 0
2098	X86DESC64GATE Gate;
2099	#endif
2100
2101	/** 8 bit unsigned interger view. */
2102	uint8_t au8[16];
2103	/** 16 bit unsigned interger view. */
2104	uint16_t au16[8];
2105	/** 32 bit unsigned interger view. */
2106	uint32_t au32[4];
2107	/** 64 bit unsigned interger view. */
2108	uint64_t au64[2];
2109	} X86DESC64;
2110	#pragma pack()
2111	/** Pointer to descriptor table entry. */
2112	typedef X86DESC64 *PX86DESC64;
2113	/** Pointer to const descriptor table entry. */
2114	typedef const X86DESC64 *PCX86DESC64;
2115
2116	#if HC_ARCH_BITS == 64
2117	typedef X86DESC64 X86DESCHC;
2118	typedef X86DESC64 *PX86DESCHC;
2119	#else
2120	typedef X86DESC X86DESCHC;
2121	typedef X86DESC *PX86DESCHC;
2122	#endif
2123
2124	/** @def X86DESC_LIMIT
2125	* Return the base of a 64-bit descriptor.
2126	*/
2127	#define X86DESC64_BASE(desc) \
2128	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2129	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2130	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2131	\| ( (desc).Gen.u16BaseLow ) )
2132
2133
2134	/** @name Selector Descriptor Types.
2135	* @{
2136	*/
2137
2138	/** @name Non-System Selector Types.
2139	* @{ */
2140	/** Code(=set)/Data(=clear) bit. */
2141	#define X86_SEL_TYPE_CODE 8
2142	/** Memory(=set)/System(=clear) bit. */
2143	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2144	/** Accessed bit. */
2145	#define X86_SEL_TYPE_ACCESSED 1
2146	/** Expand down bit (for data selectors only). */
2147	#define X86_SEL_TYPE_DOWN 4
2148	/** Conforming bit (for code selectors only). */
2149	#define X86_SEL_TYPE_CONF 4
2150	/** Write bit (for data selectors only). */
2151	#define X86_SEL_TYPE_WRITE 2
2152	/** Read bit (for code selectors only). */
2153	#define X86_SEL_TYPE_READ 2
2154
2155	/** Read only selector type. */
2156	#define X86_SEL_TYPE_RO 0
2157	/** Accessed read only selector type. */
2158	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2159	/** Read write selector type. */
2160	#define X86_SEL_TYPE_RW 2
2161	/** Accessed read write selector type. */
2162	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2163	/** Expand down read only selector type. */
2164	#define X86_SEL_TYPE_RO_DOWN 4
2165	/** Accessed expand down read only selector type. */
2166	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2167	/** Expand down read write selector type. */
2168	#define X86_SEL_TYPE_RW_DOWN 6
2169	/** Accessed expand down read write selector type. */
2170	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2171	/** Execute only selector type. */
2172	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2173	/** Accessed execute only selector type. */
2174	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2175	/** Execute and read selector type. */
2176	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2177	/** Accessed execute and read selector type. */
2178	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2179	/** Conforming execute only selector type. */
2180	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2181	/** Accessed Conforming execute only selector type. */
2182	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2183	/** Conforming execute and write selector type. */
2184	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2185	/** Accessed Conforming execute and write selector type. */
2186	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2187	/** @} */
2188
2189
2190	/** @name System Selector Types.
2191	* @{ */
2192	/** Undefined system selector type. */
2193	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2194	/** 286 TSS selector. */
2195	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2196	/** LDT selector. */
2197	#define X86_SEL_TYPE_SYS_LDT 2
2198	/** 286 TSS selector - Busy. */
2199	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2200	/** 286 Callgate selector. */
2201	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2202	/** Taskgate selector. */
2203	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2204	/** 286 Interrupt gate selector. */
2205	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2206	/** 286 Trapgate selector. */
2207	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2208	/** Undefined system selector. */
2209	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2210	/** 386 TSS selector. */
2211	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2212	/** Undefined system selector. */
2213	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2214	/** 386 TSS selector - Busy. */
2215	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2216	/** 386 Callgate selector. */
2217	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2218	/** Undefined system selector. */
2219	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2220	/** 386 Interruptgate selector. */
2221	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2222	/** 386 Trapgate selector. */
2223	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2224	/** @} */
2225
2226	/** @name AMD64 System Selector Types.
2227	* @{ */
2228	#define AMD64_SEL_TYPE_SYS_LDT 2
2229	/** 286 TSS selector - Busy. */
2230	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2231	/** 386 TSS selector - Busy. */
2232	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2233	/** 386 Callgate selector. */
2234	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2235	/** 386 Interruptgate selector. */
2236	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2237	/** 386 Trapgate selector. */
2238	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2239	/** @} */
2240
2241	/** @} */
2242
2243
2244	/** @name Descriptor Table Entry Flag Masks.
2245	* These are for the 2nd 32-bit word of a descriptor.
2246	* @{ */
2247	/** Bits 8-11 - TYPE - Descriptor type mask. */
2248	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2249	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2250	#define X86_DESC_S RT_BIT(12)
2251	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2252	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2253	/** Bit 15 - P - Present. */
2254	#define X86_DESC_P RT_BIT(15)
2255	/** Bit 20 - AVL - Available for system software. */
2256	#define X86_DESC_AVL RT_BIT(20)
2257	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2258	#define X86_DESC_DB RT_BIT(22)
2259	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2260	* used, if clear byte. */
2261	#define X86_DESC_G RT_BIT(23)
2262	/** @} */
2263
2264	/** @} */
2265
2266
2267	/** @name Selectors.
2268	* @{
2269	*/
2270
2271	/**
2272	* The shift used to convert a selector from and to index an index (C).
2273	*/
2274	#define X86_SEL_SHIFT 3
2275
2276	/**
2277	* The shift used to convert a selector from and to index an index (C).
2278	*/
2279	#define AMD64_SEL_SHIFT 4
2280
2281	#if HC_ARCH_BITS == 64
2282	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2283	#else
2284	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2285	#endif
2286
2287	/**
2288	* The mask used to mask off the table indicator and CPL of an selector.
2289	*/
2290	#define X86_SEL_MASK 0xfff8
2291
2292	/**
2293	* The bit indicating that a selector is in the LDT and not in the GDT.
2294	*/
2295	#define X86_SEL_LDT 0x0004
2296	/**
2297	* The bit mask for getting the RPL of a selector.
2298	*/
2299	#define X86_SEL_RPL 0x0003
2300
2301	/** @} */
2302
2303
2304	/**
2305	* x86 Exceptions/Faults/Traps.
2306	*/
2307	typedef enum X86XCPT
2308	{
2309	/** \#DE - Divide error. */
2310	X86_XCPT_DE = 0x00,
2311	/** \#DB - Debug event (single step, DRx, ..) */
2312	X86_XCPT_DB = 0x01,
2313	/** NMI - Non-Maskable Interrupt */
2314	X86_XCPT_NMI = 0x02,
2315	/** \#BP - Breakpoint (INT3). */
2316	X86_XCPT_BP = 0x03,
2317	/** \#OF - Overflow (INTO). */
2318	X86_XCPT_OF = 0x04,
2319	/** \#BR - Bound range exceeded (BOUND). */
2320	X86_XCPT_BR = 0x05,
2321	/** \#UD - Undefined opcode. */
2322	X86_XCPT_UD = 0x06,
2323	/** \#NM - Device not available (math coprocessor device). */
2324	X86_XCPT_NM = 0x07,
2325	/** \#DF - Double fault. */
2326	X86_XCPT_DF = 0x08,
2327	/** ??? - Coprocessor segment overrun (obsolete). */
2328	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2329	/** \#TS - Taskswitch (TSS). */
2330	X86_XCPT_TS = 0x0a,
2331	/** \#NP - Segment no present. */
2332	X86_XCPT_NP = 0x0b,
2333	/** \#SS - Stack segment fault. */
2334	X86_XCPT_SS = 0x0c,
2335	/** \#GP - General protection fault. */
2336	X86_XCPT_GP = 0x0d,
2337	/** \#PF - Page fault. */
2338	X86_XCPT_PF = 0x0e,
2339	/* 0x0f is reserved. */
2340	/** \#MF - Math fault (FPU). */
2341	X86_XCPT_MF = 0x10,
2342	/** \#AC - Alignment check. */
2343	X86_XCPT_AC = 0x11,
2344	/** \#MC - Machine check. */
2345	X86_XCPT_MC = 0x12,
2346	/** \#XF - SIMD Floating-Pointer Exception. */
2347	X86_XCPT_XF = 0x13
2348	} X86XCPT;
2349	/** Pointer to a x86 exception code. */
2350	typedef X86XCPT *PX86XCPT;
2351	/** Pointer to a const x86 exception code. */
2352	typedef const X86XCPT *PCX86XCPT;
2353
2354
2355	/** @name Trap Error Codes
2356	* @{
2357	*/
2358	/** External indicator. */
2359	#define X86_TRAP_ERR_EXTERNAL 1
2360	/** IDT indicator. */
2361	#define X86_TRAP_ERR_IDT 2
2362	/** Descriptor table indicator - If set LDT, if clear GDT. */
2363	#define X86_TRAP_ERR_TI 4
2364	/** Mask for getting the selector. */
2365	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2366	/** Shift for getting the selector table index (C type index). */
2367	#define X86_TRAP_ERR_SEL_SHIFT 3
2368	/** @} */
2369
2370
2371	/** @name \#PF Trap Error Codes
2372	* @{
2373	*/
2374	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2375	#define X86_TRAP_PF_P RT_BIT(0)
2376	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2377	#define X86_TRAP_PF_RW RT_BIT(1)
2378	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2379	#define X86_TRAP_PF_US RT_BIT(2)
2380	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2381	#define X86_TRAP_PF_RSVD RT_BIT(3)
2382	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2383	#define X86_TRAP_PF_ID RT_BIT(4)
2384	/** @} */
2385
2386	#pragma pack(1)
2387	/**
2388	* 32-bit IDTR/GDTR.
2389	*/
2390	typedef struct X86XDTR32
2391	{
2392	/** Size of the descriptor table. */
2393	uint16_t cb;
2394	/** Address of the descriptor table. */
2395	uint32_t uAddr;
2396	} X86XDTR32, *PX86XDTR32;
2397	#pragma pack()
2398
2399	#pragma pack(1)
2400	/**
2401	* 64-bit IDTR/GDTR.
2402	*/
2403	typedef struct X86XDTR64
2404	{
2405	/** Size of the descriptor table. */
2406	uint16_t cb;
2407	/** Address of the descriptor table. */
2408	uint64_t uAddr;
2409	} X86XDTR64, *PX86XDTR64;
2410	#pragma pack()
2411
2412	/** @} */
2413
2414	#endif
2415

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source: vbox/trunk/include/VBox/x86.h@ 12936

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