vm.h@ 100184

Last change on this file since 100184 was 100000, checked in by vboxsync, 17 months ago
VMM: Take the vTimer expiration into account when halting due to a WFI/WFE instruction so the guest gets woken up if no other event is pending, bugref:10389
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_vm_h
37	#define VBOX_INCLUDED_vmm_vm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# ifndef USING_VMM_COMMON_DEFS
44	# error "Compile job does not include VMM_COMMON_DEFS from src/VBox/VMM/Config.kmk - make sure you really need to include this file!"
45	# endif
46	# include <iprt/param.h>
47	# include <VBox/param.h>
48	# include <VBox/types.h>
49	# include <VBox/vmm/cpum.h>
50	# include <VBox/vmm/stam.h>
51	# include <VBox/vmm/vmapi.h>
52	# include <VBox/vmm/vmm.h>
53	# include <VBox/sup.h>
54	#else
55	# pragma D depends_on library vbox-types.d
56	# pragma D depends_on library CPUMInternal.d
57	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
58	#endif
59
60
61
62	/** @defgroup grp_vm The Virtual Machine
63	* @ingroup grp_vmm
64	* @{
65	*/
66
67	/**
68	* The state of a Virtual CPU.
69	*
70	* The basic state indicated here is whether the CPU has been started or not. In
71	* addition, there are sub-states when started for assisting scheduling (GVMM
72	* mostly).
73	*
74	* The transition out of the STOPPED state is done by a vmR3PowerOn.
75	* The transition back to the STOPPED state is done by vmR3PowerOff.
76	*
77	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
78	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
79	*/
80	typedef enum VMCPUSTATE
81	{
82	/** The customary invalid zero. */
83	VMCPUSTATE_INVALID = 0,
84
85	/** Virtual CPU has not yet been started. */
86	VMCPUSTATE_STOPPED,
87
88	/** CPU started. */
89	VMCPUSTATE_STARTED,
90	/** CPU started in HM context. */
91	VMCPUSTATE_STARTED_HM,
92	/** Executing guest code and can be poked (RC or STI bits of HM). */
93	VMCPUSTATE_STARTED_EXEC,
94	/** Executing guest code using NEM. */
95	VMCPUSTATE_STARTED_EXEC_NEM,
96	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
97	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
98	/** Halted. */
99	VMCPUSTATE_STARTED_HALTED,
100
101	/** The end of valid virtual CPU states. */
102	VMCPUSTATE_END,
103
104	/** Ensure 32-bit type. */
105	VMCPUSTATE_32BIT_HACK = 0x7fffffff
106	} VMCPUSTATE;
107
108	/** Enables 64-bit FFs. */
109	#define VMCPU_WITH_64_BIT_FFS
110
111
112	/**
113	* The cross context virtual CPU structure.
114	*
115	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
116	*/
117	typedef struct VMCPU
118	{
119	/** @name Volatile per-cpu data.
120	* @{ */
121	/** Per CPU forced action.
122	* See the VMCPU_FF_* \#defines. Updated atomically. */
123	#ifdef VMCPU_WITH_64_BIT_FFS
124	uint64_t volatile fLocalForcedActions;
125	#else
126	uint32_t volatile fLocalForcedActions;
127	uint32_t fForLocalForcedActionsExpansion;
128	#endif
129	/** The CPU state. */
130	VMCPUSTATE volatile enmState;
131
132	#if defined(VBOX_VMM_TARGET_ARMV8)
133	uint32_t u32Alignment0;
134	/** The number of nano seconds when the vTimer of the associated vCPU is supposed to activate
135	* required to get out of a halt (due to wfi/wfe).
136	*
137	* @note This actually should go into TMCPU but this drags in a whole lot of padding changes
138	* and I'm not sure yet whether this will remain in this form anyway.
139	*/
140	uint64_t cNsVTimerActivate;
141	/** Padding up to 64 bytes. */
142	uint8_t abAlignment0[64 - 12 - 8 - 4];
143	#else
144	/** Padding up to 64 bytes. */
145	uint8_t abAlignment0[64 - 12];
146	#endif
147	/** @} */
148
149	/** IEM part.
150	* @remarks This comes first as it allows the use of 8-bit immediates for the
151	* first 64 bytes of the structure, reducing code size a wee bit. */
152	#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h) /* For PDB hacking. */
153	union VMCPUUNIONIEMFULL
154	#else
155	union VMCPUUNIONIEMSTUB
156	#endif
157	{
158	#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h)
159	struct IEMCPU s;
160	#endif
161	uint8_t padding[32832]; /* multiple of 64 */
162	} iem;
163
164	/** @name Static per-cpu data.
165	* (Putting this after IEM, hoping that it's less frequently used than it.)
166	* @{ */
167	/** Ring-3 Host Context VM Pointer. */
168	PVMR3 pVMR3;
169	/** Ring-0 Host Context VM Pointer, currently used by VTG/dtrace. */
170	RTR0PTR pVCpuR0ForVtg;
171	/** Raw-mode Context VM Pointer. */
172	uint32_t pVMRC;
173	/** Padding for new raw-mode (long mode). */
174	uint32_t pVMRCPadding;
175	/** Pointer to the ring-3 UVMCPU structure. */
176	PUVMCPU pUVCpu;
177	/** The native thread handle. */
178	RTNATIVETHREAD hNativeThread;
179	/** The native R0 thread handle. (different from the R3 handle!) */
180	RTNATIVETHREAD hNativeThreadR0;
181	/** The IPRT thread handle (for VMMDevTesting). */
182	RTTHREAD hThread;
183	/** The CPU ID.
184	* This is the index into the VM::aCpu array. */
185	#ifdef IN_RING0
186	VMCPUID idCpuUnsafe;
187	#else
188	VMCPUID idCpu;
189	#endif
190
191	/** Align the structures below bit on a 64-byte boundary and make sure it starts
192	* at the same offset in both 64-bit and 32-bit builds.
193	*
194	* @remarks The alignments of the members that are larger than 48 bytes should be
195	* 64-byte for cache line reasons. structs containing small amounts of
196	* data could be lumped together at the end with a < 64 byte padding
197	* following it (to grow into and align the struct size).
198	*/
199	uint8_t abAlignment1[64 - 6 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4];
200	/** @} */
201
202	/** HM part. */
203	union VMCPUUNIONHM
204	{
205	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
206	struct HMCPU s;
207	#endif
208	uint8_t padding[9984]; /* multiple of 64 */
209	} hm;
210
211	/** NEM part. */
212	union VMCPUUNIONNEM
213	{
214	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
215	struct NEMCPU s;
216	#endif
217	uint8_t padding[4608]; /* multiple of 64 */
218	} nem;
219
220	/** TRPM part. */
221	union VMCPUUNIONTRPM
222	{
223	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
224	struct TRPMCPU s;
225	#endif
226	uint8_t padding[128]; /* multiple of 64 */
227	} trpm;
228
229	/** TM part. */
230	union VMCPUUNIONTM
231	{
232	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
233	struct TMCPU s;
234	#endif
235	uint8_t padding[5760]; /* multiple of 64 */
236	} tm;
237
238	/** VMM part. */
239	union VMCPUUNIONVMM
240	{
241	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
242	struct VMMCPU s;
243	#endif
244	uint8_t padding[9536]; /* multiple of 64 */
245	} vmm;
246
247	/** PDM part. */
248	union VMCPUUNIONPDM
249	{
250	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
251	struct PDMCPU s;
252	#endif
253	uint8_t padding[256]; /* multiple of 64 */
254	} pdm;
255
256	/** IOM part. */
257	union VMCPUUNIONIOM
258	{
259	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
260	struct IOMCPU s;
261	#endif
262	uint8_t padding[512]; /* multiple of 64 */
263	} iom;
264
265	/** DBGF part.
266	* @todo Combine this with other tiny structures. */
267	union VMCPUUNIONDBGF
268	{
269	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
270	struct DBGFCPU s;
271	#endif
272	uint8_t padding[512]; /* multiple of 64 */
273	} dbgf;
274
275	/** GIM part. */
276	union VMCPUUNIONGIM
277	{
278	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
279	struct GIMCPU s;
280	#endif
281	uint8_t padding[512]; /* multiple of 64 */
282	} gim;
283
284	#if defined(VBOX_VMM_TARGET_ARMV8)
285	/** GIC part. */
286	union VMCPUUNIONGIC
287	{
288	# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
289	struct GICCPU s;
290	# endif
291	uint8_t padding[3840]; /* multiple of 64 */
292	} gic;
293	#else
294	/** APIC part. */
295	union VMCPUUNIONAPIC
296	{
297	# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
298	struct APICCPU s;
299	# endif
300	uint8_t padding[3840]; /* multiple of 64 */
301	} apic;
302	#endif
303
304	/*
305	* Some less frequently used global members that doesn't need to take up
306	* precious space at the head of the structure.
307	*/
308
309	/** Trace groups enable flags. */
310	uint32_t fTraceGroups; /* 64 / 44 */
311	/** Number of collisions hashing the ring-0 EMT handle. */
312	uint8_t cEmtHashCollisions;
313	uint8_t abAdHoc[3];
314	/** Profiling samples for use by ad hoc profiling. */
315	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
316
317	/** Align the following members on page boundary. */
318	uint8_t abAlignment2[696];
319
320	/** PGM part. */
321	union VMCPUUNIONPGM
322	{
323	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
324	struct PGMCPU s;
325	#endif
326	uint8_t padding[4096 + 28672]; /* multiple of 4096 */
327	} pgm;
328
329	/** CPUM part. */
330	union VMCPUUNIONCPUM
331	{
332	#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
333	struct CPUMCPU s;
334	#endif
335	#ifdef VMCPU_INCL_CPUM_GST_CTX
336	/** The guest CPUM context for direct use by execution engines.
337	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
338	* others. The rest will use the function based CPUM API. */
339	CPUMCTX GstCtx;
340	#endif
341	uint8_t padding[102400]; /* multiple of 4096 */
342	} cpum;
343
344	/** EM part. */
345	union VMCPUUNIONEM
346	{
347	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
348	struct EMCPU s;
349	#endif
350	uint8_t padding[40960]; /* multiple of 4096 */
351	} em;
352
353	} VMCPU;
354
355
356	#ifndef VBOX_FOR_DTRACE_LIB
357	/* Make sure the structure size is aligned on a 16384 boundary for arm64 purposes. */
358	AssertCompileSizeAlignment(VMCPU, 16384);
359
360	/** @name Operations on VMCPU::enmState
361	* @{ */
362	/** Gets the VMCPU state. */
363	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
364	/** Sets the VMCPU state. */
365	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
366	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
367	/** Cmpares and sets the VMCPU state. */
368	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
369	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
370	/** Checks the VMCPU state. */
371	#ifdef VBOX_STRICT
372	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
373	do { \
374	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
375	AssertMsg(enmState == (enmExpectedState), \
376	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
377	enmState, enmExpectedState, (pVCpu)->idCpu)); \
378	} while (0)
379
380	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) \
381	do { \
382	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
383	AssertMsg( enmState == (enmExpectedState) \
384	\|\| enmState == (a_enmExpectedState2), \
385	("enmState=%d enmExpectedState=%d enmExpectedState2=%d idCpu=%u\n", \
386	enmState, enmExpectedState, a_enmExpectedState2, (pVCpu)->idCpu)); \
387	} while (0)
388	#else
389	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
390	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) do { } while (0)
391	#endif
392	/** Tests if the state means that the CPU is started. */
393	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
394	/** Tests if the state means that the CPU is stopped. */
395	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
396	/** @} */
397
398
399	/** The name of the raw-mode context VMM Core module. */
400	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
401	/** The name of the ring-0 context VMM Core module. */
402	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
403
404
405	/** VM Forced Action Flags.
406	*
407	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
408	* action mask of a VM.
409	*
410	* Available VM bits:
411	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30
412	*
413	*
414	* Available VMCPU bits:
415	* 14, 15, 36 to 63
416	*
417	* @todo If we run low on VMCPU, we may consider merging the SELM bits
418	*
419	* @{
420	*/
421	/** The virtual sync clock has been stopped, go to TM until it has been
422	* restarted... */
423	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
424	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
425	/** PDM Queues are pending. */
426	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
427	/** The bit number for VM_FF_PDM_QUEUES. */
428	#define VM_FF_PDM_QUEUES_BIT 3
429	/** PDM DMA transfers are pending. */
430	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
431	/** The bit number for VM_FF_PDM_DMA. */
432	#define VM_FF_PDM_DMA_BIT 4
433	/** This action forces the VM to call DBGF so DBGF can service debugger
434	* requests in the emulation thread.
435	* This action flag stays asserted till DBGF clears it.*/
436	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
437	/** The bit number for VM_FF_DBGF. */
438	#define VM_FF_DBGF_BIT 8
439	/** This action forces the VM to service pending requests from other
440	* thread or requests which must be executed in another context. */
441	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
442	#define VM_FF_REQUEST_BIT 9
443	/** Check for VM state changes and take appropriate action. */
444	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
445	/** The bit number for VM_FF_CHECK_VM_STATE. */
446	#define VM_FF_CHECK_VM_STATE_BIT 10
447	/** Reset the VM. (postponed) */
448	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
449	/** The bit number for VM_FF_RESET. */
450	#define VM_FF_RESET_BIT 11
451	/** EMT rendezvous in VMM. */
452	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
453	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
454	#define VM_FF_EMT_RENDEZVOUS_BIT 12
455
456	/** PGM needs to allocate handy pages. */
457	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
458	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
459	/** PGM is out of memory.
460	* Abandon all loops and code paths which can be resumed and get up to the EM
461	* loops. */
462	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
463	#define VM_FF_PGM_NO_MEMORY_BIT 19
464	/** PGM is about to perform a lightweight pool flush
465	* Guest SMP: all EMT threads should return to ring 3
466	*/
467	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
468	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
469	/** Suspend the VM - debug only. */
470	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
471	#define VM_FF_DEBUG_SUSPEND_BIT 31
472
473
474	#if defined(VBOX_VMM_TARGET_ARMV8)
475	/** This action forces the VM to inject an IRQ into the guest. */
476	# define VMCPU_FF_INTERRUPT_IRQ RT_BIT_64(VMCPU_FF_INTERRUPT_IRQ_BIT)
477	# define VMCPU_FF_INTERRUPT_IRQ_BIT 0
478	/** This action forces the VM to inject an FIQ into the guest. */
479	# define VMCPU_FF_INTERRUPT_FIQ RT_BIT_64(VMCPU_FF_INTERRUPT_FIQ_BIT)
480	# define VMCPU_FF_INTERRUPT_FIQ_BIT 1
481	#else
482	/** This action forces the VM to check any pending interrupts on the APIC. */
483	# define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
484	# define VMCPU_FF_INTERRUPT_APIC_BIT 0
485	/** This action forces the VM to check any pending interrups on the PIC. */
486	# define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
487	# define VMCPU_FF_INTERRUPT_PIC_BIT 1
488	#endif
489	/** This action forces the VM to schedule and run pending timer (TM).
490	* @remarks Don't move - PATM compatibility. */
491	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
492	#define VMCPU_FF_TIMER_BIT 2
493	/** This action forces the VM to check any pending NMIs. */
494	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
495	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
496	/** This action forces the VM to check any pending SMIs. */
497	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
498	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
499	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
500	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
501	#define VMCPU_FF_PDM_CRITSECT_BIT 5
502	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
503	* the virtual CPU out of the next (/current) halted state. It is not processed
504	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
505	* is cleared the next time EM leaves the HALTED state. */
506	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
507	#define VMCPU_FF_UNHALT_BIT 6
508	/** Pending IEM action (mask). */
509	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
510	/** Pending IEM action (bit number). */
511	#define VMCPU_FF_IEM_BIT 7
512	/** Pending APIC action (bit number). */
513	#define VMCPU_FF_UPDATE_APIC_BIT 8
514	/** This action forces the VM to update APIC's asynchronously arrived
515	* interrupts as pending interrupts. */
516	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
517	/** This action forces the VM to service pending requests from other
518	* thread or requests which must be executed in another context. */
519	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
520	#define VMCPU_FF_REQUEST_BIT 9
521	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
522	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
523	/** The bit number for VMCPU_FF_DBGF. */
524	#define VMCPU_FF_DBGF_BIT 10
525	/** Hardware virtualized nested-guest interrupt pending. */
526	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
527	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
528	/** This action forces PGM to update changes to CR3 when the guest was in HM mode
529	* (when using nested paging). */
530	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
531	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
532	#if defined(VBOX_VMM_TARGET_ARMV8)
533	# define VMCPU_FF_VTIMER_ACTIVATED RT_BIT_64(VMCPU_FF_VTIMER_ACTIVATED_BIT)
534	# define VMCPU_FF_VTIMER_ACTIVATED_BIT 13
535	#else
536	/* Bit 13 used to be VMCPU_FF_HM_UPDATE_PAE_PDPES. */
537	#endif
538	/** This action forces the VM to resync the page tables before going
539	* back to execute guest code. (GLOBAL FLUSH) */
540	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
541	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
542	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
543	* (NON-GLOBAL FLUSH) */
544	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
545	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
546	/** Check for pending TLB shootdown actions (deprecated)
547	* Reserved for future HM re-use if necessary / safe.
548	* Consumer: HM */
549	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
550	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
551	/** Check for pending TLB flush action.
552	* Consumer: HM
553	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
554	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
555	/** The bit number for VMCPU_FF_TLB_FLUSH. */
556	#define VMCPU_FF_TLB_FLUSH_BIT 19
557	/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
558	/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
559	/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
560	/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
561	/* 24 used to be VMCPU_FF_INHIBIT_INTERRUPTS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
562	/* 25 used to be VMCPU_FF_BLOCK_NMIS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
563	/** Force return to Ring-3. */
564	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
565	#define VMCPU_FF_TO_R3_BIT 28
566	/** Force return to ring-3 to service pending I/O or MMIO write.
567	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
568	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
569	* status codes to be propagated at the same time without loss. */
570	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
571	#define VMCPU_FF_IOM_BIT 29
572	/* 30 used to be VMCPU_FF_CPUM */
573	/** VMX-preemption timer expired. */
574	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
575	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
576	/** Pending MTF (Monitor Trap Flag) event. */
577	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
578	#define VMCPU_FF_VMX_MTF_BIT 32
579	/** VMX APIC-write emulation pending.
580	* @todo possible candidate for internal EFLAGS, or maybe just a summary bit
581	* (see also VMCPU_FF_VMX_INT_WINDOW). */
582	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
583	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
584	/** VMX interrupt-window event pending.
585	*
586	* "Pending" is misleading here, it would be better to say that the event need
587	* to be generated at the next opportunity and that this flag causes it to be
588	* polled for on every instruction boundrary and such.
589	*
590	* @todo Change the IEM side of this to not poll but to track down the places
591	* where it can be generated and set an internal EFLAGS bit that causes it
592	* to be checked out when finishing the current instruction. */
593	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
594	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
595	/** VMX NMI-window event pending.
596	* Same "pending" comment and todo in VMCPU_FF_VMX_INT_WINDOW. */
597	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
598	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
599
600
601	/** Externally VM forced actions. Used to quit the idle/wait loop. */
602	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
603	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
604	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
605
606	/** Externally forced VM actions. Used to quit the idle/wait loop. */
607	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
608	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
609	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
610	#if defined(VBOX_VMM_TARGET_ARMV8)
611	# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ \
612	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
613	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
614	\| VMCPU_FF_VTIMER_ACTIVATED)
615	#else
616	# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
617	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
618	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
619	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
620	#endif
621
622	/** High priority VM pre-execution actions. */
623	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
624	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
625	\| VM_FF_EMT_RENDEZVOUS )
626	/** High priority VMCPU pre-execution actions. */
627	#if defined(VBOX_VMM_TARGET_ARMV8)
628	# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ \
629	\| VMCPU_FF_DBGF )
630	#else
631	# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
632	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_DBGF \
633	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
634	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
635	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW )
636	#endif
637
638	/** High priority VM pre raw-mode execution mask. */
639	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
640	/** High priority VMCPU pre raw-mode execution mask. */
641	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
642
643	/** High priority post-execution actions. */
644	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
645	/** High priority post-execution actions. */
646	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM )
647
648	/** Normal priority VM post-execution actions. */
649	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
650	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
651	/** Normal priority VMCPU post-execution actions. */
652	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
653
654	/** Normal priority VM actions. */
655	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
656	/** Normal priority VMCPU actions. */
657	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
658
659	/** Flags to clear before resuming guest execution. */
660	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
661
662
663	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
664	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
665	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
666	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
667	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
668	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
669	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
670	#ifdef IN_RING3
671	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \
672	\| VMCPU_FF_VMX_MTF )
673	#else
674	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
675	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF )
676	#endif
677
678	#if !defined(VBOX_VMM_TARGET_ARMV8)
679	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
680	* enabled. */
681	# define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
682	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
683	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
684	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
685	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
686	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
687	* disabled. */
688	# define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
689	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
690	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
691	#endif
692
693	/** VM Flags that cause the HM loops to go back to ring-3. */
694	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
695	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
696	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
697	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
698	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
699
700	/** High priority ring-0 VM pre HM-mode execution mask. */
701	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
702	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
703	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
704	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST \
705	\| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_PREEMPT_TIMER)
706	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
707	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
708	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
709	\| VM_FF_PDM_DMA) )
710	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
711	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
712	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
713
714	/** All the VMX nested-guest flags. */
715	#define VMCPU_FF_VMX_ALL_MASK ( VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
716	\| VMCPU_FF_VMX_INT_WINDOW \| VMCPU_FF_VMX_NMI_WINDOW )
717
718	/** All the forced VM flags. */
719	#define VM_FF_ALL_MASK (UINT32_MAX)
720	/** All the forced VMCPU flags. */
721	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
722
723	/** All the forced VM flags except those related to raw-mode and hardware
724	* assisted execution. */
725	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
726	/** All the forced VMCPU flags except those related to raw-mode and hardware
727	* assisted execution. */
728	#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_TLB_FLUSH))
729	/** @} */
730
731	/** @def VM_FF_SET
732	* Sets a single force action flag.
733	*
734	* @param pVM The cross context VM structure.
735	* @param fFlag The flag to set.
736	*/
737	#define VM_FF_SET(pVM, fFlag) do { \
738	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
739	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
740	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
741	} while (0)
742
743	/** @def VMCPU_FF_SET
744	* Sets a single force action flag for the given VCPU.
745	*
746	* @param pVCpu The cross context virtual CPU structure.
747	* @param fFlag The flag to set.
748	* @sa VMCPU_FF_SET_MASK
749	*/
750	#ifdef VMCPU_WITH_64_BIT_FFS
751	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
752	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
753	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
754	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
755	} while (0)
756	#else
757	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
758	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
759	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
760	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
761	} while (0)
762	#endif
763
764	/** @def VMCPU_FF_SET_MASK
765	* Sets a two or more force action flag for the given VCPU.
766	*
767	* @param pVCpu The cross context virtual CPU structure.
768	* @param fFlags The flags to set.
769	* @sa VMCPU_FF_SET
770	*/
771	#ifdef VMCPU_WITH_64_BIT_FFS
772	# if ARCH_BITS > 32
773	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
774	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
775	# else
776	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
777	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
778	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
779	} while (0)
780	# endif
781	#else
782	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
783	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
784	#endif
785
786	/** @def VM_FF_CLEAR
787	* Clears a single force action flag.
788	*
789	* @param pVM The cross context VM structure.
790	* @param fFlag The flag to clear.
791	*/
792	#define VM_FF_CLEAR(pVM, fFlag) do { \
793	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
794	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
795	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
796	} while (0)
797
798	/** @def VMCPU_FF_CLEAR
799	* Clears a single force action flag for the given VCPU.
800	*
801	* @param pVCpu The cross context virtual CPU structure.
802	* @param fFlag The flag to clear.
803	*/
804	#ifdef VMCPU_WITH_64_BIT_FFS
805	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
806	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
807	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
808	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
809	} while (0)
810	#else
811	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
812	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
813	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
814	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
815	} while (0)
816	#endif
817
818	/** @def VMCPU_FF_CLEAR_MASK
819	* Clears two or more force action flags for the given VCPU.
820	*
821	* @param pVCpu The cross context virtual CPU structure.
822	* @param fFlags The flags to clear.
823	*/
824	#ifdef VMCPU_WITH_64_BIT_FFS
825	# if ARCH_BITS > 32
826	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
827	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
828	# else
829	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
830	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
831	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
832	} while (0)
833	# endif
834	#else
835	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
836	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
837	#endif
838
839	/** @def VM_FF_IS_SET
840	* Checks if single a force action flag is set.
841	*
842	* @param pVM The cross context VM structure.
843	* @param fFlag The flag to check.
844	* @sa VM_FF_IS_ANY_SET
845	*/
846	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
847	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
848	#else
849	# define VM_FF_IS_SET(pVM, fFlag) \
850	([](PVM a_pVM) -> bool \
851	{ \
852	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
853	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
854	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
855	}(pVM))
856	#endif
857
858	/** @def VMCPU_FF_IS_SET
859	* Checks if a single force action flag is set for the given VCPU.
860	*
861	* @param pVCpu The cross context virtual CPU structure.
862	* @param fFlag The flag to check.
863	* @sa VMCPU_FF_IS_ANY_SET
864	*/
865	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
866	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
867	#else
868	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
869	([](PCVMCPU a_pVCpu) -> bool \
870	{ \
871	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
872	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
873	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
874	}(pVCpu))
875	#endif
876
877	/** @def VM_FF_IS_ANY_SET
878	* Checks if one or more force action in the specified set is pending.
879	*
880	* @param pVM The cross context VM structure.
881	* @param fFlags The flags to check for.
882	* @sa VM_FF_IS_SET
883	*/
884	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
885
886	/** @def VMCPU_FF_IS_ANY_SET
887	* Checks if two or more force action flags in the specified set is set for the given VCPU.
888	*
889	* @param pVCpu The cross context virtual CPU structure.
890	* @param fFlags The flags to check for.
891	* @sa VMCPU_FF_IS_SET
892	*/
893	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
894
895	/** @def VM_FF_TEST_AND_CLEAR
896	* Checks if one (!) force action in the specified set is pending and clears it atomically
897	*
898	* @returns true if the bit was set.
899	* @returns false if the bit was clear.
900	* @param pVM The cross context VM structure.
901	* @param fFlag Flag constant to check and clear (_BIT is appended).
902	*/
903	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
904
905	/** @def VMCPU_FF_TEST_AND_CLEAR
906	* Checks if one (!) force action in the specified set is pending and clears it atomically
907	*
908	* @returns true if the bit was set.
909	* @returns false if the bit was clear.
910	* @param pVCpu The cross context virtual CPU structure.
911	* @param fFlag Flag constant to check and clear (_BIT is appended).
912	*/
913	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
914
915	/** @def VM_FF_IS_PENDING_EXCEPT
916	* Checks if one or more force action in the specified set is pending while one
917	* or more other ones are not.
918	*
919	* @param pVM The cross context VM structure.
920	* @param fFlags The flags to check for.
921	* @param fExcpt The flags that should not be set.
922	*/
923	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
924	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
925
926	/** @def VM_IS_EMT
927	* Checks if the current thread is the emulation thread (EMT).
928	*
929	* @remark The ring-0 variation will need attention if we expand the ring-0
930	* code to let threads other than EMT mess around with the VM.
931	*/
932	#ifdef IN_RC
933	# define VM_IS_EMT(pVM) true
934	#else
935	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
936	#endif
937
938	/** @def VMCPU_IS_EMT
939	* Checks if the current thread is the emulation thread (EMT) for the specified
940	* virtual CPU.
941	*/
942	#ifdef IN_RC
943	# define VMCPU_IS_EMT(pVCpu) true
944	#else
945	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
946	#endif
947
948	/** @def VM_ASSERT_EMT
949	* Asserts that the current thread IS the emulation thread (EMT).
950	*/
951	#ifdef IN_RC
952	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
953	#elif defined(IN_RING0)
954	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
955	#else
956	# define VM_ASSERT_EMT(pVM) \
957	AssertMsg(VM_IS_EMT(pVM), \
958	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
959	#endif
960
961	/** @def VMCPU_ASSERT_EMT
962	* Asserts that the current thread IS the emulation thread (EMT) of the
963	* specified virtual CPU.
964	*/
965	#ifdef IN_RC
966	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
967	#elif defined(IN_RING0)
968	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
969	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
970	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
971	(pVCpu) ? (pVCpu)->idCpu : 0))
972	#else
973	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
974	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
975	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
976	#endif
977
978	/** @def VM_ASSERT_EMT_RETURN
979	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
980	*/
981	#ifdef IN_RC
982	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
983	#elif defined(IN_RING0)
984	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
985	#else
986	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
987	AssertMsgReturn(VM_IS_EMT(pVM), \
988	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
989	(rc))
990	#endif
991
992	/** @def VMCPU_ASSERT_EMT_RETURN
993	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
994	*/
995	#ifdef IN_RC
996	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
997	#elif defined(IN_RING0)
998	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
999	#else
1000	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
1001	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
1002	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1003	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
1004	(rc))
1005	#endif
1006
1007	/** @def VMCPU_ASSERT_EMT_OR_GURU
1008	* Asserts that the current thread IS the emulation thread (EMT) of the
1009	* specified virtual CPU.
1010	*/
1011	#if defined(IN_RC) \|\| defined(IN_RING0)
1012	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
1013	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1014	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
1015	#else
1016	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
1017	AssertMsg( VMCPU_IS_EMT(pVCpu) \
1018	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1019	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
1020	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1021	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1022	#endif
1023
1024	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
1025	* Asserts that the current thread IS the emulation thread (EMT) of the
1026	* specified virtual CPU or the VM is not running.
1027	*/
1028	#if defined(IN_RC) \|\| defined(IN_RING0)
1029	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1030	Assert( VMCPU_IS_EMT(pVCpu) \
1031	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
1032	#else
1033	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1034	AssertMsg( VMCPU_IS_EMT(pVCpu) \
1035	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
1036	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1037	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1038	#endif
1039
1040	/** @def VMSTATE_IS_RUNNING
1041	* Checks if the given state indicates a running VM.
1042	*/
1043	#define VMSTATE_IS_RUNNING(a_enmVMState) \
1044	( (a_enmVMState) == VMSTATE_RUNNING \
1045	\|\| (a_enmVMState) == VMSTATE_RUNNING_LS )
1046
1047	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
1048	* Checks if the VM is running.
1049	* @note This is only for pure debug assertions. No AssertReturn or similar!
1050	* @sa VMSTATE_IS_RUNNING
1051	*/
1052	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1053	( (pVM)->enmVMState == VMSTATE_RUNNING \
1054	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS )
1055
1056
1057	/** @def VMSTATE_IS_POWERED_ON
1058	* Checks if the given state indicates the VM is powered on.
1059	*
1060	* @note Excludes all error states, so a powered on VM that hit a fatal error,
1061	* guru meditation, state load failure or similar will not be considered
1062	* powered on by this test.
1063	*/
1064	#define VMSTATE_IS_POWERED_ON(a_enmVMState) \
1065	( (a_enmVMState) >= VMSTATE_RESUMING && (a_enmVMState) < VMSTATE_POWERING_OFF )
1066
1067	/** @def VM_ASSERT_IS_NOT_RUNNING
1068	* Asserts that the VM is not running.
1069	*/
1070	#if defined(IN_RC) \|\| defined(IN_RING0)
1071	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1072	#else
1073	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1074	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1075	#endif
1076
1077	/** @def VM_ASSERT_EMT0
1078	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1079	*/
1080	#ifdef IN_RING3
1081	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
1082	#else
1083	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1084	#endif
1085
1086	/** @def VM_ASSERT_EMT0_RETURN
1087	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1088	* it isn't.
1089	*/
1090	#ifdef IN_RING3
1091	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN((pVM)->apCpusR3[0], (rc))
1092	#else
1093	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1094	#endif
1095
1096
1097	/**
1098	* Asserts that the current thread is NOT the emulation thread.
1099	*/
1100	#define VM_ASSERT_OTHER_THREAD(pVM) \
1101	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1102
1103
1104	/** @def VM_ASSERT_STATE
1105	* Asserts a certain VM state.
1106	*/
1107	#define VM_ASSERT_STATE(pVM, _enmState) \
1108	AssertMsg((pVM)->enmVMState == (_enmState), \
1109	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1110
1111	/** @def VM_ASSERT_STATE_RETURN
1112	* Asserts a certain VM state and returns if it doesn't match.
1113	*/
1114	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1115	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1116	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1117	(rc))
1118
1119	/** @def VM_IS_VALID_EXT
1120	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1121	* or terminated. */
1122	#define VM_IS_VALID_EXT(pVM) \
1123	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1124	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1125	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1126	&& VM_IS_EMT(pVM))) )
1127
1128	/** @def VM_ASSERT_VALID_EXT_RETURN
1129	* Asserts a the VM handle is valid for external access, i.e. not being
1130	* destroy or terminated.
1131	*/
1132	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1133	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1134	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1135	? VMGetStateName(pVM->enmVMState) : ""), \
1136	(rc))
1137
1138	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1139	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1140	* destroy or terminated.
1141	*/
1142	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1143	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1144	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1145	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1146	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1147	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1148	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1149	(rc))
1150
1151	#endif /* !VBOX_FOR_DTRACE_LIB */
1152
1153
1154	/**
1155	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1156	*
1157	* ONLY HM and NEM MAY USE THIS!
1158	*
1159	* @param a_pVM The cross context VM structure.
1160	* @param a_bValue The new value.
1161	* @internal
1162	*/
1163	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1164	do { \
1165	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1166	ASMCompilerBarrier(); /* just to be on the safe side */ \
1167	} while (0)
1168
1169	/**
1170	* Checks whether iem-executes-all-mode is used.
1171	*
1172	* @retval true if IEM is used.
1173	* @retval false if not.
1174	*
1175	* @param a_pVM The cross context VM structure.
1176	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1177	* @internal
1178	*/
1179	#define VM_IS_EXEC_ENGINE_IEM(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_IEM)
1180
1181	/**
1182	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1183	*
1184	* @retval true if either is used.
1185	* @retval false if software virtualization (raw-mode) is used.
1186	*
1187	* @param a_pVM The cross context VM structure.
1188	* @sa VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1189	* @internal
1190	*/
1191	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_IEM)
1192
1193	/**
1194	* Checks whether HM is being used by this VM.
1195	*
1196	* @retval true if HM (VT-x/AMD-v) is used.
1197	* @retval false if not.
1198	*
1199	* @param a_pVM The cross context VM structure.
1200	* @sa VM_IS_NEM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1201	* @internal
1202	*/
1203	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1204
1205	/**
1206	* Checks whether NEM is being used by this VM.
1207	*
1208	* @retval true if a native hypervisor API is used.
1209	* @retval false if not.
1210	*
1211	* @param a_pVM The cross context VM structure.
1212	* @sa VM_IS_HM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1213	* @internal
1214	*/
1215	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1216
1217
1218	/**
1219	* The cross context VM structure.
1220	*
1221	* It contains all the VM data which have to be available in all contexts.
1222	* Even if it contains all the data the idea is to use APIs not to modify all
1223	* the members all around the place. Therefore we make use of unions to hide
1224	* everything which isn't local to the current source module. This means we'll
1225	* have to pay a little bit of attention when adding new members to structures
1226	* in the unions and make sure to keep the padding sizes up to date.
1227	*
1228	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1229	*/
1230	typedef struct VM
1231	{
1232	/** The state of the VM.
1233	* This field is read only to everyone except the VM and EM. */
1234	VMSTATE volatile enmVMState;
1235	/** Forced action flags.
1236	* See the VM_FF_* \#defines. Updated atomically.
1237	*/
1238	volatile uint32_t fGlobalForcedActions;
1239	/** Pointer to the array of page descriptors for the VM structure allocation. */
1240	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1241	/** Session handle. For use when calling SUPR0 APIs. */
1242	#ifdef IN_RING0
1243	PSUPDRVSESSION pSessionUnsafe;
1244	#else
1245	PSUPDRVSESSION pSession;
1246	#endif
1247	/** Pointer to the ring-3 VM structure. */
1248	PUVM pUVM;
1249	/** Ring-3 Host Context VM Pointer. */
1250	#ifdef IN_RING0
1251	R3PTRTYPE(struct VM *) pVMR3Unsafe;
1252	#else
1253	R3PTRTYPE(struct VM *) pVMR3;
1254	#endif
1255	/** Ring-0 Host Context VM pointer for making ring-0 calls. */
1256	R0PTRTYPE(struct VM *) pVMR0ForCall;
1257	/** Raw-mode Context VM Pointer. */
1258	uint32_t pVMRC;
1259	/** Padding for new raw-mode (long mode). */
1260	uint32_t pVMRCPadding;
1261
1262	/** The GVM VM handle. Only the GVM should modify this field. */
1263	#ifdef IN_RING0
1264	uint32_t hSelfUnsafe;
1265	#else
1266	uint32_t hSelf;
1267	#endif
1268	/** Number of virtual CPUs. */
1269	#ifdef IN_RING0
1270	uint32_t cCpusUnsafe;
1271	#else
1272	uint32_t cCpus;
1273	#endif
1274	/** CPU excution cap (1-100) */
1275	uint32_t uCpuExecutionCap;
1276
1277	/** Size of the VM structure. */
1278	uint32_t cbSelf;
1279	/** Size of the VMCPU structure. */
1280	uint32_t cbVCpu;
1281	/** Structure version number (TBD). */
1282	uint32_t uStructVersion;
1283
1284	/** @name Various items that are frequently accessed.
1285	* @{ */
1286	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1287	* This is set early during vmR3InitRing3 by HM or NEM. */
1288	uint8_t const bMainExecutionEngine;
1289
1290	/** Hardware VM support is available and enabled.
1291	* Determined very early during init.
1292	* This is placed here for performance reasons.
1293	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1294	bool fHMEnabled;
1295	/** @} */
1296
1297	/** Alignment padding. */
1298	uint8_t uPadding1[6];
1299
1300	/** @name Debugging
1301	* @{ */
1302	/** Ring-3 Host Context VM Pointer. */
1303	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1304	/** Ring-0 Host Context VM Pointer. */
1305	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1306	/** @} */
1307
1308	/** Max EMT hash lookup collisions (in GVMM). */
1309	uint8_t cMaxEmtHashCollisions;
1310
1311	/** Padding - the unions must be aligned on a 64 bytes boundary. */
1312	uint8_t abAlignment3[HC_ARCH_BITS == 64 ? 23 : 51];
1313
1314	/** CPUM part. */
1315	union
1316	{
1317	#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
1318	struct CPUM s;
1319	#endif
1320	#ifdef VBOX_INCLUDED_vmm_cpum_h
1321	/** Read only info exposed about the host and guest CPUs. */
1322	struct
1323	{
1324	/** Padding for hidden fields. */
1325	uint8_t abHidden0[64 + 48];
1326	/** Guest CPU feature information. */
1327	CPUMFEATURES GuestFeatures;
1328	} const ro;
1329	#endif
1330	/** @todo this is rather bloated because of static MSR range allocation.
1331	* Probably a good idea to move it to a separate R0 allocation... */
1332	uint8_t padding[8832 + 1288192 + 0x1d00]; / multiple of 64 */
1333	} cpum;
1334
1335	/** PGM part.
1336	* @note 16384 aligned for zero and mmio page storage. */
1337	union
1338	{
1339	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1340	struct PGM s;
1341	#endif
1342	uint8_t padding[53888]; /* multiple of 64 */
1343	} pgm;
1344
1345	/** VMM part. */
1346	union
1347	{
1348	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1349	struct VMM s;
1350	#endif
1351	uint8_t padding[1600]; /* multiple of 64 */
1352	} vmm;
1353
1354	/** HM part. */
1355	union
1356	{
1357	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1358	struct HM s;
1359	#endif
1360	uint8_t padding[5504]; /* multiple of 64 */
1361	} hm;
1362
1363	/** TRPM part. */
1364	union
1365	{
1366	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1367	struct TRPM s;
1368	#endif
1369	uint8_t padding[2048]; /* multiple of 64 */
1370	} trpm;
1371
1372	/** SELM part. */
1373	union
1374	{
1375	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1376	struct SELM s;
1377	#endif
1378	uint8_t padding[768]; /* multiple of 64 */
1379	} selm;
1380
1381	/** MM part. */
1382	union
1383	{
1384	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1385	struct MM s;
1386	#endif
1387	uint8_t padding[192]; /* multiple of 64 */
1388	} mm;
1389
1390	/** PDM part. */
1391	union
1392	{
1393	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1394	struct PDM s;
1395	#endif
1396	uint8_t padding[22400]; /* multiple of 64 */
1397	} pdm;
1398
1399	/** IOM part. */
1400	union
1401	{
1402	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1403	struct IOM s;
1404	#endif
1405	uint8_t padding[1152]; /* multiple of 64 */
1406	} iom;
1407
1408	/** EM part. */
1409	union
1410	{
1411	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1412	struct EM s;
1413	#endif
1414	uint8_t padding[256]; /* multiple of 64 */
1415	} em;
1416
1417	/** NEM part. */
1418	union
1419	{
1420	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1421	struct NEM s;
1422	#endif
1423	uint8_t padding[4608]; /* multiple of 64 */
1424	} nem;
1425
1426	/** TM part. */
1427	union
1428	{
1429	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1430	struct TM s;
1431	#endif
1432	uint8_t padding[10112]; /* multiple of 64 */
1433	} tm;
1434
1435	/** DBGF part. */
1436	union
1437	{
1438	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1439	struct DBGF s;
1440	#endif
1441	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1442	/** Read only info exposed about interrupt breakpoints and selected events. */
1443	struct
1444	{
1445	/** Bitmap of enabled hardware interrupt breakpoints. */
1446	uint32_t bmHardIntBreakpoints[256 / 32];
1447	/** Bitmap of enabled software interrupt breakpoints. */
1448	uint32_t bmSoftIntBreakpoints[256 / 32];
1449	/** Bitmap of selected events.
1450	* This includes non-selectable events too for simplicity, we maintain the
1451	* state for some of these, as it may come in handy. */
1452	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1453	/** Enabled hardware interrupt breakpoints. */
1454	uint32_t cHardIntBreakpoints;
1455	/** Enabled software interrupt breakpoints. */
1456	uint32_t cSoftIntBreakpoints;
1457	/** The number of selected events. */
1458	uint32_t cSelectedEvents;
1459	/** The number of enabled hardware breakpoints. */
1460	uint8_t cEnabledHwBreakpoints;
1461	/** The number of enabled hardware I/O breakpoints. */
1462	uint8_t cEnabledHwIoBreakpoints;
1463	uint8_t au8Alignment1[2]; /*< Alignment padding. /
1464	/** The number of enabled INT3 breakpoints. */
1465	uint32_t volatile cEnabledInt3Breakpoints;
1466	} const ro;
1467	#endif
1468	uint8_t padding[2432]; /* multiple of 64 */
1469	} dbgf;
1470
1471	/** SSM part. */
1472	union
1473	{
1474	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1475	struct SSM s;
1476	#endif
1477	uint8_t padding[128]; /* multiple of 64 */
1478	} ssm;
1479
1480	union
1481	{
1482	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1483	struct GIM s;
1484	#endif
1485	uint8_t padding[448]; /* multiple of 64 */
1486	} gim;
1487
1488	#if defined(VBOX_VMM_TARGET_ARMV8)
1489	union
1490	{
1491	# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
1492	struct GIC s;
1493	# endif
1494	uint8_t padding[128]; /* multiple of 8 */
1495	} gic;
1496	#else
1497	union
1498	{
1499	# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1500	struct APIC s;
1501	# endif
1502	uint8_t padding[128]; /* multiple of 8 */
1503	} apic;
1504	#endif
1505
1506	/* ---- begin small stuff ---- */
1507
1508	/** VM part. */
1509	union
1510	{
1511	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1512	struct VMINT s;
1513	#endif
1514	uint8_t padding[32]; /* multiple of 8 */
1515	} vm;
1516
1517	/** CFGM part. */
1518	union
1519	{
1520	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1521	struct CFGM s;
1522	#endif
1523	uint8_t padding[8]; /* multiple of 8 */
1524	} cfgm;
1525
1526	/** IEM part. */
1527	union
1528	{
1529	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
1530	struct IEM s;
1531	#endif
1532	uint8_t padding[16]; /* multiple of 8 */
1533	} iem;
1534
1535	/** Statistics for ring-0 only components. */
1536	struct
1537	{
1538	/** GMMR0 stats. */
1539	struct
1540	{
1541	/** Chunk TLB hits. */
1542	uint64_t cChunkTlbHits;
1543	/** Chunk TLB misses. */
1544	uint64_t cChunkTlbMisses;
1545	} gmm;
1546	uint64_t au64Padding[6]; /* probably more comming here... */
1547	} R0Stats;
1548
1549	union
1550	{
1551	#ifdef VMM_INCLUDED_SRC_include_GCMInternal_h
1552	struct GCM s;
1553	#endif
1554	uint8_t padding[32]; /* multiple of 8 */
1555	} gcm;
1556
1557	/** Padding for aligning the structure size on a page boundrary. */
1558	uint8_t abAlignment2[8872 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1559
1560	/* ---- end small stuff ---- */
1561
1562	/** Array of VMCPU ring-3 pointers. */
1563	PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1564
1565	/* This point is aligned on a 16384 boundrary (for arm64 purposes). */
1566	} VM;
1567	#ifndef VBOX_FOR_DTRACE_LIB
1568	//AssertCompileSizeAlignment(VM, 16384);
1569	#endif
1570
1571
1572	#ifdef IN_RC
1573	RT_C_DECLS_BEGIN
1574
1575	/** The VM structure.
1576	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1577	* globals which we should avoid using.
1578	*/
1579	extern DECLIMPORT(VM) g_VM;
1580
1581	/** The VMCPU structure for virtual CPU \#0.
1582	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1583	* globals which we should avoid using.
1584	*/
1585	extern DECLIMPORT(VMCPU) g_VCpu0;
1586
1587	RT_C_DECLS_END
1588	#endif
1589
1590	/** @} */
1591
1592	#endif /* !VBOX_INCLUDED_vmm_vm_h */
1593

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source: vbox/trunk/include/VBox/vmm/vm.h@ 100184

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