vm.h@ 93963

Last change on this file since 93963 was 93901, checked in by vboxsync, 3 years ago
VMM,Main,++: Removed VM_IS_RAW_MODE_ENABLED/VM_EXEC_ENGINE_RAW_MODE and added VM_IS_EXEC_ENGINE_IEM/VM_EXEC_ENGINE_IEM instead. In IMachineDebugger::getExecutionEngine VMExecutionEngine_RawMode was removed and VMExecutionEngine_Emulated added. Removed dead code and updated frontends accordingly. On darwin.arm64 HM now falls back on IEM execution since neither HM or NEM is availble there. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 57.3 KB

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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_vm_h
27	#define VBOX_INCLUDED_vmm_vm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#ifndef VBOX_FOR_DTRACE_LIB
33	# ifndef USING_VMM_COMMON_DEFS
34	# error "Compile job does not include VMM_COMMON_DEFS from src/VBox/VMM/Config.kmk - make sure you really need to include this file!"
35	# endif
36	# include <iprt/param.h>
37	# include <VBox/param.h>
38	# include <VBox/types.h>
39	# include <VBox/vmm/cpum.h>
40	# include <VBox/vmm/stam.h>
41	# include <VBox/vmm/vmapi.h>
42	# include <VBox/vmm/vmm.h>
43	# include <VBox/sup.h>
44	#else
45	# pragma D depends_on library vbox-types.d
46	# pragma D depends_on library CPUMInternal.d
47	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
48	#endif
49
50
51
52	/** @defgroup grp_vm The Virtual Machine
53	* @ingroup grp_vmm
54	* @{
55	*/
56
57	/**
58	* The state of a Virtual CPU.
59	*
60	* The basic state indicated here is whether the CPU has been started or not. In
61	* addition, there are sub-states when started for assisting scheduling (GVMM
62	* mostly).
63	*
64	* The transition out of the STOPPED state is done by a vmR3PowerOn.
65	* The transition back to the STOPPED state is done by vmR3PowerOff.
66	*
67	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
68	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
69	*/
70	typedef enum VMCPUSTATE
71	{
72	/** The customary invalid zero. */
73	VMCPUSTATE_INVALID = 0,
74
75	/** Virtual CPU has not yet been started. */
76	VMCPUSTATE_STOPPED,
77
78	/** CPU started. */
79	VMCPUSTATE_STARTED,
80	/** CPU started in HM context. */
81	VMCPUSTATE_STARTED_HM,
82	/** Executing guest code and can be poked (RC or STI bits of HM). */
83	VMCPUSTATE_STARTED_EXEC,
84	/** Executing guest code using NEM. */
85	VMCPUSTATE_STARTED_EXEC_NEM,
86	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
87	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
88	/** Halted. */
89	VMCPUSTATE_STARTED_HALTED,
90
91	/** The end of valid virtual CPU states. */
92	VMCPUSTATE_END,
93
94	/** Ensure 32-bit type. */
95	VMCPUSTATE_32BIT_HACK = 0x7fffffff
96	} VMCPUSTATE;
97
98	/** Enables 64-bit FFs. */
99	#define VMCPU_WITH_64_BIT_FFS
100
101
102	/**
103	* The cross context virtual CPU structure.
104	*
105	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
106	*/
107	typedef struct VMCPU
108	{
109	/** @name Volatile per-cpu data.
110	* @{ */
111	/** Per CPU forced action.
112	* See the VMCPU_FF_* \#defines. Updated atomically. */
113	#ifdef VMCPU_WITH_64_BIT_FFS
114	uint64_t volatile fLocalForcedActions;
115	#else
116	uint32_t volatile fLocalForcedActions;
117	uint32_t fForLocalForcedActionsExpansion;
118	#endif
119	/** The CPU state. */
120	VMCPUSTATE volatile enmState;
121
122	/** Padding up to 64 bytes. */
123	uint8_t abAlignment0[64 - 12];
124	/** @} */
125
126	/** IEM part.
127	* @remarks This comes first as it allows the use of 8-bit immediates for the
128	* first 64 bytes of the structure, reducing code size a wee bit. */
129	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
130	union VMCPUUNIONIEMFULL
131	#else
132	union VMCPUUNIONIEMSTUB
133	#endif
134	{
135	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
136	struct IEMCPU s;
137	#endif
138	uint8_t padding[26688]; /* multiple of 64 */
139	} iem;
140
141	/** @name Static per-cpu data.
142	* (Putting this after IEM, hoping that it's less frequently used than it.)
143	* @{ */
144	/** Ring-3 Host Context VM Pointer. */
145	PVMR3 pVMR3;
146	/** Ring-0 Host Context VM Pointer, currently used by VTG/dtrace. */
147	RTR0PTR pVCpuR0ForVtg;
148	/** Raw-mode Context VM Pointer. */
149	uint32_t pVMRC;
150	/** Padding for new raw-mode (long mode). */
151	uint32_t pVMRCPadding;
152	/** Pointer to the ring-3 UVMCPU structure. */
153	PUVMCPU pUVCpu;
154	/** The native thread handle. */
155	RTNATIVETHREAD hNativeThread;
156	/** The native R0 thread handle. (different from the R3 handle!) */
157	RTNATIVETHREAD hNativeThreadR0;
158	/** The IPRT thread handle (for VMMDevTesting). */
159	RTTHREAD hThread;
160	/** The CPU ID.
161	* This is the index into the VM::aCpu array. */
162	#ifdef IN_RING0
163	VMCPUID idCpuUnsafe;
164	#else
165	VMCPUID idCpu;
166	#endif
167
168	/** Align the structures below bit on a 64-byte boundary and make sure it starts
169	* at the same offset in both 64-bit and 32-bit builds.
170	*
171	* @remarks The alignments of the members that are larger than 48 bytes should be
172	* 64-byte for cache line reasons. structs containing small amounts of
173	* data could be lumped together at the end with a < 64 byte padding
174	* following it (to grow into and align the struct size).
175	*/
176	uint8_t abAlignment1[64 - 6 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4];
177	/** @} */
178
179	/** HM part. */
180	union VMCPUUNIONHM
181	{
182	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
183	struct HMCPU s;
184	#endif
185	uint8_t padding[9984]; /* multiple of 64 */
186	} hm;
187
188	/** NEM part. */
189	union VMCPUUNIONNEM
190	{
191	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
192	struct NEMCPU s;
193	#endif
194	uint8_t padding[4608]; /* multiple of 64 */
195	} nem;
196
197	/** TRPM part. */
198	union VMCPUUNIONTRPM
199	{
200	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
201	struct TRPMCPU s;
202	#endif
203	uint8_t padding[128]; /* multiple of 64 */
204	} trpm;
205
206	/** TM part. */
207	union VMCPUUNIONTM
208	{
209	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
210	struct TMCPU s;
211	#endif
212	uint8_t padding[5760]; /* multiple of 64 */
213	} tm;
214
215	/** VMM part. */
216	union VMCPUUNIONVMM
217	{
218	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
219	struct VMMCPU s;
220	#endif
221	uint8_t padding[9536]; /* multiple of 64 */
222	} vmm;
223
224	/** PDM part. */
225	union VMCPUUNIONPDM
226	{
227	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
228	struct PDMCPU s;
229	#endif
230	uint8_t padding[256]; /* multiple of 64 */
231	} pdm;
232
233	/** IOM part. */
234	union VMCPUUNIONIOM
235	{
236	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
237	struct IOMCPU s;
238	#endif
239	uint8_t padding[512]; /* multiple of 64 */
240	} iom;
241
242	/** DBGF part.
243	* @todo Combine this with other tiny structures. */
244	union VMCPUUNIONDBGF
245	{
246	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
247	struct DBGFCPU s;
248	#endif
249	uint8_t padding[512]; /* multiple of 64 */
250	} dbgf;
251
252	/** GIM part. */
253	union VMCPUUNIONGIM
254	{
255	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
256	struct GIMCPU s;
257	#endif
258	uint8_t padding[512]; /* multiple of 64 */
259	} gim;
260
261	/** APIC part. */
262	union VMCPUUNIONAPIC
263	{
264	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
265	struct APICCPU s;
266	#endif
267	uint8_t padding[3840]; /* multiple of 64 */
268	} apic;
269
270	/*
271	* Some less frequently used global members that doesn't need to take up
272	* precious space at the head of the structure.
273	*/
274
275	/** Trace groups enable flags. */
276	uint32_t fTraceGroups; /* 64 / 44 */
277	/** Number of collisions hashing the ring-0 EMT handle. */
278	uint8_t cEmtHashCollisions;
279	uint8_t abAdHoc[3];
280	/** Profiling samples for use by ad hoc profiling. */
281	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
282
283	/** Align the following members on page boundary. */
284	uint8_t abAlignment2[2744];
285
286	/** PGM part. */
287	union VMCPUUNIONPGM
288	{
289	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
290	struct PGMCPU s;
291	#endif
292	uint8_t padding[4096 + 28672]; /* multiple of 4096 */
293	} pgm;
294
295	/** CPUM part. */
296	union VMCPUUNIONCPUM
297	{
298	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
299	struct CPUMCPU s;
300	#endif
301	#ifdef VMCPU_INCL_CPUM_GST_CTX
302	/** The guest CPUM context for direct use by execution engines.
303	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
304	* others. The rest will use the function based CPUM API. */
305	CPUMCTX GstCtx;
306	#endif
307	uint8_t padding[102400]; /* multiple of 4096 */
308	} cpum;
309
310	/** EM part. */
311	union VMCPUUNIONEM
312	{
313	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
314	struct EMCPU s;
315	#endif
316	uint8_t padding[40960]; /* multiple of 4096 */
317	} em;
318
319	/** Align the structure size on 16384 boundrary for arm64 purposes. */
320	uint8_t abStructPadding[4096];
321	} VMCPU;
322
323
324	#ifndef VBOX_FOR_DTRACE_LIB
325	AssertCompileSizeAlignment(VMCPU, 16384);
326
327	/** @name Operations on VMCPU::enmState
328	* @{ */
329	/** Gets the VMCPU state. */
330	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
331	/** Sets the VMCPU state. */
332	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
333	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
334	/** Cmpares and sets the VMCPU state. */
335	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
336	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
337	/** Checks the VMCPU state. */
338	#ifdef VBOX_STRICT
339	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
340	do { \
341	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
342	AssertMsg(enmState == (enmExpectedState), \
343	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
344	enmState, enmExpectedState, (pVCpu)->idCpu)); \
345	} while (0)
346
347	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) \
348	do { \
349	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
350	AssertMsg( enmState == (enmExpectedState) \
351	\|\| enmState == (a_enmExpectedState2), \
352	("enmState=%d enmExpectedState=%d enmExpectedState2=%d idCpu=%u\n", \
353	enmState, enmExpectedState, a_enmExpectedState2, (pVCpu)->idCpu)); \
354	} while (0)
355	#else
356	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
357	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) do { } while (0)
358	#endif
359	/** Tests if the state means that the CPU is started. */
360	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
361	/** Tests if the state means that the CPU is stopped. */
362	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
363	/** @} */
364
365
366	/** The name of the raw-mode context VMM Core module. */
367	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
368	/** The name of the ring-0 context VMM Core module. */
369	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
370
371
372	/** VM Forced Action Flags.
373	*
374	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
375	* action mask of a VM.
376	*
377	* Available VM bits:
378	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30
379	*
380	*
381	* Available VMCPU bits:
382	* 14, 15, 36 to 63
383	*
384	* @todo If we run low on VMCPU, we may consider merging the SELM bits
385	*
386	* @{
387	*/
388	/** The virtual sync clock has been stopped, go to TM until it has been
389	* restarted... */
390	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
391	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
392	/** PDM Queues are pending. */
393	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
394	/** The bit number for VM_FF_PDM_QUEUES. */
395	#define VM_FF_PDM_QUEUES_BIT 3
396	/** PDM DMA transfers are pending. */
397	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
398	/** The bit number for VM_FF_PDM_DMA. */
399	#define VM_FF_PDM_DMA_BIT 4
400	/** This action forces the VM to call DBGF so DBGF can service debugger
401	* requests in the emulation thread.
402	* This action flag stays asserted till DBGF clears it.*/
403	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
404	/** The bit number for VM_FF_DBGF. */
405	#define VM_FF_DBGF_BIT 8
406	/** This action forces the VM to service pending requests from other
407	* thread or requests which must be executed in another context. */
408	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
409	#define VM_FF_REQUEST_BIT 9
410	/** Check for VM state changes and take appropriate action. */
411	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
412	/** The bit number for VM_FF_CHECK_VM_STATE. */
413	#define VM_FF_CHECK_VM_STATE_BIT 10
414	/** Reset the VM. (postponed) */
415	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
416	/** The bit number for VM_FF_RESET. */
417	#define VM_FF_RESET_BIT 11
418	/** EMT rendezvous in VMM. */
419	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
420	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
421	#define VM_FF_EMT_RENDEZVOUS_BIT 12
422
423	/** PGM needs to allocate handy pages. */
424	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
425	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
426	/** PGM is out of memory.
427	* Abandon all loops and code paths which can be resumed and get up to the EM
428	* loops. */
429	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
430	#define VM_FF_PGM_NO_MEMORY_BIT 19
431	/** PGM is about to perform a lightweight pool flush
432	* Guest SMP: all EMT threads should return to ring 3
433	*/
434	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
435	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
436	/** Suspend the VM - debug only. */
437	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
438	#define VM_FF_DEBUG_SUSPEND_BIT 31
439
440
441	/** This action forces the VM to check any pending interrupts on the APIC. */
442	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
443	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
444	/** This action forces the VM to check any pending interrups on the PIC. */
445	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
446	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
447	/** This action forces the VM to schedule and run pending timer (TM).
448	* @remarks Don't move - PATM compatibility. */
449	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
450	#define VMCPU_FF_TIMER_BIT 2
451	/** This action forces the VM to check any pending NMIs. */
452	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
453	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
454	/** This action forces the VM to check any pending SMIs. */
455	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
456	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
457	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
458	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
459	#define VMCPU_FF_PDM_CRITSECT_BIT 5
460	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
461	* the virtual CPU out of the next (/current) halted state. It is not processed
462	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
463	* is cleared the next time EM leaves the HALTED state. */
464	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
465	#define VMCPU_FF_UNHALT_BIT 6
466	/** Pending IEM action (mask). */
467	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
468	/** Pending IEM action (bit number). */
469	#define VMCPU_FF_IEM_BIT 7
470	/** Pending APIC action (bit number). */
471	#define VMCPU_FF_UPDATE_APIC_BIT 8
472	/** This action forces the VM to update APIC's asynchronously arrived
473	* interrupts as pending interrupts. */
474	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
475	/** This action forces the VM to service pending requests from other
476	* thread or requests which must be executed in another context. */
477	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
478	#define VMCPU_FF_REQUEST_BIT 9
479	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
480	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
481	/** The bit number for VMCPU_FF_DBGF. */
482	#define VMCPU_FF_DBGF_BIT 10
483	/** This action forces the VM to service any pending updates to CR3 (used only
484	* by HM). */
485	/** Hardware virtualized nested-guest interrupt pending. */
486	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
487	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
488	/** This action forces PGM to update changes to CR3 when the guest was in HM mode
489	* (when using nested paging). */
490	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
491	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
492	/* Bit 13 used to be VMCPU_FF_HM_UPDATE_PAE_PDPES. */
493	/** This action forces the VM to resync the page tables before going
494	* back to execute guest code. (GLOBAL FLUSH) */
495	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
496	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
497	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
498	* (NON-GLOBAL FLUSH) */
499	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
500	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
501	/** Check for pending TLB shootdown actions (deprecated)
502	* Reserved for furture HM re-use if necessary / safe.
503	* Consumer: HM */
504	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
505	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
506	/** Check for pending TLB flush action.
507	* Consumer: HM
508	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
509	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
510	/** The bit number for VMCPU_FF_TLB_FLUSH. */
511	#define VMCPU_FF_TLB_FLUSH_BIT 19
512	/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
513	/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
514	/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
515	/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
516	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
517	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
518	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
519	/** Block injection of non-maskable interrupts to the guest. */
520	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
521	#define VMCPU_FF_BLOCK_NMIS_BIT 25
522	/** Force return to Ring-3. */
523	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
524	#define VMCPU_FF_TO_R3_BIT 28
525	/** Force return to ring-3 to service pending I/O or MMIO write.
526	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
527	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
528	* status codes to be propagated at the same time without loss. */
529	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
530	#define VMCPU_FF_IOM_BIT 29
531	/* 30 used to be VMCPU_FF_CPUM */
532	/** VMX-preemption timer expired. */
533	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
534	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
535	/** Pending MTF (Monitor Trap Flag) event. */
536	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
537	#define VMCPU_FF_VMX_MTF_BIT 32
538	/** VMX APIC-write emulation pending. */
539	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
540	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
541	/** VMX interrupt-window event pending. */
542	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
543	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
544	/** VMX NMI-window event pending. */
545	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
546	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
547
548
549	/** Externally VM forced actions. Used to quit the idle/wait loop. */
550	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
551	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
552	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
553
554	/** Externally forced VM actions. Used to quit the idle/wait loop. */
555	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
556	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
557	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
558	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
559	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
560	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
561	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
562
563	/** High priority VM pre-execution actions. */
564	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
565	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
566	\| VM_FF_EMT_RENDEZVOUS )
567	/** High priority VMCPU pre-execution actions. */
568	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
569	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
570	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
571	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
572	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW )
573
574	/** High priority VM pre raw-mode execution mask. */
575	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
576	/** High priority VMCPU pre raw-mode execution mask. */
577	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
578	\| VMCPU_FF_INHIBIT_INTERRUPTS )
579
580	/** High priority post-execution actions. */
581	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
582	/** High priority post-execution actions. */
583	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM )
584
585	/** Normal priority VM post-execution actions. */
586	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
587	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
588	/** Normal priority VMCPU post-execution actions. */
589	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
590
591	/** Normal priority VM actions. */
592	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
593	/** Normal priority VMCPU actions. */
594	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
595
596	/** Flags to clear before resuming guest execution. */
597	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
598
599
600	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
601	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
602	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
603	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
604	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
605	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
606	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
607	#ifdef IN_RING3
608	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \
609	\| VMCPU_FF_VMX_MTF )
610	#else
611	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
612	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF )
613	#endif
614	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
615	* enabled. */
616	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
617	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
618	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
619	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
620	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
621	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
622	* disabled. */
623	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
624	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
625	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
626
627	/** VM Flags that cause the HM loops to go back to ring-3. */
628	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
629	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
630	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
631	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
632	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
633
634	/** High priority ring-0 VM pre HM-mode execution mask. */
635	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
636	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
637	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
638	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST \
639	\| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_PREEMPT_TIMER)
640	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
641	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
642	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
643	\| VM_FF_PDM_DMA) )
644	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
645	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
646	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
647
648	/** All the VMX nested-guest flags. */
649	#define VMCPU_FF_VMX_ALL_MASK ( VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
650	\| VMCPU_FF_VMX_INT_WINDOW \| VMCPU_FF_VMX_NMI_WINDOW )
651
652	/** All the forced VM flags. */
653	#define VM_FF_ALL_MASK (UINT32_MAX)
654	/** All the forced VMCPU flags. */
655	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
656
657	/** All the forced VM flags except those related to raw-mode and hardware
658	* assisted execution. */
659	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
660	/** All the forced VMCPU flags except those related to raw-mode and hardware
661	* assisted execution. */
662	#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_TLB_FLUSH))
663	/** @} */
664
665	/** @def VM_FF_SET
666	* Sets a single force action flag.
667	*
668	* @param pVM The cross context VM structure.
669	* @param fFlag The flag to set.
670	*/
671	#define VM_FF_SET(pVM, fFlag) do { \
672	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
673	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
674	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
675	} while (0)
676
677	/** @def VMCPU_FF_SET
678	* Sets a single force action flag for the given VCPU.
679	*
680	* @param pVCpu The cross context virtual CPU structure.
681	* @param fFlag The flag to set.
682	* @sa VMCPU_FF_SET_MASK
683	*/
684	#ifdef VMCPU_WITH_64_BIT_FFS
685	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
686	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
687	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
688	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
689	} while (0)
690	#else
691	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
692	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
693	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
694	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
695	} while (0)
696	#endif
697
698	/** @def VMCPU_FF_SET_MASK
699	* Sets a two or more force action flag for the given VCPU.
700	*
701	* @param pVCpu The cross context virtual CPU structure.
702	* @param fFlags The flags to set.
703	* @sa VMCPU_FF_SET
704	*/
705	#ifdef VMCPU_WITH_64_BIT_FFS
706	# if ARCH_BITS > 32
707	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
708	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
709	# else
710	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
711	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
712	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
713	} while (0)
714	# endif
715	#else
716	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
717	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
718	#endif
719
720	/** @def VM_FF_CLEAR
721	* Clears a single force action flag.
722	*
723	* @param pVM The cross context VM structure.
724	* @param fFlag The flag to clear.
725	*/
726	#define VM_FF_CLEAR(pVM, fFlag) do { \
727	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
728	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
729	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
730	} while (0)
731
732	/** @def VMCPU_FF_CLEAR
733	* Clears a single force action flag for the given VCPU.
734	*
735	* @param pVCpu The cross context virtual CPU structure.
736	* @param fFlag The flag to clear.
737	*/
738	#ifdef VMCPU_WITH_64_BIT_FFS
739	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
740	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
741	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
742	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
743	} while (0)
744	#else
745	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
746	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
747	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
748	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
749	} while (0)
750	#endif
751
752	/** @def VMCPU_FF_CLEAR_MASK
753	* Clears two or more force action flags for the given VCPU.
754	*
755	* @param pVCpu The cross context virtual CPU structure.
756	* @param fFlags The flags to clear.
757	*/
758	#ifdef VMCPU_WITH_64_BIT_FFS
759	# if ARCH_BITS > 32
760	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
761	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
762	# else
763	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
764	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
765	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
766	} while (0)
767	# endif
768	#else
769	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
770	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
771	#endif
772
773	/** @def VM_FF_IS_SET
774	* Checks if single a force action flag is set.
775	*
776	* @param pVM The cross context VM structure.
777	* @param fFlag The flag to check.
778	* @sa VM_FF_IS_ANY_SET
779	*/
780	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
781	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
782	#else
783	# define VM_FF_IS_SET(pVM, fFlag) \
784	([](PVM a_pVM) -> bool \
785	{ \
786	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
787	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
788	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
789	}(pVM))
790	#endif
791
792	/** @def VMCPU_FF_IS_SET
793	* Checks if a single force action flag is set for the given VCPU.
794	*
795	* @param pVCpu The cross context virtual CPU structure.
796	* @param fFlag The flag to check.
797	* @sa VMCPU_FF_IS_ANY_SET
798	*/
799	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
800	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
801	#else
802	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
803	([](PCVMCPU a_pVCpu) -> bool \
804	{ \
805	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
806	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
807	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
808	}(pVCpu))
809	#endif
810
811	/** @def VM_FF_IS_ANY_SET
812	* Checks if one or more force action in the specified set is pending.
813	*
814	* @param pVM The cross context VM structure.
815	* @param fFlags The flags to check for.
816	* @sa VM_FF_IS_SET
817	*/
818	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
819
820	/** @def VMCPU_FF_IS_ANY_SET
821	* Checks if two or more force action flags in the specified set is set for the given VCPU.
822	*
823	* @param pVCpu The cross context virtual CPU structure.
824	* @param fFlags The flags to check for.
825	* @sa VMCPU_FF_IS_SET
826	*/
827	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
828
829	/** @def VM_FF_TEST_AND_CLEAR
830	* Checks if one (!) force action in the specified set is pending and clears it atomically
831	*
832	* @returns true if the bit was set.
833	* @returns false if the bit was clear.
834	* @param pVM The cross context VM structure.
835	* @param fFlag Flag constant to check and clear (_BIT is appended).
836	*/
837	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
838
839	/** @def VMCPU_FF_TEST_AND_CLEAR
840	* Checks if one (!) force action in the specified set is pending and clears it atomically
841	*
842	* @returns true if the bit was set.
843	* @returns false if the bit was clear.
844	* @param pVCpu The cross context virtual CPU structure.
845	* @param fFlag Flag constant to check and clear (_BIT is appended).
846	*/
847	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
848
849	/** @def VM_FF_IS_PENDING_EXCEPT
850	* Checks if one or more force action in the specified set is pending while one
851	* or more other ones are not.
852	*
853	* @param pVM The cross context VM structure.
854	* @param fFlags The flags to check for.
855	* @param fExcpt The flags that should not be set.
856	*/
857	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
858	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
859
860	/** @def VM_IS_EMT
861	* Checks if the current thread is the emulation thread (EMT).
862	*
863	* @remark The ring-0 variation will need attention if we expand the ring-0
864	* code to let threads other than EMT mess around with the VM.
865	*/
866	#ifdef IN_RC
867	# define VM_IS_EMT(pVM) true
868	#else
869	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
870	#endif
871
872	/** @def VMCPU_IS_EMT
873	* Checks if the current thread is the emulation thread (EMT) for the specified
874	* virtual CPU.
875	*/
876	#ifdef IN_RC
877	# define VMCPU_IS_EMT(pVCpu) true
878	#else
879	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
880	#endif
881
882	/** @def VM_ASSERT_EMT
883	* Asserts that the current thread IS the emulation thread (EMT).
884	*/
885	#ifdef IN_RC
886	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
887	#elif defined(IN_RING0)
888	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
889	#else
890	# define VM_ASSERT_EMT(pVM) \
891	AssertMsg(VM_IS_EMT(pVM), \
892	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
893	#endif
894
895	/** @def VMCPU_ASSERT_EMT
896	* Asserts that the current thread IS the emulation thread (EMT) of the
897	* specified virtual CPU.
898	*/
899	#ifdef IN_RC
900	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
901	#elif defined(IN_RING0)
902	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
903	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
904	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
905	(pVCpu) ? (pVCpu)->idCpu : 0))
906	#else
907	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
908	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
909	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
910	#endif
911
912	/** @def VM_ASSERT_EMT_RETURN
913	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
914	*/
915	#ifdef IN_RC
916	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
917	#elif defined(IN_RING0)
918	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
919	#else
920	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
921	AssertMsgReturn(VM_IS_EMT(pVM), \
922	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
923	(rc))
924	#endif
925
926	/** @def VMCPU_ASSERT_EMT_RETURN
927	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
928	*/
929	#ifdef IN_RC
930	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
931	#elif defined(IN_RING0)
932	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
933	#else
934	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
935	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
936	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
937	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
938	(rc))
939	#endif
940
941	/** @def VMCPU_ASSERT_EMT_OR_GURU
942	* Asserts that the current thread IS the emulation thread (EMT) of the
943	* specified virtual CPU.
944	*/
945	#if defined(IN_RC) \|\| defined(IN_RING0)
946	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
947	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
948	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
949	#else
950	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
951	AssertMsg( VMCPU_IS_EMT(pVCpu) \
952	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
953	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
954	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
955	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
956	#endif
957
958	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
959	* Asserts that the current thread IS the emulation thread (EMT) of the
960	* specified virtual CPU or the VM is not running.
961	*/
962	#if defined(IN_RC) \|\| defined(IN_RING0)
963	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
964	Assert( VMCPU_IS_EMT(pVCpu) \
965	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
966	#else
967	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
968	AssertMsg( VMCPU_IS_EMT(pVCpu) \
969	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
970	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
971	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
972	#endif
973
974	/** @def VMSTATE_IS_RUNNING
975	* Checks if the given state indicates a running VM.
976	*/
977	#define VMSTATE_IS_RUNNING(a_enmVMState) \
978	( (enmVMState) == VMSTATE_RUNNING \
979	\|\| (enmVMState) == VMSTATE_RUNNING_LS )
980
981	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
982	* Checks if the VM is running.
983	* @note This is only for pure debug assertions. No AssertReturn or similar!
984	* @sa VMSTATE_IS_RUNNING
985	*/
986	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
987	( (pVM)->enmVMState == VMSTATE_RUNNING \
988	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS )
989
990	/** @def VM_ASSERT_IS_NOT_RUNNING
991	* Asserts that the VM is not running.
992	*/
993	#if defined(IN_RC) \|\| defined(IN_RING0)
994	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
995	#else
996	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
997	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
998	#endif
999
1000	/** @def VM_ASSERT_EMT0
1001	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1002	*/
1003	#ifdef IN_RING3
1004	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
1005	#else
1006	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1007	#endif
1008
1009	/** @def VM_ASSERT_EMT0_RETURN
1010	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1011	* it isn't.
1012	*/
1013	#ifdef IN_RING3
1014	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN((pVM)->apCpusR3[0], (rc))
1015	#else
1016	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1017	#endif
1018
1019
1020	/**
1021	* Asserts that the current thread is NOT the emulation thread.
1022	*/
1023	#define VM_ASSERT_OTHER_THREAD(pVM) \
1024	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1025
1026
1027	/** @def VM_ASSERT_STATE
1028	* Asserts a certain VM state.
1029	*/
1030	#define VM_ASSERT_STATE(pVM, _enmState) \
1031	AssertMsg((pVM)->enmVMState == (_enmState), \
1032	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1033
1034	/** @def VM_ASSERT_STATE_RETURN
1035	* Asserts a certain VM state and returns if it doesn't match.
1036	*/
1037	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1038	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1039	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1040	(rc))
1041
1042	/** @def VM_IS_VALID_EXT
1043	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1044	* or terminated. */
1045	#define VM_IS_VALID_EXT(pVM) \
1046	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1047	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1048	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1049	&& VM_IS_EMT(pVM))) )
1050
1051	/** @def VM_ASSERT_VALID_EXT_RETURN
1052	* Asserts a the VM handle is valid for external access, i.e. not being
1053	* destroy or terminated.
1054	*/
1055	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1056	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1057	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1058	? VMGetStateName(pVM->enmVMState) : ""), \
1059	(rc))
1060
1061	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1062	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1063	* destroy or terminated.
1064	*/
1065	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1066	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1067	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1068	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1069	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1070	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1071	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1072	(rc))
1073
1074	#endif /* !VBOX_FOR_DTRACE_LIB */
1075
1076
1077	/**
1078	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1079	*
1080	* ONLY HM and NEM MAY USE THIS!
1081	*
1082	* @param a_pVM The cross context VM structure.
1083	* @param a_bValue The new value.
1084	* @internal
1085	*/
1086	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1087	do { \
1088	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1089	ASMCompilerBarrier(); /* just to be on the safe side */ \
1090	} while (0)
1091
1092	/**
1093	* Checks whether iem-executes-all-mode is used.
1094	*
1095	* @retval true if IEM is used.
1096	* @retval false if not.
1097	*
1098	* @param a_pVM The cross context VM structure.
1099	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1100	* @internal
1101	*/
1102	#define VM_IS_EXEC_ENGINE_IEM(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_IEM)
1103
1104	/**
1105	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1106	*
1107	* @retval true if either is used.
1108	* @retval false if software virtualization (raw-mode) is used.
1109	*
1110	* @param a_pVM The cross context VM structure.
1111	* @sa VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1112	* @internal
1113	*/
1114	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_IEM)
1115
1116	/**
1117	* Checks whether HM is being used by this VM.
1118	*
1119	* @retval true if HM (VT-x/AMD-v) is used.
1120	* @retval false if not.
1121	*
1122	* @param a_pVM The cross context VM structure.
1123	* @sa VM_IS_NEM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1124	* @internal
1125	*/
1126	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1127
1128	/**
1129	* Checks whether NEM is being used by this VM.
1130	*
1131	* @retval true if a native hypervisor API is used.
1132	* @retval false if not.
1133	*
1134	* @param a_pVM The cross context VM structure.
1135	* @sa VM_IS_HM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1136	* @internal
1137	*/
1138	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1139
1140
1141	/**
1142	* The cross context VM structure.
1143	*
1144	* It contains all the VM data which have to be available in all contexts.
1145	* Even if it contains all the data the idea is to use APIs not to modify all
1146	* the members all around the place. Therefore we make use of unions to hide
1147	* everything which isn't local to the current source module. This means we'll
1148	* have to pay a little bit of attention when adding new members to structures
1149	* in the unions and make sure to keep the padding sizes up to date.
1150	*
1151	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1152	*/
1153	typedef struct VM
1154	{
1155	/** The state of the VM.
1156	* This field is read only to everyone except the VM and EM. */
1157	VMSTATE volatile enmVMState;
1158	/** Forced action flags.
1159	* See the VM_FF_* \#defines. Updated atomically.
1160	*/
1161	volatile uint32_t fGlobalForcedActions;
1162	/** Pointer to the array of page descriptors for the VM structure allocation. */
1163	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1164	/** Session handle. For use when calling SUPR0 APIs. */
1165	#ifdef IN_RING0
1166	PSUPDRVSESSION pSessionUnsafe;
1167	#else
1168	PSUPDRVSESSION pSession;
1169	#endif
1170	/** Pointer to the ring-3 VM structure. */
1171	PUVM pUVM;
1172	/** Ring-3 Host Context VM Pointer. */
1173	#ifdef IN_RING0
1174	R3PTRTYPE(struct VM *) pVMR3Unsafe;
1175	#else
1176	R3PTRTYPE(struct VM *) pVMR3;
1177	#endif
1178	/** Ring-0 Host Context VM pointer for making ring-0 calls. */
1179	R0PTRTYPE(struct VM *) pVMR0ForCall;
1180	/** Raw-mode Context VM Pointer. */
1181	uint32_t pVMRC;
1182	/** Padding for new raw-mode (long mode). */
1183	uint32_t pVMRCPadding;
1184
1185	/** The GVM VM handle. Only the GVM should modify this field. */
1186	#ifdef IN_RING0
1187	uint32_t hSelfUnsafe;
1188	#else
1189	uint32_t hSelf;
1190	#endif
1191	/** Number of virtual CPUs. */
1192	#ifdef IN_RING0
1193	uint32_t cCpusUnsafe;
1194	#else
1195	uint32_t cCpus;
1196	#endif
1197	/** CPU excution cap (1-100) */
1198	uint32_t uCpuExecutionCap;
1199
1200	/** Size of the VM structure. */
1201	uint32_t cbSelf;
1202	/** Size of the VMCPU structure. */
1203	uint32_t cbVCpu;
1204	/** Structure version number (TBD). */
1205	uint32_t uStructVersion;
1206
1207	/** @name Various items that are frequently accessed.
1208	* @{ */
1209	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1210	* This is set early during vmR3InitRing3 by HM or NEM. */
1211	uint8_t const bMainExecutionEngine;
1212
1213	/** Hardware VM support is available and enabled.
1214	* Determined very early during init.
1215	* This is placed here for performance reasons.
1216	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1217	bool fHMEnabled;
1218	/** @} */
1219
1220	/** Alignment padding. */
1221	uint8_t uPadding1[6];
1222
1223	/** @name Debugging
1224	* @{ */
1225	/** Ring-3 Host Context VM Pointer. */
1226	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1227	/** Ring-0 Host Context VM Pointer. */
1228	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1229	/** @} */
1230
1231	/** Max EMT hash lookup collisions (in GVMM). */
1232	uint8_t cMaxEmtHashCollisions;
1233
1234	/** Padding - the unions must be aligned on a 64 bytes boundary. */
1235	uint8_t abAlignment3[HC_ARCH_BITS == 64 ? 23 : 51];
1236
1237	/** CPUM part. */
1238	union
1239	{
1240	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1241	struct CPUM s;
1242	#endif
1243	#ifdef VBOX_INCLUDED_vmm_cpum_h
1244	/** Read only info exposed about the host and guest CPUs. */
1245	struct
1246	{
1247	/** Padding for hidden fields. */
1248	uint8_t abHidden0[64];
1249	/** Host CPU feature information. */
1250	CPUMFEATURES HostFeatures;
1251	/** Guest CPU feature information. */
1252	CPUMFEATURES GuestFeatures;
1253	} const ro;
1254	#endif
1255	/** @todo this is rather bloated because of static MSR range allocation.
1256	* Probably a good idea to move it to a separate R0 allocation... */
1257	uint8_t padding[8832 + 1288192 + 0x1d00]; / multiple of 64 */
1258	} cpum;
1259
1260	/** PGM part.
1261	* @note 16384 aligned for zero and mmio page storage. */
1262	union
1263	{
1264	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1265	struct PGM s;
1266	#endif
1267	uint8_t padding[53888]; /* multiple of 64 */
1268	} pgm;
1269
1270	/** VMM part. */
1271	union
1272	{
1273	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1274	struct VMM s;
1275	#endif
1276	uint8_t padding[1600]; /* multiple of 64 */
1277	} vmm;
1278
1279	/** HM part. */
1280	union
1281	{
1282	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1283	struct HM s;
1284	#endif
1285	uint8_t padding[5504]; /* multiple of 64 */
1286	} hm;
1287
1288	/** TRPM part. */
1289	union
1290	{
1291	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1292	struct TRPM s;
1293	#endif
1294	uint8_t padding[2048]; /* multiple of 64 */
1295	} trpm;
1296
1297	/** SELM part. */
1298	union
1299	{
1300	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1301	struct SELM s;
1302	#endif
1303	uint8_t padding[768]; /* multiple of 64 */
1304	} selm;
1305
1306	/** MM part. */
1307	union
1308	{
1309	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1310	struct MM s;
1311	#endif
1312	uint8_t padding[192]; /* multiple of 64 */
1313	} mm;
1314
1315	/** PDM part. */
1316	union
1317	{
1318	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1319	struct PDM s;
1320	#endif
1321	uint8_t padding[22400]; /* multiple of 64 */
1322	} pdm;
1323
1324	/** IOM part. */
1325	union
1326	{
1327	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1328	struct IOM s;
1329	#endif
1330	uint8_t padding[1152]; /* multiple of 64 */
1331	} iom;
1332
1333	/** EM part. */
1334	union
1335	{
1336	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1337	struct EM s;
1338	#endif
1339	uint8_t padding[256]; /* multiple of 64 */
1340	} em;
1341
1342	/** NEM part. */
1343	union
1344	{
1345	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1346	struct NEM s;
1347	#endif
1348	uint8_t padding[4608]; /* multiple of 64 */
1349	} nem;
1350
1351	/** TM part. */
1352	union
1353	{
1354	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1355	struct TM s;
1356	#endif
1357	uint8_t padding[10112]; /* multiple of 64 */
1358	} tm;
1359
1360	/** DBGF part. */
1361	union
1362	{
1363	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1364	struct DBGF s;
1365	#endif
1366	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1367	/** Read only info exposed about interrupt breakpoints and selected events. */
1368	struct
1369	{
1370	/** Bitmap of enabled hardware interrupt breakpoints. */
1371	uint32_t bmHardIntBreakpoints[256 / 32];
1372	/** Bitmap of enabled software interrupt breakpoints. */
1373	uint32_t bmSoftIntBreakpoints[256 / 32];
1374	/** Bitmap of selected events.
1375	* This includes non-selectable events too for simplicity, we maintain the
1376	* state for some of these, as it may come in handy. */
1377	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1378	/** Enabled hardware interrupt breakpoints. */
1379	uint32_t cHardIntBreakpoints;
1380	/** Enabled software interrupt breakpoints. */
1381	uint32_t cSoftIntBreakpoints;
1382	/** The number of selected events. */
1383	uint32_t cSelectedEvents;
1384	/** The number of enabled hardware breakpoints. */
1385	uint8_t cEnabledHwBreakpoints;
1386	/** The number of enabled hardware I/O breakpoints. */
1387	uint8_t cEnabledHwIoBreakpoints;
1388	uint8_t au8Alignment1[2]; /*< Alignment padding. /
1389	/** The number of enabled INT3 breakpoints. */
1390	uint32_t volatile cEnabledInt3Breakpoints;
1391	} const ro;
1392	#endif
1393	uint8_t padding[2432]; /* multiple of 64 */
1394	} dbgf;
1395
1396	/** SSM part. */
1397	union
1398	{
1399	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1400	struct SSM s;
1401	#endif
1402	uint8_t padding[128]; /* multiple of 64 */
1403	} ssm;
1404
1405	union
1406	{
1407	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1408	struct GIM s;
1409	#endif
1410	uint8_t padding[448]; /* multiple of 64 */
1411	} gim;
1412
1413	union
1414	{
1415	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1416	struct APIC s;
1417	#endif
1418	uint8_t padding[128]; /* multiple of 8 */
1419	} apic;
1420
1421	/* ---- begin small stuff ---- */
1422
1423	/** VM part. */
1424	union
1425	{
1426	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1427	struct VMINT s;
1428	#endif
1429	uint8_t padding[32]; /* multiple of 8 */
1430	} vm;
1431
1432	/** CFGM part. */
1433	union
1434	{
1435	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1436	struct CFGM s;
1437	#endif
1438	uint8_t padding[8]; /* multiple of 8 */
1439	} cfgm;
1440
1441	/** IEM part. */
1442	union
1443	{
1444	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
1445	struct IEM s;
1446	#endif
1447	uint8_t padding[8]; /* multiple of 8 */
1448	} iem;
1449
1450	/** Statistics for ring-0 only components. */
1451	struct
1452	{
1453	/** GMMR0 stats. */
1454	struct
1455	{
1456	/** Chunk TLB hits. */
1457	uint64_t cChunkTlbHits;
1458	/** Chunk TLB misses. */
1459	uint64_t cChunkTlbMisses;
1460	} gmm;
1461	uint64_t au64Padding[6]; /* probably more comming here... */
1462	} R0Stats;
1463
1464	/** Padding for aligning the structure size on a page boundrary. */
1465	uint8_t abAlignment2[8912 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1466
1467	/* ---- end small stuff ---- */
1468
1469	/** Array of VMCPU ring-3 pointers. */
1470	PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1471
1472	/* This point is aligned on a 16384 boundrary (for arm64 purposes). */
1473	} VM;
1474	#ifndef VBOX_FOR_DTRACE_LIB
1475	//AssertCompileSizeAlignment(VM, 16384);
1476	#endif
1477
1478
1479	#ifdef IN_RC
1480	RT_C_DECLS_BEGIN
1481
1482	/** The VM structure.
1483	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1484	* globals which we should avoid using.
1485	*/
1486	extern DECLIMPORT(VM) g_VM;
1487
1488	/** The VMCPU structure for virtual CPU \#0.
1489	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1490	* globals which we should avoid using.
1491	*/
1492	extern DECLIMPORT(VMCPU) g_VCpu0;
1493
1494	RT_C_DECLS_END
1495	#endif
1496
1497	/** @} */
1498
1499	#endif /* !VBOX_INCLUDED_vmm_vm_h */
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