VirtualBox

source: vbox/trunk/include/VBox/vmm/pgm.h@ 91939

Last change on this file since 91939 was 91854, checked in by vboxsync, 3 years ago

VMM: Removed PGM_WITHOUT_MAPPINGS and associated mapping code. bugref:9517

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 38.9 KB
Line 
1/** @file
2 * PGM - Page Monitor / Monitor.
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_pgm_h
27#define VBOX_INCLUDED_vmm_pgm_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/types.h>
33#include <VBox/sup.h>
34#include <VBox/vmm/vmapi.h>
35#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
36#include <iprt/x86.h>
37#include <VBox/param.h>
38
39RT_C_DECLS_BEGIN
40
41/** @defgroup grp_pgm The Page Monitor / Manager API
42 * @ingroup grp_vmm
43 * @{
44 */
45
46/**
47 * FNPGMRELOCATE callback mode.
48 */
49typedef enum PGMRELOCATECALL
50{
51 /** The callback is for checking if the suggested address is suitable. */
52 PGMRELOCATECALL_SUGGEST = 1,
53 /** The callback is for executing the relocation. */
54 PGMRELOCATECALL_RELOCATE
55} PGMRELOCATECALL;
56
57
58/**
59 * Callback function which will be called when PGM is trying to find
60 * a new location for the mapping.
61 *
62 * The callback is called in two modes, 1) the check mode and 2) the relocate mode.
63 * In 1) the callback should say if it objects to a suggested new location. If it
64 * accepts the new location, it is called again for doing it's relocation.
65 *
66 *
67 * @returns true if the location is ok.
68 * @returns false if another location should be found.
69 * @param pVM The cross context VM structure.
70 * @param GCPtrOld The old virtual address.
71 * @param GCPtrNew The new virtual address.
72 * @param enmMode Used to indicate the callback mode.
73 * @param pvUser User argument.
74 * @remark The return value is no a failure indicator, it's an acceptance
75 * indicator. Relocation can not fail!
76 */
77typedef DECLCALLBACKTYPE(bool, FNPGMRELOCATE,(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser));
78/** Pointer to a relocation callback function. */
79typedef FNPGMRELOCATE *PFNPGMRELOCATE;
80
81
82/**
83 * Memory access origin.
84 */
85typedef enum PGMACCESSORIGIN
86{
87 /** Invalid zero value. */
88 PGMACCESSORIGIN_INVALID = 0,
89 /** IEM is access memory. */
90 PGMACCESSORIGIN_IEM,
91 /** HM is access memory. */
92 PGMACCESSORIGIN_HM,
93 /** Some device is access memory. */
94 PGMACCESSORIGIN_DEVICE,
95 /** Someone debugging is access memory. */
96 PGMACCESSORIGIN_DEBUGGER,
97 /** SELM is access memory. */
98 PGMACCESSORIGIN_SELM,
99 /** FTM is access memory. */
100 PGMACCESSORIGIN_FTM,
101 /** REM is access memory. */
102 PGMACCESSORIGIN_REM,
103 /** IOM is access memory. */
104 PGMACCESSORIGIN_IOM,
105 /** End of valid values. */
106 PGMACCESSORIGIN_END,
107 /** Type size hack. */
108 PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
109} PGMACCESSORIGIN;
110
111
112/**
113 * Physical page access handler kind.
114 */
115typedef enum PGMPHYSHANDLERKIND
116{
117 /** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
118 PGMPHYSHANDLERKIND_MMIO = 1,
119 /** Handler all write access to a physical page range. */
120 PGMPHYSHANDLERKIND_WRITE,
121 /** Handler all access to a physical page range. */
122 PGMPHYSHANDLERKIND_ALL
123
124} PGMPHYSHANDLERKIND;
125
126/**
127 * Guest Access type
128 */
129typedef enum PGMACCESSTYPE
130{
131 /** Read access. */
132 PGMACCESSTYPE_READ = 1,
133 /** Write access. */
134 PGMACCESSTYPE_WRITE
135} PGMACCESSTYPE;
136
137
138/** @def PGM_ALL_CB_DECL
139 * Macro for declaring a handler callback for all contexts. The handler
140 * callback is static in ring-3, and exported in RC and R0.
141 * @sa PGM_ALL_CB2_DECL.
142 */
143#if defined(IN_RC) || defined(IN_RING0)
144# ifdef __cplusplus
145# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
146# else
147# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
148# endif
149#else
150# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
151#endif
152
153/** @def PGM_ALL_CB2_DECL
154 * Macro for declaring a handler callback for all contexts. The handler
155 * callback is hidden in ring-3, and exported in RC and R0.
156 * @sa PGM_ALL_CB2_DECL.
157 */
158#if defined(IN_RC) || defined(IN_RING0)
159# ifdef __cplusplus
160# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
161# else
162# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
163# endif
164#else
165# define PGM_ALL_CB2_DECL(type) DECL_HIDDEN_CALLBACK(type)
166#endif
167
168/** @def PGM_ALL_CB2_PROTO
169 * Macro for declaring a handler callback for all contexts. The handler
170 * callback is hidden in ring-3, and exported in RC and R0.
171 * @param fnType The callback function type.
172 * @sa PGM_ALL_CB2_DECL.
173 */
174#if defined(IN_RC) || defined(IN_RING0)
175# ifdef __cplusplus
176# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
177# else
178# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
179# endif
180#else
181# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
182#endif
183
184
185/**
186 * \#PF Handler callback for physical access handler ranges in RC and R0.
187 *
188 * @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
189 * @param pVM The cross context VM structure.
190 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
191 * @param uErrorCode CPU Error code.
192 * @param pRegFrame Trap register frame.
193 * NULL on DMA and other non CPU access.
194 * @param pvFault The fault address (cr2).
195 * @param GCPhysFault The GC physical address corresponding to pvFault.
196 * @param pvUser User argument.
197 * @thread EMT(pVCpu)
198 */
199typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
200 RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser));
201/** Pointer to PGM access callback. */
202typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
203
204
205/**
206 * Access handler callback for physical access handler ranges.
207 *
208 * The handler can not raise any faults, it's mainly for monitoring write access
209 * to certain pages (like MMIO).
210 *
211 * @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
212 * the only supported informational status code is
213 * VINF_PGM_HANDLER_DO_DEFAULT.
214 * @retval VINF_SUCCESS if the handler have carried out the operation.
215 * @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
216 * access operation.
217 * @retval VINF_EM_XXX in ring-0 and raw-mode context.
218 *
219 * @param pVM The cross context VM structure.
220 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
221 * @param GCPhys The physical address the guest is writing to.
222 * @param pvPhys The HC mapping of that address.
223 * @param pvBuf What the guest is reading/writing.
224 * @param cbBuf How much it's reading/writing.
225 * @param enmAccessType The access type.
226 * @param enmOrigin The origin of this call.
227 * @param pvUser User argument.
228 * @thread EMT(pVCpu)
229 */
230typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMPHYSHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
231 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
232 PGMACCESSORIGIN enmOrigin, void *pvUser));
233/** Pointer to PGM access callback. */
234typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
235
236
237/**
238 * Paging mode.
239 *
240 * @note Part of saved state. Change with extreme care.
241 */
242typedef enum PGMMODE
243{
244 /** The usual invalid value. */
245 PGMMODE_INVALID = 0,
246 /** Real mode. */
247 PGMMODE_REAL,
248 /** Protected mode, no paging. */
249 PGMMODE_PROTECTED,
250 /** 32-bit paging. */
251 PGMMODE_32_BIT,
252 /** PAE paging. */
253 PGMMODE_PAE,
254 /** PAE paging with NX enabled. */
255 PGMMODE_PAE_NX,
256 /** 64-bit AMD paging (long mode). */
257 PGMMODE_AMD64,
258 /** 64-bit AMD paging (long mode) with NX enabled. */
259 PGMMODE_AMD64_NX,
260 /** 32-bit nested paging mode (shadow only; guest physical to host physical). */
261 PGMMODE_NESTED_32BIT,
262 /** PAE nested paging mode (shadow only; guest physical to host physical). */
263 PGMMODE_NESTED_PAE,
264 /** AMD64 nested paging mode (shadow only; guest physical to host physical). */
265 PGMMODE_NESTED_AMD64,
266 /** Extended paging (Intel) mode. */
267 PGMMODE_EPT,
268 /** Special mode used by NEM to indicate no shadow paging necessary. */
269 PGMMODE_NONE,
270 /** The max number of modes */
271 PGMMODE_MAX,
272 /** 32bit hackishness. */
273 PGMMODE_32BIT_HACK = 0x7fffffff
274} PGMMODE;
275
276/** Macro for checking if the guest is using paging.
277 * @param enmMode PGMMODE_*.
278 * @remark ASSUMES certain order of the PGMMODE_* values.
279 */
280#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
281
282/** Macro for checking if it's one of the long mode modes.
283 * @param enmMode PGMMODE_*.
284 */
285#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX || (enmMode) == PGMMODE_AMD64)
286
287/** Macro for checking if it's one of the AMD64 nested modes.
288 * @param enmMode PGMMODE_*.
289 */
290#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
291 || (enmMode) == PGMMODE_NESTED_PAE \
292 || (enmMode) == PGMMODE_NESTED_AMD64)
293
294/** Macro for checking if it's one of the PAE modes.
295 * @param enmMode PGMMODE_*.
296 */
297#define PGMMODE_IS_PAE(enmMode) ( (enmMode) == PGMMODE_PAE \
298 || (enmMode) == PGMMODE_PAE_NX)
299
300/**
301 * Is the ROM mapped (true) or is the shadow RAM mapped (false).
302 *
303 * @returns boolean.
304 * @param enmProt The PGMROMPROT value, must be valid.
305 */
306#define PGMROMPROT_IS_ROM(enmProt) \
307 ( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
308 || (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
309
310
311VMMDECL(bool) PGMIsLockOwner(PVMCC pVM);
312
313VMMDECL(int) PGMRegisterStringFormatTypes(void);
314VMMDECL(void) PGMDeregisterStringFormatTypes(void);
315VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
316VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
317VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
318VMMDECL(int) PGMVerifyAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
319VMMDECL(int) PGMIsValidAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
320VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
321VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
322VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
323VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
324VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
325/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
326 * PGMShwMakePageNotPresent
327 * @{ */
328/** The call is from an access handler for dealing with the a faulting write
329 * operation. The virtual address is within the same page. */
330#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
331/** The page is an MMIO2. */
332#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
333/** @}*/
334VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
335VMMDECL(bool) PGMGstIsPagePresent(PVMCPUCC pVCpu, RTGCPTR GCPtr);
336VMMDECL(int) PGMGstSetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
337VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
338VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
339VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
340VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3);
341
342VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
343VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal, bool fPdpesMapped);
344VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
345VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3, bool fPdpesMapped);
346VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
347VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode);
348VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
349VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
350VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
351VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
352VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
353VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
354VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
355VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
356
357/** PGM physical access handler type registration handle (heap offset, valid
358 * cross contexts without needing fixing up). Callbacks and handler type is
359 * associated with this and it is shared by all handler registrations. */
360typedef uint32_t PGMPHYSHANDLERTYPE;
361/** Pointer to a PGM physical handler type registration handle. */
362typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
363/** NIL value for PGM physical access handler type handle. */
364#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
365VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVMCC pVM, PGMPHYSHANDLERTYPE hType);
366VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
367
368VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
369 RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
370 R3PTRTYPE(const char *) pszDesc);
371VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
372VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
373VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVMCC pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0);
374VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
375VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
376VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
377VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
378 PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
379VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
380VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
381VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
382
383
384/**
385 * Page type.
386 *
387 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
388 * @remarks This is used in the saved state, so changes to it requires bumping
389 * the saved state version.
390 * @todo So, convert to \#defines!
391 */
392typedef enum PGMPAGETYPE
393{
394 /** The usual invalid zero entry. */
395 PGMPAGETYPE_INVALID = 0,
396 /** RAM page. (RWX) */
397 PGMPAGETYPE_RAM,
398 /** MMIO2 page. (RWX) */
399 PGMPAGETYPE_MMIO2,
400 /** MMIO2 page aliased over an MMIO page. (RWX)
401 * See PGMHandlerPhysicalPageAlias(). */
402 PGMPAGETYPE_MMIO2_ALIAS_MMIO,
403 /** Special page aliased over an MMIO page. (RWX)
404 * See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
405 * VT-x's APIC access page at the moment. Treated as MMIO by everyone except
406 * the shadow paging code. */
407 PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
408 /** Shadowed ROM. (RWX) */
409 PGMPAGETYPE_ROM_SHADOW,
410 /** ROM page. (R-X) */
411 PGMPAGETYPE_ROM,
412 /** MMIO page. (---) */
413 PGMPAGETYPE_MMIO,
414 /** End of valid entries. */
415 PGMPAGETYPE_END
416} PGMPAGETYPE;
417AssertCompile(PGMPAGETYPE_END == 8);
418
419/** @name PGM page type predicates.
420 * @{ */
421#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
422#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
423#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
424#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
425#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
426/** @} */
427
428
429VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
430
431VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
432VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
433VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
434VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
435VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
436VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
437
438VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
439VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
440VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
441VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
442VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
443VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
444
445/** @def PGM_PHYS_RW_IS_SUCCESS
446 * Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
447 * PGMPhysWriteGCPtr call completed the given task.
448 *
449 * @returns true if completed, false if not.
450 * @param a_rcStrict The status code.
451 * @sa IOM_SUCCESS
452 */
453#ifdef IN_RING3
454# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
455 ( (a_rcStrict) == VINF_SUCCESS \
456 || (a_rcStrict) == VINF_EM_DBG_STOP \
457 || (a_rcStrict) == VINF_EM_DBG_EVENT \
458 || (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
459 )
460#elif defined(IN_RING0)
461# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
462 ( (a_rcStrict) == VINF_SUCCESS \
463 || (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
464 || (a_rcStrict) == VINF_EM_OFF \
465 || (a_rcStrict) == VINF_EM_SUSPEND \
466 || (a_rcStrict) == VINF_EM_RESET \
467 || (a_rcStrict) == VINF_EM_HALT \
468 || (a_rcStrict) == VINF_EM_DBG_STOP \
469 || (a_rcStrict) == VINF_EM_DBG_EVENT \
470 || (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
471 )
472#elif defined(IN_RC)
473# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
474 ( (a_rcStrict) == VINF_SUCCESS \
475 || (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
476 || (a_rcStrict) == VINF_EM_OFF \
477 || (a_rcStrict) == VINF_EM_SUSPEND \
478 || (a_rcStrict) == VINF_EM_RESET \
479 || (a_rcStrict) == VINF_EM_HALT \
480 || (a_rcStrict) == VINF_SELM_SYNC_GDT \
481 || (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
482 || (a_rcStrict) == VINF_EM_DBG_STOP \
483 || (a_rcStrict) == VINF_EM_DBG_EVENT \
484 || (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
485 )
486#endif
487/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
488 * Updates the return code with a new result.
489 *
490 * Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
491 *
492 * @param a_rcStrict The current return code, to be updated.
493 * @param a_rcStrict2 The new return code to merge in.
494 */
495#ifdef IN_RING3
496# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
497 do { \
498 Assert(rcStrict == VINF_SUCCESS); \
499 Assert(rcStrict2 == VINF_SUCCESS); \
500 } while (0)
501#elif defined(IN_RING0)
502# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
503 do { \
504 Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
505 Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
506 AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
507 if ((a_rcStrict2) == VINF_SUCCESS || (a_rcStrict) == (a_rcStrict2)) \
508 { /* likely */ } \
509 else if ( (a_rcStrict) == VINF_SUCCESS \
510 || (a_rcStrict) > (a_rcStrict2)) \
511 (a_rcStrict) = (a_rcStrict2); \
512 } while (0)
513#elif defined(IN_RC)
514# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
515 do { \
516 Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
517 Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
518 AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
519 AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
520 AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
521 AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
522 AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
523 AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
524 if ((a_rcStrict2) == VINF_SUCCESS || (a_rcStrict) == (a_rcStrict2)) \
525 { /* likely */ } \
526 else if ((a_rcStrict) == VINF_SUCCESS) \
527 (a_rcStrict) = (a_rcStrict2); \
528 else if ( ( (a_rcStrict) > (a_rcStrict2) \
529 && ( (a_rcStrict2) <= VINF_EM_RESET \
530 || (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
531 || ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
532 && (a_rcStrict) > VINF_EM_RESET) ) \
533 (a_rcStrict) = (a_rcStrict2); \
534 } while (0)
535#endif
536
537VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
538VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
539VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
540VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
541
542VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
543VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
544VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
545VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
546VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
547VMMDECL(int) PGMPhysInterpretedRead(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
548VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
549VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
550
551VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
552VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
553VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
554#if defined(IN_RC)
555 R3PTRTYPE(uint8_t *) *ppb,
556#else
557 R3R0PTRTYPE(uint8_t *) *ppb,
558#endif
559 uint64_t *pfTlb);
560/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
561 * @{ */
562#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /**< Not writable (IEMTLBE_F_PG_NO_WRITE). */
563#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /**< Not readable (IEMTLBE_F_PG_NO_READ). */
564#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /**< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). */
565/** @} */
566
567/** Information returned by PGMPhysNemQueryPageInfo. */
568typedef struct PGMPHYSNEMPAGEINFO
569{
570 /** The host physical address of the page, NIL_HCPHYS if invalid page. */
571 RTHCPHYS HCPhys;
572 /** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
573 uint32_t fNemProt : 8;
574 /** The NEM state associated with the PAGE. */
575 uint32_t u2NemState : 2;
576 /** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
577 uint32_t u2OldNemState : 2;
578 /** Set if the page has handler. */
579 uint32_t fHasHandlers : 1;
580 /** Set if is the zero page backing it. */
581 uint32_t fZeroPage : 1;
582 /** Set if the page has handler. */
583 PGMPAGETYPE enmType;
584} PGMPHYSNEMPAGEINFO;
585/** Pointer to page information for NEM. */
586typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
587/**
588 * Callback for checking that the page is in sync while under the PGM lock.
589 *
590 * NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
591 * in-sync between PGM and the native hypervisor API in an atomic fashion.
592 *
593 * @returns VBox status code.
594 * @param pVM The cross context VM structure.
595 * @param pVCpu The cross context per virtual CPU structure. Optional,
596 * see PGMPhysNemQueryPageInfo.
597 * @param GCPhys The guest physical address (not A20 masked).
598 * @param pInfo The page info structure. This function updates the
599 * u2NemState memory and the caller will update the PGMPAGE
600 * copy accordingly.
601 * @param pvUser Callback user argument.
602 */
603typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMCHECKPAGE,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser));
604/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
605typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
606
607VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
608 PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
609
610/**
611 * Callback for use with PGMPhysNemEnumPagesByState.
612 * @returns VBox status code.
613 * Failure status will stop enumeration immediately and return.
614 * @param pVM The cross context VM structure.
615 * @param pVCpu The cross context per virtual CPU structure. Optional,
616 * see PGMPhysNemEnumPagesByState.
617 * @param GCPhys The guest physical address (not A20 masked).
618 * @param pu2NemState Pointer to variable with the NEM state. This can be
619 * update.
620 * @param pvUser The user argument.
621 */
622typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMENUMCALLBACK,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
623 uint8_t *pu2NemState, void *pvUser));
624/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
625typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
626VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
627 PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
628
629
630#ifdef VBOX_STRICT
631VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVMCC pVM);
632VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
633VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
634#endif /* VBOX_STRICT */
635
636VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
637
638/**
639 * Query large page usage state
640 *
641 * @returns 0 - disabled, 1 - enabled
642 * @param pVM The cross context VM structure.
643 */
644#define PGMIsUsingLargePages(pVM) ((pVM)->pgm.s.fUseLargePages)
645
646
647#ifdef IN_RING0
648/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
649 * @{
650 */
651VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM);
652VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
653VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
654VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
655VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
656VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PGVM pGVM, VMCPUID idCpu);
657VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
658 size_t offSub, size_t cbSub, void **ppvMapping);
659VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
660VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
661 PCRTGCPTR64 paRegionsGCPtrs);
662VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
663 PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
664VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
665 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
666VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
667/** @} */
668#endif /* IN_RING0 */
669
670
671
672#ifdef IN_RING3
673/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
674 * @{
675 */
676VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM);
677VMMR3DECL(int) PGMR3Init(PVM pVM);
678VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
679VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
680VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
681VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
682VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
683VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
684VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
685VMMR3DECL(int) PGMR3Term(PVM pVM);
686
687VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
688VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
689VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
690VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
691VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
692 const char **ppszDesc, bool *pfIsMmio);
693VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t *pcbTotalMem, uint64_t *pcbPrivateMem, uint64_t *pcbSharedMem, uint64_t *pcbZeroMem);
694VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t *pcbAllocMem, uint64_t *pcbFreeMem, uint64_t *pcbBallonedMem, uint64_t *pcbSharedMem);
695
696VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
697 RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
698VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
699VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
700 uint32_t fFlags, const char *pszDesc, void **ppv, PGMMMIO2HANDLE *phRegion);
701VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
702VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
703VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
704VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
705VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
706VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
707VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
708
709
710/** @name PGMR3PhysRegisterRom flags.
711 * @{ */
712/** Inidicates that ROM shadowing should be enabled. */
713#define PGMPHYS_ROM_FLAGS_SHADOWED UINT8_C(0x01)
714/** Indicates that what pvBinary points to won't go away
715 * and can be used for strictness checks. */
716#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY UINT8_C(0x02)
717/** Indicates that the ROM is allowed to be missing from saved state.
718 * @note This is a hack for EFI, see @bugref{6940} */
719#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE UINT8_C(0x04)
720/** Valid flags. */
721#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT8_C(0x07)
722/** @} */
723
724VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
725 const void *pvBinary, uint32_t cbBinary, uint8_t fFlags, const char *pszDesc);
726VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
727VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
728VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
729
730VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
731VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
732VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
733
734VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
735 PFNPGMPHYSHANDLER pfnHandlerR3,
736 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
737 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
738 const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
739VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
740 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
741 const char *pszModR0, const char *pszHandlerR0, const char *pszPfHandlerR0,
742 const char *pszModRC, const char *pszHandlerRC, const char *pszPfHandlerRC,
743 const char *pszDesc,
744 PPGMPHYSHANDLERTYPE phType);
745VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
746
747VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
748VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
749VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
750VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
751VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
752VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
753VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
754VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
755VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
756VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
757VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
758VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
759VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
760VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
761 void **papvPages, PPGMPAGEMAPLOCK paLocks);
762VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
763 void const **papvPages, PPGMPAGEMAPLOCK paLocks);
764VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
765VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
766VMMR3_INT_DECL(int) PGMR3PhysAllocateLargePage(PVM pVM, RTGCPHYS GCPhys);
767
768VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
769
770VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
771VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
772VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
773VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
774VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
775VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
776VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
777VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
778VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
779VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
780VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
781
782
783/** @name Page sharing
784 * @{ */
785VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char *pszModuleName, char *pszVersion,
786 RTGCPTR GCBaseAddr, uint32_t cbModule,
787 uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
788VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char *pszModuleName, char *pszVersion,
789 RTGCPTR GCBaseAddr, uint32_t cbModule);
790VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
791VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool *pfShared, uint64_t *pfPageFlags);
792/** @} */
793
794/** @} */
795#endif /* IN_RING3 */
796
797RT_C_DECLS_END
798
799/** @} */
800#endif /* !VBOX_INCLUDED_vmm_pgm_h */
801
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette