pgm.h@ 80074

Last change on this file since 80074 was 80074, checked in by vboxsync, 5 years ago
VMM,Main,++: Retired the unfinished FTM component.
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pgm_h
27	#define VBOX_INCLUDED_vmm_pgm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <VBox/sup.h>
34	#include <VBox/vmm/vmapi.h>
35	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
36	#include <iprt/x86.h>
37	#include <VBox/param.h>
38
39	RT_C_DECLS_BEGIN
40
41	/** @defgroup grp_pgm The Page Monitor / Manager API
42	* @ingroup grp_vmm
43	* @{
44	*/
45
46	/**
47	* FNPGMRELOCATE callback mode.
48	*/
49	typedef enum PGMRELOCATECALL
50	{
51	/** The callback is for checking if the suggested address is suitable. */
52	PGMRELOCATECALL_SUGGEST = 1,
53	/** The callback is for executing the relocation. */
54	PGMRELOCATECALL_RELOCATE
55	} PGMRELOCATECALL;
56
57
58	/**
59	* Callback function which will be called when PGM is trying to find
60	* a new location for the mapping.
61	*
62	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
63	* In 1) the callback should say if it objects to a suggested new location. If it
64	* accepts the new location, it is called again for doing it's relocation.
65	*
66	*
67	* @returns true if the location is ok.
68	* @returns false if another location should be found.
69	* @param pVM The cross context VM structure.
70	* @param GCPtrOld The old virtual address.
71	* @param GCPtrNew The new virtual address.
72	* @param enmMode Used to indicate the callback mode.
73	* @param pvUser User argument.
74	* @remark The return value is no a failure indicator, it's an acceptance
75	* indicator. Relocation can not fail!
76	*/
77	typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
78	/** Pointer to a relocation callback function. */
79	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
80
81
82	/**
83	* Memory access origin.
84	*/
85	typedef enum PGMACCESSORIGIN
86	{
87	/** Invalid zero value. */
88	PGMACCESSORIGIN_INVALID = 0,
89	/** IEM is access memory. */
90	PGMACCESSORIGIN_IEM,
91	/** HM is access memory. */
92	PGMACCESSORIGIN_HM,
93	/** Some device is access memory. */
94	PGMACCESSORIGIN_DEVICE,
95	/** Someone debugging is access memory. */
96	PGMACCESSORIGIN_DEBUGGER,
97	/** SELM is access memory. */
98	PGMACCESSORIGIN_SELM,
99	/** FTM is access memory. */
100	PGMACCESSORIGIN_FTM,
101	/** REM is access memory. */
102	PGMACCESSORIGIN_REM,
103	/** IOM is access memory. */
104	PGMACCESSORIGIN_IOM,
105	/** End of valid values. */
106	PGMACCESSORIGIN_END,
107	/** Type size hack. */
108	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
109	} PGMACCESSORIGIN;
110
111
112	/**
113	* Physical page access handler kind.
114	*/
115	typedef enum PGMPHYSHANDLERKIND
116	{
117	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
118	PGMPHYSHANDLERKIND_MMIO = 1,
119	/** Handler all write access to a physical page range. */
120	PGMPHYSHANDLERKIND_WRITE,
121	/** Handler all access to a physical page range. */
122	PGMPHYSHANDLERKIND_ALL
123
124	} PGMPHYSHANDLERKIND;
125
126	/**
127	* Guest Access type
128	*/
129	typedef enum PGMACCESSTYPE
130	{
131	/** Read access. */
132	PGMACCESSTYPE_READ = 1,
133	/** Write access. */
134	PGMACCESSTYPE_WRITE
135	} PGMACCESSTYPE;
136
137
138	/** @def PGM_ALL_CB_DECL
139	* Macro for declaring a handler callback for all contexts. The handler
140	* callback is static in ring-3, and exported in RC and R0.
141	* @sa PGM_ALL_CB2_DECL.
142	*/
143	#if defined(IN_RC) \|\| defined(IN_RING0)
144	# ifdef __cplusplus
145	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
146	# else
147	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
148	# endif
149	#else
150	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
151	#endif
152
153	/** @def PGM_ALL_CB2_DECL
154	* Macro for declaring a handler callback for all contexts. The handler
155	* callback is hidden in ring-3, and exported in RC and R0.
156	* @sa PGM_ALL_CB2_DECL.
157	*/
158	#if defined(IN_RC) \|\| defined(IN_RING0)
159	# ifdef __cplusplus
160	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
161	# else
162	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
163	# endif
164	#else
165	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLHIDDEN(type))
166	#endif
167
168	/** @def PGM_ALL_CB2_PROTO
169	* Macro for declaring a handler callback for all contexts. The handler
170	* callback is hidden in ring-3, and exported in RC and R0.
171	* @param fnType The callback function type.
172	* @sa PGM_ALL_CB2_DECL.
173	*/
174	#if defined(IN_RC) \|\| defined(IN_RING0)
175	# ifdef __cplusplus
176	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
177	# else
178	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
179	# endif
180	#else
181	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
182	#endif
183
184
185	/**
186	* \#PF Handler callback for physical access handler ranges in RC and R0.
187	*
188	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
189	* @param pVM The cross context VM structure.
190	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
191	* @param uErrorCode CPU Error code.
192	* @param pRegFrame Trap register frame.
193	* NULL on DMA and other non CPU access.
194	* @param pvFault The fault address (cr2).
195	* @param GCPhysFault The GC physical address corresponding to pvFault.
196	* @param pvUser User argument.
197	* @thread EMT(pVCpu)
198	*/
199	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRZPHYSPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
200	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
201	/** Pointer to PGM access callback. */
202	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
203
204
205	/**
206	* Access handler callback for physical access handler ranges.
207	*
208	* The handler can not raise any faults, it's mainly for monitoring write access
209	* to certain pages (like MMIO).
210	*
211	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
212	* the only supported informational status code is
213	* VINF_PGM_HANDLER_DO_DEFAULT.
214	* @retval VINF_SUCCESS if the handler have carried out the operation.
215	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
216	* access operation.
217	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
218	*
219	* @param pVM The cross context VM structure.
220	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
221	* @param GCPhys The physical address the guest is writing to.
222	* @param pvPhys The HC mapping of that address.
223	* @param pvBuf What the guest is reading/writing.
224	* @param cbBuf How much it's reading/writing.
225	* @param enmAccessType The access type.
226	* @param enmOrigin The origin of this call.
227	* @param pvUser User argument.
228	* @thread EMT(pVCpu)
229	*/
230	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMPHYSHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
231	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
232	/** Pointer to PGM access callback. */
233	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
234
235
236	/**
237	* Virtual access handler type.
238	*/
239	typedef enum PGMVIRTHANDLERKIND
240	{
241	/** Write access handled. */
242	PGMVIRTHANDLERKIND_WRITE = 1,
243	/** All access handled. */
244	PGMVIRTHANDLERKIND_ALL,
245	/** Hypervisor write access handled.
246	* This is used to catch the guest trying to write to LDT, TSS and any other
247	* system structure which the brain dead intel guys let unprivilegde code find. */
248	PGMVIRTHANDLERKIND_HYPERVISOR
249	} PGMVIRTHANDLERKIND;
250
251	/**
252	* \#PF handler callback for virtual access handler ranges, RC.
253	*
254	* Important to realize that a physical page in a range can have aliases, and
255	* for ALL and WRITE handlers these will also trigger.
256	*
257	* @returns Strict VBox status code (appropriate for raw-mode).
258	* @param pVM The cross context VM structure.
259	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
260	* @param uErrorCode CPU Error code (X86_TRAP_PF_XXX).
261	* @param pRegFrame Trap register frame.
262	* @param pvFault The fault address (cr2).
263	* @param pvRange The base address of the handled virtual range.
264	* @param offRange The offset of the access into this range.
265	* (If it's a EIP range this is the EIP, if not it's pvFault.)
266	* @param pvUser User argument.
267	* @thread EMT(pVCpu)
268	*/
269	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRCVIRTPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
270	RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange, void *pvUser);
271	/** Pointer to PGM access callback. */
272	typedef FNPGMRCVIRTPFHANDLER *PFNPGMRCVIRTPFHANDLER;
273
274	/**
275	* Access handler callback for virtual access handler ranges.
276	*
277	* Important to realize that a physical page in a range can have aliases, and
278	* for ALL and WRITE handlers these will also trigger.
279	*
280	* @returns VINF_SUCCESS if the handler have carried out the operation.
281	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
282	* @param pVM The cross context VM structure.
283	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
284	* @param GCPtr The virtual address the guest is writing to. This
285	* is the registered address corresponding to the
286	* access, so no aliasing trouble here.
287	* @param pvPtr The HC mapping of that address.
288	* @param pvBuf What the guest is reading/writing.
289	* @param cbBuf How much it's reading/writing.
290	* @param enmAccessType The access type.
291	* @param enmOrigin Who is calling.
292	* @param pvUser User argument.
293	* @thread EMT(pVCpu)
294	*/
295	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMVIRTHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
296	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
297	/** Pointer to PGM access callback. */
298	typedef FNPGMVIRTHANDLER *PFNPGMVIRTHANDLER;
299
300	/**
301	* \#PF Handler callback for invalidation of virtual access handler ranges.
302	*
303	* @param pVM The cross context VM structure.
304	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
305	* @param GCPtr The virtual address the guest has changed.
306	* @param pvUser User argument.
307	* @thread EMT(pVCpu)
308	*
309	* @todo FNPGMR3VIRTINVALIDATE will not actually be called! It was introduced
310	* in r13179 (1.1) and stopped working with r13806 (PGMPool merge,
311	* v1.2), exactly a month later.
312	*/
313	typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void *pvUser);
314	/** Pointer to PGM invalidation callback. */
315	typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
316
317
318	/**
319	* Paging mode.
320	*
321	* @note Part of saved state. Change with extreme care.
322	*/
323	typedef enum PGMMODE
324	{
325	/** The usual invalid value. */
326	PGMMODE_INVALID = 0,
327	/** Real mode. */
328	PGMMODE_REAL,
329	/** Protected mode, no paging. */
330	PGMMODE_PROTECTED,
331	/** 32-bit paging. */
332	PGMMODE_32_BIT,
333	/** PAE paging. */
334	PGMMODE_PAE,
335	/** PAE paging with NX enabled. */
336	PGMMODE_PAE_NX,
337	/** 64-bit AMD paging (long mode). */
338	PGMMODE_AMD64,
339	/** 64-bit AMD paging (long mode) with NX enabled. */
340	PGMMODE_AMD64_NX,
341	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
342	PGMMODE_NESTED_32BIT,
343	/** PAE nested paging mode (shadow only; guest physical to host physical). */
344	PGMMODE_NESTED_PAE,
345	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
346	PGMMODE_NESTED_AMD64,
347	/** Extended paging (Intel) mode. */
348	PGMMODE_EPT,
349	/** Special mode used by NEM to indicate no shadow paging necessary. */
350	PGMMODE_NONE,
351	/** The max number of modes */
352	PGMMODE_MAX,
353	/** 32bit hackishness. */
354	PGMMODE_32BIT_HACK = 0x7fffffff
355	} PGMMODE;
356
357	/** Macro for checking if the guest is using paging.
358	* @param enmMode PGMMODE_*.
359	* @remark ASSUMES certain order of the PGMMODE_* values.
360	*/
361	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
362
363	/** Macro for checking if it's one of the long mode modes.
364	* @param enmMode PGMMODE_*.
365	*/
366	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
367
368	/** Macro for checking if it's one of the AMD64 nested modes.
369	* @param enmMode PGMMODE_*.
370	*/
371	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
372	\|\| (enmMode) == PGMMODE_NESTED_PAE \
373	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
374
375	/**
376	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
377	*
378	* @returns boolean.
379	* @param enmProt The PGMROMPROT value, must be valid.
380	*/
381	#define PGMROMPROT_IS_ROM(enmProt) \
382	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
383	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
384
385
386	VMMDECL(bool) PGMIsLockOwner(PVM pVM);
387
388	VMMDECL(int) PGMRegisterStringFormatTypes(void);
389	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
390	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
391	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
392	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
393	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
394	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
395	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
396	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
397	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
398	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
399	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
400	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
401	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
402	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
403	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
404	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
405	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
406	#ifndef IN_RING0
407	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
408	#endif
409	#ifdef VBOX_STRICT
410	VMMDECL(void) PGMMapCheck(PVM pVM);
411	#endif
412	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
413	VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
414	VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
415	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
416	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
417	* PGMShwMakePageNotPresent
418	* @{ */
419	/** The call is from an access handler for dealing with the a faulting write
420	* operation. The virtual address is within the same page. */
421	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
422	/** The page is an MMIO2. */
423	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
424	/** @}*/
425	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
426	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
427	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
428	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
429	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes);
430	VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes);
431
432	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
433	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
434	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
435	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
436	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
437	VMM_INT_DECL(int) PGMHCChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
438	VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu);
439	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
440	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
441	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
442	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
443	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
444	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
445	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
446
447	/** PGM physical access handler type registration handle (heap offset, valid
448	* cross contexts without needing fixing up). Callbacks and handler type is
449	* associated with this and it is shared by all handler registrations. */
450	typedef uint32_t PGMPHYSHANDLERTYPE;
451	/** Pointer to a PGM physical handler type registration handle. */
452	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
453	/** NIL value for PGM physical access handler type handle. */
454	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
455	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVM pVM, PGMPHYSHANDLERTYPE hType);
456	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
457
458	VMMDECL(int) PGMHandlerPhysicalRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
459	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
460	R3PTRTYPE(const char *) pszDesc);
461	VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
462	VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
463	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVM pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC);
464	VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
465	VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
466	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
467	VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
468	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
469	VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
470	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
471
472	/** PGM virtual access handler type registration handle (heap offset, valid
473	* cross contexts without needing fixing up). Callbacks and handler type is
474	* associated with this and it is shared by all handler registrations. */
475	typedef uint32_t PGMVIRTHANDLERTYPE;
476	/** Pointer to a PGM virtual handler type registration handle. */
477	typedef PGMVIRTHANDLERTYPE *PPGMVIRTHANDLERTYPE;
478	/** NIL value for PGM virtual access handler type handle. */
479	#define NIL_PGMVIRTHANDLERTYPE UINT32_MAX
480	#ifdef VBOX_WITH_RAW_MODE
481	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRelease(PVM pVM, PGMVIRTHANDLERTYPE hType);
482	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRetain(PVM pVM, PGMVIRTHANDLERTYPE hType);
483	VMM_INT_DECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
484	#endif
485
486
487	/**
488	* Page type.
489	*
490	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
491	* @remarks This is used in the saved state, so changes to it requires bumping
492	* the saved state version.
493	* @todo So, convert to \#defines!
494	*/
495	typedef enum PGMPAGETYPE
496	{
497	/** The usual invalid zero entry. */
498	PGMPAGETYPE_INVALID = 0,
499	/** RAM page. (RWX) */
500	PGMPAGETYPE_RAM,
501	/** MMIO2 page. (RWX) */
502	PGMPAGETYPE_MMIO2,
503	/** MMIO2 page aliased over an MMIO page. (RWX)
504	* See PGMHandlerPhysicalPageAlias(). */
505	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
506	/** Special page aliased over an MMIO page. (RWX)
507	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
508	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
509	* the shadow paging code. */
510	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
511	/** Shadowed ROM. (RWX) */
512	PGMPAGETYPE_ROM_SHADOW,
513	/** ROM page. (R-X) */
514	PGMPAGETYPE_ROM,
515	/** MMIO page. (---) */
516	PGMPAGETYPE_MMIO,
517	/** End of valid entries. */
518	PGMPAGETYPE_END
519	} PGMPAGETYPE;
520	AssertCompile(PGMPAGETYPE_END == 8);
521
522	/** @name PGM page type predicates.
523	* @{ */
524	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
525	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
526	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
527	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
528	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
529	/** @} */
530
531
532	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVM pVM, RTGCPHYS GCPhys);
533
534	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
535	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
536	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
537	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
538	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
539	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
540
541	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
542	VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
543	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
544	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
545	VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
546	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVM pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
547
548	/** @def PGM_PHYS_RW_IS_SUCCESS
549	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
550	* PGMPhysWriteGCPtr call completed the given task.
551	*
552	* @returns true if completed, false if not.
553	* @param a_rcStrict The status code.
554	* @sa IOM_SUCCESS
555	*/
556	#ifdef IN_RING3
557	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
558	( (a_rcStrict) == VINF_SUCCESS \
559	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
560	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
561	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
562	)
563	#elif defined(IN_RING0)
564	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
565	( (a_rcStrict) == VINF_SUCCESS \
566	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
567	\|\| (a_rcStrict) == VINF_EM_OFF \
568	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
569	\|\| (a_rcStrict) == VINF_EM_RESET \
570	\|\| (a_rcStrict) == VINF_EM_HALT \
571	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
572	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
573	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
574	)
575	#elif defined(IN_RC)
576	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
577	( (a_rcStrict) == VINF_SUCCESS \
578	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
579	\|\| (a_rcStrict) == VINF_EM_OFF \
580	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
581	\|\| (a_rcStrict) == VINF_EM_RESET \
582	\|\| (a_rcStrict) == VINF_EM_HALT \
583	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
584	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
585	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
586	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
587	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
588	)
589	#endif
590	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
591	* Updates the return code with a new result.
592	*
593	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
594	*
595	* @param a_rcStrict The current return code, to be updated.
596	* @param a_rcStrict2 The new return code to merge in.
597	*/
598	#ifdef IN_RING3
599	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
600	do { \
601	Assert(rcStrict == VINF_SUCCESS); \
602	Assert(rcStrict2 == VINF_SUCCESS); \
603	} while (0)
604	#elif defined(IN_RING0)
605	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
606	do { \
607	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
608	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
609	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
610	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
611	{ /* likely */ } \
612	else if ( (a_rcStrict) == VINF_SUCCESS \
613	\|\| (a_rcStrict) > (a_rcStrict2)) \
614	(a_rcStrict) = (a_rcStrict2); \
615	} while (0)
616	#elif defined(IN_RC)
617	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
618	do { \
619	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
620	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
621	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
622	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
623	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
624	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
625	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
626	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
627	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
628	{ /* likely */ } \
629	else if ((a_rcStrict) == VINF_SUCCESS) \
630	(a_rcStrict) = (a_rcStrict2); \
631	else if ( ( (a_rcStrict) > (a_rcStrict2) \
632	&& ( (a_rcStrict2) <= VINF_EM_RESET \
633	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
634	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
635	&& (a_rcStrict) > VINF_EM_RESET) ) \
636	(a_rcStrict) = (a_rcStrict2); \
637	} while (0)
638	#endif
639
640	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
641	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
642	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
643	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
644
645	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
646	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
647	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
648	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
649	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
650	VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
651	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
652	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
653
654	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
655	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVM pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
656	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
657	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
658	R3PTRTYPE(uint8_t ) ppb,
659	#else
660	R3R0PTRTYPE(uint8_t ) ppb,
661	#endif
662	uint64_t *pfTlb);
663	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
664	* @{ */
665	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
666	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
667	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
668	/** @} */
669
670	/** Information returned by PGMPhysNemQueryPageInfo. */
671	typedef struct PGMPHYSNEMPAGEINFO
672	{
673	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
674	RTHCPHYS HCPhys;
675	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
676	uint32_t fNemProt : 8;
677	/** The NEM state associated with the PAGE. */
678	uint32_t u2NemState : 2;
679	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
680	uint32_t u2OldNemState : 2;
681	/** Set if the page has handler. */
682	uint32_t fHasHandlers : 1;
683	/** Set if is the zero page backing it. */
684	uint32_t fZeroPage : 1;
685	/** Set if the page has handler. */
686	PGMPAGETYPE enmType;
687	} PGMPHYSNEMPAGEINFO;
688	/** Pointer to page information for NEM. */
689	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
690	/**
691	* Callback for checking that the page is in sync while under the PGM lock.
692	*
693	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
694	* in-sync between PGM and the native hypervisor API in an atomic fashion.
695	*
696	* @returns VBox status code.
697	* @param pVM The cross context VM structure.
698	* @param pVCpu The cross context per virtual CPU structure. Optional,
699	* see PGMPhysNemQueryPageInfo.
700	* @param GCPhys The guest physical address (not A20 masked).
701	* @param pInfo The page info structure. This function updates the
702	* u2NemState memory and the caller will update the PGMPAGE
703	* copy accordingly.
704	* @param pvUser Callback user argument.
705	*/
706	typedef DECLCALLBACK(int) FNPGMPHYSNEMCHECKPAGE(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser);
707	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
708	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
709
710	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
711	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
712
713	/**
714	* Callback for use with PGMPhysNemEnumPagesByState.
715	* @returns VBox status code.
716	* Failure status will stop enumeration immediately and return.
717	* @param pVM The cross context VM structure.
718	* @param pVCpu The cross context per virtual CPU structure. Optional,
719	* see PGMPhysNemEnumPagesByState.
720	* @param GCPhys The guest physical address (not A20 masked).
721	* @param pu2NemState Pointer to variable with the NEM state. This can be
722	* update.
723	* @param pvUser The user argument.
724	*/
725	typedef DECLCALLBACK(int) FNPGMPHYSNEMENUMCALLBACK(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint8_t pu2NemState, void pvUser);
726	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
727	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
728	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVM pVM, PVMCPU VCpu, uint8_t uMinState,
729	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
730
731
732	#ifdef VBOX_STRICT
733	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
734	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
735	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
736	#endif /* VBOX_STRICT */
737
738	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
739	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
740	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
741	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
742	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
743	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
744	#endif
745
746	VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages);
747
748	/**
749	* Query large page usage state
750	*
751	* @returns 0 - disabled, 1 - enabled
752	* @param pVM The cross context VM structure.
753	*/
754	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
755
756
757	#ifdef IN_RC
758	/** @defgroup grp_pgm_gc The PGM Guest Context API
759	* @{
760	*/
761	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
762	/** @} */
763	#endif /* IN_RC */
764
765
766	#ifdef IN_RING0
767	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
768	* @{
769	*/
770	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, PVM pVM, VMCPUID idCpu);
771	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, PVM pVM, VMCPUID idCpu);
772	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PGVM pGVM, PVM pVM, VMCPUID idCpu);
773	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM, PVM pVM);
774	VMMR0DECL(int) PGMR0SharedModuleCheck(PVM pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule, PCRTGCPTR64 paRegionsGCPtrs);
775	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
776	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
777	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
778	VMMR0DECL(int) PGMR0DynMapInit(void);
779	VMMR0DECL(void) PGMR0DynMapTerm(void);
780	VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
781	VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
782	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
783	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu);
784	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu);
785	# endif
786	/** @} */
787	#endif /* IN_RING0 */
788
789
790
791	#ifdef IN_RING3
792	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
793	* @{
794	*/
795	VMMR3DECL(int) PGMR3Init(PVM pVM);
796	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
797	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
798	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
799	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
800	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
801	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
802	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
803	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
804	VMMR3DECL(int) PGMR3Term(PVM pVM);
805	VMMR3DECL(int) PGMR3LockCall(PVM pVM);
806
807	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
808	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
809	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
810	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
811	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
812	const char *ppszDesc, bool pfIsMmio);
813	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
814	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
815
816	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
817	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
818	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
819	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc);
820	VMMR3DECL(int) PGMR3PhysMMIOExPreRegister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion, PGMPHYSHANDLERTYPE hType,
821	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
822	VMMR3DECL(int) PGMR3PhysMMIOExDeregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion);
823	VMMR3DECL(int) PGMR3PhysMMIOExMap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
824	VMMR3DECL(int) PGMR3PhysMMIOExUnmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
825	VMMR3_INT_DECL(int) PGMR3PhysMMIOExReduce(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion);
826	VMMR3DECL(bool) PGMR3PhysMMIOExIsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
827	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
828	VMMR3_INT_DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
829	VMMR3_INT_DECL(int) PGMR3PhysMMIOExChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, uint32_t iNewRegion);
830
831
832	/** @name PGMR3PhysRegisterRom flags.
833	* @{ */
834	/** Inidicates that ROM shadowing should be enabled. */
835	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
836	/** Indicates that what pvBinary points to won't go away
837	* and can be used for strictness checks. */
838	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
839	/** @} */
840
841	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
842	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
843	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
844	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
845	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
846	/** @name PGMR3MapPT flags.
847	* @{ */
848	/** The mapping may be unmapped later. The default is permanent mappings. */
849	#define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
850	/** @} */
851	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
852	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
853	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
854	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
855	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
856	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
857	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
858	#if defined(VBOX_WITH_RAW_MODE) \|\| HC_ARCH_BITS == 32 /* (latter for 64-bit guests on 32-bit hosts) */
859	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
860	#endif
861	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
862
863	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
864	PFNPGMPHYSHANDLER pfnHandlerR3,
865	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
866	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
867	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC,
868	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC,
869	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
870	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
871	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
872	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
873	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
874	const char *pszDesc,
875	PPGMPHYSHANDLERTYPE phType);
876	#ifdef VBOX_WITH_RAW_MODE
877	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegisterEx(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
878	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
879	PFNPGMVIRTHANDLER pfnHandlerR3,
880	RCPTRTYPE(FNPGMVIRTHANDLER) pfnHandlerRC,
881	RCPTRTYPE(FNPGMRCVIRTPFHANDLER) pfnPfHandlerRC,
882	const char *pszDesc, PPGMVIRTHANDLERTYPE phType);
883	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegister(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
884	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
885	PFNPGMVIRTHANDLER pfnHandlerR3,
886	const char pszHandlerRC, const char pszPfHandlerRC, const char *pszDesc,
887	PPGMVIRTHANDLERTYPE phType);
888	VMMR3_INT_DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PVMCPU pVCpu, PGMVIRTHANDLERTYPE hType, RTGCPTR GCPtr,
889	RTGCPTR GCPtrLast, void pvUserR3, RTRCPTR pvUserRC, const char pszDesc);
890	VMMR3_INT_DECL(int) PGMHandlerVirtualChangeType(PVM pVM, RTGCPTR GCPtr, PGMVIRTHANDLERTYPE hNewType);
891	VMMR3_INT_DECL(int) PGMHandlerVirtualDeregister(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, bool fHypervisor);
892	#endif
893	VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
894
895	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
896	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
897	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
898	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
899	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
900	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
901	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
902	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
903	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
904	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
905	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
906	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
907	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
908	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
909	void **papvPages, PPGMPAGEMAPLOCK paLocks);
910	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
911	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
912	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
913	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
914	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
915	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
916
917	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
918
919	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
920	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
921	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
922	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
923	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
924	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
925	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
926	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
927	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
928	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
929	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
930
931
932	/** @name Page sharing
933	* @{ */
934	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
935	RTGCPTR GCBaseAddr, uint32_t cbModule,
936	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
937	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
938	RTGCPTR GCBaseAddr, uint32_t cbModule);
939	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
940	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
941	/** @} */
942
943	/** @} */
944	#endif /* IN_RING3 */
945
946	RT_C_DECLS_END
947
948	/** @} */
949	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
950

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 80074

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