1 | /* $Id: pdmpcidevint.h 96407 2022-08-22 17:43:14Z vboxsync $ */
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2 | /** @file
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3 | * DevPCI - PDM PCI Internal header - Only for hiding bits of PDMPCIDEV.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2022 Oracle and/or its affiliates.
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8 | *
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9 | * This file is part of VirtualBox base platform packages, as
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10 | * available from https://www.virtualbox.org.
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11 | *
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12 | * This program is free software; you can redistribute it and/or
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13 | * modify it under the terms of the GNU General Public License
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14 | * as published by the Free Software Foundation, in version 3 of the
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15 | * License.
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16 | *
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17 | * This program is distributed in the hope that it will be useful, but
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18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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20 | * General Public License for more details.
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21 | *
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22 | * You should have received a copy of the GNU General Public License
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23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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24 | *
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25 | * The contents of this file may alternatively be used under the terms
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26 | * of the Common Development and Distribution License Version 1.0
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27 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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28 | * in the VirtualBox distribution, in which case the provisions of the
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29 | * CDDL are applicable instead of those of the GPL.
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30 | *
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31 | * You may elect to license modified versions of this file under the
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32 | * terms and conditions of either the GPL or the CDDL or both.
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33 | *
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34 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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35 | */
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36 |
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37 | #ifndef VBOX_INCLUDED_vmm_pdmpcidevint_h
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38 | #define VBOX_INCLUDED_vmm_pdmpcidevint_h
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39 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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40 | # pragma once
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41 | #endif
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42 |
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43 | #include <VBox/vmm/pdmdev.h>
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44 |
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45 | /** @defgroup grp_pdm_pcidev_int The PDM PCI Device Internals
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46 | * @ingroup grp_pdm_pcidev
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47 | *
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48 | * @remarks The PDM PCI device internals are visible to both PDM and the PCI Bus
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49 | * implementation, thus it lives among the the public headers despite
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50 | * being rather private and internal.
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51 | *
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52 | * @{
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53 | */
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54 |
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55 |
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56 | /**
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57 | * PCI I/O region.
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58 | */
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59 | typedef struct PCIIOREGION
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60 | {
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61 | /** Current PCI mapping address, INVALID_PCI_ADDRESS (0xffffffff) means not mapped. */
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62 | uint64_t addr;
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63 | /** The region size. Power of 2. */
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64 | uint64_t size;
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65 | /** Handle or UINT64_MAX (see PDMPCIDEV_IORGN_F_HANDLE_MASK in fFlags). */
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66 | uint64_t hHandle;
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67 | /** PDMPCIDEV_IORGN_F_XXXX. */
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68 | uint32_t fFlags;
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69 | /** PCIADDRESSSPACE */
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70 | uint8_t type;
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71 | uint8_t abPadding0[3];
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72 | /** Callback called when the region is mapped or unmapped (new style devs). */
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73 | R3PTRTYPE(PFNPCIIOREGIONMAP) pfnMap;
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74 | #if R3_ARCH_BITS == 32
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75 | uint32_t u32Padding2;
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76 | #endif
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77 | } PCIIOREGION;
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78 | AssertCompileSize(PCIIOREGION, 5*8);
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79 | /** Pointer to a PCI I/O region. */
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80 | typedef PCIIOREGION *PPCIIOREGION;
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81 | /** Pointer to a const PCI I/O region. */
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82 | typedef PCIIOREGION const *PCPCIIOREGION;
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83 |
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84 | /**
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85 | * Callback function for reading from the PCI configuration space.
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86 | *
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87 | * @returns Strict VBox status code.
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88 | * @param pDevIns Pointer to the device instance of the PCI bus.
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89 | * @param iBus The bus number this device is on.
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90 | * @param iDevice The number of the device on the bus.
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91 | * @param u32Address The configuration space register address. [0..255]
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92 | * @param cb The register size. [1,2,4]
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93 | * @param pu32Value Where to return the register value.
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94 | */
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95 | typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPCIBRIDGECONFIGREAD,(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
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96 | uint32_t u32Address, unsigned cb, uint32_t *pu32Value));
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97 | /** Pointer to a FNPCICONFIGREAD() function. */
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98 | typedef FNPCIBRIDGECONFIGREAD *PFNPCIBRIDGECONFIGREAD;
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99 | #if !RT_CLANG_PREREQ(11, 0) /* Clang 11 (at least) has trouble with nothrow and pointers to function pointers. */
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100 | /** Pointer to a PFNPCICONFIGREAD. */
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101 | typedef PFNPCIBRIDGECONFIGREAD *PPFNPCIBRIDGECONFIGREAD;
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102 | #endif
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103 |
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104 | /**
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105 | * Callback function for writing to the PCI configuration space.
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106 | *
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107 | * @returns Strict VBox status code.
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108 | * @param pDevIns Pointer to the device instance of the PCI bus.
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109 | * @param iBus The bus number this device is on.
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110 | * @param iDevice The number of the device on the bus.
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111 | * @param u32Address The configuration space register address. [0..255]
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112 | * @param cb The register size. [1,2,4]
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113 | * @param u32Value The value that's being written. The number of bits actually used from
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114 | * this value is determined by the cb parameter.
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115 | */
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116 | typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPCIBRIDGECONFIGWRITE,(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
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117 | uint32_t u32Address, unsigned cb, uint32_t u32Value));
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118 | /** Pointer to a FNPCICONFIGWRITE() function. */
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119 | typedef FNPCIBRIDGECONFIGWRITE *PFNPCIBRIDGECONFIGWRITE;
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120 | #if !RT_CLANG_PREREQ(11, 0) /* Clang 11 (at least) has trouble with nothrow and pointers to function pointers. */
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121 | /** Pointer to a PFNPCICONFIGWRITE. */
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122 | typedef PFNPCIBRIDGECONFIGWRITE *PPFNPCIBRIDGECONFIGWRITE;
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123 | #endif
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124 |
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125 | /* Forward declaration */
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126 | struct DEVPCIBUS;
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127 |
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128 | enum {
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129 | /** Flag whether the device is a pci-to-pci bridge.
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130 | * This is set prior to device registration. */
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131 | PCIDEV_FLAG_PCI_TO_PCI_BRIDGE = RT_BIT_32(1),
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132 | /** Flag whether the device is a PCI Express device.
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133 | * This is set prior to device registration. */
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134 | PCIDEV_FLAG_PCI_EXPRESS_DEVICE = RT_BIT_32(2),
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135 | /** Flag whether the device is capable of MSI.
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136 | * This one is set by MsiInit(). */
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137 | PCIDEV_FLAG_MSI_CAPABLE = RT_BIT_32(3),
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138 | /** Flag whether the device is capable of MSI-X.
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139 | * This one is set by MsixInit(). */
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140 | PCIDEV_FLAG_MSIX_CAPABLE = RT_BIT_32(4),
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141 | /** Flag if device represents real physical device in passthrough mode. */
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142 | PCIDEV_FLAG_PASSTHROUGH = RT_BIT_32(5),
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143 | /** Flag whether the device is capable of MSI using 64-bit address. */
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144 | PCIDEV_FLAG_MSI64_CAPABLE = RT_BIT_32(6)
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145 |
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146 | };
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147 |
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148 |
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149 | /**
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150 | * PDM PCI Device - Internal data.
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151 | *
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152 | * @sa PDMPCIDEV
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153 | */
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154 | typedef struct PDMPCIDEVINT
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155 | {
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156 | /** @name Owned by PDM.
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157 | * @remarks The bus may use the device instance pointers.
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158 | * @{
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159 | */
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160 | /** Pointer to the PDM device the PCI device belongs to. (R3 ptr) */
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161 | PPDMDEVINSR3 pDevInsR3;
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162 | /** The CFGM device configuration index (default, PciDev1..255).
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163 | * This also works as the internal sub-device ordinal with MMIOEx.
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164 | * @note Same value as idxSubDev, can therefore be removed later. */
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165 | uint8_t idxDevCfg;
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166 | /** Set if the it can be reassigned to a different PCI device number. */
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167 | bool fReassignableDevNo;
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168 | /** Set if the it can be reassigned to a different PCI function number. */
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169 | bool fReassignableFunNo;
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170 | /** Alignment padding - used by ICH9 for region swapping (DevVGA hack). */
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171 | uint8_t bPadding0;
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172 | /** Index into the PDM internal bus array (PDM::aPciBuses). */
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173 | uint8_t idxPdmBus;
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174 | /** Set if this device has been registered. */
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175 | bool fRegistered;
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176 | /** Index into PDMDEVINSR3::apPciDevs (same as PDMPCIDEV::idxSubDev). */
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177 | uint16_t idxSubDev;
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178 | /** @} */
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179 |
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180 | /** @name Owned by the PCI Bus
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181 | * @remarks PDM will not touch anything here (includes not relocating anything).
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182 | * @{
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183 | */
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184 | /** Pointer to the PCI bus of the device. (R3 ptr) */
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185 | R3PTRTYPE(struct DEVPCIBUS *) pBusR3;
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186 | /** Read config callback. */
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187 | R3PTRTYPE(PFNPCICONFIGREAD) pfnConfigRead;
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188 | /** Write config callback. */
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189 | R3PTRTYPE(PFNPCICONFIGWRITE) pfnConfigWrite;
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190 | /** Read config callback for PCI bridges to pass requests
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191 | * to devices on another bus. */
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192 | R3PTRTYPE(PFNPCIBRIDGECONFIGREAD) pfnBridgeConfigRead;
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193 | /** Write config callback for PCI bridges to pass requests
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194 | * to devices on another bus. */
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195 | R3PTRTYPE(PFNPCIBRIDGECONFIGWRITE) pfnBridgeConfigWrite;
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196 |
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197 | /** Flags of this PCI device, see PCIDEV_FLAG_XXX constants. */
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198 | uint32_t fFlags;
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199 | /** Current state of the IRQ pin of the device. */
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200 | int32_t uIrqPinState;
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201 |
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202 | /** Offset of MSI PCI capability in config space, or 0.
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203 | * @todo fix non-standard naming. */
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204 | uint8_t u8MsiCapOffset;
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205 | /** Size of MSI PCI capability in config space, or 0.
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206 | * @todo fix non-standard naming. */
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207 | uint8_t u8MsiCapSize;
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208 | /** Offset of MSI-X PCI capability in config space, or 0.
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209 | * @todo fix non-standard naming. */
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210 | uint8_t u8MsixCapOffset;
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211 | /** Size of MSI-X PCI capability in config space, or 0.
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212 | * @todo fix non-standard naming. */
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213 | uint8_t u8MsixCapSize;
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214 | /** Size of the MSI-X region. */
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215 | uint16_t cbMsixRegion;
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216 | /** Offset to the PBA for MSI-X. */
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217 | uint16_t offMsixPba;
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218 | /** Add padding to align aIORegions to an 16 byte boundary. */
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219 | uint8_t abPadding2[HC_ARCH_BITS == 32 ? 12 : 8];
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220 | /** The MMIO handle for the MSI-X MMIO bar. */
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221 | IOMMMIOHANDLE hMmioMsix;
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222 |
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223 | /** Pointer to bus specific data. (R3 ptr) */
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224 | R3PTRTYPE(const void *) pvPciBusPtrR3;
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225 | /** I/O regions. */
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226 | PCIIOREGION aIORegions[VBOX_PCI_NUM_REGIONS];
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227 | /** @} */
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228 | } PDMPCIDEVINT;
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229 | AssertCompileMemberAlignment(PDMPCIDEVINT, aIORegions, 8);
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230 | AssertCompileSize(PDMPCIDEVINT, HC_ARCH_BITS == 32 ? 0x98 : 0x178);
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231 |
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232 | /** Indicate that PDMPCIDEV::Int.s can be declared. */
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233 | #define PDMPCIDEVINT_DECLARED
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234 |
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235 | /** @} */
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236 |
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237 | #endif /* !VBOX_INCLUDED_vmm_pdmpcidevint_h */
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238 |
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