pdmdev.h@ 87261

Last change on this file since 87261 was 87127, checked in by vboxsync, 4 years ago
DMA,PDM: Pass the pDevIns of the caller to PDMDMAREG::pfnRegister. DMA controller now locks all registered DMA devices before doing callbacks, as it is in the best position to deal with the lock order inversion issue. bugref:9888
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File size: 351.3 KB

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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
27	#define VBOX_INCLUDED_vmm_pdmdev_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmqueue.h>
34	#include <VBox/vmm/pdmtask.h>
35	#ifdef IN_RING3
36	# include <VBox/vmm/pdmthread.h>
37	#endif
38	#include <VBox/vmm/pdmifs.h>
39	#include <VBox/vmm/pdmins.h>
40	#include <VBox/vmm/pdmcommon.h>
41	#include <VBox/vmm/pdmpcidev.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/tm.h>
44	#include <VBox/vmm/ssm.h>
45	#include <VBox/vmm/cfgm.h>
46	#include <VBox/vmm/cpum.h>
47	#include <VBox/vmm/dbgf.h>
48	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
49	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
50	#include <VBox/msi.h>
51	#include <iprt/stdarg.h>
52	#include <iprt/list.h>
53
54
55	RT_C_DECLS_BEGIN
56
57	/** @defgroup grp_pdm_device The PDM Devices API
58	* @ingroup grp_pdm
59	* @{
60	*/
61
62	/**
63	* Construct a device instance for a VM.
64	*
65	* @returns VBox status.
66	* @param pDevIns The device instance data. If the registration structure
67	* is needed, it can be accessed thru pDevIns->pReg.
68	* @param iInstance Instance number. Use this to figure out which registers
69	* and such to use. The instance number is also found in
70	* pDevIns->iInstance, but since it's likely to be
71	* frequently used PDM passes it as parameter.
72	* @param pCfg Configuration node handle for the driver. This is
73	* expected to be in high demand in the constructor and is
74	* therefore passed as an argument. When using it at other
75	* times, it can be found in pDevIns->pCfg.
76	*/
77	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
78	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
79	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
80
81	/**
82	* Destruct a device instance.
83	*
84	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
85	* resources can be freed correctly.
86	*
87	* @returns VBox status.
88	* @param pDevIns The device instance data.
89	*
90	* @remarks The device critical section is not entered. The routine may delete
91	* the critical section, so the caller cannot exit it.
92	*/
93	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
94	/** Pointer to a FNPDMDEVDESTRUCT() function. */
95	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
96
97	/**
98	* Device relocation callback.
99	*
100	* This is called when the instance data has been relocated in raw-mode context
101	* (RC). It is also called when the RC hypervisor selects changes. The device
102	* must fixup all necessary pointers and re-query all interfaces to other RC
103	* devices and drivers.
104	*
105	* Before the RC code is executed the first time, this function will be called
106	* with a 0 delta so RC pointer calculations can be one in one place.
107	*
108	* @param pDevIns Pointer to the device instance.
109	* @param offDelta The relocation delta relative to the old location.
110	*
111	* @remarks A relocation CANNOT fail.
112	*
113	* @remarks The device critical section is not entered. The relocations should
114	* not normally require any locking.
115	*/
116	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
117	/** Pointer to a FNPDMDEVRELOCATE() function. */
118	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
119
120	/**
121	* Power On notification.
122	*
123	* @returns VBox status.
124	* @param pDevIns The device instance data.
125	*
126	* @remarks Caller enters the device critical section.
127	*/
128	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
129	/** Pointer to a FNPDMDEVPOWERON() function. */
130	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
131
132	/**
133	* Reset notification.
134	*
135	* @returns VBox status.
136	* @param pDevIns The device instance data.
137	*
138	* @remarks Caller enters the device critical section.
139	*/
140	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
141	/** Pointer to a FNPDMDEVRESET() function. */
142	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
143
144	/**
145	* Soft reset notification.
146	*
147	* This is mainly for emulating the 286 style protected mode exits, in which
148	* most devices should remain in their current state.
149	*
150	* @returns VBox status.
151	* @param pDevIns The device instance data.
152	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
153	*
154	* @remarks Caller enters the device critical section.
155	*/
156	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
157	/** Pointer to a FNPDMDEVSOFTRESET() function. */
158	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
159
160	/** @name PDMVMRESET_F_XXX - VM reset flags.
161	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
162	* reset via PDMDevHlpVMReset.
163	* @{ */
164	/** Unknown reason. */
165	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
166	/** GIM triggered reset. */
167	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
168	/** The last source always causing hard resets. */
169	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
170	/** ACPI triggered reset. */
171	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
172	/** PS/2 system port A (92h) reset. */
173	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
174	/** Keyboard reset. */
175	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
176	/** Tripple fault. */
177	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
178	/** Reset source mask. */
179	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
180	/** @} */
181
182	/**
183	* Suspend notification.
184	*
185	* @returns VBox status.
186	* @param pDevIns The device instance data.
187	* @thread EMT(0)
188	*
189	* @remarks Caller enters the device critical section.
190	*/
191	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
192	/** Pointer to a FNPDMDEVSUSPEND() function. */
193	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
194
195	/**
196	* Resume notification.
197	*
198	* @returns VBox status.
199	* @param pDevIns The device instance data.
200	*
201	* @remarks Caller enters the device critical section.
202	*/
203	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
204	/** Pointer to a FNPDMDEVRESUME() function. */
205	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
206
207	/**
208	* Power Off notification.
209	*
210	* This is always called when VMR3PowerOff is called.
211	* There will be no callback when hot plugging devices.
212	*
213	* @param pDevIns The device instance data.
214	* @thread EMT(0)
215	*
216	* @remarks Caller enters the device critical section.
217	*/
218	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
219	/** Pointer to a FNPDMDEVPOWEROFF() function. */
220	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
221
222	/**
223	* Attach command.
224	*
225	* This is called to let the device attach to a driver for a specified LUN
226	* at runtime. This is not called during VM construction, the device
227	* constructor has to attach to all the available drivers.
228	*
229	* This is like plugging in the keyboard or mouse after turning on the PC.
230	*
231	* @returns VBox status code.
232	* @param pDevIns The device instance.
233	* @param iLUN The logical unit which is being attached.
234	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
235	*
236	* @remarks Caller enters the device critical section.
237	*/
238	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
239	/** Pointer to a FNPDMDEVATTACH() function. */
240	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
241
242	/**
243	* Detach notification.
244	*
245	* This is called when a driver is detaching itself from a LUN of the device.
246	* The device should adjust its state to reflect this.
247	*
248	* This is like unplugging the network cable to use it for the laptop or
249	* something while the PC is still running.
250	*
251	* @param pDevIns The device instance.
252	* @param iLUN The logical unit which is being detached.
253	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
254	*
255	* @remarks Caller enters the device critical section.
256	*/
257	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
258	/** Pointer to a FNPDMDEVDETACH() function. */
259	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
260
261	/**
262	* Query the base interface of a logical unit.
263	*
264	* @returns VBOX status code.
265	* @param pDevIns The device instance.
266	* @param iLUN The logicial unit to query.
267	* @param ppBase Where to store the pointer to the base interface of the LUN.
268	*
269	* @remarks The device critical section is not entered.
270	*/
271	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
272	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
273	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
274
275	/**
276	* Init complete notification (after ring-0 & RC init since 5.1).
277	*
278	* This can be done to do communication with other devices and other
279	* initialization which requires everything to be in place.
280	*
281	* @returns VBOX status code.
282	* @param pDevIns The device instance.
283	*
284	* @remarks Caller enters the device critical section.
285	*/
286	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
287	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
288	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
289
290
291	/**
292	* The context of a pfnMemSetup call.
293	*/
294	typedef enum PDMDEVMEMSETUPCTX
295	{
296	/** Invalid zero value. */
297	PDMDEVMEMSETUPCTX_INVALID = 0,
298	/** After construction. */
299	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
300	/** After reset. */
301	PDMDEVMEMSETUPCTX_AFTER_RESET,
302	/** Type size hack. */
303	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
304	} PDMDEVMEMSETUPCTX;
305
306
307	/**
308	* PDM Device Registration Structure.
309	*
310	* This structure is used when registering a device from VBoxInitDevices() in HC
311	* Ring-3. PDM will continue use till the VM is terminated.
312	*
313	* @note The first part is the same in every context.
314	*/
315	typedef struct PDMDEVREGR3
316	{
317	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
318	uint32_t u32Version;
319	/** Reserved, must be zero. */
320	uint32_t uReserved0;
321	/** Device name, must match the ring-3 one. */
322	char szName[32];
323	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
324	uint32_t fFlags;
325	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
326	uint32_t fClass;
327	/** Maximum number of instances (per VM). */
328	uint32_t cMaxInstances;
329	/** The shared data structure version number. */
330	uint32_t uSharedVersion;
331	/** Size of the instance data. */
332	uint32_t cbInstanceShared;
333	/** Size of the ring-0 instance data. */
334	uint32_t cbInstanceCC;
335	/** Size of the raw-mode instance data. */
336	uint32_t cbInstanceRC;
337	/** Max number of PCI devices. */
338	uint16_t cMaxPciDevices;
339	/** Max number of MSI-X vectors in any of the PCI devices. */
340	uint16_t cMaxMsixVectors;
341	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
342	* remain unchanged from registration till VM destruction. */
343	const char *pszDescription;
344
345	/** Name of the raw-mode context module (no path).
346	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
347	const char *pszRCMod;
348	/** Name of the ring-0 module (no path).
349	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
350	const char *pszR0Mod;
351
352	/** Construct instance - required. */
353	PFNPDMDEVCONSTRUCT pfnConstruct;
354	/** Destruct instance - optional.
355	* Critical section NOT entered (will be destroyed). */
356	PFNPDMDEVDESTRUCT pfnDestruct;
357	/** Relocation command - optional.
358	* Critical section NOT entered. */
359	PFNPDMDEVRELOCATE pfnRelocate;
360	/**
361	* Memory setup callback.
362	*
363	* @param pDevIns The device instance data.
364	* @param enmCtx Indicates the context of the call.
365	* @remarks The critical section is entered prior to calling this method.
366	*/
367	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
368	/** Power on notification - optional.
369	* Critical section is entered. */
370	PFNPDMDEVPOWERON pfnPowerOn;
371	/** Reset notification - optional.
372	* Critical section is entered. */
373	PFNPDMDEVRESET pfnReset;
374	/** Suspend notification - optional.
375	* Critical section is entered. */
376	PFNPDMDEVSUSPEND pfnSuspend;
377	/** Resume notification - optional.
378	* Critical section is entered. */
379	PFNPDMDEVRESUME pfnResume;
380	/** Attach command - optional.
381	* Critical section is entered. */
382	PFNPDMDEVATTACH pfnAttach;
383	/** Detach notification - optional.
384	* Critical section is entered. */
385	PFNPDMDEVDETACH pfnDetach;
386	/** Query a LUN base interface - optional.
387	* Critical section is NOT entered. */
388	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
389	/** Init complete notification - optional.
390	* Critical section is entered. */
391	PFNPDMDEVINITCOMPLETE pfnInitComplete;
392	/** Power off notification - optional.
393	* Critical section is entered. */
394	PFNPDMDEVPOWEROFF pfnPowerOff;
395	/** Software system reset notification - optional.
396	* Critical section is entered. */
397	PFNPDMDEVSOFTRESET pfnSoftReset;
398
399	/** @name Reserved for future extensions, must be zero.
400	* @{ */
401	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
402	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
403	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
404	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
405	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
406	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
407	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
408	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
409	/** @} */
410
411	/** Initialization safty marker. */
412	uint32_t u32VersionEnd;
413	} PDMDEVREGR3;
414	/** Pointer to a PDM Device Structure. */
415	typedef PDMDEVREGR3 *PPDMDEVREGR3;
416	/** Const pointer to a PDM Device Structure. */
417	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
418	/** Current DEVREGR3 version number. */
419	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
420
421
422	/** PDM Device Flags.
423	* @{ */
424	/** This flag is used to indicate that the device has a R0 component. */
425	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
426	/** Requires the ring-0 component, ignore configuration values. */
427	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
428	/** Requires the ring-0 component, ignore configuration values. */
429	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
430
431	/** This flag is used to indicate that the device has a RC component. */
432	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
433	/** Requires the raw-mode component, ignore configuration values. */
434	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
435	/** Requires the raw-mode component, ignore configuration values. */
436	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
437
438	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
439	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
440
441	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
442	* The bit count for the current host.
443	* @note Superfluous, but still around for hysterical raisins. */
444	#if HC_ARCH_BITS == 32
445	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
446	#elif HC_ARCH_BITS == 64
447	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
448	#else
449	# error Unsupported HC_ARCH_BITS value.
450	#endif
451	/** The host bit count mask. */
452	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
453
454	/** The device support only 32-bit guests. */
455	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
456	/** The device support only 64-bit guests. */
457	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
458	/** The device support both 32-bit & 64-bit guests. */
459	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
460	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
461	* The guest bit count for the current compilation. */
462	#if GC_ARCH_BITS == 32
463	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
464	#elif GC_ARCH_BITS == 64
465	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
466	#else
467	# error Unsupported GC_ARCH_BITS value.
468	#endif
469	/** The guest bit count mask. */
470	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
471
472	/** A convenience. */
473	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
474
475	/** Indicates that the device needs to be notified before the drivers when suspending. */
476	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
477	/** Indicates that the device needs to be notified before the drivers when powering off. */
478	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
479	/** Indicates that the device needs to be notified before the drivers when resetting. */
480	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
481
482	/** This flag is used to indicate that the device has been converted to the
483	* new device style. */
484	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
485
486	/** @} */
487
488
489	/** PDM Device Classes.
490	* The order is important, lower bit earlier instantiation.
491	* @{ */
492	/** Architecture device. */
493	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
494	/** Architecture BIOS device. */
495	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
496	/** PCI bus brigde. */
497	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
498	/** PCI built-in device (e.g. PCI root complex devices). */
499	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
500	/** Input device (mouse, keyboard, joystick, HID, ...). */
501	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
502	/** Interrupt controller (PIC). */
503	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
504	/** Interval controoler (PIT). */
505	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
506	/** RTC/CMOS. */
507	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
508	/** DMA controller. */
509	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
510	/** VMM Device. */
511	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
512	/** Graphics device, like VGA. */
513	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
514	/** Storage controller device. */
515	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
516	/** Network interface controller. */
517	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
518	/** Audio. */
519	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
520	/** USB HIC. */
521	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
522	/** ACPI. */
523	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
524	/** Serial controller device. */
525	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
526	/** Parallel controller device */
527	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
528	/** Host PCI pass-through device */
529	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
530	/** Misc devices (always last). */
531	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
532	/** @} */
533
534
535	/**
536	* PDM Device Registration Structure, ring-0.
537	*
538	* This structure is used when registering a device from VBoxInitDevices() in HC
539	* Ring-0. PDM will continue use till the VM is terminated.
540	*/
541	typedef struct PDMDEVREGR0
542	{
543	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
544	uint32_t u32Version;
545	/** Reserved, must be zero. */
546	uint32_t uReserved0;
547	/** Device name, must match the ring-3 one. */
548	char szName[32];
549	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
550	uint32_t fFlags;
551	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
552	uint32_t fClass;
553	/** Maximum number of instances (per VM). */
554	uint32_t cMaxInstances;
555	/** The shared data structure version number. */
556	uint32_t uSharedVersion;
557	/** Size of the instance data. */
558	uint32_t cbInstanceShared;
559	/** Size of the ring-0 instance data. */
560	uint32_t cbInstanceCC;
561	/** Size of the raw-mode instance data. */
562	uint32_t cbInstanceRC;
563	/** Max number of PCI devices. */
564	uint16_t cMaxPciDevices;
565	/** Max number of MSI-X vectors in any of the PCI devices. */
566	uint16_t cMaxMsixVectors;
567	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
568	* remain unchanged from registration till VM destruction. */
569	const char *pszDescription;
570
571	/**
572	* Early construction callback (optional).
573	*
574	* This is called right after the device instance structure has been allocated
575	* and before the ring-3 constructor gets called.
576	*
577	* @returns VBox status code.
578	* @param pDevIns The device instance data.
579	* @note The destructure is always called, regardless of the return status.
580	*/
581	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
582
583	/**
584	* Regular construction callback (optional).
585	*
586	* This is called after (or during) the ring-3 constructor.
587	*
588	* @returns VBox status code.
589	* @param pDevIns The device instance data.
590	* @note The destructure is always called, regardless of the return status.
591	*/
592	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
593
594	/**
595	* Destructor (optional).
596	*
597	* This is called after the ring-3 destruction. This is not called if ring-3
598	* fails to trigger it (e.g. process is killed or crashes).
599	*
600	* @param pDevIns The device instance data.
601	*/
602	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
603
604	/**
605	* Final destructor (optional).
606	*
607	* This is called right before the memory is freed, which happens when the
608	* VM/GVM object is destroyed. This is always called.
609	*
610	* @param pDevIns The device instance data.
611	*/
612	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
613
614	/**
615	* Generic request handler (optional).
616	*
617	* @param pDevIns The device instance data.
618	* @param uReq Device specific request.
619	* @param uArg Request argument.
620	*/
621	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
622
623	/** @name Reserved for future extensions, must be zero.
624	* @{ */
625	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
626	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
627	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
628	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
629	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
630	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
631	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
632	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
633	/** @} */
634
635	/** Initialization safty marker. */
636	uint32_t u32VersionEnd;
637	} PDMDEVREGR0;
638	/** Pointer to a ring-0 PDM device registration structure. */
639	typedef PDMDEVREGR0 *PPDMDEVREGR0;
640	/** Pointer to a const ring-0 PDM device registration structure. */
641	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
642	/** Current DEVREGR0 version number. */
643	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
644
645
646	/**
647	* PDM Device Registration Structure, raw-mode
648	*
649	* At the moment, this structure is mostly here to match the other two contexts.
650	*/
651	typedef struct PDMDEVREGRC
652	{
653	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
654	uint32_t u32Version;
655	/** Reserved, must be zero. */
656	uint32_t uReserved0;
657	/** Device name, must match the ring-3 one. */
658	char szName[32];
659	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
660	uint32_t fFlags;
661	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
662	uint32_t fClass;
663	/** Maximum number of instances (per VM). */
664	uint32_t cMaxInstances;
665	/** The shared data structure version number. */
666	uint32_t uSharedVersion;
667	/** Size of the instance data. */
668	uint32_t cbInstanceShared;
669	/** Size of the ring-0 instance data. */
670	uint32_t cbInstanceCC;
671	/** Size of the raw-mode instance data. */
672	uint32_t cbInstanceRC;
673	/** Max number of PCI devices. */
674	uint16_t cMaxPciDevices;
675	/** Max number of MSI-X vectors in any of the PCI devices. */
676	uint16_t cMaxMsixVectors;
677	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
678	* remain unchanged from registration till VM destruction. */
679	const char *pszDescription;
680
681	/**
682	* Constructor callback.
683	*
684	* This is called much later than both the ring-0 and ring-3 constructors, since
685	* raw-mode v2 require a working VMM to run actual code.
686	*
687	* @returns VBox status code.
688	* @param pDevIns The device instance data.
689	* @note The destructure is always called, regardless of the return status.
690	*/
691	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
692
693	/** @name Reserved for future extensions, must be zero.
694	* @{ */
695	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
696	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
697	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
698	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
699	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
700	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
701	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
702	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
703	/** @} */
704
705	/** Initialization safty marker. */
706	uint32_t u32VersionEnd;
707	} PDMDEVREGRC;
708	/** Pointer to a raw-mode PDM device registration structure. */
709	typedef PDMDEVREGRC *PPDMDEVREGRC;
710	/** Pointer to a const raw-mode PDM device registration structure. */
711	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
712	/** Current DEVREGRC version number. */
713	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
714
715
716
717	/** @def PDM_DEVREG_VERSION
718	* Current DEVREG version number. */
719	/** @typedef PDMDEVREGR3
720	* A current context PDM device registration structure. */
721	/** @typedef PPDMDEVREGR3
722	* Pointer to a current context PDM device registration structure. */
723	/** @typedef PCPDMDEVREGR3
724	* Pointer to a const current context PDM device registration structure. */
725	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
726	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
727	typedef PDMDEVREGR3 PDMDEVREG;
728	typedef PPDMDEVREGR3 PPDMDEVREG;
729	typedef PCPDMDEVREGR3 PCPDMDEVREG;
730	#elif defined(IN_RING0)
731	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
732	typedef PDMDEVREGR0 PDMDEVREG;
733	typedef PPDMDEVREGR0 PPDMDEVREG;
734	typedef PCPDMDEVREGR0 PCPDMDEVREG;
735	#elif defined(IN_RC)
736	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
737	typedef PDMDEVREGRC PDMDEVREG;
738	typedef PPDMDEVREGRC PPDMDEVREG;
739	typedef PCPDMDEVREGRC PCPDMDEVREG;
740	#else
741	# error "Not IN_RING3, IN_RING0 or IN_RC"
742	#endif
743
744
745	/**
746	* Device registrations for ring-0 modules.
747	*
748	* This structure is used directly and must therefore reside in persistent
749	* memory (i.e. the data section).
750	*/
751	typedef struct PDMDEVMODREGR0
752	{
753	/** The structure version (PDM_DEVMODREGR0_VERSION). */
754	uint32_t u32Version;
755	/** Number of devices in the array papDevRegs points to. */
756	uint32_t cDevRegs;
757	/** Pointer to device registration structures. */
758	PCPDMDEVREGR0 *papDevRegs;
759	/** The ring-0 module handle - PDM internal, fingers off. */
760	void *hMod;
761	/** List entry - PDM internal, fingers off. */
762	RTLISTNODE ListEntry;
763	} PDMDEVMODREGR0;
764	/** Pointer to device registriations for a ring-0 module. */
765	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
766	/** Current PDMDEVMODREGR0 version number. */
767	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
768
769
770	/** @name IRQ Level for use with the *SetIrq APIs.
771	* @{
772	*/
773	/** Assert the IRQ (can assume value 1). */
774	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
775	/** Deassert the IRQ (can assume value 0). */
776	#define PDM_IRQ_LEVEL_LOW 0
777	/** flip-flop - deassert and then assert the IRQ again immediately. */
778	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
779	/** @} */
780
781	/**
782	* Registration record for MSI/MSI-X emulation.
783	*/
784	typedef struct PDMMSIREG
785	{
786	/** Number of MSI interrupt vectors, 0 if MSI not supported */
787	uint16_t cMsiVectors;
788	/** Offset of MSI capability */
789	uint8_t iMsiCapOffset;
790	/** Offset of next capability to MSI */
791	uint8_t iMsiNextOffset;
792	/** If we support 64-bit MSI addressing */
793	bool fMsi64bit;
794	/** If we do not support per-vector masking */
795	bool fMsiNoMasking;
796
797	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
798	uint16_t cMsixVectors;
799	/** Offset of MSI-X capability */
800	uint8_t iMsixCapOffset;
801	/** Offset of next capability to MSI-X */
802	uint8_t iMsixNextOffset;
803	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
804	uint8_t iMsixBar;
805	} PDMMSIREG;
806	typedef PDMMSIREG *PPDMMSIREG;
807
808	/**
809	* PCI Bus registration structure.
810	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
811	*/
812	typedef struct PDMPCIBUSREGR3
813	{
814	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
815	uint32_t u32Version;
816
817	/**
818	* Registers the device with the default PCI bus.
819	*
820	* @returns VBox status code.
821	* @param pDevIns Device instance of the PCI Bus.
822	* @param pPciDev The PCI device structure.
823	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
824	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
825	* device number (0-31).
826	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
827	* function number (0-7).
828	* @param pszName Device name (static but not unique).
829	*
830	* @remarks Caller enters the PDM critical section.
831	*/
832	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
833	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
834
835	/**
836	* Initialize MSI or MSI-X emulation support in a PCI device.
837	*
838	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
839	* vast majority of device emulation it covers everything necessary. It's
840	* fully automatic, taking care of all BAR and config space requirements,
841	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
842	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
843	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
844	*
845	* A device not using this can still offer MSI/MSI-X. In this case it's
846	* completely up to the device (in the MSI-X case) to create/register the
847	* necessary MMIO BAR, handle all config space/BAR updating and take care
848	* of delivering the interrupts appropriately.
849	*
850	* @returns VBox status code.
851	* @param pDevIns Device instance of the PCI Bus.
852	* @param pPciDev The PCI device structure.
853	* @param pMsiReg MSI emulation registration structure
854	* @remarks Caller enters the PDM critical section.
855	*/
856	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
857
858	/**
859	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
860	*
861	* @returns VBox status code.
862	* @param pDevIns Device instance of the PCI Bus.
863	* @param pPciDev The PCI device structure.
864	* @param iRegion The region number.
865	* @param cbRegion Size of the region.
866	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
867	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
868	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
869	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
870	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
871	* @a fFlags, UINT64_MAX if no handle is passed
872	* (old style).
873	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
874	* is given.
875	* @remarks Caller enters the PDM critical section.
876	*/
877	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
878	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
879	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
880
881	/**
882	* Register PCI configuration space read/write intercept callbacks.
883	*
884	* @param pDevIns Device instance of the PCI Bus.
885	* @param pPciDev The PCI device structure.
886	* @param pfnRead Pointer to the user defined PCI config read function.
887	* @param pfnWrite Pointer to the user defined PCI config write function.
888	* to call default PCI config write function. Can be NULL.
889	* @remarks Caller enters the PDM critical section.
890	* @thread EMT
891	*/
892	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
893	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
894
895	/**
896	* Perform a PCI configuration space write, bypassing interception.
897	*
898	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
899	*
900	* @returns Strict VBox status code (mainly DBGFSTOP).
901	* @param pDevIns Device instance of the PCI Bus.
902	* @param pPciDev The PCI device which config space is being read.
903	* @param uAddress The config space address.
904	* @param cb The size of the read: 1, 2 or 4 bytes.
905	* @param u32Value The value to write.
906	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
907	* that the (root) bus will have done that already.
908	*/
909	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
910	uint32_t uAddress, unsigned cb, uint32_t u32Value));
911
912	/**
913	* Perform a PCI configuration space read, bypassing interception.
914	*
915	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
916	*
917	* @returns Strict VBox status code (mainly DBGFSTOP).
918	* @param pDevIns Device instance of the PCI Bus.
919	* @param pPciDev The PCI device which config space is being read.
920	* @param uAddress The config space address.
921	* @param cb The size of the read: 1, 2 or 4 bytes.
922	* @param pu32Value Where to return the value.
923	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
924	* that the (root) bus will have done that already.
925	*/
926	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
927	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
928
929	/**
930	* Set the IRQ for a PCI device.
931	*
932	* @param pDevIns Device instance of the PCI Bus.
933	* @param pPciDev The PCI device structure.
934	* @param iIrq IRQ number to set.
935	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
936	* @param uTagSrc The IRQ tag and source (for tracing).
937	* @remarks Caller enters the PDM critical section.
938	*/
939	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
940
941	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
942	uint32_t u32EndVersion;
943	} PDMPCIBUSREGR3;
944	/** Pointer to a PCI bus registration structure. */
945	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
946	/** Current PDMPCIBUSREGR3 version number. */
947	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
948
949	/**
950	* PCI Bus registration structure for ring-0.
951	*/
952	typedef struct PDMPCIBUSREGR0
953	{
954	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
955	uint32_t u32Version;
956	/** The PCI bus number (from ring-3 registration). */
957	uint32_t iBus;
958	/**
959	* Set the IRQ for a PCI device.
960	*
961	* @param pDevIns Device instance of the PCI Bus.
962	* @param pPciDev The PCI device structure.
963	* @param iIrq IRQ number to set.
964	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
965	* @param uTagSrc The IRQ tag and source (for tracing).
966	* @remarks Caller enters the PDM critical section.
967	*/
968	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
969	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
970	uint32_t u32EndVersion;
971	} PDMPCIBUSREGR0;
972	/** Pointer to a PCI bus ring-0 registration structure. */
973	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
974	/** Current PDMPCIBUSREGR0 version number. */
975	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
976
977	/**
978	* PCI Bus registration structure for raw-mode.
979	*/
980	typedef struct PDMPCIBUSREGRC
981	{
982	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
983	uint32_t u32Version;
984	/** The PCI bus number (from ring-3 registration). */
985	uint32_t iBus;
986	/**
987	* Set the IRQ for a PCI device.
988	*
989	* @param pDevIns Device instance of the PCI Bus.
990	* @param pPciDev The PCI device structure.
991	* @param iIrq IRQ number to set.
992	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
993	* @param uTagSrc The IRQ tag and source (for tracing).
994	* @remarks Caller enters the PDM critical section.
995	*/
996	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
997	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
998	uint32_t u32EndVersion;
999	} PDMPCIBUSREGRC;
1000	/** Pointer to a PCI bus raw-mode registration structure. */
1001	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1002	/** Current PDMPCIBUSREGRC version number. */
1003	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1004
1005	/** PCI bus registration structure for the current context. */
1006	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1007	/** Pointer to a PCI bus registration structure for the current context. */
1008	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1009	/** PCI bus registration structure version for the current context. */
1010	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1011
1012
1013	/**
1014	* PCI Bus RC helpers.
1015	*/
1016	typedef struct PDMPCIHLPRC
1017	{
1018	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1019	uint32_t u32Version;
1020
1021	/**
1022	* Set an ISA IRQ.
1023	*
1024	* @param pDevIns PCI device instance.
1025	* @param iIrq IRQ number to set.
1026	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1027	* @param uTagSrc The IRQ tag and source (for tracing).
1028	* @thread EMT only.
1029	*/
1030	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1031
1032	/**
1033	* Set an I/O-APIC IRQ.
1034	*
1035	* @param pDevIns PCI device instance.
1036	* @param uBusDevFn The bus:device:function of the device initiating the
1037	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1038	* interrupt.
1039	* @param iIrq IRQ number to set.
1040	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1041	* @param uTagSrc The IRQ tag and source (for tracing).
1042	* @thread EMT only.
1043	*/
1044	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1045
1046	/**
1047	* Send an MSI.
1048	*
1049	* @param pDevIns PCI device instance.
1050	* @param uBusDevFn The bus:device:function of the device initiating the
1051	* MSI. Cannot be NIL_PCIBDF.
1052	* @param pMsi The MSI to send.
1053	* @param uTagSrc The IRQ tag and source (for tracing).
1054	* @thread EMT only.
1055	*/
1056	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1057
1058
1059	/**
1060	* Acquires the PDM lock.
1061	*
1062	* @returns VINF_SUCCESS on success.
1063	* @returns rc if we failed to acquire the lock.
1064	* @param pDevIns The PCI device instance.
1065	* @param rc What to return if we fail to acquire the lock.
1066	*/
1067	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1068
1069	/**
1070	* Releases the PDM lock.
1071	*
1072	* @param pDevIns The PCI device instance.
1073	*/
1074	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1075
1076	/**
1077	* Gets a bus by it's PDM ordinal (typically the parent bus).
1078	*
1079	* @returns Pointer to the device instance of the bus.
1080	* @param pDevIns The PCI bus device instance.
1081	* @param idxPdmBus The PDM ordinal value of the bus to get.
1082	*/
1083	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1084
1085	/** Just a safety precaution. */
1086	uint32_t u32TheEnd;
1087	} PDMPCIHLPRC;
1088	/** Pointer to PCI helpers. */
1089	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1090	/** Pointer to const PCI helpers. */
1091	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1092
1093	/** Current PDMPCIHLPRC version number. */
1094	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1095
1096
1097	/**
1098	* PCI Bus R0 helpers.
1099	*/
1100	typedef struct PDMPCIHLPR0
1101	{
1102	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1103	uint32_t u32Version;
1104
1105	/**
1106	* Set an ISA IRQ.
1107	*
1108	* @param pDevIns PCI device instance.
1109	* @param iIrq IRQ number to set.
1110	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1111	* @param uTagSrc The IRQ tag and source (for tracing).
1112	* @thread EMT only.
1113	*/
1114	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1115
1116	/**
1117	* Set an I/O-APIC IRQ.
1118	*
1119	* @param pDevIns PCI device instance.
1120	* @param uBusDevFn The bus:device:function of the device initiating the
1121	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1122	* interrupt.
1123	* @param iIrq IRQ number to set.
1124	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1125	* @param uTagSrc The IRQ tag and source (for tracing).
1126	* @thread EMT only.
1127	*/
1128	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1129
1130	/**
1131	* Send an MSI.
1132	*
1133	* @param pDevIns PCI device instance.
1134	* @param uBusDevFn The bus:device:function of the device initiating the
1135	* MSI. Cannot be NIL_PCIBDF.
1136	* @param pMsi The MSI to send.
1137	* @param uTagSrc The IRQ tag and source (for tracing).
1138	* @thread EMT only.
1139	*/
1140	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1141
1142	/**
1143	* Acquires the PDM lock.
1144	*
1145	* @returns VINF_SUCCESS on success.
1146	* @returns rc if we failed to acquire the lock.
1147	* @param pDevIns The PCI device instance.
1148	* @param rc What to return if we fail to acquire the lock.
1149	*/
1150	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1151
1152	/**
1153	* Releases the PDM lock.
1154	*
1155	* @param pDevIns The PCI device instance.
1156	*/
1157	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1158
1159	/**
1160	* Gets a bus by it's PDM ordinal (typically the parent bus).
1161	*
1162	* @returns Pointer to the device instance of the bus.
1163	* @param pDevIns The PCI bus device instance.
1164	* @param idxPdmBus The PDM ordinal value of the bus to get.
1165	*/
1166	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1167
1168	/** Just a safety precaution. */
1169	uint32_t u32TheEnd;
1170	} PDMPCIHLPR0;
1171	/** Pointer to PCI helpers. */
1172	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1173	/** Pointer to const PCI helpers. */
1174	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1175
1176	/** Current PDMPCIHLPR0 version number. */
1177	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1178
1179	/**
1180	* PCI device helpers.
1181	*/
1182	typedef struct PDMPCIHLPR3
1183	{
1184	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1185	uint32_t u32Version;
1186
1187	/**
1188	* Set an ISA IRQ.
1189	*
1190	* @param pDevIns The PCI device instance.
1191	* @param iIrq IRQ number to set.
1192	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1193	* @param uTagSrc The IRQ tag and source (for tracing).
1194	*/
1195	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1196
1197	/**
1198	* Set an I/O-APIC IRQ.
1199	*
1200	* @param pDevIns The PCI device instance.
1201	* @param uBusDevFn The bus:device:function of the device initiating the
1202	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1203	* interrupt.
1204	* @param iIrq IRQ number to set.
1205	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1206	* @param uTagSrc The IRQ tag and source (for tracing).
1207	*/
1208	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1209
1210	/**
1211	* Send an MSI.
1212	*
1213	* @param pDevIns PCI device instance.
1214	* @param uBusDevFn The bus:device:function of the device initiating the
1215	* MSI. Cannot be NIL_PCIBDF.
1216	* @param pMsi The MSI to send.
1217	* @param uTagSrc The IRQ tag and source (for tracing).
1218	*/
1219	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1220
1221	/**
1222	* Acquires the PDM lock.
1223	*
1224	* @returns VINF_SUCCESS on success.
1225	* @returns Fatal error on failure.
1226	* @param pDevIns The PCI device instance.
1227	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1228	*/
1229	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1230
1231	/**
1232	* Releases the PDM lock.
1233	*
1234	* @param pDevIns The PCI device instance.
1235	*/
1236	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1237
1238	/**
1239	* Gets a bus by it's PDM ordinal (typically the parent bus).
1240	*
1241	* @returns Pointer to the device instance of the bus.
1242	* @param pDevIns The PCI bus device instance.
1243	* @param idxPdmBus The PDM ordinal value of the bus to get.
1244	*/
1245	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1246
1247	/** Just a safety precaution. */
1248	uint32_t u32TheEnd;
1249	} PDMPCIHLPR3;
1250	/** Pointer to PCI helpers. */
1251	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1252	/** Pointer to const PCI helpers. */
1253	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1254
1255	/** Current PDMPCIHLPR3 version number. */
1256	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1257
1258
1259	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1260	* These flags are used for memory access transactions via the IOMMU interface.
1261	* @{ */
1262	/** Memory read. */
1263	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1264	/** Memory write. */
1265	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1266	/** Valid flag mask. */
1267	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1268	/** @} */
1269
1270	/**
1271	* IOMMU registration structure for ring-0.
1272	*/
1273	typedef struct PDMIOMMUREGR0
1274	{
1275	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1276	* version. */
1277	uint32_t u32Version;
1278	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1279	uint32_t idxIommu;
1280
1281	/**
1282	* Translates the physical address for a memory transaction through the IOMMU.
1283	*
1284	* @returns VBox status code.
1285	* @param pDevIns The IOMMU device instance.
1286	* @param uDevId The device identifier (bus, device, function).
1287	* @param uIova The I/O virtual address being accessed.
1288	* @param cbAccess The number of bytes being accessed.
1289	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1290	* @param pGCPhysSpa Where to store the translated system physical address.
1291	*
1292	* @thread Any.
1293	*/
1294	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
1295	uint32_t fFlags, PRTGCPHYS pGCPhysSpa));
1296
1297	/**
1298	* Translates in bulk physical page addresses for memory transactions through the
1299	* IOMMU.
1300	*
1301	* @returns VBox status code.
1302	* @param pDevIns The IOMMU device instance.
1303	* @param uDevId The device identifier (bus, device, function).
1304	* @param cIovas The number of I/O virtual addresses being accessed.
1305	* @param pauIovas The I/O virtual addresses being accessed.
1306	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1307	* @param paGCPhysSpa Where to store the translated system physical page
1308	* addresses.
1309	*
1310	* @thread Any.
1311	*/
1312	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
1313	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1314
1315	/**
1316	* Performs an interrupt remap request through the IOMMU.
1317	*
1318	* @returns VBox status code.
1319	* @param pDevIns The IOMMU device instance.
1320	* @param uDevId The device identifier (bus, device, function).
1321	* @param pMsiIn The source MSI.
1322	* @param pMsiOut Where to store the remapped MSI.
1323	*
1324	* @thread Any.
1325	*/
1326	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1327
1328	/** Just a safety precaution. */
1329	uint32_t u32TheEnd;
1330	} PDMIOMMUREGR0;
1331	/** Pointer to a IOMMU registration structure. */
1332	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1333
1334	/** Current PDMIOMMUREG version number. */
1335	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 2, 0)
1336
1337
1338	/**
1339	* IOMMU registration structure for raw-mode.
1340	*/
1341	typedef struct PDMIOMMUREGRC
1342	{
1343	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1344	* version. */
1345	uint32_t u32Version;
1346	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1347	uint32_t idxIommu;
1348
1349	/**
1350	* Translates the physical address for a memory transaction through the IOMMU.
1351	*
1352	* @returns VBox status code.
1353	* @param pDevIns The IOMMU device instance.
1354	* @param uDevId The device identifier (bus, device, function).
1355	* @param uIova The I/O virtual address being accessed.
1356	* @param cbAccess The number of bytes being accessed.
1357	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1358	* @param pGCPhysSpa Where to store the translated system physical address.
1359	*
1360	* @thread Any.
1361	*/
1362	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
1363	uint32_t fFlags, PRTGCPHYS pGCPhysSpa));
1364
1365	/**
1366	* Translates in bulk physical page addresses for memory transactions through the
1367	* IOMMU.
1368	*
1369	* @returns VBox status code.
1370	* @param pDevIns The IOMMU device instance.
1371	* @param uDevId The device identifier (bus, device, function).
1372	* @param cIovas The number of I/O virtual addresses being accessed.
1373	* @param pauIovas The I/O virtual addresses being accessed.
1374	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1375	* @param paGCPhysSpa Where to store the translated system physical page
1376	* addresses.
1377	*
1378	* @thread Any.
1379	*/
1380	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
1381	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1382
1383	/**
1384	* Performs an interrupt remap request through the IOMMU.
1385	*
1386	* @returns VBox status code.
1387	* @param pDevIns The IOMMU device instance.
1388	* @param uDevId The device identifier (bus, device, function).
1389	* @param pMsiIn The source MSI.
1390	* @param pMsiOut Where to store the remapped MSI.
1391	*
1392	* @thread Any.
1393	*/
1394	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1395
1396	/** Just a safety precaution. */
1397	uint32_t u32TheEnd;
1398	} PDMIOMMUREGRC;
1399	/** Pointer to a IOMMU registration structure. */
1400	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1401
1402	/** Current PDMIOMMUREG version number. */
1403	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 2, 0)
1404
1405
1406	/**
1407	* IOMMU registration structure for ring-3.
1408	*/
1409	typedef struct PDMIOMMUREGR3
1410	{
1411	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1412	* version. */
1413	uint32_t u32Version;
1414	/** Padding. */
1415	uint32_t uPadding0;
1416
1417	/**
1418	* Translates the physical address for a memory transaction through the IOMMU.
1419	*
1420	* @returns VBox status code.
1421	* @param pDevIns The IOMMU device instance.
1422	* @param uDevId The device identifier (bus, device, function).
1423	* @param uIova The I/O virtual address being accessed.
1424	* @param cbAccess The number of bytes being accessed.
1425	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1426	* @param pGCPhysSpa Where to store the translated system physical address.
1427	*
1428	* @thread Any.
1429	*/
1430	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
1431	uint32_t fFlags, PRTGCPHYS pGCPhysSpa));
1432
1433	/**
1434	* Translates in bulk physical page addresses for memory transactions through the
1435	* IOMMU.
1436	*
1437	* @returns VBox status code.
1438	* @param pDevIns The IOMMU device instance.
1439	* @param uDevId The device identifier (bus, device, function).
1440	* @param cIovas The number of I/O virtual addresses being accessed.
1441	* @param pauIovas The I/O virtual addresses being accessed.
1442	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1443	* @param paGCPhysSpa Where to store the translated system physical page
1444	* addresses.
1445	*
1446	* @thread Any.
1447	*/
1448	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
1449	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1450
1451	/**
1452	* Performs an interrupt remap request through the IOMMU.
1453	*
1454	* @returns VBox status code.
1455	* @param pDevIns The IOMMU device instance.
1456	* @param uDevId The device identifier (bus, device, function).
1457	* @param pMsiIn The source MSI.
1458	* @param pMsiOut Where to store the remapped MSI.
1459	*
1460	* @thread Any.
1461	*/
1462	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1463
1464	/** Just a safety precaution. */
1465	uint32_t u32TheEnd;
1466	} PDMIOMMUREGR3;
1467	/** Pointer to a IOMMU registration structure. */
1468	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1469
1470	/** Current PDMIOMMUREG version number. */
1471	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 2, 0)
1472
1473	/** IOMMU registration structure for the current context. */
1474	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1475	/** Pointer to an IOMMU registration structure for the current context. */
1476	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1477	/** IOMMU registration structure version for the current context. */
1478	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1479
1480
1481	/**
1482	* IOMMU helpers for ring-0.
1483	*/
1484	typedef struct PDMIOMMUHLPR0
1485	{
1486	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1487	uint32_t u32Version;
1488	/** Just a safety precaution. */
1489	uint32_t u32TheEnd;
1490	} PDMIOMMUHLPR0;
1491	/** Pointer to IOMMU helpers for ring-0. */
1492	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1493	/** Pointer to const IOMMU helpers for ring-0. */
1494	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1495
1496	/** Current PDMIOMMUHLPR0 version number. */
1497	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 1, 0)
1498
1499
1500	/**
1501	* IOMMU helpers for raw-mode.
1502	*/
1503	typedef struct PDMIOMMUHLPRC
1504	{
1505	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1506	uint32_t u32Version;
1507	/** Just a safety precaution. */
1508	uint32_t u32TheEnd;
1509	} PDMIOMMUHLPRC;
1510	/** Pointer to IOMMU helpers for raw-mode. */
1511	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1512	/** Pointer to const IOMMU helpers for raw-mode. */
1513	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1514
1515	/** Current PDMIOMMUHLPRC version number. */
1516	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 1, 0)
1517
1518
1519	/**
1520	* IOMMU helpers for ring-3.
1521	*/
1522	typedef struct PDMIOMMUHLPR3
1523	{
1524	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1525	uint32_t u32Version;
1526	/** Just a safety precaution. */
1527	uint32_t u32TheEnd;
1528	} PDMIOMMUHLPR3;
1529	/** Pointer to IOMMU helpers for raw-mode. */
1530	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1531	/** Pointer to const IOMMU helpers for raw-mode. */
1532	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1533
1534	/** Current PDMIOMMUHLPR3 version number. */
1535	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 1, 0)
1536
1537
1538	/**
1539	* Programmable Interrupt Controller registration structure (all contexts).
1540	*/
1541	typedef struct PDMPICREG
1542	{
1543	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1544	uint32_t u32Version;
1545
1546	/**
1547	* Set the an IRQ.
1548	*
1549	* @param pDevIns Device instance of the PIC.
1550	* @param iIrq IRQ number to set.
1551	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1552	* @param uTagSrc The IRQ tag and source (for tracing).
1553	* @remarks Caller enters the PDM critical section.
1554	*/
1555	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1556
1557	/**
1558	* Get a pending interrupt.
1559	*
1560	* @returns Pending interrupt number.
1561	* @param pDevIns Device instance of the PIC.
1562	* @param puTagSrc Where to return the IRQ tag and source.
1563	* @remarks Caller enters the PDM critical section.
1564	*/
1565	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1566
1567	/** Just a safety precaution. */
1568	uint32_t u32TheEnd;
1569	} PDMPICREG;
1570	/** Pointer to a PIC registration structure. */
1571	typedef PDMPICREG *PPDMPICREG;
1572
1573	/** Current PDMPICREG version number. */
1574	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1575
1576	/**
1577	* PIC helpers, same in all contexts.
1578	*/
1579	typedef struct PDMPICHLP
1580	{
1581	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1582	uint32_t u32Version;
1583
1584	/**
1585	* Set the interrupt force action flag.
1586	*
1587	* @param pDevIns Device instance of the PIC.
1588	*/
1589	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1590
1591	/**
1592	* Clear the interrupt force action flag.
1593	*
1594	* @param pDevIns Device instance of the PIC.
1595	*/
1596	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1597
1598	/**
1599	* Acquires the PDM lock.
1600	*
1601	* @returns VINF_SUCCESS on success.
1602	* @returns rc if we failed to acquire the lock.
1603	* @param pDevIns The PIC device instance.
1604	* @param rc What to return if we fail to acquire the lock.
1605	*/
1606	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1607
1608	/**
1609	* Releases the PDM lock.
1610	*
1611	* @param pDevIns The PIC device instance.
1612	*/
1613	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1614
1615	/** Just a safety precaution. */
1616	uint32_t u32TheEnd;
1617	} PDMPICHLP;
1618	/** Pointer to PIC helpers. */
1619	typedef PDMPICHLP *PPDMPICHLP;
1620	/** Pointer to const PIC helpers. */
1621	typedef const PDMPICHLP *PCPDMPICHLP;
1622
1623	/** Current PDMPICHLP version number. */
1624	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1625
1626
1627	/**
1628	* Firmware registration structure.
1629	*/
1630	typedef struct PDMFWREG
1631	{
1632	/** Struct version+magic number (PDM_FWREG_VERSION). */
1633	uint32_t u32Version;
1634
1635	/**
1636	* Checks whether this is a hard or soft reset.
1637	*
1638	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1639	* is 5, 9 or 0xA.
1640	*
1641	* @returns true if hard reset, false if soft.
1642	* @param pDevIns Device instance of the firmware.
1643	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1644	*/
1645	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1646
1647	/** Just a safety precaution. */
1648	uint32_t u32TheEnd;
1649	} PDMFWREG;
1650	/** Pointer to a FW registration structure. */
1651	typedef PDMFWREG *PPDMFWREG;
1652	/** Pointer to a const FW registration structure. */
1653	typedef PDMFWREG const *PCPDMFWREG;
1654
1655	/** Current PDMFWREG version number. */
1656	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1657
1658	/**
1659	* Firmware R3 helpers.
1660	*/
1661	typedef struct PDMFWHLPR3
1662	{
1663	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1664	uint32_t u32Version;
1665
1666	/** Just a safety precaution. */
1667	uint32_t u32TheEnd;
1668	} PDMFWHLPR3;
1669
1670	/** Pointer to FW R3 helpers. */
1671	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1672	/** Pointer to const FW R3 helpers. */
1673	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1674
1675	/** Current PDMFWHLPR3 version number. */
1676	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1677
1678
1679	/**
1680	* APIC mode argument for apicR3SetCpuIdFeatureLevel.
1681	*
1682	* Also used in saved-states, CFGM don't change existing values.
1683	*/
1684	typedef enum PDMAPICMODE
1685	{
1686	/** Invalid 0 entry. */
1687	PDMAPICMODE_INVALID = 0,
1688	/** No APIC. */
1689	PDMAPICMODE_NONE,
1690	/** Standard APIC (X86_CPUID_FEATURE_EDX_APIC). */
1691	PDMAPICMODE_APIC,
1692	/** Intel X2APIC (X86_CPUID_FEATURE_ECX_X2APIC). */
1693	PDMAPICMODE_X2APIC,
1694	/** The usual 32-bit paranoia. */
1695	PDMAPICMODE_32BIT_HACK = 0x7fffffff
1696	} PDMAPICMODE;
1697
1698	/**
1699	* APIC irq argument for pfnSetInterruptFF and pfnClearInterruptFF.
1700	*/
1701	typedef enum PDMAPICIRQ
1702	{
1703	/** Invalid 0 entry. */
1704	PDMAPICIRQ_INVALID = 0,
1705	/** Normal hardware interrupt. */
1706	PDMAPICIRQ_HARDWARE,
1707	/** NMI. */
1708	PDMAPICIRQ_NMI,
1709	/** SMI. */
1710	PDMAPICIRQ_SMI,
1711	/** ExtINT (HW interrupt via PIC). */
1712	PDMAPICIRQ_EXTINT,
1713	/** Interrupt arrived, needs to be updated to the IRR. */
1714	PDMAPICIRQ_UPDATE_PENDING,
1715	/** The usual 32-bit paranoia. */
1716	PDMAPICIRQ_32BIT_HACK = 0x7fffffff
1717	} PDMAPICIRQ;
1718
1719
1720	/**
1721	* I/O APIC registration structure (all contexts).
1722	*/
1723	typedef struct PDMIOAPICREG
1724	{
1725	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1726	uint32_t u32Version;
1727
1728	/**
1729	* Set an IRQ.
1730	*
1731	* @param pDevIns Device instance of the I/O APIC.
1732	* @param uBusDevFn The bus:device:function of the device initiating the
1733	* IRQ. Can be NIL_PCIBDF.
1734	* @param iIrq IRQ number to set.
1735	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1736	* @param uTagSrc The IRQ tag and source (for tracing).
1737	*
1738	* @remarks Caller enters the PDM critical section
1739	* Actually, as per 2018-07-21 this isn't true (bird).
1740	*/
1741	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1742
1743	/**
1744	* Send a MSI.
1745	*
1746	* @param pDevIns Device instance of the I/O APIC.
1747	* @param uBusDevFn The bus:device:function of the device initiating the
1748	* MSI. Cannot be NIL_PCIBDF.
1749	* @param pMsi The MSI to send.
1750	* @param uTagSrc The IRQ tag and source (for tracing).
1751	*
1752	* @remarks Caller enters the PDM critical section
1753	* Actually, as per 2018-07-21 this isn't true (bird).
1754	*/
1755	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1756
1757	/**
1758	* Set the EOI for an interrupt vector.
1759	*
1760	* @returns Strict VBox status code - only the following informational status codes:
1761	* @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
1762	* @retval VINF_SUCCESS
1763	*
1764	* @param pDevIns Device instance of the I/O APIC.
1765	* @param u8Vector The vector.
1766	*
1767	* @remarks Caller enters the PDM critical section
1768	* Actually, as per 2018-07-21 this isn't true (bird).
1769	*/
1770	DECLCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1771
1772	/** Just a safety precaution. */
1773	uint32_t u32TheEnd;
1774	} PDMIOAPICREG;
1775	/** Pointer to an APIC registration structure. */
1776	typedef PDMIOAPICREG *PPDMIOAPICREG;
1777
1778	/** Current PDMAPICREG version number. */
1779	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 7, 0)
1780
1781
1782	/**
1783	* IOAPIC helpers, same in all contexts.
1784	*/
1785	typedef struct PDMIOAPICHLP
1786	{
1787	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1788	uint32_t u32Version;
1789
1790	/**
1791	* Private interface between the IOAPIC and APIC.
1792	*
1793	* @returns status code.
1794	* @param pDevIns Device instance of the IOAPIC.
1795	* @param u8Dest See APIC implementation.
1796	* @param u8DestMode See APIC implementation.
1797	* @param u8DeliveryMode See APIC implementation.
1798	* @param uVector See APIC implementation.
1799	* @param u8Polarity See APIC implementation.
1800	* @param u8TriggerMode See APIC implementation.
1801	* @param uTagSrc The IRQ tag and source (for tracing).
1802	*
1803	* @sa APICBusDeliver()
1804	*/
1805	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1806	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1807
1808	/**
1809	* Acquires the PDM lock.
1810	*
1811	* @returns VINF_SUCCESS on success.
1812	* @returns rc if we failed to acquire the lock.
1813	* @param pDevIns The IOAPIC device instance.
1814	* @param rc What to return if we fail to acquire the lock.
1815	*/
1816	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1817
1818	/**
1819	* Releases the PDM lock.
1820	*
1821	* @param pDevIns The IOAPIC device instance.
1822	*/
1823	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1824
1825	/**
1826	* Private interface between the IOAPIC and IOMMU.
1827	*
1828	* @returns status code.
1829	* @param pDevIns Device instance of the IOAPIC.
1830	* @param uDevId The device ID (bus, device, function) for the source MSI.
1831	* @param pMsiIn The source MSI.
1832	* @param pMsiOut Where to store the remapped MSI.
1833	*
1834	* @sa iommuAmdDeviceMsiRemap().
1835	*/
1836	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevIt, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1837
1838	/** Just a safety precaution. */
1839	uint32_t u32TheEnd;
1840	} PDMIOAPICHLP;
1841	/** Pointer to IOAPIC helpers. */
1842	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1843	/** Pointer to const IOAPIC helpers. */
1844	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1845
1846	/** Current PDMIOAPICHLP version number. */
1847	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 2, 1)
1848
1849
1850	/**
1851	* HPET registration structure.
1852	*/
1853	typedef struct PDMHPETREG
1854	{
1855	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1856	uint32_t u32Version;
1857	} PDMHPETREG;
1858	/** Pointer to an HPET registration structure. */
1859	typedef PDMHPETREG *PPDMHPETREG;
1860
1861	/** Current PDMHPETREG version number. */
1862	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1863
1864	/**
1865	* HPET RC helpers.
1866	*
1867	* @remarks Keep this around in case HPET will need PDM interaction in again RC
1868	* at some later point.
1869	*/
1870	typedef struct PDMHPETHLPRC
1871	{
1872	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
1873	uint32_t u32Version;
1874
1875	/** Just a safety precaution. */
1876	uint32_t u32TheEnd;
1877	} PDMHPETHLPRC;
1878
1879	/** Pointer to HPET RC helpers. */
1880	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
1881	/** Pointer to const HPET RC helpers. */
1882	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
1883
1884	/** Current PDMHPETHLPRC version number. */
1885	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
1886
1887
1888	/**
1889	* HPET R0 helpers.
1890	*
1891	* @remarks Keep this around in case HPET will need PDM interaction in again R0
1892	* at some later point.
1893	*/
1894	typedef struct PDMHPETHLPR0
1895	{
1896	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
1897	uint32_t u32Version;
1898
1899	/** Just a safety precaution. */
1900	uint32_t u32TheEnd;
1901	} PDMHPETHLPR0;
1902
1903	/** Pointer to HPET R0 helpers. */
1904	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
1905	/** Pointer to const HPET R0 helpers. */
1906	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
1907
1908	/** Current PDMHPETHLPR0 version number. */
1909	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
1910
1911	/**
1912	* HPET R3 helpers.
1913	*/
1914	typedef struct PDMHPETHLPR3
1915	{
1916	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
1917	uint32_t u32Version;
1918
1919	/**
1920	* Set legacy mode on PIT and RTC.
1921	*
1922	* @returns VINF_SUCCESS on success.
1923	* @returns rc if we failed to set legacy mode.
1924	* @param pDevIns Device instance of the HPET.
1925	* @param fActivated Whether legacy mode is activated or deactivated.
1926	*/
1927	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
1928
1929
1930	/**
1931	* Set IRQ, bypassing ISA bus override rules.
1932	*
1933	* @returns VINF_SUCCESS on success.
1934	* @returns rc if we failed to set legacy mode.
1935	* @param pDevIns Device instance of the HPET.
1936	* @param iIrq IRQ number to set.
1937	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1938	*/
1939	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
1940
1941	/** Just a safety precaution. */
1942	uint32_t u32TheEnd;
1943	} PDMHPETHLPR3;
1944
1945	/** Pointer to HPET R3 helpers. */
1946	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
1947	/** Pointer to const HPET R3 helpers. */
1948	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
1949
1950	/** Current PDMHPETHLPR3 version number. */
1951	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
1952
1953
1954	/**
1955	* Raw PCI device registration structure.
1956	*/
1957	typedef struct PDMPCIRAWREG
1958	{
1959	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
1960	uint32_t u32Version;
1961	/** Just a safety precaution. */
1962	uint32_t u32TheEnd;
1963	} PDMPCIRAWREG;
1964	/** Pointer to a raw PCI registration structure. */
1965	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
1966
1967	/** Current PDMPCIRAWREG version number. */
1968	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
1969
1970	/**
1971	* Raw PCI device raw-mode context helpers.
1972	*/
1973	typedef struct PDMPCIRAWHLPRC
1974	{
1975	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
1976	uint32_t u32Version;
1977	/** Just a safety precaution. */
1978	uint32_t u32TheEnd;
1979	} PDMPCIRAWHLPRC;
1980	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
1981	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
1982	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
1983	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
1984
1985	/** Current PDMPCIRAWHLPRC version number. */
1986	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
1987
1988	/**
1989	* Raw PCI device ring-0 context helpers.
1990	*/
1991	typedef struct PDMPCIRAWHLPR0
1992	{
1993	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
1994	uint32_t u32Version;
1995	/** Just a safety precaution. */
1996	uint32_t u32TheEnd;
1997	} PDMPCIRAWHLPR0;
1998	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
1999	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2000	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2001	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2002
2003	/** Current PDMPCIRAWHLPR0 version number. */
2004	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2005
2006
2007	/**
2008	* Raw PCI device ring-3 context helpers.
2009	*/
2010	typedef struct PDMPCIRAWHLPR3
2011	{
2012	/** Undefined structure version and magic number. */
2013	uint32_t u32Version;
2014
2015	/**
2016	* Gets the address of the RC raw PCI device helpers.
2017	*
2018	* This should be called at both construction and relocation time to obtain
2019	* the correct address of the RC helpers.
2020	*
2021	* @returns RC pointer to the raw PCI device helpers.
2022	* @param pDevIns Device instance of the raw PCI device.
2023	*/
2024	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2025
2026	/**
2027	* Gets the address of the R0 raw PCI device helpers.
2028	*
2029	* This should be called at both construction and relocation time to obtain
2030	* the correct address of the R0 helpers.
2031	*
2032	* @returns R0 pointer to the raw PCI device helpers.
2033	* @param pDevIns Device instance of the raw PCI device.
2034	*/
2035	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2036
2037	/** Just a safety precaution. */
2038	uint32_t u32TheEnd;
2039	} PDMPCIRAWHLPR3;
2040	/** Pointer to raw PCI R3 helpers. */
2041	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2042	/** Pointer to const raw PCI R3 helpers. */
2043	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2044
2045	/** Current PDMPCIRAWHLPR3 version number. */
2046	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2047
2048
2049	#ifdef IN_RING3
2050
2051	/**
2052	* DMA Transfer Handler.
2053	*
2054	* @returns Number of bytes transferred.
2055	* @param pDevIns The device instance that registered the handler.
2056	* @param pvUser User pointer.
2057	* @param uChannel Channel number.
2058	* @param off DMA position.
2059	* @param cb Block size.
2060	* @remarks The device lock is take before the callback (in fact, the locks of
2061	* DMA devices and the DMA controller itself are taken).
2062	*/
2063	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2064	uint32_t off, uint32_t cb));
2065	/** Pointer to a FNDMATRANSFERHANDLER(). */
2066	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2067
2068	/**
2069	* DMA Controller registration structure.
2070	*/
2071	typedef struct PDMDMAREG
2072	{
2073	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2074	uint32_t u32Version;
2075
2076	/**
2077	* Execute pending transfers.
2078	*
2079	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2080	* @param pDevIns Device instance of the DMAC.
2081	* @remarks No locks held, called on EMT(0) as a form of serialization.
2082	*/
2083	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2084
2085	/**
2086	* Register transfer function for DMA channel.
2087	*
2088	* @param pDevIns Device instance of the DMAC.
2089	* @param uChannel Channel number.
2090	* @param pDevInsHandler The device instance of the device making the
2091	* regstration (will be passed to the callback).
2092	* @param pfnTransferHandler Device specific transfer function.
2093	* @param pvUser User pointer to be passed to the callback.
2094	* @remarks No locks held, called on an EMT.
2095	*/
2096	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2097	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2098
2099	/**
2100	* Read memory
2101	*
2102	* @returns Number of bytes read.
2103	* @param pDevIns Device instance of the DMAC.
2104	* @param uChannel Channel number.
2105	* @param pvBuffer Pointer to target buffer.
2106	* @param off DMA position.
2107	* @param cbBlock Block size.
2108	* @remarks No locks held, called on an EMT.
2109	*/
2110	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2111
2112	/**
2113	* Write memory
2114	*
2115	* @returns Number of bytes written.
2116	* @param pDevIns Device instance of the DMAC.
2117	* @param uChannel Channel number.
2118	* @param pvBuffer Memory to write.
2119	* @param off DMA position.
2120	* @param cbBlock Block size.
2121	* @remarks No locks held, called on an EMT.
2122	*/
2123	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2124
2125	/**
2126	* Set the DREQ line.
2127	*
2128	* @param pDevIns Device instance of the DMAC.
2129	* @param uChannel Channel number.
2130	* @param uLevel Level of the line.
2131	* @remarks No locks held, called on an EMT.
2132	*/
2133	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2134
2135	/**
2136	* Get channel mode
2137	*
2138	* @returns Channel mode.
2139	* @param pDevIns Device instance of the DMAC.
2140	* @param uChannel Channel number.
2141	* @remarks No locks held, called on an EMT.
2142	*/
2143	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2144
2145	} PDMDMACREG;
2146	/** Pointer to a DMAC registration structure. */
2147	typedef PDMDMACREG *PPDMDMACREG;
2148
2149	/** Current PDMDMACREG version number. */
2150	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2151
2152
2153	/**
2154	* DMA Controller device helpers.
2155	*/
2156	typedef struct PDMDMACHLP
2157	{
2158	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2159	uint32_t u32Version;
2160
2161	/* to-be-defined */
2162
2163	} PDMDMACHLP;
2164	/** Pointer to DMAC helpers. */
2165	typedef PDMDMACHLP *PPDMDMACHLP;
2166	/** Pointer to const DMAC helpers. */
2167	typedef const PDMDMACHLP *PCPDMDMACHLP;
2168
2169	/** Current PDMDMACHLP version number. */
2170	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2171
2172	#endif /* IN_RING3 */
2173
2174
2175
2176	/**
2177	* RTC registration structure.
2178	*/
2179	typedef struct PDMRTCREG
2180	{
2181	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2182	uint32_t u32Version;
2183	uint32_t u32Alignment; /*< structure size alignment. /
2184
2185	/**
2186	* Write to a CMOS register and update the checksum if necessary.
2187	*
2188	* @returns VBox status code.
2189	* @param pDevIns Device instance of the RTC.
2190	* @param iReg The CMOS register index.
2191	* @param u8Value The CMOS register value.
2192	* @remarks Caller enters the device critical section.
2193	*/
2194	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2195
2196	/**
2197	* Read a CMOS register.
2198	*
2199	* @returns VBox status code.
2200	* @param pDevIns Device instance of the RTC.
2201	* @param iReg The CMOS register index.
2202	* @param pu8Value Where to store the CMOS register value.
2203	* @remarks Caller enters the device critical section.
2204	*/
2205	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2206
2207	} PDMRTCREG;
2208	/** Pointer to a RTC registration structure. */
2209	typedef PDMRTCREG *PPDMRTCREG;
2210	/** Pointer to a const RTC registration structure. */
2211	typedef const PDMRTCREG *PCPDMRTCREG;
2212
2213	/** Current PDMRTCREG version number. */
2214	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2215
2216
2217	/**
2218	* RTC device helpers.
2219	*/
2220	typedef struct PDMRTCHLP
2221	{
2222	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2223	uint32_t u32Version;
2224
2225	/* to-be-defined */
2226
2227	} PDMRTCHLP;
2228	/** Pointer to RTC helpers. */
2229	typedef PDMRTCHLP *PPDMRTCHLP;
2230	/** Pointer to const RTC helpers. */
2231	typedef const PDMRTCHLP *PCPDMRTCHLP;
2232
2233	/** Current PDMRTCHLP version number. */
2234	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2235
2236
2237
2238	/** @name Flags for PCI I/O region registration
2239	* @{ */
2240	/** No handle is passed. */
2241	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2242	/** An I/O port handle is passed. */
2243	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2244	/** An MMIO range handle is passed. */
2245	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2246	/** An MMIO2 handle is passed. */
2247	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2248	/** Handle type mask. */
2249	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2250	/** New-style (mostly wrt callbacks). */
2251	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2252	/** Mask of valid flags. */
2253	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2254	/** @} */
2255
2256
2257	/** @name Flags for the guest physical read/write helpers
2258	* @{ */
2259	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2260	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2261	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2262	* by the device in any way. */
2263	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2264	/** The data is metadata and being processed by the device in some way. */
2265	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2266	/** @} */
2267
2268
2269	#ifdef IN_RING3
2270
2271	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2272	* @{ */
2273	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2274	* This is handy when registering multiple PCI device functions and the device
2275	* number is left up to the PCI bus. In order to facilitate one PDM device
2276	* instance for each PCI function, this searches earlier PDM device
2277	* instances as well. */
2278	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2279	/** Use the first unused device number (all functions must be unused). */
2280	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2281	/** Use the first unused device function. */
2282	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2283
2284	/** The device and function numbers are not mandatory, just suggestions. */
2285	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2286	/** Registering a PCI bridge device. */
2287	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2288	/** Valid flag mask. */
2289	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2290	/** @} */
2291
2292	/** Current PDMDEVHLPR3 version number. */
2293	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 45, 0)
2294
2295	/**
2296	* PDM Device API.
2297	*/
2298	typedef struct PDMDEVHLPR3
2299	{
2300	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2301	uint32_t u32Version;
2302
2303	/** @name I/O ports
2304	* @{ */
2305	/**
2306	* Creates a range of I/O ports for a device.
2307	*
2308	* The I/O port range must be mapped in a separately call. Any ring-0 and
2309	* raw-mode context callback handlers needs to be set up in the respective
2310	* contexts.
2311	*
2312	* @returns VBox status.
2313	* @param pDevIns The device instance to register the ports with.
2314	* @param cPorts Number of ports to register.
2315	* @param fFlags IOM_IOPORT_F_XXX.
2316	* @param pPciDev The PCI device the range is associated with, if
2317	* applicable.
2318	* @param iPciRegion The PCI device region in the high 16-bit word and
2319	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2320	* @param pfnOut Pointer to function which is gonna handle OUT
2321	* operations. Optional.
2322	* @param pfnIn Pointer to function which is gonna handle IN operations.
2323	* Optional.
2324	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2325	* operations. Optional.
2326	* @param pfnInStr Pointer to function which is gonna handle string IN
2327	* operations. Optional.
2328	* @param pvUser User argument to pass to the callbacks.
2329	* @param pszDesc Pointer to description string. This must not be freed.
2330	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2331	* coverage is allowed. This must not be freed.
2332	* @param phIoPorts Where to return the I/O port range handle.
2333	*
2334	* @remarks Caller enters the device critical section prior to invoking the
2335	* registered callback methods.
2336	*
2337	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2338	* PDMDevHlpIoPortUnmap.
2339	*/
2340	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2341	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2342	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2343	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2344
2345	/**
2346	* Maps an I/O port range.
2347	*
2348	* @returns VBox status.
2349	* @param pDevIns The device instance to register the ports with.
2350	* @param hIoPorts The I/O port range handle.
2351	* @param Port Where to map the range.
2352	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2353	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2354	*/
2355	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2356
2357	/**
2358	* Unmaps an I/O port range.
2359	*
2360	* @returns VBox status.
2361	* @param pDevIns The device instance to register the ports with.
2362	* @param hIoPorts The I/O port range handle.
2363	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2364	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2365	*/
2366	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2367
2368	/**
2369	* Gets the mapping address of the I/O port range @a hIoPorts.
2370	*
2371	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2372	* parameters).
2373	* @param pDevIns The device instance to register the ports with.
2374	* @param hIoPorts The I/O port range handle.
2375	*/
2376	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2377	/** @} */
2378
2379	/** @name MMIO
2380	* @{ */
2381	/**
2382	* Creates a memory mapped I/O (MMIO) region for a device.
2383	*
2384	* The MMIO region must be mapped in a separately call. Any ring-0 and
2385	* raw-mode context callback handlers needs to be set up in the respective
2386	* contexts.
2387	*
2388	* @returns VBox status.
2389	* @param pDevIns The device instance to register the ports with.
2390	* @param cbRegion The size of the region in bytes.
2391	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2392	* @param pPciDev The PCI device the range is associated with, if
2393	* applicable.
2394	* @param iPciRegion The PCI device region in the high 16-bit word and
2395	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2396	* @param pfnWrite Pointer to function which is gonna handle Write
2397	* operations.
2398	* @param pfnRead Pointer to function which is gonna handle Read
2399	* operations.
2400	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2401	* operations. (optional)
2402	* @param pvUser User argument to pass to the callbacks.
2403	* @param pszDesc Pointer to description string. This must not be freed.
2404	* @param phRegion Where to return the MMIO region handle.
2405	*
2406	* @remarks Caller enters the device critical section prior to invoking the
2407	* registered callback methods.
2408	*
2409	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2410	*/
2411	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2412	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2413	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2414	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2415
2416	/**
2417	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2418	*
2419	* @returns VBox status.
2420	* @param pDevIns The device instance the region is associated with.
2421	* @param hRegion The MMIO region handle.
2422	* @param GCPhys Where to map the region.
2423	* @note An MMIO range may overlap with base memory if a lot of RAM is
2424	* configured for the VM, in which case we'll drop the base memory
2425	* pages. Presently we will make no attempt to preserve anything that
2426	* happens to be present in the base memory that is replaced, this is
2427	* technically incorrect but it's just not worth the effort to do
2428	* right, at least not at this point.
2429	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2430	* PDMDevHlpMmioSetUpContext
2431	*/
2432	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2433
2434	/**
2435	* Unmaps a memory mapped I/O (MMIO) region.
2436	*
2437	* @returns VBox status.
2438	* @param pDevIns The device instance the region is associated with.
2439	* @param hRegion The MMIO region handle.
2440	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2441	* PDMDevHlpMmioSetUpContext
2442	*/
2443	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2444
2445	/**
2446	* Reduces the length of a MMIO range.
2447	*
2448	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2449	* only work during saved state restore. It will not call the PCI bus code, as
2450	* that is expected to restore the saved resource configuration.
2451	*
2452	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2453	* called it will only map @a cbRegion bytes and not the value set during
2454	* registration.
2455	*
2456	* @return VBox status code.
2457	* @param pDevIns The device owning the range.
2458	* @param hRegion The MMIO region handle.
2459	* @param cbRegion The new size, must be smaller.
2460	*/
2461	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2462
2463	/**
2464	* Gets the mapping address of the MMIO region @a hRegion.
2465	*
2466	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2467	* @param pDevIns The device instance to register the ports with.
2468	* @param hRegion The MMIO region handle.
2469	*/
2470	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2471	/** @} */
2472
2473	/** @name MMIO2
2474	* @{ */
2475	/**
2476	* Creates a MMIO2 region.
2477	*
2478	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2479	* associated with a device. It is also non-shared memory with a permanent
2480	* ring-3 mapping and page backing (presently).
2481	*
2482	* @returns VBox status.
2483	* @param pDevIns The device instance.
2484	* @param pPciDev The PCI device the region is associated with, or
2485	* NULL if no PCI device association.
2486	* @param iPciRegion The region number. Use the PCI region number as
2487	* this must be known to the PCI bus device too. If
2488	* it's not associated with the PCI device, then
2489	* any number up to UINT8_MAX is fine.
2490	* @param cbRegion The size (in bytes) of the region.
2491	* @param fFlags Reserved for future use, must be zero.
2492	* @param pszDesc Pointer to description string. This must not be
2493	* freed.
2494	* @param ppvMapping Where to store the address of the ring-3 mapping
2495	* of the memory.
2496	* @param phRegion Where to return the MMIO2 region handle.
2497	*
2498	* @thread EMT(0)
2499	*/
2500	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2501	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2502
2503	/**
2504	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2505	*
2506	* Any physical access handlers registered for the region must be deregistered
2507	* before calling this function.
2508	*
2509	* @returns VBox status code.
2510	* @param pDevIns The device instance.
2511	* @param hRegion The MMIO2 region handle.
2512	* @thread EMT.
2513	*/
2514	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2515
2516	/**
2517	* Maps a MMIO2 region (into the guest physical address space).
2518	*
2519	* @returns VBox status.
2520	* @param pDevIns The device instance the region is associated with.
2521	* @param hRegion The MMIO2 region handle.
2522	* @param GCPhys Where to map the region.
2523	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2524	* configured for the VM, in which case we'll drop the base memory
2525	* pages. Presently we will make no attempt to preserve anything that
2526	* happens to be present in the base memory that is replaced, this is
2527	* technically incorrect but it's just not worth the effort to do
2528	* right, at least not at this point.
2529	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2530	*/
2531	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2532
2533	/**
2534	* Unmaps a MMIO2 region.
2535	*
2536	* @returns VBox status.
2537	* @param pDevIns The device instance the region is associated with.
2538	* @param hRegion The MMIO2 region handle.
2539	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2540	*/
2541	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2542
2543	/**
2544	* Reduces the length of a MMIO range.
2545	*
2546	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2547	* only work during saved state restore. It will not call the PCI bus code, as
2548	* that is expected to restore the saved resource configuration.
2549	*
2550	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2551	* called it will only map @a cbRegion bytes and not the value set during
2552	* registration.
2553	*
2554	* @return VBox status code.
2555	* @param pDevIns The device owning the range.
2556	* @param hRegion The MMIO2 region handle.
2557	* @param cbRegion The new size, must be smaller.
2558	*/
2559	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2560
2561	/**
2562	* Gets the mapping address of the MMIO region @a hRegion.
2563	*
2564	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2565	* @param pDevIns The device instance to register the ports with.
2566	* @param hRegion The MMIO2 region handle.
2567	*/
2568	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2569
2570	/**
2571	* Changes the number of an MMIO2 or pre-registered MMIO region.
2572	*
2573	* This should only be used to deal with saved state problems, so there is no
2574	* convenience inline wrapper for this method.
2575	*
2576	* @returns VBox status code.
2577	* @param pDevIns The device instance.
2578	* @param hRegion The MMIO2 region handle.
2579	* @param iNewRegion The new region index.
2580	*
2581	* @sa @bugref{9359}
2582	*/
2583	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2584	/** @} */
2585
2586	/**
2587	* Register a ROM (BIOS) region.
2588	*
2589	* It goes without saying that this is read-only memory. The memory region must be
2590	* in unassigned memory. I.e. from the top of the address space or on the PC in
2591	* the 0xa0000-0xfffff range.
2592	*
2593	* @returns VBox status.
2594	* @param pDevIns The device instance owning the ROM region.
2595	* @param GCPhysStart First physical address in the range.
2596	* Must be page aligned!
2597	* @param cbRange The size of the range (in bytes).
2598	* Must be page aligned!
2599	* @param pvBinary Pointer to the binary data backing the ROM image.
2600	* @param cbBinary The size of the binary pointer. This must
2601	* be equal or smaller than @a cbRange.
2602	* @param fFlags Shadow ROM flags, PGMPHYS_ROM_FLAGS_* in pgm.h.
2603	* @param pszDesc Pointer to description string. This must not be freed.
2604	*
2605	* @remark There is no way to remove the rom, automatically on device cleanup or
2606	* manually from the device yet. At present I doubt we need such features...
2607	*/
2608	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2609	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2610
2611	/**
2612	* Changes the protection of shadowed ROM mapping.
2613	*
2614	* This is intented for use by the system BIOS, chipset or device in question to
2615	* change the protection of shadowed ROM code after init and on reset.
2616	*
2617	* @param pDevIns The device instance.
2618	* @param GCPhysStart Where the mapping starts.
2619	* @param cbRange The size of the mapping.
2620	* @param enmProt The new protection type.
2621	*/
2622	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2623
2624	/**
2625	* Register a save state data unit.
2626	*
2627	* @returns VBox status.
2628	* @param pDevIns The device instance.
2629	* @param uVersion Data layout version number.
2630	* @param cbGuess The approximate amount of data in the unit.
2631	* Only for progress indicators.
2632	* @param pszBefore Name of data unit which we should be put in
2633	* front of. Optional (NULL).
2634	*
2635	* @param pfnLivePrep Prepare live save callback, optional.
2636	* @param pfnLiveExec Execute live save callback, optional.
2637	* @param pfnLiveVote Vote live save callback, optional.
2638	*
2639	* @param pfnSavePrep Prepare save callback, optional.
2640	* @param pfnSaveExec Execute save callback, optional.
2641	* @param pfnSaveDone Done save callback, optional.
2642	*
2643	* @param pfnLoadPrep Prepare load callback, optional.
2644	* @param pfnLoadExec Execute load callback, optional.
2645	* @param pfnLoadDone Done load callback, optional.
2646	* @remarks Caller enters the device critical section prior to invoking the
2647	* registered callback methods.
2648	*/
2649	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2650	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2651	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2652	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2653
2654	/** @name Exported SSM Functions
2655	* @{ */
2656	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2657	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2658	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2659	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2660	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2661	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2662	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2663	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2664	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2665	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2666	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2667	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2668	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2669	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2670	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2671	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2672	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2673	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2674	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2675	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2676	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2677	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2678	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2679	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2680	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2681	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2682	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2683	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2684	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2685	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2686	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2687	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2688	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2689	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2690	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2691	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2692	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2693	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2694	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2695	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2696	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2697	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2698	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2699	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2700	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2701	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2702	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2703	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2704	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2705	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2706	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2707	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2708	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2709	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2710	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2711	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2712	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2713	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2714	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2715	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2716	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2717	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2718	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2719	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2720	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2721	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2722	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2723	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2724	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2725	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2726	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2727	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2728	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2729	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2730	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2731	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2732	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2733	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2734	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2735	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2736	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2737	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2738	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2739	/** @} */
2740
2741	/**
2742	* Creates a timer.
2743	*
2744	* @returns VBox status.
2745	* @param pDevIns The device instance.
2746	* @param enmClock The clock to use on this timer.
2747	* @param pfnCallback Callback function.
2748	* @param pvUser User argument for the callback.
2749	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2750	* @param pszDesc Pointer to description string which must stay around
2751	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2752	* @param ppTimer Where to store the timer on success.
2753	* @remarks Caller enters the device critical section prior to invoking the
2754	* callback.
2755	*/
2756	DECLR3CALLBACKMEMBER(int, pfnTMTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2757	void pvUser, uint32_t fFlags, const char pszDesc, PPTMTIMERR3 ppTimer));
2758
2759	/**
2760	* Creates a timer w/ a cross context handle.
2761	*
2762	* @returns VBox status.
2763	* @param pDevIns The device instance.
2764	* @param enmClock The clock to use on this timer.
2765	* @param pfnCallback Callback function.
2766	* @param pvUser User argument for the callback.
2767	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2768	* @param pszDesc Pointer to description string which must stay around
2769	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2770	* @param phTimer Where to store the timer handle on success.
2771	* @remarks Caller enters the device critical section prior to invoking the
2772	* callback.
2773	*/
2774	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2775	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2776
2777	/**
2778	* Translates a timer handle to a pointer.
2779	*
2780	* @returns The time address.
2781	* @param pDevIns The device instance.
2782	* @param hTimer The timer handle.
2783	*/
2784	DECLR3CALLBACKMEMBER(PTMTIMERR3, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2785
2786	/** @name Timer handle method wrappers
2787	* @{ */
2788	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2789	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2790	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2791	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2792	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2793	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2794	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2795	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2796	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
2797	/** Takes the clock lock then enters the specified critical section. */
2798	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
2799	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
2800	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
2801	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
2802	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
2803	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
2804	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
2805	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2806	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2807	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2808	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
2809	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2810	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
2811	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2812	/** @sa TMR3TimerSkip */
2813	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
2814	/** @} */
2815
2816	/**
2817	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
2818	*
2819	* @returns pTime.
2820	* @param pDevIns The device instance.
2821	* @param pTime Where to store the time.
2822	*/
2823	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
2824
2825	/** @name Exported CFGM Functions.
2826	* @{ */
2827	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
2828	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
2829	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
2830	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2831	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2832	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
2833	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
2834	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
2835	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
2836	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
2837	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
2838	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
2839	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
2840	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
2841	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
2842	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
2843	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
2844	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
2845	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
2846	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
2847	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
2848	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
2849	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
2850	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
2851	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
2852	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
2853	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
2854	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
2855	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
2856	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
2857	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
2858	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
2859	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtr,( PCFGMNODE pNode, const char pszName, void *ppv));
2860	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPtrDef,( PCFGMNODE pNode, const char pszName, void ppv, void pvDef));
2861	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
2862	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
2863	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
2864	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
2865	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
2866	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
2867	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
2868	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
2869	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
2870	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
2871	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
2872	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
2873	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
2874	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
2875	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
2876	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
2877	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
2878	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
2879	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
2880	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
2881	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
2882	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
2883	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
2884	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
2885	const char pszValidValues, const char pszValidNodes,
2886	const char *pszWho, uint32_t uInstance));
2887	/** @} */
2888
2889	/**
2890	* Read physical memory.
2891	*
2892	* @returns VINF_SUCCESS (for now).
2893	* @param pDevIns The device instance.
2894	* @param GCPhys Physical address start reading from.
2895	* @param pvBuf Where to put the read bits.
2896	* @param cbRead How many bytes to read.
2897	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
2898	* @thread Any thread, but the call may involve the emulation thread.
2899	*/
2900	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
2901
2902	/**
2903	* Write to physical memory.
2904	*
2905	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
2906	* @param pDevIns The device instance.
2907	* @param GCPhys Physical address to write to.
2908	* @param pvBuf What to write.
2909	* @param cbWrite How many bytes to write.
2910	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
2911	* @thread Any thread, but the call may involve the emulation thread.
2912	*/
2913	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
2914
2915	/**
2916	* Requests the mapping of a guest page into ring-3.
2917	*
2918	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2919	* release it.
2920	*
2921	* This API will assume your intention is to write to the page, and will
2922	* therefore replace shared and zero pages. If you do not intend to modify the
2923	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
2924	*
2925	* @returns VBox status code.
2926	* @retval VINF_SUCCESS on success.
2927	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2928	* backing or if the page has any active access handlers. The caller
2929	* must fall back on using PGMR3PhysWriteExternal.
2930	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2931	*
2932	* @param pDevIns The device instance.
2933	* @param GCPhys The guest physical address of the page that
2934	* should be mapped.
2935	* @param fFlags Flags reserved for future use, MBZ.
2936	* @param ppv Where to store the address corresponding to
2937	* GCPhys.
2938	* @param pLock Where to store the lock information that
2939	* pfnPhysReleasePageMappingLock needs.
2940	*
2941	* @remark Avoid calling this API from within critical sections (other than the
2942	* PGM one) because of the deadlock risk when we have to delegating the
2943	* task to an EMT.
2944	* @thread Any.
2945	*/
2946	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
2947	PPGMPAGEMAPLOCK pLock));
2948
2949	/**
2950	* Requests the mapping of a guest page into ring-3, external threads.
2951	*
2952	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
2953	* release it.
2954	*
2955	* @returns VBox status code.
2956	* @retval VINF_SUCCESS on success.
2957	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
2958	* backing or if the page as an active ALL access handler. The caller
2959	* must fall back on using PGMPhysRead.
2960	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2961	*
2962	* @param pDevIns The device instance.
2963	* @param GCPhys The guest physical address of the page that
2964	* should be mapped.
2965	* @param fFlags Flags reserved for future use, MBZ.
2966	* @param ppv Where to store the address corresponding to
2967	* GCPhys.
2968	* @param pLock Where to store the lock information that
2969	* pfnPhysReleasePageMappingLock needs.
2970	*
2971	* @remark Avoid calling this API from within critical sections.
2972	* @thread Any.
2973	*/
2974	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
2975	void const **ppv, PPGMPAGEMAPLOCK pLock));
2976
2977	/**
2978	* Release the mapping of a guest page.
2979	*
2980	* This is the counter part of pfnPhysGCPhys2CCPtr and
2981	* pfnPhysGCPhys2CCPtrReadOnly.
2982	*
2983	* @param pDevIns The device instance.
2984	* @param pLock The lock structure initialized by the mapping
2985	* function.
2986	*/
2987	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
2988
2989	/**
2990	* Read guest physical memory by virtual address.
2991	*
2992	* @param pDevIns The device instance.
2993	* @param pvDst Where to put the read bits.
2994	* @param GCVirtSrc Guest virtual address to start reading from.
2995	* @param cb How many bytes to read.
2996	* @thread The emulation thread.
2997	*/
2998	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
2999
3000	/**
3001	* Write to guest physical memory by virtual address.
3002	*
3003	* @param pDevIns The device instance.
3004	* @param GCVirtDst Guest virtual address to write to.
3005	* @param pvSrc What to write.
3006	* @param cb How many bytes to write.
3007	* @thread The emulation thread.
3008	*/
3009	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3010
3011	/**
3012	* Convert a guest virtual address to a guest physical address.
3013	*
3014	* @returns VBox status code.
3015	* @param pDevIns The device instance.
3016	* @param GCPtr Guest virtual address.
3017	* @param pGCPhys Where to store the GC physical address
3018	* corresponding to GCPtr.
3019	* @thread The emulation thread.
3020	* @remark Careful with page boundaries.
3021	*/
3022	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3023
3024	/**
3025	* Allocate memory which is associated with current VM instance
3026	* and automatically freed on it's destruction.
3027	*
3028	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3029	* @param pDevIns The device instance.
3030	* @param cb Number of bytes to allocate.
3031	*/
3032	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3033
3034	/**
3035	* Allocate memory which is associated with current VM instance
3036	* and automatically freed on it's destruction. The memory is ZEROed.
3037	*
3038	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3039	* @param pDevIns The device instance.
3040	* @param cb Number of bytes to allocate.
3041	*/
3042	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3043
3044	/**
3045	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3046	*
3047	* @param pDevIns The device instance.
3048	* @param pv Pointer to the memory to free.
3049	*/
3050	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3051
3052	/**
3053	* Gets the VM state.
3054	*
3055	* @returns VM state.
3056	* @param pDevIns The device instance.
3057	* @thread Any thread (just keep in mind that it's volatile info).
3058	*/
3059	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3060
3061	/**
3062	* Checks if the VM was teleported and hasn't been fully resumed yet.
3063	*
3064	* @returns true / false.
3065	* @param pDevIns The device instance.
3066	* @thread Any thread.
3067	*/
3068	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3069
3070	/**
3071	* Set the VM error message
3072	*
3073	* @returns rc.
3074	* @param pDevIns The device instance.
3075	* @param rc VBox status code.
3076	* @param SRC_POS Use RT_SRC_POS.
3077	* @param pszFormat Error message format string.
3078	* @param ... Error message arguments.
3079	*/
3080	DECLR3CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3081	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
3082
3083	/**
3084	* Set the VM error message
3085	*
3086	* @returns rc.
3087	* @param pDevIns The device instance.
3088	* @param rc VBox status code.
3089	* @param SRC_POS Use RT_SRC_POS.
3090	* @param pszFormat Error message format string.
3091	* @param va Error message arguments.
3092	*/
3093	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3094	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3095
3096	/**
3097	* Set the VM runtime error message
3098	*
3099	* @returns VBox status code.
3100	* @param pDevIns The device instance.
3101	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3102	* @param pszErrorId Error ID string.
3103	* @param pszFormat Error message format string.
3104	* @param ... Error message arguments.
3105	*/
3106	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3107	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
3108
3109	/**
3110	* Set the VM runtime error message
3111	*
3112	* @returns VBox status code.
3113	* @param pDevIns The device instance.
3114	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3115	* @param pszErrorId Error ID string.
3116	* @param pszFormat Error message format string.
3117	* @param va Error message arguments.
3118	*/
3119	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3120	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3121
3122	/**
3123	* Stops the VM and enters the debugger to look at the guest state.
3124	*
3125	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3126	* invoking this function directly.
3127	*
3128	* @returns VBox status code which must be passed up to the VMM.
3129	* @param pDevIns The device instance.
3130	* @param pszFile Filename of the assertion location.
3131	* @param iLine The linenumber of the assertion location.
3132	* @param pszFunction Function of the assertion location.
3133	* @param pszFormat Message. (optional)
3134	* @param args Message parameters.
3135	*/
3136	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3137	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3138
3139	/**
3140	* Register a info handler with DBGF.
3141	*
3142	* @returns VBox status code.
3143	* @param pDevIns The device instance.
3144	* @param pszName The identifier of the info.
3145	* @param pszDesc The description of the info and any arguments
3146	* the handler may take.
3147	* @param pfnHandler The handler function to be called to display the
3148	* info.
3149	*/
3150	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3151
3152	/**
3153	* Register a info handler with DBGF, argv style.
3154	*
3155	* @returns VBox status code.
3156	* @param pDevIns The device instance.
3157	* @param pszName The identifier of the info.
3158	* @param pszDesc The description of the info and any arguments
3159	* the handler may take.
3160	* @param pfnHandler The handler function to be called to display the
3161	* info.
3162	*/
3163	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3164
3165	/**
3166	* Registers a set of registers for a device.
3167	*
3168	* The @a pvUser argument of the getter and setter callbacks will be
3169	* @a pDevIns. The register names will be prefixed by the device name followed
3170	* immediately by the instance number.
3171	*
3172	* @returns VBox status code.
3173	* @param pDevIns The device instance.
3174	* @param paRegisters The register descriptors.
3175	*
3176	* @remarks The device critical section is NOT entered prior to working the
3177	* callbacks registered via this helper!
3178	*/
3179	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3180
3181	/**
3182	* Gets the trace buffer handle.
3183	*
3184	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3185	* really inteded for direct usage, thus no inline wrapper function.
3186	*
3187	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3188	* @param pDevIns The device instance.
3189	*/
3190	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3191
3192	/**
3193	* Registers a statistics sample.
3194	*
3195	* @param pDevIns Device instance of the DMA.
3196	* @param pvSample Pointer to the sample.
3197	* @param enmType Sample type. This indicates what pvSample is
3198	* pointing at.
3199	* @param pszName Sample name, unix path style. If this does not
3200	* start with a '/', the default prefix will be
3201	* prepended, otherwise it will be used as-is.
3202	* @param enmUnit Sample unit.
3203	* @param pszDesc Sample description.
3204	*/
3205	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3206
3207	/**
3208	* Same as pfnSTAMRegister except that the name is specified in a
3209	* RTStrPrintfV like fashion.
3210	*
3211	* @returns VBox status.
3212	* @param pDevIns Device instance of the DMA.
3213	* @param pvSample Pointer to the sample.
3214	* @param enmType Sample type. This indicates what pvSample is
3215	* pointing at.
3216	* @param enmVisibility Visibility type specifying whether unused
3217	* statistics should be visible or not.
3218	* @param enmUnit Sample unit.
3219	* @param pszDesc Sample description.
3220	* @param pszName Sample name format string, unix path style. If
3221	* this does not start with a '/', the default
3222	* prefix will be prepended, otherwise it will be
3223	* used as-is.
3224	* @param args Arguments to the format string.
3225	*/
3226	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3227	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3228	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3229
3230	/**
3231	* Registers a PCI device with the default PCI bus.
3232	*
3233	* If a PDM device has more than one PCI device, they must be registered in the
3234	* order of PDMDEVINSR3::apPciDevs.
3235	*
3236	* @returns VBox status code.
3237	* @param pDevIns The device instance.
3238	* @param pPciDev The PCI device structure.
3239	* This must be kept in the instance data.
3240	* The PCI configuration must be initialized before registration.
3241	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3242	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3243	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3244	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3245	* device number (0-31). This will be ignored if
3246	* the CFGM configuration contains a PCIDeviceNo
3247	* value.
3248	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3249	* function number (0-7). This will be ignored if
3250	* the CFGM configuration contains a PCIFunctionNo
3251	* value.
3252	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3253	* The pointer is saved, so don't free or changed.
3254	* @note The PCI device configuration is now implicit from the apPciDevs
3255	* index, meaning that the zero'th entry is the primary one and
3256	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3257	*/
3258	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3259	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3260
3261	/**
3262	* Initialize MSI or MSI-X emulation support for the given PCI device.
3263	*
3264	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3265	*
3266	* @returns VBox status code.
3267	* @param pDevIns The device instance.
3268	* @param pPciDev The PCI device. NULL is an alias for the first
3269	* one registered.
3270	* @param pMsiReg MSI emulation registration structure.
3271	*/
3272	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3273
3274	/**
3275	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3276	*
3277	* @returns VBox status code.
3278	* @param pDevIns The device instance.
3279	* @param pPciDev The PCI device structure. If NULL the default
3280	* PCI device for this device instance is used.
3281	* @param iRegion The region number.
3282	* @param cbRegion Size of the region.
3283	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3284	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3285	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3286	* @a fFlags, UINT64_MAX if no handle is passed
3287	* (old style).
3288	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3289	* handle is specified. The callback will be
3290	* invoked holding only the PDM lock. The device
3291	* lock will _not_ be taken (due to lock order).
3292	*/
3293	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3294	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3295	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3296
3297	/**
3298	* Register PCI configuration space read/write callbacks.
3299	*
3300	* @returns VBox status code.
3301	* @param pDevIns The device instance.
3302	* @param pPciDev The PCI device structure. If NULL the default
3303	* PCI device for this device instance is used.
3304	* @param pfnRead Pointer to the user defined PCI config read function.
3305	* to call default PCI config read function. Can be NULL.
3306	* @param pfnWrite Pointer to the user defined PCI config write function.
3307	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3308	* is NOT take because that is very likely be a lock order violation.
3309	* @thread EMT(0)
3310	* @note Only callable during VM creation.
3311	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3312	*/
3313	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3314	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3315
3316	/**
3317	* Perform a PCI configuration space write.
3318	*
3319	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3320	*
3321	* @returns Strict VBox status code (mainly DBGFSTOP).
3322	* @param pDevIns The device instance.
3323	* @param pPciDev The PCI device which config space is being read.
3324	* @param uAddress The config space address.
3325	* @param cb The size of the read: 1, 2 or 4 bytes.
3326	* @param u32Value The value to write.
3327	*/
3328	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3329	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3330
3331	/**
3332	* Perform a PCI configuration space read.
3333	*
3334	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3335	*
3336	* @returns Strict VBox status code (mainly DBGFSTOP).
3337	* @param pDevIns The device instance.
3338	* @param pPciDev The PCI device which config space is being read.
3339	* @param uAddress The config space address.
3340	* @param cb The size of the read: 1, 2 or 4 bytes.
3341	* @param pu32Value Where to return the value.
3342	*/
3343	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3344	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3345
3346	/**
3347	* Bus master physical memory read.
3348	*
3349	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3350	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3351	* @param pDevIns The device instance.
3352	* @param pPciDev The PCI device structure. If NULL the default
3353	* PCI device for this device instance is used.
3354	* @param GCPhys Physical address start reading from.
3355	* @param pvBuf Where to put the read bits.
3356	* @param cbRead How many bytes to read.
3357	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3358	* @thread Any thread, but the call may involve the emulation thread.
3359	*/
3360	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3361
3362	/**
3363	* Bus master physical memory write.
3364	*
3365	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3366	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3367	* @param pDevIns The device instance.
3368	* @param pPciDev The PCI device structure. If NULL the default
3369	* PCI device for this device instance is used.
3370	* @param GCPhys Physical address to write to.
3371	* @param pvBuf What to write.
3372	* @param cbWrite How many bytes to write.
3373	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3374	* @thread Any thread, but the call may involve the emulation thread.
3375	*/
3376	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3377
3378	/**
3379	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3380	* physical memory write operation.
3381	*
3382	* Refer pfnPhysGCPhys2CCPtr() for further details.
3383	*
3384	* @returns VBox status code.
3385	* @param pDevIns The device instance.
3386	* @param pPciDev The PCI device structure. If NULL the default
3387	* PCI device for this device instance is used.
3388	* @param GCPhys The guest physical address of the page that should be
3389	* mapped.
3390	* @param fFlags Flags reserved for future use, MBZ.
3391	* @param ppv Where to store the address corresponding to GCPhys.
3392	* @param pLock Where to store the lock information that
3393	* pfnPhysReleasePageMappingLock needs.
3394	*
3395	* @remarks Avoid calling this API from within critical sections (other than the PGM
3396	* one) because of the deadlock risk when we have to delegating the task to
3397	* an EMT.
3398	* @thread Any.
3399	*/
3400	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3401	void **ppv, PPGMPAGEMAPLOCK pLock));
3402
3403	/**
3404	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3405	* for a bus master physical memory read operation.
3406	*
3407	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3408	*
3409	* @returns VBox status code.
3410	* @param pDevIns The device instance.
3411	* @param pPciDev The PCI device structure. If NULL the default
3412	* PCI device for this device instance is used.
3413	* @param GCPhys The guest physical address of the page that
3414	* should be mapped.
3415	* @param fFlags Flags reserved for future use, MBZ.
3416	* @param ppv Where to store the address corresponding to
3417	* GCPhys.
3418	* @param pLock Where to store the lock information that
3419	* pfnPhysReleasePageMappingLock needs.
3420	*
3421	* @remarks Avoid calling this API from within critical sections.
3422	* @thread Any.
3423	*/
3424	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3425	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3426
3427	/**
3428	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3429	* master physical memory write operation.
3430	*
3431	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3432	* ASAP to release them.
3433	*
3434	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3435	*
3436	* @returns VBox status code.
3437	* @param pDevIns The device instance.
3438	* @param pPciDev The PCI device structure. If NULL the default
3439	* PCI device for this device instance is used.
3440	* @param cPages Number of pages to lock.
3441	* @param paGCPhysPages The guest physical address of the pages that
3442	* should be mapped (@a cPages entries).
3443	* @param fFlags Flags reserved for future use, MBZ.
3444	* @param papvPages Where to store the ring-3 mapping addresses
3445	* corresponding to @a paGCPhysPages.
3446	* @param paLocks Where to store the locking information that
3447	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3448	* in length).
3449	*/
3450	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3451	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3452	PPGMPAGEMAPLOCK paLocks));
3453
3454	/**
3455	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3456	* master physical memory read operation.
3457	*
3458	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3459	* ASAP to release them.
3460	*
3461	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3462	*
3463	* @returns VBox status code.
3464	* @param pDevIns The device instance.
3465	* @param pPciDev The PCI device structure. If NULL the default
3466	* PCI device for this device instance is used.
3467	* @param cPages Number of pages to lock.
3468	* @param paGCPhysPages The guest physical address of the pages that
3469	* should be mapped (@a cPages entries).
3470	* @param fFlags Flags reserved for future use, MBZ.
3471	* @param papvPages Where to store the ring-3 mapping addresses
3472	* corresponding to @a paGCPhysPages.
3473	* @param paLocks Where to store the lock information that
3474	* pfnPhysReleasePageMappingLock needs (@a cPages
3475	* in length).
3476	*/
3477	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3478	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3479	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3480
3481	/**
3482	* Sets the IRQ for the given PCI device.
3483	*
3484	* @param pDevIns The device instance.
3485	* @param pPciDev The PCI device structure. If NULL the default
3486	* PCI device for this device instance is used.
3487	* @param iIrq IRQ number to set.
3488	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3489	* @thread Any thread, but will involve the emulation thread.
3490	*/
3491	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3492
3493	/**
3494	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3495	* the request when not called from EMT.
3496	*
3497	* @param pDevIns The device instance.
3498	* @param pPciDev The PCI device structure. If NULL the default
3499	* PCI device for this device instance is used.
3500	* @param iIrq IRQ number to set.
3501	* @param iLevel IRQ level.
3502	* @thread Any thread, but will involve the emulation thread.
3503	*/
3504	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3505
3506	/**
3507	* Set ISA IRQ for a device.
3508	*
3509	* @param pDevIns The device instance.
3510	* @param iIrq IRQ number to set.
3511	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3512	* @thread Any thread, but will involve the emulation thread.
3513	*/
3514	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3515
3516	/**
3517	* Set the ISA IRQ for a device, but don't wait for EMT to process
3518	* the request when not called from EMT.
3519	*
3520	* @param pDevIns The device instance.
3521	* @param iIrq IRQ number to set.
3522	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3523	* @thread Any thread, but will involve the emulation thread.
3524	*/
3525	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3526
3527	/**
3528	* Attaches a driver (chain) to the device.
3529	*
3530	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3531	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3532	*
3533	* @returns VBox status code.
3534	* @param pDevIns The device instance.
3535	* @param iLun The logical unit to attach.
3536	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3537	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3538	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3539	* for the live of the device instance.
3540	*/
3541	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3542	PPDMIBASE ppBaseInterface, const char pszDesc));
3543
3544	/**
3545	* Detaches an attached driver (chain) from the device again.
3546	*
3547	* @returns VBox status code.
3548	* @param pDevIns The device instance.
3549	* @param pDrvIns The driver instance to detach.
3550	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3551	*/
3552	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3553
3554	/**
3555	* Reconfigures the driver chain for a LUN, detaching any driver currently
3556	* present there.
3557	*
3558	* Caller will have attach it, of course.
3559	*
3560	* @returns VBox status code.
3561	* @param pDevIns The device instance.
3562	* @param iLun The logical unit to reconfigure.
3563	* @param cDepth The depth of the driver chain. Determins the
3564	* size of @a papszDrivers and @a papConfigs.
3565	* @param papszDrivers The names of the drivers to configure in the
3566	* chain, first entry is the one immediately
3567	* below the device/LUN
3568	* @param papConfigs The configurations for each of the drivers
3569	* in @a papszDrivers array. NULL entries
3570	* corresponds to empty 'Config' nodes. This
3571	* function will take ownership of non-NULL
3572	* CFGM sub-trees and set the array member to
3573	* NULL, so the caller can do cleanups on
3574	* failure. This parameter is optional.
3575	* @param fFlags Reserved, MBZ.
3576	*/
3577	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3578	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3579
3580	/** @name Exported PDM Queue Functions
3581	* @{ */
3582	/**
3583	* Create a queue.
3584	*
3585	* @returns VBox status code.
3586	* @param pDevIns The device instance.
3587	* @param cbItem The size of a queue item.
3588	* @param cItems The number of items in the queue.
3589	* @param cMilliesInterval The number of milliseconds between polling the queue.
3590	* If 0 then the emulation thread will be notified whenever an item arrives.
3591	* @param pfnCallback The consumer function.
3592	* @param fRZEnabled Set if the queue should work in RC and R0.
3593	* @param pszName The queue base name. The instance number will be
3594	* appended automatically.
3595	* @param ppQueue Where to store the queue pointer on success.
3596	* @thread The emulation thread.
3597	* @remarks The device critical section will NOT be entered before calling the
3598	* callback. No locks will be held, but for now it's safe to assume
3599	* that only one EMT will do queue callbacks at any one time.
3600	*/
3601	DECLR3CALLBACKMEMBER(int, pfnQueueCreatePtr,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3602	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3603	PPDMQUEUE *ppQueue));
3604
3605	/**
3606	* Create a queue.
3607	*
3608	* @returns VBox status code.
3609	* @param pDevIns The device instance.
3610	* @param cbItem The size of a queue item.
3611	* @param cItems The number of items in the queue.
3612	* @param cMilliesInterval The number of milliseconds between polling the queue.
3613	* If 0 then the emulation thread will be notified whenever an item arrives.
3614	* @param pfnCallback The consumer function.
3615	* @param fRZEnabled Set if the queue should work in RC and R0.
3616	* @param pszName The queue base name. The instance number will be
3617	* appended automatically.
3618	* @param phQueue Where to store the queue handle on success.
3619	* @thread EMT(0)
3620	* @remarks The device critical section will NOT be entered before calling the
3621	* callback. No locks will be held, but for now it's safe to assume
3622	* that only one EMT will do queue callbacks at any one time.
3623	*/
3624	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3625	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3626	PDMQUEUEHANDLE *phQueue));
3627
3628	DECLR3CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3629	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3630	DECLR3CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3631	DECLR3CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
3632	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3633	/** @} */
3634
3635	/** @name PDM Task
3636	* @{ */
3637	/**
3638	* Create an asynchronous ring-3 task.
3639	*
3640	* @returns VBox status code.
3641	* @param pDevIns The device instance.
3642	* @param fFlags PDMTASK_F_XXX
3643	* @param pszName The function name or similar. Used for statistics,
3644	* so no slashes.
3645	* @param pfnCallback The task function.
3646	* @param pvUser User argument for the task function.
3647	* @param phTask Where to return the task handle.
3648	* @thread EMT(0)
3649	*/
3650	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
3651	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
3652	/**
3653	* Triggers the running the given task.
3654	*
3655	* @returns VBox status code.
3656	* @retval VINF_ALREADY_POSTED is the task is already pending.
3657	* @param pDevIns The device instance.
3658	* @param hTask The task to trigger.
3659	* @thread Any thread.
3660	*/
3661	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
3662	/** @} */
3663
3664	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
3665	* These semaphores can be signalled from ring-0.
3666	* @{ */
3667	/** @sa SUPSemEventCreate */
3668	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
3669	/** @sa SUPSemEventClose */
3670	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3671	/** @sa SUPSemEventSignal */
3672	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
3673	/** @sa SUPSemEventWaitNoResume */
3674	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
3675	/** @sa SUPSemEventWaitNsAbsIntr */
3676	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
3677	/** @sa SUPSemEventWaitNsRelIntr */
3678	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
3679	/** @sa SUPSemEventGetResolution */
3680	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
3681	/** @} */
3682
3683	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
3684	* These semaphores can be signalled from ring-0.
3685	* @{ */
3686	/** @sa SUPSemEventMultiCreate */
3687	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
3688	/** @sa SUPSemEventMultiClose */
3689	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3690	/** @sa SUPSemEventMultiSignal */
3691	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3692	/** @sa SUPSemEventMultiReset */
3693	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
3694	/** @sa SUPSemEventMultiWaitNoResume */
3695	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
3696	/** @sa SUPSemEventMultiWaitNsAbsIntr */
3697	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
3698	/** @sa SUPSemEventMultiWaitNsRelIntr */
3699	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
3700	/** @sa SUPSemEventMultiGetResolution */
3701	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
3702	/** @} */
3703
3704	/**
3705	* Initializes a PDM critical section.
3706	*
3707	* The PDM critical sections are derived from the IPRT critical sections, but
3708	* works in RC and R0 as well.
3709	*
3710	* @returns VBox status code.
3711	* @param pDevIns The device instance.
3712	* @param pCritSect Pointer to the critical section.
3713	* @param SRC_POS Use RT_SRC_POS.
3714	* @param pszNameFmt Format string for naming the critical section.
3715	* For statistics and lock validation.
3716	* @param va Arguments for the format string.
3717	*/
3718	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
3719	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3720
3721	/**
3722	* Gets the NOP critical section.
3723	*
3724	* @returns The ring-3 address of the NOP critical section.
3725	* @param pDevIns The device instance.
3726	*/
3727	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
3728
3729	/**
3730	* Gets the NOP critical section.
3731	*
3732	* @returns The ring-0 address of the NOP critical section.
3733	* @param pDevIns The device instance.
3734	* @deprecated
3735	*/
3736	DECLR3CALLBACKMEMBER(R0PTRTYPE(PPDMCRITSECT), pfnCritSectGetNopR0,(PPDMDEVINS pDevIns));
3737
3738	/**
3739	* Gets the NOP critical section.
3740	*
3741	* @returns The raw-mode context address of the NOP critical section.
3742	* @param pDevIns The device instance.
3743	* @deprecated
3744	*/
3745	DECLR3CALLBACKMEMBER(RCPTRTYPE(PPDMCRITSECT), pfnCritSectGetNopRC,(PPDMDEVINS pDevIns));
3746
3747	/**
3748	* Changes the device level critical section from the automatically created
3749	* default to one desired by the device constructor.
3750	*
3751	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
3752	* the additional contexts.
3753	*
3754	* @returns VBox status code.
3755	* @param pDevIns The device instance.
3756	* @param pCritSect The critical section to use. NULL is not
3757	* valid, instead use the NOP critical
3758	* section.
3759	*/
3760	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3761
3762	/** @name Exported PDM Critical Section Functions
3763	* @{ */
3764	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3765	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
3766	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3767	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3768	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
3769	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3770	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3771	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3772	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3773	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
3774	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
3775	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
3776	/** @} */
3777
3778	/**
3779	* Creates a PDM thread.
3780	*
3781	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
3782	* resuming, and destroying the thread as the VM state changes.
3783	*
3784	* @returns VBox status code.
3785	* @param pDevIns The device instance.
3786	* @param ppThread Where to store the thread 'handle'.
3787	* @param pvUser The user argument to the thread function.
3788	* @param pfnThread The thread function.
3789	* @param pfnWakeup The wakup callback. This is called on the EMT
3790	* thread when a state change is pending.
3791	* @param cbStack See RTThreadCreate.
3792	* @param enmType See RTThreadCreate.
3793	* @param pszName See RTThreadCreate.
3794	* @remarks The device critical section will NOT be entered prior to invoking
3795	* the function pointers.
3796	*/
3797	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
3798	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
3799
3800	/** @name Exported PDM Thread Functions
3801	* @{ */
3802	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
3803	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
3804	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
3805	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
3806	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
3807	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
3808	/** @} */
3809
3810	/**
3811	* Set up asynchronous handling of a suspend, reset or power off notification.
3812	*
3813	* This shall only be called when getting the notification. It must be called
3814	* for each one.
3815	*
3816	* @returns VBox status code.
3817	* @param pDevIns The device instance.
3818	* @param pfnAsyncNotify The callback.
3819	* @thread EMT(0)
3820	* @remarks The caller will enter the device critical section prior to invoking
3821	* the callback.
3822	*/
3823	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
3824
3825	/**
3826	* Notify EMT(0) that the device has completed the asynchronous notification
3827	* handling.
3828	*
3829	* This can be called at any time, spurious calls will simply be ignored.
3830	*
3831	* @param pDevIns The device instance.
3832	* @thread Any
3833	*/
3834	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
3835
3836	/**
3837	* Register the RTC device.
3838	*
3839	* @returns VBox status code.
3840	* @param pDevIns The device instance.
3841	* @param pRtcReg Pointer to a RTC registration structure.
3842	* @param ppRtcHlp Where to store the pointer to the helper
3843	* functions.
3844	*/
3845	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
3846
3847	/**
3848	* Register a PCI Bus.
3849	*
3850	* @returns VBox status code, but the positive values 0..31 are used to indicate
3851	* bus number rather than informational status codes.
3852	* @param pDevIns The device instance.
3853	* @param pPciBusReg Pointer to PCI bus registration structure.
3854	* @param ppPciHlp Where to store the pointer to the PCI Bus
3855	* helpers.
3856	* @param piBus Where to return the PDM bus number. Optional.
3857	*/
3858	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
3859	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
3860
3861	/**
3862	* Register the IOMMU device.
3863	*
3864	* @returns VBox status code.
3865	* @param pDevIns The device instance.
3866	* @param pIommuReg Pointer to a IOMMU registration structure.
3867	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
3868	* helpers.
3869	* @param pidxIommu Where to return the IOMMU index. Optional.
3870	*/
3871	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
3872	uint32_t *pidxIommu));
3873
3874	/**
3875	* Register the PIC device.
3876	*
3877	* @returns VBox status code.
3878	* @param pDevIns The device instance.
3879	* @param pPicReg Pointer to a PIC registration structure.
3880	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
3881	* helpers.
3882	* @sa PDMDevHlpPICSetUpContext
3883	*/
3884	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
3885
3886	/**
3887	* Register the APIC device.
3888	*
3889	* @returns VBox status code.
3890	* @param pDevIns The device instance.
3891	*/
3892	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
3893
3894	/**
3895	* Register the I/O APIC device.
3896	*
3897	* @returns VBox status code.
3898	* @param pDevIns The device instance.
3899	* @param pIoApicReg Pointer to a I/O APIC registration structure.
3900	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
3901	* helpers.
3902	*/
3903	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
3904
3905	/**
3906	* Register the HPET device.
3907	*
3908	* @returns VBox status code.
3909	* @param pDevIns The device instance.
3910	* @param pHpetReg Pointer to a HPET registration structure.
3911	* @param ppHpetHlpR3 Where to store the pointer to the HPET
3912	* helpers.
3913	*/
3914	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
3915
3916	/**
3917	* Register a raw PCI device.
3918	*
3919	* @returns VBox status code.
3920	* @param pDevIns The device instance.
3921	* @param pPciRawReg Pointer to a raw PCI registration structure.
3922	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
3923	* device helpers.
3924	*/
3925	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
3926
3927	/**
3928	* Register the DMA device.
3929	*
3930	* @returns VBox status code.
3931	* @param pDevIns The device instance.
3932	* @param pDmacReg Pointer to a DMAC registration structure.
3933	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
3934	*/
3935	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
3936
3937	/**
3938	* Register transfer function for DMA channel.
3939	*
3940	* @returns VBox status code.
3941	* @param pDevIns The device instance.
3942	* @param uChannel Channel number.
3943	* @param pfnTransferHandler Device specific transfer callback function.
3944	* @param pvUser User pointer to pass to the callback.
3945	* @thread EMT
3946	*/
3947	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
3948
3949	/**
3950	* Read memory.
3951	*
3952	* @returns VBox status code.
3953	* @param pDevIns The device instance.
3954	* @param uChannel Channel number.
3955	* @param pvBuffer Pointer to target buffer.
3956	* @param off DMA position.
3957	* @param cbBlock Block size.
3958	* @param pcbRead Where to store the number of bytes which was
3959	* read. optional.
3960	* @thread EMT
3961	*/
3962	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
3963
3964	/**
3965	* Write memory.
3966	*
3967	* @returns VBox status code.
3968	* @param pDevIns The device instance.
3969	* @param uChannel Channel number.
3970	* @param pvBuffer Memory to write.
3971	* @param off DMA position.
3972	* @param cbBlock Block size.
3973	* @param pcbWritten Where to store the number of bytes which was
3974	* written. optional.
3975	* @thread EMT
3976	*/
3977	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
3978
3979	/**
3980	* Set the DREQ line.
3981	*
3982	* @returns VBox status code.
3983	* @param pDevIns Device instance.
3984	* @param uChannel Channel number.
3985	* @param uLevel Level of the line.
3986	* @thread EMT
3987	*/
3988	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
3989
3990	/**
3991	* Get channel mode.
3992	*
3993	* @returns Channel mode. See specs.
3994	* @param pDevIns The device instance.
3995	* @param uChannel Channel number.
3996	* @thread EMT
3997	*/
3998	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
3999
4000	/**
4001	* Schedule DMA execution.
4002	*
4003	* @param pDevIns The device instance.
4004	* @thread Any thread.
4005	*/
4006	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4007
4008	/**
4009	* Write CMOS value and update the checksum(s).
4010	*
4011	* @returns VBox status code.
4012	* @param pDevIns The device instance.
4013	* @param iReg The CMOS register index.
4014	* @param u8Value The CMOS register value.
4015	* @thread EMT
4016	*/
4017	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4018
4019	/**
4020	* Read CMOS value.
4021	*
4022	* @returns VBox status code.
4023	* @param pDevIns The device instance.
4024	* @param iReg The CMOS register index.
4025	* @param pu8Value Where to store the CMOS register value.
4026	* @thread EMT
4027	*/
4028	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4029
4030	/**
4031	* Assert that the current thread is the emulation thread.
4032	*
4033	* @returns True if correct.
4034	* @returns False if wrong.
4035	* @param pDevIns The device instance.
4036	* @param pszFile Filename of the assertion location.
4037	* @param iLine The linenumber of the assertion location.
4038	* @param pszFunction Function of the assertion location.
4039	*/
4040	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4041
4042	/**
4043	* Assert that the current thread is NOT the emulation thread.
4044	*
4045	* @returns True if correct.
4046	* @returns False if wrong.
4047	* @param pDevIns The device instance.
4048	* @param pszFile Filename of the assertion location.
4049	* @param iLine The linenumber of the assertion location.
4050	* @param pszFunction Function of the assertion location.
4051	*/
4052	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4053
4054	/**
4055	* Resolves the symbol for a raw-mode context interface.
4056	*
4057	* @returns VBox status code.
4058	* @param pDevIns The device instance.
4059	* @param pvInterface The interface structure.
4060	* @param cbInterface The size of the interface structure.
4061	* @param pszSymPrefix What to prefix the symbols in the list with
4062	* before resolving them. This must start with
4063	* 'dev' and contain the driver name.
4064	* @param pszSymList List of symbols corresponding to the interface.
4065	* There is generally a there is generally a define
4066	* holding this list associated with the interface
4067	* definition (INTERFACE_SYM_LIST). For more
4068	* details see PDMR3LdrGetInterfaceSymbols.
4069	* @thread EMT
4070	*/
4071	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4072	const char pszSymPrefix, const char pszSymList));
4073
4074	/**
4075	* Resolves the symbol for a ring-0 context interface.
4076	*
4077	* @returns VBox status code.
4078	* @param pDevIns The device instance.
4079	* @param pvInterface The interface structure.
4080	* @param cbInterface The size of the interface structure.
4081	* @param pszSymPrefix What to prefix the symbols in the list with
4082	* before resolving them. This must start with
4083	* 'dev' and contain the driver name.
4084	* @param pszSymList List of symbols corresponding to the interface.
4085	* There is generally a there is generally a define
4086	* holding this list associated with the interface
4087	* definition (INTERFACE_SYM_LIST). For more
4088	* details see PDMR3LdrGetInterfaceSymbols.
4089	* @thread EMT
4090	*/
4091	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4092	const char pszSymPrefix, const char pszSymList));
4093
4094	/**
4095	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4096	*
4097	* @returns VBox status code.
4098	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4099	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4100	*
4101	* @param pDevIns The device instance.
4102	* @param uOperation The operation to perform.
4103	* @param u64Arg 64-bit integer argument.
4104	* @thread EMT
4105	*/
4106	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4107
4108	/**
4109	* Gets the reason for the most recent VM suspend.
4110	*
4111	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4112	* suspend has been made or if the pDevIns is invalid.
4113	* @param pDevIns The device instance.
4114	*/
4115	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4116
4117	/**
4118	* Gets the reason for the most recent VM resume.
4119	*
4120	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4121	* resume has been made or if the pDevIns is invalid.
4122	* @param pDevIns The device instance.
4123	*/
4124	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4125
4126	/**
4127	* Requests the mapping of multiple guest page into ring-3.
4128	*
4129	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4130	* ASAP to release them.
4131	*
4132	* This API will assume your intention is to write to the pages, and will
4133	* therefore replace shared and zero pages. If you do not intend to modify the
4134	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4135	*
4136	* @returns VBox status code.
4137	* @retval VINF_SUCCESS on success.
4138	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4139	* backing or if any of the pages the page has any active access
4140	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4141	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4142	* an invalid physical address.
4143	*
4144	* @param pDevIns The device instance.
4145	* @param cPages Number of pages to lock.
4146	* @param paGCPhysPages The guest physical address of the pages that
4147	* should be mapped (@a cPages entries).
4148	* @param fFlags Flags reserved for future use, MBZ.
4149	* @param papvPages Where to store the ring-3 mapping addresses
4150	* corresponding to @a paGCPhysPages.
4151	* @param paLocks Where to store the locking information that
4152	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4153	* in length).
4154	*
4155	* @remark Avoid calling this API from within critical sections (other than the
4156	* PGM one) because of the deadlock risk when we have to delegating the
4157	* task to an EMT.
4158	* @thread Any.
4159	* @since 6.0.6
4160	*/
4161	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4162	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4163
4164	/**
4165	* Requests the mapping of multiple guest page into ring-3, for reading only.
4166	*
4167	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4168	* ASAP to release them.
4169	*
4170	* @returns VBox status code.
4171	* @retval VINF_SUCCESS on success.
4172	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4173	* backing or if any of the pages the page has an active ALL access
4174	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4175	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4176	* an invalid physical address.
4177	*
4178	* @param pDevIns The device instance.
4179	* @param cPages Number of pages to lock.
4180	* @param paGCPhysPages The guest physical address of the pages that
4181	* should be mapped (@a cPages entries).
4182	* @param fFlags Flags reserved for future use, MBZ.
4183	* @param papvPages Where to store the ring-3 mapping addresses
4184	* corresponding to @a paGCPhysPages.
4185	* @param paLocks Where to store the lock information that
4186	* pfnPhysReleasePageMappingLock needs (@a cPages
4187	* in length).
4188	*
4189	* @remark Avoid calling this API from within critical sections.
4190	* @thread Any.
4191	* @since 6.0.6
4192	*/
4193	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4194	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4195
4196	/**
4197	* Release the mappings of multiple guest pages.
4198	*
4199	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4200	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4201	*
4202	* @param pDevIns The device instance.
4203	* @param cPages Number of pages to unlock.
4204	* @param paLocks The lock structures initialized by the mapping
4205	* function (@a cPages in length).
4206	* @thread Any.
4207	* @since 6.0.6
4208	*/
4209	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4210
4211	/**
4212	* Returns the micro architecture used for the guest.
4213	*
4214	* @returns CPU micro architecture enum.
4215	* @param pDevIns The device instance.
4216	*/
4217	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4218
4219	/** Space reserved for future members.
4220	* @{ */
4221	DECLR3CALLBACKMEMBER(void, pfnReserved1,(void));
4222	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4223	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4224	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4225	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4226	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4227	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4228	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4229	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4230	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4231	/** @} */
4232
4233
4234	/** API available to trusted devices only.
4235	*
4236	* These APIs are providing unrestricted access to the guest and the VM,
4237	* or they are interacting intimately with PDM.
4238	*
4239	* @{
4240	*/
4241
4242	/**
4243	* Gets the user mode VM handle. Restricted API.
4244	*
4245	* @returns User mode VM Handle.
4246	* @param pDevIns The device instance.
4247	*/
4248	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4249
4250	/**
4251	* Gets the global VM handle. Restricted API.
4252	*
4253	* @returns VM Handle.
4254	* @param pDevIns The device instance.
4255	*/
4256	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4257
4258	/**
4259	* Gets the VMCPU handle. Restricted API.
4260	*
4261	* @returns VMCPU Handle.
4262	* @param pDevIns The device instance.
4263	*/
4264	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4265
4266	/**
4267	* The the VM CPU ID of the current thread (restricted API).
4268	*
4269	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4270	* @param pDevIns The device instance.
4271	*/
4272	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4273
4274	/**
4275	* Registers the VMM device heap or notifies about mapping/unmapping.
4276	*
4277	* This interface serves three purposes:
4278	*
4279	* -# Register the VMM device heap during device construction
4280	* for the HM to use.
4281	* -# Notify PDM/HM that it's mapped into guest address
4282	* space (i.e. usable).
4283	* -# Notify PDM/HM that it is being unmapped from the guest
4284	* address space (i.e. not usable).
4285	*
4286	* @returns VBox status code.
4287	* @param pDevIns The device instance.
4288	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4289	* not mapped.
4290	* @param pvHeap Ring 3 heap pointer.
4291	* @param cbHeap Size of the heap.
4292	* @thread EMT.
4293	*/
4294	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4295
4296	/**
4297	* Registers the firmware (BIOS, EFI) device with PDM.
4298	*
4299	* The firmware provides a callback table and gets a special PDM helper table.
4300	* There can only be one firmware device for a VM.
4301	*
4302	* @returns VBox status code.
4303	* @param pDevIns The device instance.
4304	* @param pFwReg Firmware registration structure.
4305	* @param ppFwHlp Where to return the firmware helper structure.
4306	* @remarks Only valid during device construction.
4307	* @thread EMT(0)
4308	*/
4309	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4310
4311	/**
4312	* Resets the VM.
4313	*
4314	* @returns The appropriate VBox status code to pass around on reset.
4315	* @param pDevIns The device instance.
4316	* @param fFlags PDMVMRESET_F_XXX flags.
4317	* @thread The emulation thread.
4318	*/
4319	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4320
4321	/**
4322	* Suspends the VM.
4323	*
4324	* @returns The appropriate VBox status code to pass around on suspend.
4325	* @param pDevIns The device instance.
4326	* @thread The emulation thread.
4327	*/
4328	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4329
4330	/**
4331	* Suspends, saves and powers off the VM.
4332	*
4333	* @returns The appropriate VBox status code to pass around.
4334	* @param pDevIns The device instance.
4335	* @thread An emulation thread.
4336	*/
4337	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4338
4339	/**
4340	* Power off the VM.
4341	*
4342	* @returns The appropriate VBox status code to pass around on power off.
4343	* @param pDevIns The device instance.
4344	* @thread The emulation thread.
4345	*/
4346	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4347
4348	/**
4349	* Checks if the Gate A20 is enabled or not.
4350	*
4351	* @returns true if A20 is enabled.
4352	* @returns false if A20 is disabled.
4353	* @param pDevIns The device instance.
4354	* @thread The emulation thread.
4355	*/
4356	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4357
4358	/**
4359	* Enables or disables the Gate A20.
4360	*
4361	* @param pDevIns The device instance.
4362	* @param fEnable Set this flag to enable the Gate A20; clear it
4363	* to disable.
4364	* @thread The emulation thread.
4365	*/
4366	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4367
4368	/**
4369	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4370	* thread.
4371	*
4372	* @param pDevIns The device instance.
4373	* @param iLeaf The CPUID leaf to get.
4374	* @param pEax Where to store the EAX value.
4375	* @param pEbx Where to store the EBX value.
4376	* @param pEcx Where to store the ECX value.
4377	* @param pEdx Where to store the EDX value.
4378	* @thread EMT.
4379	*/
4380	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4381
4382	/**
4383	* Get the current virtual clock time in a VM. The clock frequency must be
4384	* queried separately.
4385	*
4386	* @returns Current clock time.
4387	* @param pDevIns The device instance.
4388	*/
4389	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4390
4391	/**
4392	* Get the frequency of the virtual clock.
4393	*
4394	* @returns The clock frequency (not variable at run-time).
4395	* @param pDevIns The device instance.
4396	*/
4397	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4398
4399	/**
4400	* Get the current virtual clock time in a VM, in nanoseconds.
4401	*
4402	* @returns Current clock time (in ns).
4403	* @param pDevIns The device instance.
4404	*/
4405	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4406
4407	/**
4408	* Gets the support driver session.
4409	*
4410	* This is intended for working with the semaphore API.
4411	*
4412	* @returns Support driver session handle.
4413	* @param pDevIns The device instance.
4414	*/
4415	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4416
4417	/**
4418	* Queries a generic object from the VMM user.
4419	*
4420	* @returns Pointer to the object if found, NULL if not.
4421	* @param pDevIns The device instance.
4422	* @param pUuid The UUID of what's being queried. The UUIDs and
4423	* the usage conventions are defined by the user.
4424	*
4425	* @note It is strictly forbidden to call this internally in VBox! This
4426	* interface is exclusively for hacks in externally developed devices.
4427	*/
4428	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4429
4430	/**
4431	* Register a physical page access handler type.
4432	*
4433	* @returns VBox status code.
4434	* @param pDevIns The device instance.
4435	* @param enmKind The kind of access handler.
4436	* @param pfnHandlerR3 Pointer to the ring-3 handler callback.
4437	* @param pszHandlerR0 The name of the ring-0 handler, NULL if the ring-3
4438	* handler should be called.
4439	* @param pszPfHandlerR0 The name of the ring-0 \#PF handler, NULL if the
4440	* ring-3 handler should be called.
4441	* @param pszHandlerRC The name of the raw-mode context handler, NULL if
4442	* the ring-3 handler should be called.
4443	* @param pszPfHandlerRC The name of the raw-mode context \#PF handler, NULL
4444	* if the ring-3 handler should be called.
4445	* @param pszDesc The type description.
4446	* @param phType Where to return the type handle (cross context
4447	* safe).
4448	*/
4449	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4450	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
4451	const char pszHandlerR0, const char pszPfHandlerR0,
4452	const char pszHandlerRC, const char pszPfHandlerRC,
4453	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4454
4455	/** @} */
4456
4457	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
4458	uint32_t u32TheEnd;
4459	} PDMDEVHLPR3;
4460	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
4461	/** Pointer to the R3 PDM Device API. */
4462	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
4463	/** Pointer to the R3 PDM Device API, const variant. */
4464	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
4465
4466
4467	/**
4468	* PDM Device API - RC Variant.
4469	*/
4470	typedef struct PDMDEVHLPRC
4471	{
4472	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
4473	uint32_t u32Version;
4474
4475	/**
4476	* Sets up raw-mode context callback handlers for an I/O port range.
4477	*
4478	* The range must have been registered in ring-3 first using
4479	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4480	*
4481	* @returns VBox status.
4482	* @param pDevIns The device instance to register the ports with.
4483	* @param hIoPorts The I/O port range handle.
4484	* @param pfnOut Pointer to function which is gonna handle OUT
4485	* operations. Optional.
4486	* @param pfnIn Pointer to function which is gonna handle IN operations.
4487	* Optional.
4488	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4489	* operations. Optional.
4490	* @param pfnInStr Pointer to function which is gonna handle string IN
4491	* operations. Optional.
4492	* @param pvUser User argument to pass to the callbacks.
4493	*
4494	* @remarks Caller enters the device critical section prior to invoking the
4495	* registered callback methods.
4496	*
4497	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
4498	* PDMDevHlpIoPortUnmap.
4499	*/
4500	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4501	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4502	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4503	void *pvUser));
4504
4505	/**
4506	* Sets up raw-mode context callback handlers for an MMIO region.
4507	*
4508	* The region must have been registered in ring-3 first using
4509	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
4510	*
4511	* @returns VBox status.
4512	* @param pDevIns The device instance to register the ports with.
4513	* @param hRegion The MMIO region handle.
4514	* @param pfnWrite Pointer to function which is gonna handle Write
4515	* operations.
4516	* @param pfnRead Pointer to function which is gonna handle Read
4517	* operations.
4518	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4519	* operations. (optional)
4520	* @param pvUser User argument to pass to the callbacks.
4521	*
4522	* @remarks Caller enters the device critical section prior to invoking the
4523	* registered callback methods.
4524	*
4525	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
4526	* PDMDevHlpMmioUnmap.
4527	*/
4528	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4529	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4530
4531	/**
4532	* Sets up a raw-mode mapping for an MMIO2 region.
4533	*
4534	* The region must have been created in ring-3 first using
4535	* PDMDevHlpMmio2Create().
4536	*
4537	* @returns VBox status.
4538	* @param pDevIns The device instance to register the ports with.
4539	* @param hRegion The MMIO2 region handle.
4540	* @param offSub Start of what to map into raw-mode. Must be page aligned.
4541	* @param cbSub Number of bytes to map into raw-mode. Must be page
4542	* aligned. Zero is an alias for everything.
4543	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4544	* @thread EMT(0)
4545	* @note Only available at VM creation time.
4546	*
4547	* @sa PDMDevHlpMmio2Create().
4548	*/
4549	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
4550	size_t offSub, size_t cbSub, void **ppvMapping));
4551
4552	/**
4553	* Bus master physical memory read from the given PCI device.
4554	*
4555	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
4556	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4557	* @param pDevIns The device instance.
4558	* @param pPciDev The PCI device structure. If NULL the default
4559	* PCI device for this device instance is used.
4560	* @param GCPhys Physical address start reading from.
4561	* @param pvBuf Where to put the read bits.
4562	* @param cbRead How many bytes to read.
4563	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4564	* @thread Any thread, but the call may involve the emulation thread.
4565	*/
4566	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4567	void *pvBuf, size_t cbRead, uint32_t fFlags));
4568
4569	/**
4570	* Bus master physical memory write from the given PCI device.
4571	*
4572	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
4573	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
4574	* @param pDevIns The device instance.
4575	* @param pPciDev The PCI device structure. If NULL the default
4576	* PCI device for this device instance is used.
4577	* @param GCPhys Physical address to write to.
4578	* @param pvBuf What to write.
4579	* @param cbWrite How many bytes to write.
4580	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4581	* @thread Any thread, but the call may involve the emulation thread.
4582	*/
4583	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
4584	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4585
4586	/**
4587	* Set the IRQ for the given PCI device.
4588	*
4589	* @param pDevIns Device instance.
4590	* @param pPciDev The PCI device structure. If NULL the default
4591	* PCI device for this device instance is used.
4592	* @param iIrq IRQ number to set.
4593	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4594	* @thread Any thread, but will involve the emulation thread.
4595	*/
4596	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
4597
4598	/**
4599	* Set ISA IRQ for a device.
4600	*
4601	* @param pDevIns Device instance.
4602	* @param iIrq IRQ number to set.
4603	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
4604	* @thread Any thread, but will involve the emulation thread.
4605	*/
4606	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
4607
4608	/**
4609	* Read physical memory.
4610	*
4611	* @returns VINF_SUCCESS (for now).
4612	* @param pDevIns Device instance.
4613	* @param GCPhys Physical address start reading from.
4614	* @param pvBuf Where to put the read bits.
4615	* @param cbRead How many bytes to read.
4616	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4617	*/
4618	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
4619
4620	/**
4621	* Write to physical memory.
4622	*
4623	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
4624	* @param pDevIns Device instance.
4625	* @param GCPhys Physical address to write to.
4626	* @param pvBuf What to write.
4627	* @param cbWrite How many bytes to write.
4628	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
4629	*/
4630	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
4631
4632	/**
4633	* Checks if the Gate A20 is enabled or not.
4634	*
4635	* @returns true if A20 is enabled.
4636	* @returns false if A20 is disabled.
4637	* @param pDevIns Device instance.
4638	* @thread The emulation thread.
4639	*/
4640	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4641
4642	/**
4643	* Gets the VM state.
4644	*
4645	* @returns VM state.
4646	* @param pDevIns The device instance.
4647	* @thread Any thread (just keep in mind that it's volatile info).
4648	*/
4649	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
4650
4651	/**
4652	* Set the VM error message
4653	*
4654	* @returns rc.
4655	* @param pDevIns Driver instance.
4656	* @param rc VBox status code.
4657	* @param SRC_POS Use RT_SRC_POS.
4658	* @param pszFormat Error message format string.
4659	* @param ... Error message arguments.
4660	*/
4661	DECLRCCALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4662	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
4663
4664	/**
4665	* Set the VM error message
4666	*
4667	* @returns rc.
4668	* @param pDevIns Driver instance.
4669	* @param rc VBox status code.
4670	* @param SRC_POS Use RT_SRC_POS.
4671	* @param pszFormat Error message format string.
4672	* @param va Error message arguments.
4673	*/
4674	DECLRCCALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
4675	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4676
4677	/**
4678	* Set the VM runtime error message
4679	*
4680	* @returns VBox status code.
4681	* @param pDevIns Device instance.
4682	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4683	* @param pszErrorId Error ID string.
4684	* @param pszFormat Error message format string.
4685	* @param ... Error message arguments.
4686	*/
4687	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4688	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
4689
4690	/**
4691	* Set the VM runtime error message
4692	*
4693	* @returns VBox status code.
4694	* @param pDevIns Device instance.
4695	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
4696	* @param pszErrorId Error ID string.
4697	* @param pszFormat Error message format string.
4698	* @param va Error message arguments.
4699	*/
4700	DECLRCCALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
4701	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
4702
4703	/**
4704	* Gets the VM handle. Restricted API.
4705	*
4706	* @returns VM Handle.
4707	* @param pDevIns Device instance.
4708	*/
4709	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4710
4711	/**
4712	* Gets the VMCPU handle. Restricted API.
4713	*
4714	* @returns VMCPU Handle.
4715	* @param pDevIns The device instance.
4716	*/
4717	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4718
4719	/**
4720	* The the VM CPU ID of the current thread (restricted API).
4721	*
4722	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4723	* @param pDevIns The device instance.
4724	*/
4725	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4726
4727	/**
4728	* Get the current virtual clock time in a VM. The clock frequency must be
4729	* queried separately.
4730	*
4731	* @returns Current clock time.
4732	* @param pDevIns The device instance.
4733	*/
4734	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4735
4736	/**
4737	* Get the frequency of the virtual clock.
4738	*
4739	* @returns The clock frequency (not variable at run-time).
4740	* @param pDevIns The device instance.
4741	*/
4742	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4743
4744	/**
4745	* Get the current virtual clock time in a VM, in nanoseconds.
4746	*
4747	* @returns Current clock time (in ns).
4748	* @param pDevIns The device instance.
4749	*/
4750	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4751
4752	/**
4753	* Gets the NOP critical section.
4754	*
4755	* @returns The ring-3 address of the NOP critical section.
4756	* @param pDevIns The device instance.
4757	*/
4758	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4759
4760	/**
4761	* Changes the device level critical section from the automatically created
4762	* default to one desired by the device constructor.
4763	*
4764	* Must first be done in ring-3.
4765	*
4766	* @returns VBox status code.
4767	* @param pDevIns The device instance.
4768	* @param pCritSect The critical section to use. NULL is not
4769	* valid, instead use the NOP critical
4770	* section.
4771	*/
4772	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4773
4774	/** @name Exported PDM Critical Section Functions
4775	* @{ */
4776	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4777	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4778	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4779	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4780	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4781	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4782	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4783	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4784	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4785	/** @} */
4786
4787	/**
4788	* Gets the trace buffer handle.
4789	*
4790	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
4791	* really inteded for direct usage, thus no inline wrapper function.
4792	*
4793	* @returns Trace buffer handle or NIL_RTTRACEBUF.
4794	* @param pDevIns The device instance.
4795	*/
4796	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
4797
4798	/**
4799	* Sets up the PCI bus for the raw-mode context.
4800	*
4801	* This must be called after ring-3 has registered the PCI bus using
4802	* PDMDevHlpPCIBusRegister().
4803	*
4804	* @returns VBox status code.
4805	* @param pDevIns The device instance.
4806	* @param pPciBusReg The PCI bus registration information for raw-mode,
4807	* considered volatile.
4808	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
4809	*/
4810	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
4811
4812	/**
4813	* Sets up the IOMMU for the raw-mode context.
4814	*
4815	* This must be called after ring-3 has registered the IOMMU using
4816	* PDMDevHlpIommuRegister().
4817	*
4818	* @returns VBox status code.
4819	* @param pDevIns The device instance.
4820	* @param pIommuReg The IOMMU registration information for raw-mode,
4821	* considered volatile.
4822	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
4823	*/
4824	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
4825
4826	/**
4827	* Sets up the PIC for the ring-0 context.
4828	*
4829	* This must be called after ring-3 has registered the PIC using
4830	* PDMDevHlpPICRegister().
4831	*
4832	* @returns VBox status code.
4833	* @param pDevIns The device instance.
4834	* @param pPicReg The PIC registration information for ring-0,
4835	* considered volatile and copied.
4836	* @param ppPicHlp Where to return the ring-0 PIC helpers.
4837	*/
4838	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4839
4840	/**
4841	* Sets up the APIC for the raw-mode context.
4842	*
4843	* This must be called after ring-3 has registered the APIC using
4844	* PDMDevHlpApicRegister().
4845	*
4846	* @returns VBox status code.
4847	* @param pDevIns The device instance.
4848	*/
4849	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
4850
4851	/**
4852	* Sets up the IOAPIC for the ring-0 context.
4853	*
4854	* This must be called after ring-3 has registered the PIC using
4855	* PDMDevHlpIoApicRegister().
4856	*
4857	* @returns VBox status code.
4858	* @param pDevIns The device instance.
4859	* @param pIoApicReg The PIC registration information for ring-0,
4860	* considered volatile and copied.
4861	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
4862	*/
4863	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4864
4865	/**
4866	* Sets up the HPET for the raw-mode context.
4867	*
4868	* This must be called after ring-3 has registered the PIC using
4869	* PDMDevHlpHpetRegister().
4870	*
4871	* @returns VBox status code.
4872	* @param pDevIns The device instance.
4873	* @param pHpetReg The PIC registration information for raw-mode,
4874	* considered volatile and copied.
4875	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
4876	*/
4877	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
4878
4879	/** Space reserved for future members.
4880	* @{ */
4881	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
4882	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
4883	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
4884	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
4885	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
4886	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
4887	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
4888	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
4889	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
4890	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
4891	/** @} */
4892
4893	/** Just a safety precaution. */
4894	uint32_t u32TheEnd;
4895	} PDMDEVHLPRC;
4896	/** Pointer PDM Device RC API. */
4897	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
4898	/** Pointer PDM Device RC API. */
4899	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
4900
4901	/** Current PDMDEVHLP version number. */
4902	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 16, 0)
4903
4904
4905	/**
4906	* PDM Device API - R0 Variant.
4907	*/
4908	typedef struct PDMDEVHLPR0
4909	{
4910	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
4911	uint32_t u32Version;
4912
4913	/**
4914	* Sets up ring-0 callback handlers for an I/O port range.
4915	*
4916	* The range must have been created in ring-3 first using
4917	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
4918	*
4919	* @returns VBox status.
4920	* @param pDevIns The device instance to register the ports with.
4921	* @param hIoPorts The I/O port range handle.
4922	* @param pfnOut Pointer to function which is gonna handle OUT
4923	* operations. Optional.
4924	* @param pfnIn Pointer to function which is gonna handle IN operations.
4925	* Optional.
4926	* @param pfnOutStr Pointer to function which is gonna handle string OUT
4927	* operations. Optional.
4928	* @param pfnInStr Pointer to function which is gonna handle string IN
4929	* operations. Optional.
4930	* @param pvUser User argument to pass to the callbacks.
4931	*
4932	* @remarks Caller enters the device critical section prior to invoking the
4933	* registered callback methods.
4934	*
4935	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
4936	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
4937	*/
4938	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
4939	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
4940	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
4941	void *pvUser));
4942
4943	/**
4944	* Sets up ring-0 callback handlers for an MMIO region.
4945	*
4946	* The region must have been created in ring-3 first using
4947	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
4948	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
4949	*
4950	* @returns VBox status.
4951	* @param pDevIns The device instance to register the ports with.
4952	* @param hRegion The MMIO region handle.
4953	* @param pfnWrite Pointer to function which is gonna handle Write
4954	* operations.
4955	* @param pfnRead Pointer to function which is gonna handle Read
4956	* operations.
4957	* @param pfnFill Pointer to function which is gonna handle Fill/memset
4958	* operations. (optional)
4959	* @param pvUser User argument to pass to the callbacks.
4960	*
4961	* @remarks Caller enters the device critical section prior to invoking the
4962	* registered callback methods.
4963	*
4964	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
4965	* PDMDevHlpMmioUnmap().
4966	*/
4967	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
4968	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
4969
4970	/**
4971	* Sets up a ring-0 mapping for an MMIO2 region.
4972	*
4973	* The region must have been created in ring-3 first using
4974	* PDMDevHlpMmio2Create().
4975	*
4976	* @returns VBox status.
4977	* @param pDevIns The device instance to register the ports with.
4978	* @param hRegion The MMIO2 region handle.
4979	* @param offSub Start of what to map into ring-0. Must be page aligned.
4980	* @param cbSub Number of bytes to map into ring-0. Must be page
4981	* aligned. Zero is an alias for everything.
4982	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
4983	*
4984	* @thread EMT(0)
4985	* @note Only available at VM creation time.
4986	*
4987	* @sa PDMDevHlpMmio2Create().
4988	*/
4989	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
4990	void **ppvMapping));
4991
4992	/**
4993	* Bus master physical memory read from the given PCI device.
4994	*
4995	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
4996	* VERR_EM_MEMORY.
4997	* @param pDevIns The device instance.
4998	* @param pPciDev The PCI device structure. If NULL the default
4999	* PCI device for this device instance is used.
5000	* @param GCPhys Physical address start reading from.
5001	* @param pvBuf Where to put the read bits.
5002	* @param cbRead How many bytes to read.
5003	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5004	* @thread Any thread, but the call may involve the emulation thread.
5005	*/
5006	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5007	void *pvBuf, size_t cbRead, uint32_t fFlags));
5008
5009	/**
5010	* Bus master physical memory write from the given PCI device.
5011	*
5012	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5013	* VERR_EM_MEMORY.
5014	* @param pDevIns The device instance.
5015	* @param pPciDev The PCI device structure. If NULL the default
5016	* PCI device for this device instance is used.
5017	* @param GCPhys Physical address to write to.
5018	* @param pvBuf What to write.
5019	* @param cbWrite How many bytes to write.
5020	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5021	* @thread Any thread, but the call may involve the emulation thread.
5022	*/
5023	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5024	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5025
5026	/**
5027	* Set the IRQ for the given PCI device.
5028	*
5029	* @param pDevIns Device instance.
5030	* @param pPciDev The PCI device structure. If NULL the default
5031	* PCI device for this device instance is used.
5032	* @param iIrq IRQ number to set.
5033	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5034	* @thread Any thread, but will involve the emulation thread.
5035	*/
5036	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5037
5038	/**
5039	* Set ISA IRQ for a device.
5040	*
5041	* @param pDevIns Device instance.
5042	* @param iIrq IRQ number to set.
5043	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5044	* @thread Any thread, but will involve the emulation thread.
5045	*/
5046	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5047
5048	/**
5049	* Read physical memory.
5050	*
5051	* @returns VINF_SUCCESS (for now).
5052	* @param pDevIns Device instance.
5053	* @param GCPhys Physical address start reading from.
5054	* @param pvBuf Where to put the read bits.
5055	* @param cbRead How many bytes to read.
5056	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5057	*/
5058	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5059
5060	/**
5061	* Write to physical memory.
5062	*
5063	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5064	* @param pDevIns Device instance.
5065	* @param GCPhys Physical address to write to.
5066	* @param pvBuf What to write.
5067	* @param cbWrite How many bytes to write.
5068	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5069	*/
5070	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5071
5072	/**
5073	* Checks if the Gate A20 is enabled or not.
5074	*
5075	* @returns true if A20 is enabled.
5076	* @returns false if A20 is disabled.
5077	* @param pDevIns Device instance.
5078	* @thread The emulation thread.
5079	*/
5080	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5081
5082	/**
5083	* Gets the VM state.
5084	*
5085	* @returns VM state.
5086	* @param pDevIns The device instance.
5087	* @thread Any thread (just keep in mind that it's volatile info).
5088	*/
5089	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5090
5091	/**
5092	* Set the VM error message
5093	*
5094	* @returns rc.
5095	* @param pDevIns Driver instance.
5096	* @param rc VBox status code.
5097	* @param SRC_POS Use RT_SRC_POS.
5098	* @param pszFormat Error message format string.
5099	* @param ... Error message arguments.
5100	*/
5101	DECLR0CALLBACKMEMBER(int, pfnVMSetError,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5102	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
5103
5104	/**
5105	* Set the VM error message
5106	*
5107	* @returns rc.
5108	* @param pDevIns Driver instance.
5109	* @param rc VBox status code.
5110	* @param SRC_POS Use RT_SRC_POS.
5111	* @param pszFormat Error message format string.
5112	* @param va Error message arguments.
5113	*/
5114	DECLR0CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
5115	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
5116
5117	/**
5118	* Set the VM runtime error message
5119	*
5120	* @returns VBox status code.
5121	* @param pDevIns Device instance.
5122	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5123	* @param pszErrorId Error ID string.
5124	* @param pszFormat Error message format string.
5125	* @param ... Error message arguments.
5126	*/
5127	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeError,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5128	const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(4, 5));
5129
5130	/**
5131	* Set the VM runtime error message
5132	*
5133	* @returns VBox status code.
5134	* @param pDevIns Device instance.
5135	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
5136	* @param pszErrorId Error ID string.
5137	* @param pszFormat Error message format string.
5138	* @param va Error message arguments.
5139	*/
5140	DECLR0CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
5141	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
5142
5143	/**
5144	* Gets the VM handle. Restricted API.
5145	*
5146	* @returns VM Handle.
5147	* @param pDevIns Device instance.
5148	*/
5149	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5150
5151	/**
5152	* Gets the VMCPU handle. Restricted API.
5153	*
5154	* @returns VMCPU Handle.
5155	* @param pDevIns The device instance.
5156	*/
5157	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5158
5159	/**
5160	* The the VM CPU ID of the current thread (restricted API).
5161	*
5162	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5163	* @param pDevIns The device instance.
5164	*/
5165	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5166
5167	/**
5168	* Translates a timer handle to a pointer.
5169	*
5170	* @returns The time address.
5171	* @param pDevIns The device instance.
5172	* @param hTimer The timer handle.
5173	*/
5174	DECLR0CALLBACKMEMBER(PTMTIMERR0, pfnTimerToPtr,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5175
5176	/** @name Timer handle method wrappers
5177	* @{ */
5178	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5179	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5180	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5181	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5182	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5183	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5184	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5185	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5186	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5187	/** Takes the clock lock then enters the specified critical section. */
5188	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5189	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5190	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5191	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5192	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5193	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5194	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5195	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5196	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5197	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5198	/** @} */
5199
5200	/**
5201	* Get the current virtual clock time in a VM. The clock frequency must be
5202	* queried separately.
5203	*
5204	* @returns Current clock time.
5205	* @param pDevIns The device instance.
5206	*/
5207	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5208
5209	/**
5210	* Get the frequency of the virtual clock.
5211	*
5212	* @returns The clock frequency (not variable at run-time).
5213	* @param pDevIns The device instance.
5214	*/
5215	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5216
5217	/**
5218	* Get the current virtual clock time in a VM, in nanoseconds.
5219	*
5220	* @returns Current clock time (in ns).
5221	* @param pDevIns The device instance.
5222	*/
5223	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5224
5225	/** @name Exported PDM Queue Functions
5226	* @{ */
5227	DECLR0CALLBACKMEMBER(PPDMQUEUE, pfnQueueToPtr,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5228	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5229	DECLR0CALLBACKMEMBER(void, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5230	DECLR0CALLBACKMEMBER(void, pfnQueueInsertEx,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay));
5231	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5232	/** @} */
5233
5234	/** @name PDM Task
5235	* @{ */
5236	/**
5237	* Triggers the running the given task.
5238	*
5239	* @returns VBox status code.
5240	* @retval VINF_ALREADY_POSTED is the task is already pending.
5241	* @param pDevIns The device instance.
5242	* @param hTask The task to trigger.
5243	* @thread Any thread.
5244	*/
5245	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5246	/** @} */
5247
5248	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5249	* These semaphores can be signalled from ring-0.
5250	* @{ */
5251	/** @sa SUPSemEventSignal */
5252	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5253	/** @sa SUPSemEventWaitNoResume */
5254	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5255	/** @sa SUPSemEventWaitNsAbsIntr */
5256	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5257	/** @sa SUPSemEventWaitNsRelIntr */
5258	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5259	/** @sa SUPSemEventGetResolution */
5260	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5261	/** @} */
5262
5263	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5264	* These semaphores can be signalled from ring-0.
5265	* @{ */
5266	/** @sa SUPSemEventMultiSignal */
5267	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5268	/** @sa SUPSemEventMultiReset */
5269	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5270	/** @sa SUPSemEventMultiWaitNoResume */
5271	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5272	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5273	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5274	/** @sa SUPSemEventMultiWaitNsRelIntr */
5275	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5276	/** @sa SUPSemEventMultiGetResolution */
5277	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5278	/** @} */
5279
5280	/**
5281	* Gets the NOP critical section.
5282	*
5283	* @returns The ring-3 address of the NOP critical section.
5284	* @param pDevIns The device instance.
5285	*/
5286	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5287
5288	/**
5289	* Changes the device level critical section from the automatically created
5290	* default to one desired by the device constructor.
5291	*
5292	* Must first be done in ring-3.
5293	*
5294	* @returns VBox status code.
5295	* @param pDevIns The device instance.
5296	* @param pCritSect The critical section to use. NULL is not
5297	* valid, instead use the NOP critical
5298	* section.
5299	*/
5300	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5301
5302	/** @name Exported PDM Critical Section Functions
5303	* @{ */
5304	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5305	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5306	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5307	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5308	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5309	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5310	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5311	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5312	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5313	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5314	/** @} */
5315
5316	/**
5317	* Gets the trace buffer handle.
5318	*
5319	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5320	* really inteded for direct usage, thus no inline wrapper function.
5321	*
5322	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5323	* @param pDevIns The device instance.
5324	*/
5325	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5326
5327	/**
5328	* Sets up the PCI bus for the ring-0 context.
5329	*
5330	* This must be called after ring-3 has registered the PCI bus using
5331	* PDMDevHlpPCIBusRegister().
5332	*
5333	* @returns VBox status code.
5334	* @param pDevIns The device instance.
5335	* @param pPciBusReg The PCI bus registration information for ring-0,
5336	* considered volatile and copied.
5337	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5338	*/
5339	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5340
5341	/**
5342	* Sets up the IOMMU for the ring-0 context.
5343	*
5344	* This must be called after ring-3 has registered the IOMMU using
5345	* PDMDevHlpIommuRegister().
5346	*
5347	* @returns VBox status code.
5348	* @param pDevIns The device instance.
5349	* @param pIommuReg The IOMMU registration information for ring-0,
5350	* considered volatile and copied.
5351	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5352	*/
5353	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5354
5355	/**
5356	* Sets up the PIC for the ring-0 context.
5357	*
5358	* This must be called after ring-3 has registered the PIC using
5359	* PDMDevHlpPICRegister().
5360	*
5361	* @returns VBox status code.
5362	* @param pDevIns The device instance.
5363	* @param pPicReg The PIC registration information for ring-0,
5364	* considered volatile and copied.
5365	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5366	*/
5367	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5368
5369	/**
5370	* Sets up the APIC for the ring-0 context.
5371	*
5372	* This must be called after ring-3 has registered the APIC using
5373	* PDMDevHlpApicRegister().
5374	*
5375	* @returns VBox status code.
5376	* @param pDevIns The device instance.
5377	*/
5378	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5379
5380	/**
5381	* Sets up the IOAPIC for the ring-0 context.
5382	*
5383	* This must be called after ring-3 has registered the PIC using
5384	* PDMDevHlpIoApicRegister().
5385	*
5386	* @returns VBox status code.
5387	* @param pDevIns The device instance.
5388	* @param pIoApicReg The PIC registration information for ring-0,
5389	* considered volatile and copied.
5390	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5391	*/
5392	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5393
5394	/**
5395	* Sets up the HPET for the ring-0 context.
5396	*
5397	* This must be called after ring-3 has registered the PIC using
5398	* PDMDevHlpHpetRegister().
5399	*
5400	* @returns VBox status code.
5401	* @param pDevIns The device instance.
5402	* @param pHpetReg The PIC registration information for ring-0,
5403	* considered volatile and copied.
5404	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5405	*/
5406	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5407
5408	/** Space reserved for future members.
5409	* @{ */
5410	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
5411	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
5412	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
5413	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
5414	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
5415	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
5416	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
5417	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
5418	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
5419	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
5420	/** @} */
5421
5422	/** Just a safety precaution. */
5423	uint32_t u32TheEnd;
5424	} PDMDEVHLPR0;
5425	/** Pointer PDM Device R0 API. */
5426	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
5427	/** Pointer PDM Device GC API. */
5428	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
5429
5430	/** Current PDMDEVHLP version number. */
5431	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 18, 0)
5432
5433
5434	/**
5435	* PDM Device Instance.
5436	*/
5437	typedef struct PDMDEVINSR3
5438	{
5439	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
5440	uint32_t u32Version;
5441	/** Device instance number. */
5442	uint32_t iInstance;
5443	/** Size of the ring-3, raw-mode and shared bits. */
5444	uint32_t cbRing3;
5445	/** Set if ring-0 context is enabled. */
5446	bool fR0Enabled;
5447	/** Set if raw-mode context is enabled. */
5448	bool fRCEnabled;
5449	/** Alignment padding. */
5450	bool afReserved[2];
5451	/** Pointer the HC PDM Device API. */
5452	PCPDMDEVHLPR3 pHlpR3;
5453	/** Pointer to the shared device instance data. */
5454	RTR3PTR pvInstanceDataR3;
5455	/** Pointer to the device instance data for ring-3. */
5456	RTR3PTR pvInstanceDataForR3;
5457	/** The critical section for the device.
5458	*
5459	* TM and IOM will enter this critical section before calling into the device
5460	* code. PDM will when doing power on, power off, reset, suspend and resume
5461	* notifications. SSM will currently not, but this will be changed later on.
5462	*
5463	* The device gets a critical section automatically assigned to it before
5464	* the constructor is called. If the constructor wishes to use a different
5465	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5466	* very early on.
5467	*/
5468	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
5469	/** Pointer to device registration structure. */
5470	R3PTRTYPE(PCPDMDEVREG) pReg;
5471	/** Configuration handle. */
5472	R3PTRTYPE(PCFGMNODE) pCfg;
5473	/** The base interface of the device.
5474	*
5475	* The device constructor initializes this if it has any
5476	* device level interfaces to export. To obtain this interface
5477	* call PDMR3QueryDevice(). */
5478	PDMIBASE IBase;
5479
5480	/** Tracing indicator. */
5481	uint32_t fTracing;
5482	/** The tracing ID of this device. */
5483	uint32_t idTracing;
5484
5485	/** Ring-3 pointer to the raw-mode device instance. */
5486	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
5487	/** Raw-mode address of the raw-mode device instance. */
5488	RTRGPTR pDevInsForRC;
5489	/** Ring-3 pointer to the raw-mode instance data. */
5490	RTR3PTR pvInstanceDataForRCR3;
5491
5492	/** PCI device structure size. */
5493	uint32_t cbPciDev;
5494	/** Number of PCI devices in apPciDevs. */
5495	uint32_t cPciDevs;
5496	/** Pointer to the PCI devices for this device.
5497	* (Allocated after the shared instance data.)
5498	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5499	* two devices ever needing it can use cbPciDev and do the address
5500	* calculations that for entries 8+. */
5501	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5502
5503	/** Temporarily. */
5504	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
5505	/** Temporarily. */
5506	RTR0PTR pvInstanceDataR0;
5507	/** Temporarily. */
5508	RTRCPTR pvInstanceDataRC;
5509	/** Align the internal data more naturally. */
5510	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
5511
5512	/** Internal data. */
5513	union
5514	{
5515	#ifdef PDMDEVINSINT_DECLARED
5516	PDMDEVINSINTR3 s;
5517	#endif
5518	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
5519	} Internal;
5520
5521	/** Device instance data for ring-3. The size of this area is defined
5522	* in the PDMDEVREG::cbInstanceR3 field. */
5523	char achInstanceData[8];
5524	} PDMDEVINSR3;
5525
5526	/** Current PDMDEVINSR3 version number. */
5527	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
5528
5529	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
5530	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
5531
5532
5533	/**
5534	* PDM ring-0 device instance.
5535	*/
5536	typedef struct PDMDEVINSR0
5537	{
5538	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
5539	uint32_t u32Version;
5540	/** Device instance number. */
5541	uint32_t iInstance;
5542
5543	/** Pointer the HC PDM Device API. */
5544	PCPDMDEVHLPR0 pHlpR0;
5545	/** Pointer to the shared device instance data. */
5546	RTR0PTR pvInstanceDataR0;
5547	/** Pointer to the device instance data for ring-0. */
5548	RTR0PTR pvInstanceDataForR0;
5549	/** The critical section for the device.
5550	*
5551	* TM and IOM will enter this critical section before calling into the device
5552	* code. PDM will when doing power on, power off, reset, suspend and resume
5553	* notifications. SSM will currently not, but this will be changed later on.
5554	*
5555	* The device gets a critical section automatically assigned to it before
5556	* the constructor is called. If the constructor wishes to use a different
5557	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5558	* very early on.
5559	*/
5560	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
5561	/** Pointer to the ring-0 device registration structure. */
5562	R0PTRTYPE(PCPDMDEVREGR0) pReg;
5563	/** Ring-3 address of the ring-3 device instance. */
5564	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
5565	/** Ring-0 pointer to the ring-3 device instance. */
5566	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
5567	/** Ring-0 pointer to the ring-3 instance data. */
5568	RTR0PTR pvInstanceDataForR3R0;
5569	/** Raw-mode address of the raw-mode device instance. */
5570	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
5571	/** Ring-0 pointer to the raw-mode device instance. */
5572	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
5573	/** Ring-0 pointer to the raw-mode instance data. */
5574	RTR0PTR pvInstanceDataForRCR0;
5575
5576	/** PCI device structure size. */
5577	uint32_t cbPciDev;
5578	/** Number of PCI devices in apPciDevs. */
5579	uint32_t cPciDevs;
5580	/** Pointer to the PCI devices for this device.
5581	* (Allocated after the shared instance data.)
5582	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
5583	* two devices ever needing it can use cbPciDev and do the address
5584	* calculations that for entries 8+. */
5585	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5586
5587	/** Align the internal data more naturally. */
5588	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
5589
5590	/** Internal data. */
5591	union
5592	{
5593	#ifdef PDMDEVINSINT_DECLARED
5594	PDMDEVINSINTR0 s;
5595	#endif
5596	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
5597	} Internal;
5598
5599	/** Device instance data for ring-0. The size of this area is defined
5600	* in the PDMDEVREG::cbInstanceR0 field. */
5601	char achInstanceData[8];
5602	} PDMDEVINSR0;
5603
5604	/** Current PDMDEVINSR0 version number. */
5605	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
5606
5607
5608	/**
5609	* PDM raw-mode device instance.
5610	*/
5611	typedef struct PDMDEVINSRC
5612	{
5613	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
5614	uint32_t u32Version;
5615	/** Device instance number. */
5616	uint32_t iInstance;
5617
5618	/** Pointer the HC PDM Device API. */
5619	PCPDMDEVHLPRC pHlpRC;
5620	/** Pointer to the shared device instance data. */
5621	RTRGPTR pvInstanceDataRC;
5622	/** Pointer to the device instance data for raw-mode. */
5623	RTRGPTR pvInstanceDataForRC;
5624	/** The critical section for the device.
5625	*
5626	* TM and IOM will enter this critical section before calling into the device
5627	* code. PDM will when doing power on, power off, reset, suspend and resume
5628	* notifications. SSM will currently not, but this will be changed later on.
5629	*
5630	* The device gets a critical section automatically assigned to it before
5631	* the constructor is called. If the constructor wishes to use a different
5632	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
5633	* very early on.
5634	*/
5635	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
5636	/** Pointer to the raw-mode device registration structure. */
5637	RGPTRTYPE(PCPDMDEVREGRC) pReg;
5638
5639	/** PCI device structure size. */
5640	uint32_t cbPciDev;
5641	/** Number of PCI devices in apPciDevs. */
5642	uint32_t cPciDevs;
5643	/** Pointer to the PCI devices for this device.
5644	* (Allocated after the shared instance data.) */
5645	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
5646
5647	/** Align the internal data more naturally. */
5648	uint32_t au32Padding[14];
5649
5650	/** Internal data. */
5651	union
5652	{
5653	#ifdef PDMDEVINSINT_DECLARED
5654	PDMDEVINSINTRC s;
5655	#endif
5656	uint8_t padding[0x10];
5657	} Internal;
5658
5659	/** Device instance data for ring-0. The size of this area is defined
5660	* in the PDMDEVREG::cbInstanceR0 field. */
5661	char achInstanceData[8];
5662	} PDMDEVINSRC;
5663
5664	/** Current PDMDEVINSR0 version number. */
5665	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
5666
5667
5668	/** @def PDM_DEVINS_VERSION
5669	* Current PDMDEVINS version number. */
5670	/** @typedef PDMDEVINS
5671	* The device instance structure for the current context. */
5672	#ifdef IN_RING3
5673	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
5674	typedef PDMDEVINSR3 PDMDEVINS;
5675	#elif defined(IN_RING0)
5676	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
5677	typedef PDMDEVINSR0 PDMDEVINS;
5678	#elif defined(IN_RC)
5679	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
5680	typedef PDMDEVINSRC PDMDEVINS;
5681	#else
5682	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
5683	#endif
5684
5685	/**
5686	* Get the pointer to an PCI device.
5687	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5688	*/
5689	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
5690	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
5691	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
5692
5693	/**
5694	* Calc the pointer to of a given PCI device.
5695	* @note Returns NULL if @a a_idxPciDev is out of bounds.
5696	*/
5697	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
5698	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
5699	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
5700	: (PPDMPCIDEV)NULL )
5701
5702
5703	/**
5704	* Checks the structure versions of the device instance and device helpers,
5705	* returning if they are incompatible.
5706	*
5707	* This is for use in the constructor.
5708	*
5709	* @param pDevIns The device instance pointer.
5710	*/
5711	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
5712	do \
5713	{ \
5714	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5715	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5716	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
5717	VERR_PDM_DEVINS_VERSION_MISMATCH); \
5718	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5719	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
5720	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
5721	} while (0)
5722
5723	/**
5724	* Quietly checks the structure versions of the device instance and device
5725	* helpers, returning if they are incompatible.
5726	*
5727	* This is for use in the destructor.
5728	*
5729	* @param pDevIns The device instance pointer.
5730	*/
5731	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
5732	do \
5733	{ \
5734	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
5735	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
5736	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
5737	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
5738	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
5739	} while (0)
5740
5741	/**
5742	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
5743	* constructor - returns on failure.
5744	*
5745	* This should be invoked after having initialized the instance data
5746	* sufficiently for the correct operation of the destructor. The destructor is
5747	* always called!
5748	*
5749	* @param pDevIns Pointer to the PDM device instance.
5750	* @param pszValidValues Patterns describing the valid value names. See
5751	* RTStrSimplePatternMultiMatch for details on the
5752	* pattern syntax.
5753	* @param pszValidNodes Patterns describing the valid node (key) names.
5754	* Pass empty string if no valid nodes.
5755	*/
5756	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
5757	do \
5758	{ \
5759	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
5760	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
5761	if (RT_SUCCESS(rcValCfg)) \
5762	{ /* likely */ } else return rcValCfg; \
5763	} while (0)
5764
5765	/** @def PDMDEV_ASSERT_EMT
5766	* Assert that the current thread is the emulation thread.
5767	*/
5768	#ifdef VBOX_STRICT
5769	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5770	#else
5771	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
5772	#endif
5773
5774	/** @def PDMDEV_ASSERT_OTHER
5775	* Assert that the current thread is NOT the emulation thread.
5776	*/
5777	#ifdef VBOX_STRICT
5778	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5779	#else
5780	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
5781	#endif
5782
5783	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
5784	* Assert that the current thread is owner of the VM lock.
5785	*/
5786	#ifdef VBOX_STRICT
5787	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
5788	#else
5789	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
5790	#endif
5791
5792	/** @def PDMDEV_SET_ERROR
5793	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
5794	*/
5795	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
5796	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
5797
5798	/** @def PDMDEV_SET_RUNTIME_ERROR
5799	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
5800	*/
5801	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
5802	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
5803
5804	/** @def PDMDEVINS_2_RCPTR
5805	* Converts a PDM Device instance pointer a RC PDM Device instance pointer.
5806	*/
5807	#ifdef IN_RC
5808	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
5809	#else
5810	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
5811	#endif
5812
5813	/** @def PDMDEVINS_2_R3PTR
5814	* Converts a PDM Device instance pointer a R3 PDM Device instance pointer.
5815	*/
5816	#ifdef IN_RING3
5817	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
5818	#else
5819	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
5820	#endif
5821
5822	/** @def PDMDEVINS_2_R0PTR
5823	* Converts a PDM Device instance pointer a R0 PDM Device instance pointer.
5824	*/
5825	#ifdef IN_RING0
5826	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
5827	#else
5828	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
5829	#endif
5830
5831	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
5832	* Converts a PDM device instance data pointer to a ring-0 one.
5833	* @deprecated
5834	*/
5835	#ifdef IN_RING0
5836	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
5837	#else
5838	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
5839	#endif
5840
5841
5842	/** @def PDMDEVINS_2_DATA
5843	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
5844	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
5845	*
5846	* @note Do no use this macro in common code working on a core structure which
5847	* device specific code has expanded.
5848	*/
5849	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5850	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
5851	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5852	{ \
5853	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
5854	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
5855	return pLambdaRet; \
5856	}(a_pDevIns))
5857	#else
5858	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
5859	#endif
5860
5861	/** @def PDMDEVINS_2_DATA_CC
5862	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
5863	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
5864	*
5865	* @note Do no use this macro in common code working on a core structure which
5866	* device specific code has expanded.
5867	*/
5868	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
5869	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
5870	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
5871	{ \
5872	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
5873	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
5874	return pLambdaRet; \
5875	}(a_pDevIns))
5876	#else
5877	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
5878	#endif
5879
5880
5881	#ifdef IN_RING3
5882
5883	/**
5884	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
5885	*/
5886	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5887	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
5888	PIOMIOPORTHANDLE phIoPorts)
5889	{
5890	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5891	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5892	if (RT_SUCCESS(rc))
5893	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5894	return rc;
5895	}
5896
5897	/**
5898	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
5899	*/
5900	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5901	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
5902	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5903	{
5904	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5905	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5906	if (RT_SUCCESS(rc))
5907	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5908	return rc;
5909	}
5910
5911	/**
5912	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
5913	*/
5914	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5915	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5916	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5917	{
5918	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5919	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
5920	if (RT_SUCCESS(rc))
5921	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5922	return rc;
5923	}
5924
5925	/**
5926	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
5927	*/
5928	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
5929	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5930	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5931	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5932	{
5933	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
5934	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5935	if (RT_SUCCESS(rc))
5936	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
5937	return rc;
5938	}
5939
5940	/**
5941	* @sa PDMDevHlpIoPortCreateEx
5942	*/
5943	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
5944	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
5945	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5946	{
5947	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
5948	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5949	}
5950
5951
5952	/**
5953	* @sa PDMDevHlpIoPortCreateEx
5954	*/
5955	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
5956	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
5957	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5958	{
5959	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
5960	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
5961	}
5962
5963	/**
5964	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
5965	*/
5966	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
5967	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5968	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
5969	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
5970	{
5971	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
5972	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
5973	}
5974
5975	/**
5976	* @copydoc PDMDEVHLPR3::pfnIoPortMap
5977	*/
5978	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
5979	{
5980	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
5981	}
5982
5983	/**
5984	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
5985	*/
5986	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5987	{
5988	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
5989	}
5990
5991	/**
5992	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
5993	*/
5994	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
5995	{
5996	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
5997	}
5998
5999
6000	#endif /* IN_RING3 */
6001	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6002
6003	/**
6004	* @sa PDMDevHlpIoPortSetUpContextEx
6005	*/
6006	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6007	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6008	{
6009	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6010	}
6011
6012	/**
6013	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6014	*/
6015	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6016	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6017	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6018	{
6019	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6020	}
6021
6022	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6023	#ifdef IN_RING3
6024
6025	/**
6026	* @sa PDMDevHlpMmioCreateEx
6027	*/
6028	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6029	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6030	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6031	{
6032	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6033	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6034	}
6035
6036	/**
6037	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6038	*/
6039	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6040	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6041	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6042	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6043	{
6044	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6045	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6046	}
6047
6048	/**
6049	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6050	*/
6051	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6052	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6053	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6054	{
6055	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6056	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6057	if (RT_SUCCESS(rc))
6058	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6059	return rc;
6060	}
6061
6062	/**
6063	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6064	*/
6065	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6066	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6067	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6068	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6069	{
6070	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6071	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6072	if (RT_SUCCESS(rc))
6073	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6074	return rc;
6075	}
6076
6077	/**
6078	* @copydoc PDMDEVHLPR3::pfnMmioMap
6079	*/
6080	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6081	{
6082	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6083	}
6084
6085	/**
6086	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6087	*/
6088	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6089	{
6090	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6091	}
6092
6093	/**
6094	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6095	*/
6096	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6097	{
6098	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6099	}
6100
6101	/**
6102	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6103	*/
6104	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6105	{
6106	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6107	}
6108
6109	#endif /* IN_RING3 */
6110	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6111
6112	/**
6113	* @sa PDMDevHlpMmioSetUpContextEx
6114	*/
6115	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6116	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6117	{
6118	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6119	}
6120
6121	/**
6122	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6123	*/
6124	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6125	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6126	{
6127	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6128	}
6129
6130	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6131	#ifdef IN_RING3
6132
6133	/**
6134	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6135	*/
6136	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6137	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6138	{
6139	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6140	}
6141
6142	/**
6143	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6144	*/
6145	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6146	{
6147	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6148	}
6149
6150	/**
6151	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6152	*/
6153	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6154	{
6155	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6156	}
6157
6158	/**
6159	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6160	*/
6161	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6162	{
6163	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6164	}
6165
6166	/**
6167	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6168	*/
6169	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6170	{
6171	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6172	}
6173
6174	#endif /* IN_RING3 */
6175	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6176
6177	/**
6178	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6179	*/
6180	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6181	size_t offSub, size_t cbSub, void **ppvMapping)
6182	{
6183	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6184	}
6185
6186	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6187	#ifdef IN_RING3
6188
6189	/**
6190	* @copydoc PDMDEVHLPR3::pfnROMRegister
6191	*/
6192	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6193	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6194	{
6195	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6196	}
6197
6198	/**
6199	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6200	*/
6201	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6202	{
6203	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6204	}
6205
6206	/**
6207	* Register a save state data unit.
6208	*
6209	* @returns VBox status.
6210	* @param pDevIns The device instance.
6211	* @param uVersion Data layout version number.
6212	* @param cbGuess The approximate amount of data in the unit.
6213	* Only for progress indicators.
6214	* @param pfnSaveExec Execute save callback, optional.
6215	* @param pfnLoadExec Execute load callback, optional.
6216	*/
6217	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6218	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6219	{
6220	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6221	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6222	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6223	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6224	}
6225
6226	/**
6227	* Register a save state data unit with a live save callback as well.
6228	*
6229	* @returns VBox status.
6230	* @param pDevIns The device instance.
6231	* @param uVersion Data layout version number.
6232	* @param cbGuess The approximate amount of data in the unit.
6233	* Only for progress indicators.
6234	* @param pfnLiveExec Execute live callback, optional.
6235	* @param pfnSaveExec Execute save callback, optional.
6236	* @param pfnLoadExec Execute load callback, optional.
6237	*/
6238	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6239	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6240	{
6241	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6242	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6243	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6244	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6245	}
6246
6247	/**
6248	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6249	*/
6250	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6251	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6252	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6253	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6254	{
6255	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6256	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6257	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6258	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6259	}
6260
6261	/**
6262	* @copydoc PDMDEVHLPR3::pfnTMTimerCreate
6263	*/
6264	DECLINLINE(int) PDMDevHlpTMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6265	uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
6266	{
6267	return pDevIns->pHlpR3->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
6268	}
6269
6270	/**
6271	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6272	*/
6273	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6274	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6275	{
6276	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6277	}
6278
6279	#endif /* IN_RING3 */
6280
6281	/**
6282	* @copydoc PDMDEVHLPR3::pfnTimerToPtr
6283	*/
6284	DECLINLINE(PTMTIMER) PDMDevHlpTimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6285	{
6286	return pDevIns->CTX_SUFF(pHlp)->pfnTimerToPtr(pDevIns, hTimer);
6287	}
6288
6289	/**
6290	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6291	*/
6292	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6293	{
6294	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6295	}
6296
6297	/**
6298	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6299	*/
6300	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6301	{
6302	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6303	}
6304
6305	/**
6306	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
6307	*/
6308	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
6309	{
6310	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
6311	}
6312
6313	/**
6314	* @copydoc PDMDEVHLPR3::pfnTimerGet
6315	*/
6316	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6317	{
6318	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
6319	}
6320
6321	/**
6322	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
6323	*/
6324	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6325	{
6326	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
6327	}
6328
6329	/**
6330	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
6331	*/
6332	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6333	{
6334	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
6335	}
6336
6337	/**
6338	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
6339	*/
6340	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6341	{
6342	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
6343	}
6344
6345	/**
6346	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
6347	*/
6348	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6349	{
6350	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
6351	}
6352
6353	/**
6354	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
6355	*/
6356	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
6357	{
6358	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
6359	}
6360
6361	/**
6362	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
6363	*/
6364	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
6365	{
6366	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
6367	}
6368
6369	/**
6370	* @copydoc PDMDEVHLPR3::pfnTimerSet
6371	*/
6372	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
6373	{
6374	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
6375	}
6376
6377	/**
6378	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
6379	*/
6380	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
6381	{
6382	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
6383	}
6384
6385	/**
6386	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
6387	*/
6388	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
6389	{
6390	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
6391	}
6392
6393	/**
6394	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
6395	*/
6396	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
6397	{
6398	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
6399	}
6400
6401	/**
6402	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
6403	*/
6404	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
6405	{
6406	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
6407	}
6408
6409	/**
6410	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
6411	*/
6412	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
6413	{
6414	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
6415	}
6416
6417	/**
6418	* @copydoc PDMDEVHLPR3::pfnTimerStop
6419	*/
6420	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6421	{
6422	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
6423	}
6424
6425	/**
6426	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
6427	*/
6428	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6429	{
6430	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
6431	}
6432
6433	/**
6434	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
6435	*/
6436	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6437	{
6438	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
6439	}
6440
6441	#ifdef IN_RING3
6442
6443	/**
6444	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
6445	*/
6446	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
6447	{
6448	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
6449	}
6450
6451	/**
6452	* @copydoc PDMDEVHLPR3::pfnTimerSave
6453	*/
6454	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6455	{
6456	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
6457	}
6458
6459	/**
6460	* @copydoc PDMDEVHLPR3::pfnTimerLoad
6461	*/
6462	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
6463	{
6464	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
6465	}
6466
6467	/**
6468	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
6469	*/
6470	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
6471	{
6472	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
6473	}
6474
6475	/**
6476	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
6477	*/
6478	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
6479	{
6480	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
6481	}
6482
6483	#endif
6484
6485	/**
6486	* Read physical memory - unknown data usage.
6487	*
6488	* @returns VINF_SUCCESS (for now).
6489	* @param pDevIns The device instance.
6490	* @param GCPhys Physical address start reading from.
6491	* @param pvBuf Where to put the read bits.
6492	* @param cbRead How many bytes to read.
6493	* @thread Any thread, but the call may involve the emulation thread.
6494	*/
6495	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6496	{
6497	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6498	}
6499
6500	/**
6501	* Write to physical memory - unknown data usage.
6502	*
6503	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6504	* @param pDevIns The device instance.
6505	* @param GCPhys Physical address to write to.
6506	* @param pvBuf What to write.
6507	* @param cbWrite How many bytes to write.
6508	* @thread Any thread, but the call may involve the emulation thread.
6509	*/
6510	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6511	{
6512	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
6513	}
6514
6515	/**
6516	* Read physical memory - reads meta data processed by the device.
6517	*
6518	* @returns VINF_SUCCESS (for now).
6519	* @param pDevIns The device instance.
6520	* @param GCPhys Physical address start reading from.
6521	* @param pvBuf Where to put the read bits.
6522	* @param cbRead How many bytes to read.
6523	* @thread Any thread, but the call may involve the emulation thread.
6524	*/
6525	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6526	{
6527	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6528	}
6529
6530	/**
6531	* Write to physical memory - written data was created/altered by the device.
6532	*
6533	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6534	* @param pDevIns The device instance.
6535	* @param GCPhys Physical address to write to.
6536	* @param pvBuf What to write.
6537	* @param cbWrite How many bytes to write.
6538	* @thread Any thread, but the call may involve the emulation thread.
6539	*/
6540	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6541	{
6542	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
6543	}
6544
6545	/**
6546	* Read physical memory - read data will not be touched by the device.
6547	*
6548	* @returns VINF_SUCCESS (for now).
6549	* @param pDevIns The device instance.
6550	* @param GCPhys Physical address start reading from.
6551	* @param pvBuf Where to put the read bits.
6552	* @param cbRead How many bytes to read.
6553	* @thread Any thread, but the call may involve the emulation thread.
6554	*/
6555	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
6556	{
6557	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6558	}
6559
6560	/**
6561	* Write to physical memory - written data was not touched/created by the device.
6562	*
6563	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
6564	* @param pDevIns The device instance.
6565	* @param GCPhys Physical address to write to.
6566	* @param pvBuf What to write.
6567	* @param cbWrite How many bytes to write.
6568	* @thread Any thread, but the call may involve the emulation thread.
6569	*/
6570	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
6571	{
6572	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
6573	}
6574
6575	#ifdef IN_RING3
6576
6577	/**
6578	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
6579	*/
6580	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
6581	{
6582	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
6583	}
6584
6585	/**
6586	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
6587	*/
6588	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
6589	PPGMPAGEMAPLOCK pLock)
6590	{
6591	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
6592	}
6593
6594	/**
6595	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
6596	*/
6597	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
6598	{
6599	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
6600	}
6601
6602	/**
6603	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
6604	*/
6605	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6606	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
6607	{
6608	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6609	}
6610
6611	/**
6612	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
6613	*/
6614	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
6615	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
6616	{
6617	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
6618	}
6619
6620	/**
6621	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
6622	*/
6623	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
6624	{
6625	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
6626	}
6627
6628	/**
6629	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
6630	*/
6631	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
6632	{
6633	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
6634	}
6635
6636	/**
6637	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
6638	*/
6639	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
6640	{
6641	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
6642	}
6643
6644	/**
6645	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
6646	*/
6647	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
6648	{
6649	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
6650	}
6651
6652	/**
6653	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
6654	*/
6655	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
6656	{
6657	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
6658	}
6659
6660	/**
6661	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
6662	*/
6663	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
6664	{
6665	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
6666	}
6667
6668	/**
6669	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
6670	*/
6671	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
6672	{
6673	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
6674	}
6675
6676	/**
6677	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
6678	*/
6679	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
6680	{
6681	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
6682	}
6683	#endif /* IN_RING3 */
6684
6685	/**
6686	* @copydoc PDMDEVHLPR3::pfnVMState
6687	*/
6688	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
6689	{
6690	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
6691	}
6692
6693	#ifdef IN_RING3
6694	/**
6695	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
6696	*/
6697	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
6698	{
6699	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
6700	}
6701	#endif /* IN_RING3 */
6702
6703	/**
6704	* @copydoc PDMDEVHLPR3::pfnVMSetError
6705	*/
6706	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
6707	const char *pszFormat, ...)
6708	{
6709	va_list va;
6710	va_start(va, pszFormat);
6711	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
6712	va_end(va);
6713	return rc;
6714	}
6715
6716	/**
6717	* @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError
6718	*/
6719	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
6720	const char *pszFormat, ...)
6721	{
6722	va_list va;
6723	int rc;
6724	va_start(va, pszFormat);
6725	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
6726	va_end(va);
6727	return rc;
6728	}
6729
6730	/**
6731	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
6732	*
6733	* @returns VBox status code which must be passed up to the VMM. This will be
6734	* VINF_SUCCESS in non-strict builds.
6735	* @param pDevIns The device instance.
6736	* @param SRC_POS Use RT_SRC_POS.
6737	* @param pszFormat Message. (optional)
6738	* @param ... Message parameters.
6739	*/
6740	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
6741	{
6742	#ifdef VBOX_STRICT
6743	# ifdef IN_RING3
6744	int rc;
6745	va_list args;
6746	va_start(args, pszFormat);
6747	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
6748	va_end(args);
6749	return rc;
6750	# else
6751	NOREF(pDevIns);
6752	NOREF(pszFile);
6753	NOREF(iLine);
6754	NOREF(pszFunction);
6755	NOREF(pszFormat);
6756	return VINF_EM_DBG_STOP;
6757	# endif
6758	#else
6759	NOREF(pDevIns);
6760	NOREF(pszFile);
6761	NOREF(iLine);
6762	NOREF(pszFunction);
6763	NOREF(pszFormat);
6764	return VINF_SUCCESS;
6765	#endif
6766	}
6767
6768	#ifdef IN_RING3
6769
6770	/**
6771	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
6772	*/
6773	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
6774	{
6775	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
6776	}
6777
6778	/**
6779	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
6780	*/
6781	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
6782	{
6783	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
6784	}
6785
6786	/**
6787	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
6788	*/
6789	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
6790	{
6791	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
6792	}
6793
6794	/**
6795	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
6796	*/
6797	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
6798	{
6799	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
6800	}
6801
6802	/**
6803	* Same as pfnSTAMRegister except that the name is specified in a
6804	* RTStrPrintf like fashion.
6805	*
6806	* @returns VBox status.
6807	* @param pDevIns Device instance of the DMA.
6808	* @param pvSample Pointer to the sample.
6809	* @param enmType Sample type. This indicates what pvSample is
6810	* pointing at.
6811	* @param enmVisibility Visibility type specifying whether unused
6812	* statistics should be visible or not.
6813	* @param enmUnit Sample unit.
6814	* @param pszDesc Sample description.
6815	* @param pszName Sample name format string, unix path style. If
6816	* this does not start with a '/', the default
6817	* prefix will be prepended, otherwise it will be
6818	* used as-is.
6819	* @param ... Arguments to the format string.
6820	*/
6821	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
6822	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
6823	const char pszDesc, const char pszName, ...)
6824	{
6825	va_list va;
6826	va_start(va, pszName);
6827	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
6828	va_end(va);
6829	}
6830
6831	/**
6832	* Registers the device with the default PCI bus.
6833	*
6834	* @returns VBox status code.
6835	* @param pDevIns The device instance.
6836	* @param pPciDev The PCI device structure.
6837	* This must be kept in the instance data.
6838	* The PCI configuration must be initialized before registration.
6839	*/
6840	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
6841	{
6842	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
6843	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
6844	}
6845
6846	/**
6847	* @copydoc PDMDEVHLPR3::pfnPCIRegister
6848	*/
6849	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
6850	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
6851	{
6852	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
6853	}
6854
6855	/**
6856	* Initialize MSI emulation support for the first PCI device.
6857	*
6858	* @returns VBox status code.
6859	* @param pDevIns The device instance.
6860	* @param pMsiReg MSI emulation registration structure.
6861	*/
6862	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
6863	{
6864	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
6865	}
6866
6867	/**
6868	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
6869	*/
6870	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
6871	{
6872	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
6873	}
6874
6875	/**
6876	* Registers a I/O port region for the default PCI device.
6877	*
6878	* @returns VBox status code.
6879	* @param pDevIns The device instance.
6880	* @param iRegion The region number.
6881	* @param cbRegion Size of the region.
6882	* @param hIoPorts Handle to the I/O port region.
6883	*/
6884	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
6885	{
6886	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6887	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
6888	}
6889
6890	/**
6891	* Registers a I/O port region for the default PCI device, custom map/unmap.
6892	*
6893	* @returns VBox status code.
6894	* @param pDevIns The device instance.
6895	* @param iRegion The region number.
6896	* @param cbRegion Size of the region.
6897	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6898	* callback will be invoked holding only the PDM lock.
6899	* The device lock will _not_ be taken (due to lock
6900	* order).
6901	*/
6902	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
6903	PFNPCIIOREGIONMAP pfnMapUnmap)
6904	{
6905	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
6906	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6907	UINT64_MAX, pfnMapUnmap);
6908	}
6909
6910	/**
6911	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
6912	* and registering an I/O port region for the default PCI device.
6913	*
6914	* @returns VBox status code.
6915	* @param pDevIns The device instance to register the ports with.
6916	* @param cPorts The count of I/O ports in the region (the size).
6917	* @param iPciRegion The PCI device region.
6918	* @param pfnOut Pointer to function which is gonna handle OUT
6919	* operations. Optional.
6920	* @param pfnIn Pointer to function which is gonna handle IN operations.
6921	* Optional.
6922	* @param pvUser User argument to pass to the callbacks.
6923	* @param pszDesc Pointer to description string. This must not be freed.
6924	* @param paExtDescs Extended per-port descriptions, optional. Partial range
6925	* coverage is allowed. This must not be freed.
6926	* @param phIoPorts Where to return the I/O port range handle.
6927	*
6928	*/
6929	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
6930	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6931	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6932
6933	{
6934	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
6935	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6936	if (RT_SUCCESS(rc))
6937	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
6938	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6939	phIoPorts, NULL /pfnMapUnmap*/);
6940	return rc;
6941	}
6942
6943	/**
6944	* Registers an MMIO region for the default PCI device.
6945	*
6946	* @returns VBox status code.
6947	* @param pDevIns The device instance.
6948	* @param iRegion The region number.
6949	* @param cbRegion Size of the region.
6950	* @param enmType PCI_ADDRESS_SPACE_MEM or
6951	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6952	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6953	* @param hMmioRegion Handle to the MMIO region.
6954	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6955	* callback will be invoked holding only the PDM lock.
6956	* The device lock will _not_ be taken (due to lock
6957	* order).
6958	*/
6959	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
6960	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
6961	{
6962	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
6963	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6964	hMmioRegion, pfnMapUnmap);
6965	}
6966
6967	/**
6968	* Registers an MMIO region for the default PCI device, extended version.
6969	*
6970	* @returns VBox status code.
6971	* @param pDevIns The device instance.
6972	* @param pPciDev The PCI device structure.
6973	* @param iRegion The region number.
6974	* @param cbRegion Size of the region.
6975	* @param enmType PCI_ADDRESS_SPACE_MEM or
6976	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
6977	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
6978	* @param hMmioRegion Handle to the MMIO region.
6979	* @param pfnMapUnmap Callback for doing the mapping, optional. The
6980	* callback will be invoked holding only the PDM lock.
6981	* The device lock will _not_ be taken (due to lock
6982	* order).
6983	*/
6984	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
6985	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
6986	PFNPCIIOREGIONMAP pfnMapUnmap)
6987	{
6988	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
6989	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
6990	hMmioRegion, pfnMapUnmap);
6991	}
6992
6993	/**
6994	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
6995	* and registering an MMIO region for the default PCI device.
6996	*
6997	* @returns VBox status code.
6998	* @param pDevIns The device instance to register the ports with.
6999	* @param cbRegion The size of the region in bytes.
7000	* @param iPciRegion The PCI device region.
7001	* @param enmType PCI_ADDRESS_SPACE_MEM or
7002	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7003	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7004	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7005	* @param pfnWrite Pointer to function which is gonna handle Write
7006	* operations.
7007	* @param pfnRead Pointer to function which is gonna handle Read
7008	* operations.
7009	* @param pvUser User argument to pass to the callbacks.
7010	* @param pszDesc Pointer to description string. This must not be freed.
7011	* @param phRegion Where to return the MMIO region handle.
7012	*
7013	*/
7014	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7015	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7016	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7017
7018	{
7019	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7020	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7021	if (RT_SUCCESS(rc))
7022	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7023	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7024	phRegion, NULL /pfnMapUnmap*/);
7025	return rc;
7026	}
7027
7028
7029	/**
7030	* Registers an MMIO2 region for the default PCI device.
7031	*
7032	* @returns VBox status code.
7033	* @param pDevIns The device instance.
7034	* @param iRegion The region number.
7035	* @param cbRegion Size of the region.
7036	* @param enmType PCI_ADDRESS_SPACE_MEM or
7037	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7038	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7039	* @param hMmio2Region Handle to the MMIO2 region.
7040	*/
7041	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7042	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7043	{
7044	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7045	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7046	hMmio2Region, NULL);
7047	}
7048
7049	/**
7050	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7051	* and registering an MMIO2 region for the default PCI device, extended edition.
7052	*
7053	* @returns VBox status code.
7054	* @param pDevIns The device instance to register the ports with.
7055	* @param cbRegion The size of the region in bytes.
7056	* @param iPciRegion The PCI device region.
7057	* @param enmType PCI_ADDRESS_SPACE_MEM or
7058	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7059	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7060	* @param pszDesc Pointer to description string. This must not be freed.
7061	* @param ppvMapping Where to store the address of the ring-3 mapping of
7062	* the memory.
7063	* @param phRegion Where to return the MMIO2 region handle.
7064	*
7065	*/
7066	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7067	PCIADDRESSSPACE enmType, const char *pszDesc,
7068	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
7069
7070	{
7071	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
7072	pszDesc, ppvMapping, phRegion);
7073	if (RT_SUCCESS(rc))
7074	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7075	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7076	phRegion, NULL /pfnCallback*/);
7077	return rc;
7078	}
7079
7080	/**
7081	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
7082	* and registering an MMIO2 region for the default PCI device.
7083	*
7084	* @returns VBox status code.
7085	* @param pDevIns The device instance to register the ports with.
7086	* @param cbRegion The size of the region in bytes.
7087	* @param iPciRegion The PCI device region.
7088	* @param enmType PCI_ADDRESS_SPACE_MEM or
7089	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7090	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7091	* @param fMmio2Flags To be defined, must be zero.
7092	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7093	* callback will be invoked holding only the PDM lock.
7094	* The device lock will _not_ be taken (due to lock
7095	* order).
7096	* @param pszDesc Pointer to description string. This must not be freed.
7097	* @param ppvMapping Where to store the address of the ring-3 mapping of
7098	* the memory.
7099	* @param phRegion Where to return the MMIO2 region handle.
7100	*
7101	*/
7102	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
7103	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
7104	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
7105
7106	{
7107	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
7108	pszDesc, ppvMapping, phRegion);
7109	if (RT_SUCCESS(rc))
7110	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7111	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7112	*phRegion, pfnMapUnmap);
7113	return rc;
7114	}
7115
7116	/**
7117	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
7118	*/
7119	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
7120	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
7121	{
7122	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
7123	}
7124
7125	/**
7126	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
7127	*/
7128	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7129	unsigned cb, uint32_t *pu32Value)
7130	{
7131	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
7132	}
7133
7134	/**
7135	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
7136	*/
7137	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
7138	unsigned cb, uint32_t u32Value)
7139	{
7140	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
7141	}
7142
7143	#endif /* IN_RING3 */
7144
7145	/**
7146	* Bus master physical memory read from the default PCI device.
7147	*
7148	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7149	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7150	* @param pDevIns The device instance.
7151	* @param GCPhys Physical address start reading from.
7152	* @param pvBuf Where to put the read bits.
7153	* @param cbRead How many bytes to read.
7154	* @thread Any thread, but the call may involve the emulation thread.
7155	*/
7156	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7157	{
7158	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7159	}
7160
7161	/**
7162	* Bus master physical memory read - unknown data usage.
7163	*
7164	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7165	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7166	* @param pDevIns The device instance.
7167	* @param pPciDev The PCI device structure. If NULL the default
7168	* PCI device for this device instance is used.
7169	* @param GCPhys Physical address start reading from.
7170	* @param pvBuf Where to put the read bits.
7171	* @param cbRead How many bytes to read.
7172	* @thread Any thread, but the call may involve the emulation thread.
7173	*/
7174	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7175	{
7176	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7177	}
7178
7179	/**
7180	* Bus master physical memory read from the default PCI device.
7181	*
7182	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7183	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7184	* @param pDevIns The device instance.
7185	* @param GCPhys Physical address start reading from.
7186	* @param pvBuf Where to put the read bits.
7187	* @param cbRead How many bytes to read.
7188	* @thread Any thread, but the call may involve the emulation thread.
7189	*/
7190	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7191	{
7192	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7193	}
7194
7195	/**
7196	* Bus master physical memory read - reads meta data processed by the device.
7197	*
7198	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7199	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7200	* @param pDevIns The device instance.
7201	* @param pPciDev The PCI device structure. If NULL the default
7202	* PCI device for this device instance is used.
7203	* @param GCPhys Physical address start reading from.
7204	* @param pvBuf Where to put the read bits.
7205	* @param cbRead How many bytes to read.
7206	* @thread Any thread, but the call may involve the emulation thread.
7207	*/
7208	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7209	{
7210	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7211	}
7212
7213	/**
7214	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
7215	*
7216	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7217	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7218	* @param pDevIns The device instance.
7219	* @param GCPhys Physical address start reading from.
7220	* @param pvBuf Where to put the read bits.
7221	* @param cbRead How many bytes to read.
7222	* @thread Any thread, but the call may involve the emulation thread.
7223	*/
7224	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7225	{
7226	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7227	}
7228
7229	/**
7230	* Bus master physical memory read - read data will not be touched by the device.
7231	*
7232	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
7233	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7234	* @param pDevIns The device instance.
7235	* @param pPciDev The PCI device structure. If NULL the default
7236	* PCI device for this device instance is used.
7237	* @param GCPhys Physical address start reading from.
7238	* @param pvBuf Where to put the read bits.
7239	* @param cbRead How many bytes to read.
7240	* @thread Any thread, but the call may involve the emulation thread.
7241	*/
7242	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7243	{
7244	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7245	}
7246
7247	/**
7248	* Bus master physical memory write from the default PCI device - unknown data usage.
7249	*
7250	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7251	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7252	* @param pDevIns The device instance.
7253	* @param GCPhys Physical address to write to.
7254	* @param pvBuf What to write.
7255	* @param cbWrite How many bytes to write.
7256	* @thread Any thread, but the call may involve the emulation thread.
7257	*/
7258	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7259	{
7260	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7261	}
7262
7263	/**
7264	* Bus master physical memory write - unknown data usage.
7265	*
7266	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7267	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7268	* @param pDevIns The device instance.
7269	* @param pPciDev The PCI device structure. If NULL the default
7270	* PCI device for this device instance is used.
7271	* @param GCPhys Physical address to write to.
7272	* @param pvBuf What to write.
7273	* @param cbWrite How many bytes to write.
7274	* @thread Any thread, but the call may involve the emulation thread.
7275	*/
7276	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7277	{
7278	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7279	}
7280
7281	/**
7282	* Bus master physical memory write from the default PCI device.
7283	*
7284	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7285	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7286	* @param pDevIns The device instance.
7287	* @param GCPhys Physical address to write to.
7288	* @param pvBuf What to write.
7289	* @param cbWrite How many bytes to write.
7290	* @thread Any thread, but the call may involve the emulation thread.
7291	*/
7292	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7293	{
7294	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7295	}
7296
7297	/**
7298	* Bus master physical memory write - written data was created/altered by the device.
7299	*
7300	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7301	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7302	* @param pDevIns The device instance.
7303	* @param pPciDev The PCI device structure. If NULL the default
7304	* PCI device for this device instance is used.
7305	* @param GCPhys Physical address to write to.
7306	* @param pvBuf What to write.
7307	* @param cbWrite How many bytes to write.
7308	* @thread Any thread, but the call may involve the emulation thread.
7309	*/
7310	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7311	{
7312	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7313	}
7314
7315	/**
7316	* Bus master physical memory write from the default PCI device.
7317	*
7318	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7319	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7320	* @param pDevIns The device instance.
7321	* @param GCPhys Physical address to write to.
7322	* @param pvBuf What to write.
7323	* @param cbWrite How many bytes to write.
7324	* @thread Any thread, but the call may involve the emulation thread.
7325	*/
7326	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7327	{
7328	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7329	}
7330
7331	/**
7332	* Bus master physical memory write - written data was not touched/created by the device.
7333	*
7334	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
7335	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
7336	* @param pDevIns The device instance.
7337	* @param pPciDev The PCI device structure. If NULL the default
7338	* PCI device for this device instance is used.
7339	* @param GCPhys Physical address to write to.
7340	* @param pvBuf What to write.
7341	* @param cbWrite How many bytes to write.
7342	* @thread Any thread, but the call may involve the emulation thread.
7343	*/
7344	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7345	{
7346	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7347	}
7348
7349	#ifdef IN_RING3
7350	/**
7351	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
7352	*/
7353	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7354	void **ppv, PPGMPAGEMAPLOCK pLock)
7355	{
7356	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7357	}
7358
7359	/**
7360	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
7361	*/
7362	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
7363	void const **ppv, PPGMPAGEMAPLOCK pLock)
7364	{
7365	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
7366	}
7367
7368	/**
7369	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
7370	*/
7371	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7372	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
7373	PPGMPAGEMAPLOCK paLocks)
7374	{
7375	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
7376	paLocks);
7377	}
7378
7379	/**
7380	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
7381	*/
7382	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
7383	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
7384	PPGMPAGEMAPLOCK paLocks)
7385	{
7386	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
7387	papvPages, paLocks);
7388	}
7389	#endif /* IN_RING3 */
7390
7391	/**
7392	* Sets the IRQ for the default PCI device.
7393	*
7394	* @param pDevIns The device instance.
7395	* @param iIrq IRQ number to set.
7396	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
7397	* @thread Any thread, but will involve the emulation thread.
7398	*/
7399	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7400	{
7401	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7402	}
7403
7404	/**
7405	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
7406	*/
7407	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7408	{
7409	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7410	}
7411
7412	/**
7413	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
7414	* the request when not called from EMT.
7415	*
7416	* @param pDevIns The device instance.
7417	* @param iIrq IRQ number to set.
7418	* @param iLevel IRQ level.
7419	* @thread Any thread, but will involve the emulation thread.
7420	*/
7421	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7422	{
7423	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
7424	}
7425
7426	/**
7427	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
7428	*/
7429	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
7430	{
7431	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
7432	}
7433
7434	/**
7435	* @copydoc PDMDEVHLPR3::pfnISASetIrq
7436	*/
7437	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7438	{
7439	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7440	}
7441
7442	/**
7443	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
7444	*/
7445	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
7446	{
7447	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
7448	}
7449
7450	#ifdef IN_RING3
7451
7452	/**
7453	* @copydoc PDMDEVHLPR3::pfnDriverAttach
7454	*/
7455	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
7456	{
7457	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
7458	}
7459
7460	/**
7461	* @copydoc PDMDEVHLPR3::pfnDriverDetach
7462	*/
7463	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
7464	{
7465	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
7466	}
7467
7468	/**
7469	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
7470	*/
7471	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
7472	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
7473	{
7474	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
7475	}
7476
7477	/**
7478	* Reconfigures with a single driver reattachement, no config, noflags.
7479	* @sa PDMDevHlpDriverReconfigure
7480	*/
7481	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
7482	{
7483	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
7484	}
7485
7486	/**
7487	* Reconfigures with a two drivers reattachement, no config, noflags.
7488	* @sa PDMDevHlpDriverReconfigure
7489	*/
7490	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
7491	{
7492	char const * apszDrivers[2];
7493	apszDrivers[0] = pszDriver0;
7494	apszDrivers[1] = pszDriver1;
7495	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
7496	}
7497
7498	/**
7499	* @copydoc PDMDEVHLPR3::pfnQueueCreatePtr
7500	*/
7501	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7502	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PPDMQUEUE ppQueue)
7503	{
7504	return pDevIns->pHlpR3->pfnQueueCreatePtr(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
7505	}
7506
7507	/**
7508	* @copydoc PDMDEVHLPR3::pfnQueueCreate
7509	*/
7510	DECLINLINE(int) PDMDevHlpQueueCreateNew(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
7511	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
7512	{
7513	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
7514	}
7515
7516	#endif /* IN_RING3 */
7517
7518	/**
7519	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
7520	*/
7521	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7522	{
7523	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
7524	}
7525
7526	/**
7527	* @copydoc PDMDEVHLPR3::pfnQueueInsert
7528	*/
7529	DECLINLINE(void) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
7530	{
7531	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
7532	}
7533
7534	/**
7535	* @copydoc PDMDEVHLPR3::pfnQueueInsertEx
7536	*/
7537	DECLINLINE(void) PDMDevHlpQueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem, uint64_t cNanoMaxDelay)
7538	{
7539	pDevIns->CTX_SUFF(pHlp)->pfnQueueInsertEx(pDevIns, hQueue, pItem, cNanoMaxDelay);
7540	}
7541
7542	/**
7543	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
7544	*/
7545	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
7546	{
7547	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
7548	}
7549
7550	#ifdef IN_RING3
7551	/**
7552	* @copydoc PDMDEVHLPR3::pfnTaskCreate
7553	*/
7554	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
7555	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
7556	{
7557	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
7558	}
7559	#endif
7560
7561	/**
7562	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
7563	*/
7564	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
7565	{
7566	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
7567	}
7568
7569	#ifdef IN_RING3
7570
7571	/**
7572	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
7573	*/
7574	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
7575	{
7576	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
7577	}
7578
7579	/**
7580	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
7581	*/
7582	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7583	{
7584	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
7585	}
7586
7587	#endif /* IN_RING3 */
7588
7589	/**
7590	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
7591	*/
7592	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
7593	{
7594	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
7595	}
7596
7597	/**
7598	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
7599	*/
7600	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
7601	{
7602	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
7603	}
7604
7605	/**
7606	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
7607	*/
7608	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
7609	{
7610	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
7611	}
7612
7613	/**
7614	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
7615	*/
7616	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
7617	{
7618	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
7619	}
7620
7621	/**
7622	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
7623	*/
7624	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
7625	{
7626	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
7627	}
7628
7629	#ifdef IN_RING3
7630
7631	/**
7632	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
7633	*/
7634	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
7635	{
7636	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
7637	}
7638
7639	/**
7640	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
7641	*/
7642	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7643	{
7644	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
7645	}
7646
7647	#endif /* IN_RING3 */
7648
7649	/**
7650	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
7651	*/
7652	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7653	{
7654	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
7655	}
7656
7657	/**
7658	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
7659	*/
7660	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
7661	{
7662	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
7663	}
7664
7665	/**
7666	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
7667	*/
7668	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
7669	{
7670	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
7671	}
7672
7673	/**
7674	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
7675	*/
7676	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
7677	{
7678	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
7679	}
7680
7681	/**
7682	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
7683	*/
7684	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
7685	{
7686	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
7687	}
7688
7689	/**
7690	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
7691	*/
7692	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
7693	{
7694	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
7695	}
7696
7697	#ifdef IN_RING3
7698
7699	/**
7700	* Initializes a PDM critical section.
7701	*
7702	* The PDM critical sections are derived from the IPRT critical sections, but
7703	* works in RC and R0 as well.
7704	*
7705	* @returns VBox status code.
7706	* @param pDevIns The device instance.
7707	* @param pCritSect Pointer to the critical section.
7708	* @param SRC_POS Use RT_SRC_POS.
7709	* @param pszNameFmt Format string for naming the critical section.
7710	* For statistics and lock validation.
7711	* @param ... Arguments for the format string.
7712	*/
7713	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
7714	const char *pszNameFmt, ...)
7715	{
7716	int rc;
7717	va_list va;
7718	va_start(va, pszNameFmt);
7719	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
7720	va_end(va);
7721	return rc;
7722	}
7723
7724	#endif /* IN_RING3 */
7725
7726	/**
7727	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
7728	*/
7729	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
7730	{
7731	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
7732	}
7733
7734	#ifdef IN_RING3
7735
7736	/**
7737	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopR0
7738	*/
7739	DECLINLINE(R0PTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopR0(PPDMDEVINS pDevIns)
7740	{
7741	return pDevIns->pHlpR3->pfnCritSectGetNopR0(pDevIns);
7742	}
7743
7744	/**
7745	* @copydoc PDMDEVHLPR3::pfnCritSectGetNopRC
7746	*/
7747	DECLINLINE(RCPTRTYPE(PPDMCRITSECT)) PDMDevHlpCritSectGetNopRC(PPDMDEVINS pDevIns)
7748	{
7749	return pDevIns->pHlpR3->pfnCritSectGetNopRC(pDevIns);
7750	}
7751
7752	#endif /* IN_RING3 */
7753
7754	/**
7755	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
7756	*/
7757	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7758	{
7759	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
7760	}
7761
7762	/**
7763	* @copydoc PDMCritSectEnter
7764	* @param pDevIns The device instance.
7765	*/
7766	DECLINLINE(int) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
7767	{
7768	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
7769	}
7770
7771	/**
7772	* @copydoc PDMCritSectEnterDebug
7773	* @param pDevIns The device instance.
7774	*/
7775	DECLINLINE(int) PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7776	{
7777	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
7778	}
7779
7780	/**
7781	* @copydoc PDMCritSectTryEnter
7782	* @param pDevIns The device instance.
7783	*/
7784	DECLINLINE(int) PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7785	{
7786	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
7787	}
7788
7789	/**
7790	* @copydoc PDMCritSectTryEnterDebug
7791	* @param pDevIns The device instance.
7792	*/
7793	DECLINLINE(int) PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
7794	{
7795	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
7796	}
7797
7798	/**
7799	* @copydoc PDMCritSectLeave
7800	* @param pDevIns The device instance.
7801	*/
7802	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7803	{
7804	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
7805	}
7806
7807	/**
7808	* @copydoc PDMCritSectIsOwner
7809	* @param pDevIns The device instance.
7810	*/
7811	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7812	{
7813	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
7814	}
7815
7816	/**
7817	* @copydoc PDMCritSectIsInitialized
7818	* @param pDevIns The device instance.
7819	*/
7820	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7821	{
7822	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
7823	}
7824
7825	/**
7826	* @copydoc PDMCritSectHasWaiters
7827	* @param pDevIns The device instance.
7828	*/
7829	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7830	{
7831	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
7832	}
7833
7834	/**
7835	* @copydoc PDMCritSectGetRecursion
7836	* @param pDevIns The device instance.
7837	*/
7838	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
7839	{
7840	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
7841	}
7842
7843	#if defined(IN_RING3) \|\| defined(IN_RING0)
7844	/**
7845	* @copydoc PDMHCCritSectScheduleExitEvent
7846	* @param pDevIns The device instance.
7847	*/
7848	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
7849	{
7850	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
7851	}
7852	#endif
7853
7854	/* Strict build: Remap the two enter calls to the debug versions. */
7855	#ifdef VBOX_STRICT
7856	# ifdef IPRT_INCLUDED_asm_h
7857	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7858	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
7859	# else
7860	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
7861	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
7862	# endif
7863	#endif
7864
7865	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
7866
7867	/**
7868	* @copydoc PDMR3CritSectDelete
7869	* @param pDevIns The device instance.
7870	*/
7871	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
7872	{
7873	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
7874	}
7875
7876	/**
7877	* @copydoc PDMDEVHLPR3::pfnThreadCreate
7878	*/
7879	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
7880	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
7881	{
7882	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
7883	}
7884
7885	/**
7886	* @copydoc PDMR3ThreadDestroy
7887	* @param pDevIns The device instance.
7888	*/
7889	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
7890	{
7891	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
7892	}
7893
7894	/**
7895	* @copydoc PDMR3ThreadIAmSuspending
7896	* @param pDevIns The device instance.
7897	*/
7898	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7899	{
7900	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
7901	}
7902
7903	/**
7904	* @copydoc PDMR3ThreadIAmRunning
7905	* @param pDevIns The device instance.
7906	*/
7907	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7908	{
7909	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
7910	}
7911
7912	/**
7913	* @copydoc PDMR3ThreadSleep
7914	* @param pDevIns The device instance.
7915	*/
7916	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
7917	{
7918	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
7919	}
7920
7921	/**
7922	* @copydoc PDMR3ThreadSuspend
7923	* @param pDevIns The device instance.
7924	*/
7925	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7926	{
7927	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
7928	}
7929
7930	/**
7931	* @copydoc PDMR3ThreadResume
7932	* @param pDevIns The device instance.
7933	*/
7934	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7935	{
7936	return pDevIns->pHlpR3->pfnThreadResume(pThread);
7937	}
7938
7939	/**
7940	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
7941	*/
7942	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
7943	{
7944	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
7945	}
7946
7947	/**
7948	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
7949	*/
7950	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
7951	{
7952	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
7953	}
7954
7955	/**
7956	* @copydoc PDMDEVHLPR3::pfnA20Set
7957	*/
7958	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
7959	{
7960	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
7961	}
7962
7963	/**
7964	* @copydoc PDMDEVHLPR3::pfnRTCRegister
7965	*/
7966	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
7967	{
7968	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
7969	}
7970
7971	/**
7972	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
7973	*/
7974	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
7975	{
7976	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
7977	}
7978
7979	/**
7980	* @copydoc PDMDEVHLPR3::pfnIommuRegister
7981	*/
7982	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
7983	{
7984	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
7985	}
7986
7987	/**
7988	* @copydoc PDMDEVHLPR3::pfnPICRegister
7989	*/
7990	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
7991	{
7992	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
7993	}
7994
7995	/**
7996	* @copydoc PDMDEVHLPR3::pfnApicRegister
7997	*/
7998	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
7999	{
8000	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
8001	}
8002
8003	/**
8004	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
8005	*/
8006	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8007	{
8008	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
8009	}
8010
8011	/**
8012	* @copydoc PDMDEVHLPR3::pfnHpetRegister
8013	*/
8014	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
8015	{
8016	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
8017	}
8018
8019	/**
8020	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
8021	*/
8022	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
8023	{
8024	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
8025	}
8026
8027	/**
8028	* @copydoc PDMDEVHLPR3::pfnDMACRegister
8029	*/
8030	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
8031	{
8032	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
8033	}
8034
8035	/**
8036	* @copydoc PDMDEVHLPR3::pfnDMARegister
8037	*/
8038	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
8039	{
8040	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
8041	}
8042
8043	/**
8044	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
8045	*/
8046	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
8047	{
8048	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
8049	}
8050
8051	/**
8052	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
8053	*/
8054	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
8055	{
8056	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
8057	}
8058
8059	/**
8060	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
8061	*/
8062	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
8063	{
8064	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
8065	}
8066
8067	/**
8068	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
8069	*/
8070	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
8071	{
8072	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
8073	}
8074
8075	/**
8076	* @copydoc PDMDEVHLPR3::pfnDMASchedule
8077	*/
8078	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
8079	{
8080	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
8081	}
8082
8083	/**
8084	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
8085	*/
8086	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
8087	{
8088	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
8089	}
8090
8091	/**
8092	* @copydoc PDMDEVHLPR3::pfnCMOSRead
8093	*/
8094	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
8095	{
8096	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
8097	}
8098
8099	/**
8100	* @copydoc PDMDEVHLPR3::pfnCallR0
8101	*/
8102	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
8103	{
8104	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
8105	}
8106
8107	/**
8108	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
8109	*/
8110	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
8111	{
8112	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
8113	}
8114
8115	/**
8116	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
8117	*/
8118	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
8119	{
8120	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
8121	}
8122
8123	/**
8124	* @copydoc PDMDEVHLPR3::pfnGetUVM
8125	*/
8126	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
8127	{
8128	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
8129	}
8130
8131	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
8132
8133	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8134
8135	/**
8136	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
8137	*/
8138	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
8139	{
8140	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
8141	}
8142
8143	/**
8144	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
8145	*/
8146	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
8147	{
8148	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
8149	}
8150
8151	/**
8152	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
8153	*/
8154	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
8155	{
8156	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
8157	}
8158
8159	/**
8160	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
8161	*/
8162	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
8163	{
8164	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
8165	}
8166
8167	/**
8168	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
8169	*/
8170	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
8171	{
8172	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
8173	}
8174
8175	/**
8176	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
8177	*/
8178	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
8179	{
8180	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
8181	}
8182
8183	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
8184
8185	/**
8186	* @copydoc PDMDEVHLPR3::pfnGetVM
8187	*/
8188	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
8189	{
8190	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
8191	}
8192
8193	/**
8194	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
8195	*/
8196	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
8197	{
8198	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
8199	}
8200
8201	/**
8202	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
8203	*/
8204	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
8205	{
8206	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
8207	}
8208
8209	/**
8210	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
8211	*/
8212	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
8213	{
8214	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
8215	}
8216
8217	/**
8218	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8219	*/
8220	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
8221	{
8222	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
8223	}
8224
8225	/**
8226	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
8227	*/
8228	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
8229	{
8230	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
8231	}
8232
8233	#ifdef IN_RING3
8234
8235	/**
8236	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
8237	*/
8238	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
8239	{
8240	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
8241	}
8242
8243	/**
8244	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
8245	*/
8246	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
8247	{
8248	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
8249	}
8250
8251	/**
8252	* @copydoc PDMDEVHLPR3::pfnVMReset
8253	*/
8254	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
8255	{
8256	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
8257	}
8258
8259	/**
8260	* @copydoc PDMDEVHLPR3::pfnVMSuspend
8261	*/
8262	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
8263	{
8264	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
8265	}
8266
8267	/**
8268	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
8269	*/
8270	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
8271	{
8272	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
8273	}
8274
8275	/**
8276	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
8277	*/
8278	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
8279	{
8280	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
8281	}
8282
8283	#endif /* IN_RING3 */
8284
8285	/**
8286	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
8287	*/
8288	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
8289	{
8290	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
8291	}
8292
8293	#ifdef IN_RING3
8294
8295	/**
8296	* @copydoc PDMDEVHLPR3::pfnGetCpuId
8297	*/
8298	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
8299	{
8300	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
8301	}
8302
8303	/**
8304	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
8305	*/
8306	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
8307	{
8308	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
8309	}
8310
8311	/**
8312	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
8313	*/
8314	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
8315	{
8316	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
8317	}
8318
8319	/**
8320	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
8321	*/
8322	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
8323	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
8324	const char pszHandlerR0, const char pszPfHandlerR0,
8325	const char pszHandlerRC, const char pszPfHandlerRC,
8326	const char *pszDesc, PPGMPHYSHANDLERTYPE phType)
8327	{
8328	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandlerR3,
8329	pszHandlerR0, pszPfHandlerR0,
8330	pszHandlerRC, pszPfHandlerRC,
8331	pszDesc, phType);
8332	}
8333
8334	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
8335	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8336	do { \
8337	uint32_t u32GetEnumTmp = 0; \
8338	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
8339	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8340	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
8341	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
8342	} while (0)
8343
8344	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
8345	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
8346	do { \
8347	uint8_t bGetEnumTmp = 0; \
8348	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
8349	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
8350	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
8351	} while (0)
8352
8353	#endif /* IN_RING3 */
8354
8355	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
8356	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
8357
8358	/**
8359	* Callbacks for VBoxDeviceRegister().
8360	*/
8361	typedef struct PDMDEVREGCB
8362	{
8363	/** Interface version.
8364	* This is set to PDM_DEVREG_CB_VERSION. */
8365	uint32_t u32Version;
8366
8367	/**
8368	* Registers a device with the current VM instance.
8369	*
8370	* @returns VBox status code.
8371	* @param pCallbacks Pointer to the callback table.
8372	* @param pReg Pointer to the device registration record.
8373	* This data must be permanent and readonly.
8374	*/
8375	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
8376	} PDMDEVREGCB;
8377
8378	/** Current version of the PDMDEVREGCB structure. */
8379	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
8380
8381
8382	/**
8383	* The VBoxDevicesRegister callback function.
8384	*
8385	* PDM will invoke this function after loading a device module and letting
8386	* the module decide which devices to register and how to handle conflicts.
8387	*
8388	* @returns VBox status code.
8389	* @param pCallbacks Pointer to the callback table.
8390	* @param u32Version VBox version number.
8391	*/
8392	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
8393
8394	/** @} */
8395
8396	RT_C_DECLS_END
8397
8398	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 87261

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