| 1 | /** @file
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| 2 | * IEM - Interpreted Execution Manager.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2011-2023 Oracle and/or its affiliates.
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| 7 | *
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| 8 | * This file is part of VirtualBox base platform packages, as
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| 9 | * available from https://www.virtualbox.org.
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| 10 | *
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| 11 | * This program is free software; you can redistribute it and/or
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| 12 | * modify it under the terms of the GNU General Public License
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| 13 | * as published by the Free Software Foundation, in version 3 of the
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| 14 | * License.
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| 15 | *
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| 16 | * This program is distributed in the hope that it will be useful, but
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| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 19 | * General Public License for more details.
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| 20 | *
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| 21 | * You should have received a copy of the GNU General Public License
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| 22 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 23 | *
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| 24 | * The contents of this file may alternatively be used under the terms
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| 25 | * of the Common Development and Distribution License Version 1.0
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| 26 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 27 | * in the VirtualBox distribution, in which case the provisions of the
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| 28 | * CDDL are applicable instead of those of the GPL.
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| 29 | *
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| 30 | * You may elect to license modified versions of this file under the
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| 31 | * terms and conditions of either the GPL or the CDDL or both.
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| 32 | *
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| 33 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 34 | */
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| 35 |
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| 36 | #ifndef VBOX_INCLUDED_vmm_iem_armv8_h
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| 37 | #define VBOX_INCLUDED_vmm_iem_armv8_h
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| 38 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 39 | # pragma once
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| 40 | #endif
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| 41 |
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| 42 | RT_C_DECLS_BEGIN
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| 43 |
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| 44 | /** @addtogroup grp_iem
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| 45 | * @{ */
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| 46 |
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| 47 | /** @name Instruction mode.
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| 48 | * @{ */
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| 49 | typedef uint8_t IEMMODE;
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| 50 | /** AARCH64 instruction mode. */
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| 51 | #define IEMMODE_AARCH64 0
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| 52 | /** AARCH32 A32 instruction mode. */
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| 53 | #define IEMMODE_AARCH32_A32 1
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| 54 | /** AARCH32 T32 (aka Thumb) instruction mode. */
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| 55 | #define IEMMODE_AARCH32_T32 1
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| 56 | /** @} */
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| 57 |
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| 58 |
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| 59 | /** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.
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| 60 | * IEM will ASSUME the caller of IEM APIs has ensured these are already present. */
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| 61 | #define IEM_CPUMCTX_EXTRN_MUST_MASK ( CPUMCTX_EXTRN_GPRS_MASK \
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| 62 | | CPUMCTX_EXTRN_PC \
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| 63 | | CPUMCTX_EXTRN_SPSR \
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| 64 | | CPUMCTX_EXTRN_ELR \
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| 65 | | CPUMCTX_EXTRN_SP \
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| 66 | | CPUMCTX_EXTRN_PSTATE )
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| 67 | /** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.
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| 68 | * IEM will import missing bits, callers are encouraged to make these registers
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| 69 | * available prior to injection calls if fetching state anyway. */
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| 70 | #define IEM_CPUMCTX_EXTRN_XCPT_MASK ( IEM_CPUMCTX_EXTRN_MUST_MASK ) /** @todo */
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| 71 | /** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
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| 72 | * IEMExecDecoded API not using memory. IEM will ASSUME the caller of IEM
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| 73 | * APIs has ensured these are already present.
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| 74 | * @note ASSUMES execution engine has checked for instruction breakpoints
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| 75 | * during decoding. */
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| 76 | #define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ( CPUMCTX_EXTRN_PC \
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| 77 | | CPUMCTX_EXTRN_PSTATE )
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| 78 | /** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
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| 79 | * IEMExecDecoded API using memory. IEM will ASSUME the caller of IEM
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| 80 | * APIs has ensured these are already present.
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| 81 | * @note ASSUMES execution engine has checked for instruction breakpoints
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| 82 | * during decoding. */
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| 83 | #define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ) /** @todo */
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| 84 |
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| 85 | /** @} */
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| 86 |
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| 87 | RT_C_DECLS_END
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| 88 |
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| 89 | #endif /* !VBOX_INCLUDED_vmm_iem_armv8_h */
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| 90 |
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