hm_vmx.h@ 74429

Last change on this file since 74429 was 74429, checked in by vboxsync, 6 years ago
VMM/IEM: Nested VMX: bugref:9180 VM-exit bits.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# pragma warning(push)
38	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
39	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
40	# include <intrin.h>
41	# pragma warning(pop)
42	/* We always want them as intrinsics, no functions. */
43	# pragma intrinsic(__vmx_on)
44	# pragma intrinsic(__vmx_off)
45	# pragma intrinsic(__vmx_vmclear)
46	# pragma intrinsic(__vmx_vmptrld)
47	# pragma intrinsic(__vmx_vmread)
48	# pragma intrinsic(__vmx_vmwrite)
49	# define VMX_USE_MSC_INTRINSICS 1
50	#else
51	# define VMX_USE_MSC_INTRINSICS 0
52	#endif
53
54
55	/** @defgroup grp_hm_vmx VMX Types and Definitions
56	* @ingroup grp_hm
57	* @{
58	*/
59
60	/** @name Host-state restoration flags.
61	* @note If you change these values don't forget to update the assembly
62	* defines as well!
63	* @{
64	*/
65	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
66	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
67	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
68	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
69	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
70	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
71	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
72	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
73	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
74	#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(9)
75	/** @} */
76
77	/**
78	* Host-state restoration structure.
79	* This holds host-state fields that require manual restoration.
80	* Assembly version found in hm_vmx.mac (should be automatically verified).
81	*/
82	typedef struct VMXRESTOREHOST
83	{
84	RTSEL uHostSelDS; /* 0x00 */
85	RTSEL uHostSelES; /* 0x02 */
86	RTSEL uHostSelFS; /* 0x04 */
87	RTSEL uHostSelGS; /* 0x06 */
88	RTSEL uHostSelTR; /* 0x08 */
89	uint8_t abPadding0[4];
90	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
91	uint8_t abPadding1[6];
92	X86XDTR64 HostGdtrRw; /*< 0x1e - should be aligned by it's 64-bit member. /
93	uint8_t abPadding2[6];
94	X86XDTR64 HostIdtr; /*< 0x2e - should be aligned by it's 64-bit member. /
95	uint64_t uHostFSBase; /* 0x38 */
96	uint64_t uHostGSBase; /* 0x40 */
97	} VMXRESTOREHOST;
98	/** Pointer to VMXRESTOREHOST. */
99	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
100	AssertCompileSize(X86XDTR64, 10);
101	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
102	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
103	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 48);
104	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 56);
105	AssertCompileSize(VMXRESTOREHOST, 72);
106	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
107
108	/** @name Host-state MSR lazy-restoration flags.
109	* @{
110	*/
111	/** The host MSRs have been saved. */
112	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
113	/** The guest MSRs are loaded and in effect. */
114	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
115	/** @} */
116
117	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
118	* UFC = Unsupported Feature Combination.
119	* @{
120	*/
121	/** Unsupported pin-based VM-execution controls combo. */
122	#define VMX_UFC_CTRL_PIN_EXEC 1
123	/** Unsupported processor-based VM-execution controls combo. */
124	#define VMX_UFC_CTRL_PROC_EXEC 2
125	/** Unsupported move debug register VM-exit combo. */
126	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
127	/** Unsupported VM-entry controls combo. */
128	#define VMX_UFC_CTRL_ENTRY 4
129	/** Unsupported VM-exit controls combo. */
130	#define VMX_UFC_CTRL_EXIT 5
131	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
132	* for storing host MSRs. */
133	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
134	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
135	* for storing guest MSRs. */
136	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
137	/** Invalid VMCS size. */
138	#define VMX_UFC_INVALID_VMCS_SIZE 8
139	/** Unsupported secondary processor-based VM-execution controls combo. */
140	#define VMX_UFC_CTRL_PROC_EXEC2 9
141	/** Invalid unrestricted-guest execution controls combo. */
142	#define VMX_UFC_INVALID_UX_COMBO 10
143	/** EPT flush type not supported. */
144	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
145	/** EPT paging structure memory type is not write-back. */
146	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
147	/** EPT requires INVEPT instr. support but it's not available. */
148	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
149	/** EPT requires page-walk length of 4. */
150	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
151	/** @} */
152
153	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
154	* VCI = VMCS-field Cache Invalid.
155	* @{
156	*/
157	/** Cache of VM-entry controls invalid. */
158	#define VMX_VCI_CTRL_ENTRY 300
159	/** Cache of VM-exit controls invalid. */
160	#define VMX_VCI_CTRL_EXIT 301
161	/** Cache of pin-based VM-execution controls invalid. */
162	#define VMX_VCI_CTRL_PIN_EXEC 302
163	/** Cache of processor-based VM-execution controls invalid. */
164	#define VMX_VCI_CTRL_PROC_EXEC 303
165	/** Cache of secondary processor-based VM-execution controls invalid. */
166	#define VMX_VCI_CTRL_PROC_EXEC2 304
167	/** Cache of exception bitmap invalid. */
168	#define VMX_VCI_CTRL_XCPT_BITMAP 305
169	/** Cache of TSC offset invalid. */
170	#define VMX_VCI_CTRL_TSC_OFFSET 306
171	/** @} */
172
173	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
174	* IGS = Invalid Guest State.
175	* @{
176	*/
177	/** An error occurred while checking invalid-guest-state. */
178	#define VMX_IGS_ERROR 500
179	/** The invalid guest-state checks did not find any reason why. */
180	#define VMX_IGS_REASON_NOT_FOUND 501
181	/** CR0 fixed1 bits invalid. */
182	#define VMX_IGS_CR0_FIXED1 502
183	/** CR0 fixed0 bits invalid. */
184	#define VMX_IGS_CR0_FIXED0 503
185	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
186	#define VMX_IGS_CR0_PG_PE_COMBO 504
187	/** CR4 fixed1 bits invalid. */
188	#define VMX_IGS_CR4_FIXED1 505
189	/** CR4 fixed0 bits invalid. */
190	#define VMX_IGS_CR4_FIXED0 506
191	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
192	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
193	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
194	/** CR0.PG not set for long-mode when not using unrestricted guest. */
195	#define VMX_IGS_CR0_PG_LONGMODE 508
196	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
197	#define VMX_IGS_CR4_PAE_LONGMODE 509
198	/** CR4.PCIDE set for 32-bit guest. */
199	#define VMX_IGS_CR4_PCIDE 510
200	/** VMCS' DR7 reserved bits not set to 0. */
201	#define VMX_IGS_DR7_RESERVED 511
202	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
203	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
204	/** VMCS' EFER MSR reserved bits not set to 0. */
205	#define VMX_IGS_EFER_MSR_RESERVED 513
206	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
207	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
208	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
209	* without unrestricted guest. */
210	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
211	/** CS.Attr.P bit invalid. */
212	#define VMX_IGS_CS_ATTR_P_INVALID 516
213	/** CS.Attr reserved bits not set to 0. */
214	#define VMX_IGS_CS_ATTR_RESERVED 517
215	/** CS.Attr.G bit invalid. */
216	#define VMX_IGS_CS_ATTR_G_INVALID 518
217	/** CS is unusable. */
218	#define VMX_IGS_CS_ATTR_UNUSABLE 519
219	/** CS and SS DPL unequal. */
220	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
221	/** CS and SS DPL mismatch. */
222	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
223	/** CS Attr.Type invalid. */
224	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
225	/** CS and SS RPL unequal. */
226	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
227	/** SS.Attr.DPL and SS RPL unequal. */
228	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
229	/** SS.Attr.DPL invalid for segment type. */
230	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
231	/** SS.Attr.Type invalid. */
232	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
233	/** SS.Attr.P bit invalid. */
234	#define VMX_IGS_SS_ATTR_P_INVALID 527
235	/** SS.Attr reserved bits not set to 0. */
236	#define VMX_IGS_SS_ATTR_RESERVED 528
237	/** SS.Attr.G bit invalid. */
238	#define VMX_IGS_SS_ATTR_G_INVALID 529
239	/** DS.Attr.A bit invalid. */
240	#define VMX_IGS_DS_ATTR_A_INVALID 530
241	/** DS.Attr.P bit invalid. */
242	#define VMX_IGS_DS_ATTR_P_INVALID 531
243	/** DS.Attr.DPL and DS RPL unequal. */
244	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
245	/** DS.Attr reserved bits not set to 0. */
246	#define VMX_IGS_DS_ATTR_RESERVED 533
247	/** DS.Attr.G bit invalid. */
248	#define VMX_IGS_DS_ATTR_G_INVALID 534
249	/** DS.Attr.Type invalid. */
250	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
251	/** ES.Attr.A bit invalid. */
252	#define VMX_IGS_ES_ATTR_A_INVALID 536
253	/** ES.Attr.P bit invalid. */
254	#define VMX_IGS_ES_ATTR_P_INVALID 537
255	/** ES.Attr.DPL and DS RPL unequal. */
256	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
257	/** ES.Attr reserved bits not set to 0. */
258	#define VMX_IGS_ES_ATTR_RESERVED 539
259	/** ES.Attr.G bit invalid. */
260	#define VMX_IGS_ES_ATTR_G_INVALID 540
261	/** ES.Attr.Type invalid. */
262	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
263	/** FS.Attr.A bit invalid. */
264	#define VMX_IGS_FS_ATTR_A_INVALID 542
265	/** FS.Attr.P bit invalid. */
266	#define VMX_IGS_FS_ATTR_P_INVALID 543
267	/** FS.Attr.DPL and DS RPL unequal. */
268	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
269	/** FS.Attr reserved bits not set to 0. */
270	#define VMX_IGS_FS_ATTR_RESERVED 545
271	/** FS.Attr.G bit invalid. */
272	#define VMX_IGS_FS_ATTR_G_INVALID 546
273	/** FS.Attr.Type invalid. */
274	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
275	/** GS.Attr.A bit invalid. */
276	#define VMX_IGS_GS_ATTR_A_INVALID 548
277	/** GS.Attr.P bit invalid. */
278	#define VMX_IGS_GS_ATTR_P_INVALID 549
279	/** GS.Attr.DPL and DS RPL unequal. */
280	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
281	/** GS.Attr reserved bits not set to 0. */
282	#define VMX_IGS_GS_ATTR_RESERVED 551
283	/** GS.Attr.G bit invalid. */
284	#define VMX_IGS_GS_ATTR_G_INVALID 552
285	/** GS.Attr.Type invalid. */
286	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
287	/** V86 mode CS.Base invalid. */
288	#define VMX_IGS_V86_CS_BASE_INVALID 554
289	/** V86 mode CS.Limit invalid. */
290	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
291	/** V86 mode CS.Attr invalid. */
292	#define VMX_IGS_V86_CS_ATTR_INVALID 556
293	/** V86 mode SS.Base invalid. */
294	#define VMX_IGS_V86_SS_BASE_INVALID 557
295	/** V86 mode SS.Limit invalid. */
296	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
297	/** V86 mode SS.Attr invalid. */
298	#define VMX_IGS_V86_SS_ATTR_INVALID 559
299	/** V86 mode DS.Base invalid. */
300	#define VMX_IGS_V86_DS_BASE_INVALID 560
301	/** V86 mode DS.Limit invalid. */
302	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
303	/** V86 mode DS.Attr invalid. */
304	#define VMX_IGS_V86_DS_ATTR_INVALID 562
305	/** V86 mode ES.Base invalid. */
306	#define VMX_IGS_V86_ES_BASE_INVALID 563
307	/** V86 mode ES.Limit invalid. */
308	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
309	/** V86 mode ES.Attr invalid. */
310	#define VMX_IGS_V86_ES_ATTR_INVALID 565
311	/** V86 mode FS.Base invalid. */
312	#define VMX_IGS_V86_FS_BASE_INVALID 566
313	/** V86 mode FS.Limit invalid. */
314	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
315	/** V86 mode FS.Attr invalid. */
316	#define VMX_IGS_V86_FS_ATTR_INVALID 568
317	/** V86 mode GS.Base invalid. */
318	#define VMX_IGS_V86_GS_BASE_INVALID 569
319	/** V86 mode GS.Limit invalid. */
320	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
321	/** V86 mode GS.Attr invalid. */
322	#define VMX_IGS_V86_GS_ATTR_INVALID 571
323	/** Longmode CS.Base invalid. */
324	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
325	/** Longmode SS.Base invalid. */
326	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
327	/** Longmode DS.Base invalid. */
328	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
329	/** Longmode ES.Base invalid. */
330	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
331	/** SYSENTER ESP is not canonical. */
332	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
333	/** SYSENTER EIP is not canonical. */
334	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
335	/** PAT MSR invalid. */
336	#define VMX_IGS_PAT_MSR_INVALID 578
337	/** PAT MSR reserved bits not set to 0. */
338	#define VMX_IGS_PAT_MSR_RESERVED 579
339	/** GDTR.Base is not canonical. */
340	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
341	/** IDTR.Base is not canonical. */
342	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
343	/** GDTR.Limit invalid. */
344	#define VMX_IGS_GDTR_LIMIT_INVALID 582
345	/** IDTR.Limit invalid. */
346	#define VMX_IGS_IDTR_LIMIT_INVALID 583
347	/** Longmode RIP is invalid. */
348	#define VMX_IGS_LONGMODE_RIP_INVALID 584
349	/** RFLAGS reserved bits not set to 0. */
350	#define VMX_IGS_RFLAGS_RESERVED 585
351	/** RFLAGS RA1 reserved bits not set to 1. */
352	#define VMX_IGS_RFLAGS_RESERVED1 586
353	/** RFLAGS.VM (V86 mode) invalid. */
354	#define VMX_IGS_RFLAGS_VM_INVALID 587
355	/** RFLAGS.IF invalid. */
356	#define VMX_IGS_RFLAGS_IF_INVALID 588
357	/** Activity state invalid. */
358	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
359	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
360	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
361	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
362	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
363	/** Activity state SIPI WAIT invalid. */
364	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
365	/** Interruptibility state reserved bits not set to 0. */
366	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
367	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
368	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
369	/** Interruptibility state block-by-STI invalid for EFLAGS. */
370	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
371	/** Interruptibility state invalid while trying to deliver external
372	* interrupt. */
373	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
374	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
375	* NMI. */
376	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
377	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
378	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
379	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
380	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
381	/** Interruptibility state block-by-STI (maybe) invalid when trying to
382	* deliver an NMI. */
383	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
384	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
385	* active. */
386	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
387	/** Pending debug exceptions reserved bits not set to 0. */
388	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
389	/** Longmode pending debug exceptions reserved bits not set to 0. */
390	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
391	/** Pending debug exceptions.BS bit is not set when it should be. */
392	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
393	/** Pending debug exceptions.BS bit is not clear when it should be. */
394	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
395	/** VMCS link pointer reserved bits not set to 0. */
396	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
397	/** TR cannot index into LDT, TI bit MBZ. */
398	#define VMX_IGS_TR_TI_INVALID 607
399	/** LDTR cannot index into LDT. TI bit MBZ. */
400	#define VMX_IGS_LDTR_TI_INVALID 608
401	/** TR.Base is not canonical. */
402	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
403	/** FS.Base is not canonical. */
404	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
405	/** GS.Base is not canonical. */
406	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
407	/** LDTR.Base is not canonical. */
408	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
409	/** TR is unusable. */
410	#define VMX_IGS_TR_ATTR_UNUSABLE 613
411	/** TR.Attr.S bit invalid. */
412	#define VMX_IGS_TR_ATTR_S_INVALID 614
413	/** TR is not present. */
414	#define VMX_IGS_TR_ATTR_P_INVALID 615
415	/** TR.Attr reserved bits not set to 0. */
416	#define VMX_IGS_TR_ATTR_RESERVED 616
417	/** TR.Attr.G bit invalid. */
418	#define VMX_IGS_TR_ATTR_G_INVALID 617
419	/** Longmode TR.Attr.Type invalid. */
420	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
421	/** TR.Attr.Type invalid. */
422	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
423	/** CS.Attr.S invalid. */
424	#define VMX_IGS_CS_ATTR_S_INVALID 620
425	/** CS.Attr.DPL invalid. */
426	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
427	/** PAE PDPTE reserved bits not set to 0. */
428	#define VMX_IGS_PAE_PDPTE_RESERVED 623
429	/** @} */
430
431	/** @name VMX VMCS-Read cache indices.
432	* @{
433	*/
434	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
435	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
436	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
437	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
438	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
439	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
440	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
441	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
442	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
443	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
444	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
445	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
446	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
447	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
448	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
449	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
450	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
451	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
452	/** @} */
453
454	/** @name VMX EPT paging structures
455	* @{
456	*/
457
458	/**
459	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
460	*/
461	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
462
463	/**
464	* EPT Page Directory Pointer Entry. Bit view.
465	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
466	* this did cause trouble with one compiler/version).
467	*/
468	typedef struct EPTPML4EBITS
469	{
470	/** Present bit. */
471	uint64_t u1Present : 1;
472	/** Writable bit. */
473	uint64_t u1Write : 1;
474	/** Executable bit. */
475	uint64_t u1Execute : 1;
476	/** Reserved (must be 0). */
477	uint64_t u5Reserved : 5;
478	/** Available for software. */
479	uint64_t u4Available : 4;
480	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
481	uint64_t u40PhysAddr : 40;
482	/** Available for software. */
483	uint64_t u12Available : 12;
484	} EPTPML4EBITS;
485	AssertCompileSize(EPTPML4EBITS, 8);
486
487	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
488	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
489	/** The page shift to get the PML4 index. */
490	#define EPT_PML4_SHIFT X86_PML4_SHIFT
491	/** The PML4 index mask (apply to a shifted page address). */
492	#define EPT_PML4_MASK X86_PML4_MASK
493
494	/**
495	* EPT PML4E.
496	*/
497	typedef union EPTPML4E
498	{
499	/** Normal view. */
500	EPTPML4EBITS n;
501	/** Unsigned integer view. */
502	X86PGPAEUINT u;
503	/** 64 bit unsigned integer view. */
504	uint64_t au64[1];
505	/** 32 bit unsigned integer view. */
506	uint32_t au32[2];
507	} EPTPML4E;
508	AssertCompileSize(EPTPML4E, 8);
509	/** Pointer to a PML4 table entry. */
510	typedef EPTPML4E *PEPTPML4E;
511	/** Pointer to a const PML4 table entry. */
512	typedef const EPTPML4E *PCEPTPML4E;
513
514	/**
515	* EPT PML4 Table.
516	*/
517	typedef struct EPTPML4
518	{
519	EPTPML4E a[EPT_PG_ENTRIES];
520	} EPTPML4;
521	AssertCompileSize(EPTPML4, 0x1000);
522	/** Pointer to an EPT PML4 Table. */
523	typedef EPTPML4 *PEPTPML4;
524	/** Pointer to a const EPT PML4 Table. */
525	typedef const EPTPML4 *PCEPTPML4;
526
527	/**
528	* EPT Page Directory Pointer Entry. Bit view.
529	*/
530	typedef struct EPTPDPTEBITS
531	{
532	/** Present bit. */
533	uint64_t u1Present : 1;
534	/** Writable bit. */
535	uint64_t u1Write : 1;
536	/** Executable bit. */
537	uint64_t u1Execute : 1;
538	/** Reserved (must be 0). */
539	uint64_t u5Reserved : 5;
540	/** Available for software. */
541	uint64_t u4Available : 4;
542	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
543	uint64_t u40PhysAddr : 40;
544	/** Available for software. */
545	uint64_t u12Available : 12;
546	} EPTPDPTEBITS;
547	AssertCompileSize(EPTPDPTEBITS, 8);
548
549	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
550	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
551	/** The page shift to get the PDPT index. */
552	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
553	/** The PDPT index mask (apply to a shifted page address). */
554	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
555
556	/**
557	* EPT Page Directory Pointer.
558	*/
559	typedef union EPTPDPTE
560	{
561	/** Normal view. */
562	EPTPDPTEBITS n;
563	/** Unsigned integer view. */
564	X86PGPAEUINT u;
565	/** 64 bit unsigned integer view. */
566	uint64_t au64[1];
567	/** 32 bit unsigned integer view. */
568	uint32_t au32[2];
569	} EPTPDPTE;
570	AssertCompileSize(EPTPDPTE, 8);
571	/** Pointer to an EPT Page Directory Pointer Entry. */
572	typedef EPTPDPTE *PEPTPDPTE;
573	/** Pointer to a const EPT Page Directory Pointer Entry. */
574	typedef const EPTPDPTE *PCEPTPDPTE;
575
576	/**
577	* EPT Page Directory Pointer Table.
578	*/
579	typedef struct EPTPDPT
580	{
581	EPTPDPTE a[EPT_PG_ENTRIES];
582	} EPTPDPT;
583	AssertCompileSize(EPTPDPT, 0x1000);
584	/** Pointer to an EPT Page Directory Pointer Table. */
585	typedef EPTPDPT *PEPTPDPT;
586	/** Pointer to a const EPT Page Directory Pointer Table. */
587	typedef const EPTPDPT *PCEPTPDPT;
588
589	/**
590	* EPT Page Directory Table Entry. Bit view.
591	*/
592	typedef struct EPTPDEBITS
593	{
594	/** Present bit. */
595	uint64_t u1Present : 1;
596	/** Writable bit. */
597	uint64_t u1Write : 1;
598	/** Executable bit. */
599	uint64_t u1Execute : 1;
600	/** Reserved (must be 0). */
601	uint64_t u4Reserved : 4;
602	/** Big page (must be 0 here). */
603	uint64_t u1Size : 1;
604	/** Available for software. */
605	uint64_t u4Available : 4;
606	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
607	uint64_t u40PhysAddr : 40;
608	/** Available for software. */
609	uint64_t u12Available : 12;
610	} EPTPDEBITS;
611	AssertCompileSize(EPTPDEBITS, 8);
612
613	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
614	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
615	/** The page shift to get the PD index. */
616	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
617	/** The PD index mask (apply to a shifted page address). */
618	#define EPT_PD_MASK X86_PD_PAE_MASK
619
620	/**
621	* EPT 2MB Page Directory Table Entry. Bit view.
622	*/
623	typedef struct EPTPDE2MBITS
624	{
625	/** Present bit. */
626	uint64_t u1Present : 1;
627	/** Writable bit. */
628	uint64_t u1Write : 1;
629	/** Executable bit. */
630	uint64_t u1Execute : 1;
631	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
632	uint64_t u3EMT : 3;
633	/** Ignore PAT memory type */
634	uint64_t u1IgnorePAT : 1;
635	/** Big page (must be 1 here). */
636	uint64_t u1Size : 1;
637	/** Available for software. */
638	uint64_t u4Available : 4;
639	/** Reserved (must be 0). */
640	uint64_t u9Reserved : 9;
641	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
642	uint64_t u31PhysAddr : 31;
643	/** Available for software. */
644	uint64_t u12Available : 12;
645	} EPTPDE2MBITS;
646	AssertCompileSize(EPTPDE2MBITS, 8);
647
648	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
649	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
650
651	/**
652	* EPT Page Directory Table Entry.
653	*/
654	typedef union EPTPDE
655	{
656	/** Normal view. */
657	EPTPDEBITS n;
658	/** 2MB view (big). */
659	EPTPDE2MBITS b;
660	/** Unsigned integer view. */
661	X86PGPAEUINT u;
662	/** 64 bit unsigned integer view. */
663	uint64_t au64[1];
664	/** 32 bit unsigned integer view. */
665	uint32_t au32[2];
666	} EPTPDE;
667	AssertCompileSize(EPTPDE, 8);
668	/** Pointer to an EPT Page Directory Table Entry. */
669	typedef EPTPDE *PEPTPDE;
670	/** Pointer to a const EPT Page Directory Table Entry. */
671	typedef const EPTPDE *PCEPTPDE;
672
673	/**
674	* EPT Page Directory Table.
675	*/
676	typedef struct EPTPD
677	{
678	EPTPDE a[EPT_PG_ENTRIES];
679	} EPTPD;
680	AssertCompileSize(EPTPD, 0x1000);
681	/** Pointer to an EPT Page Directory Table. */
682	typedef EPTPD *PEPTPD;
683	/** Pointer to a const EPT Page Directory Table. */
684	typedef const EPTPD *PCEPTPD;
685
686	/**
687	* EPT Page Table Entry. Bit view.
688	*/
689	typedef struct EPTPTEBITS
690	{
691	/** 0 - Present bit.
692	* @remarks This is a convenience "misnomer". The bit actually indicates read access
693	* and the CPU will consider an entry with any of the first three bits set
694	* as present. Since all our valid entries will have this bit set, it can
695	* be used as a present indicator and allow some code sharing. */
696	uint64_t u1Present : 1;
697	/** 1 - Writable bit. */
698	uint64_t u1Write : 1;
699	/** 2 - Executable bit. */
700	uint64_t u1Execute : 1;
701	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
702	uint64_t u3EMT : 3;
703	/** 6 - Ignore PAT memory type */
704	uint64_t u1IgnorePAT : 1;
705	/** 11:7 - Available for software. */
706	uint64_t u5Available : 5;
707	/** 51:12 - Physical address of page. Restricted by maximum physical
708	* address width of the cpu. */
709	uint64_t u40PhysAddr : 40;
710	/** 63:52 - Available for software. */
711	uint64_t u12Available : 12;
712	} EPTPTEBITS;
713	AssertCompileSize(EPTPTEBITS, 8);
714
715	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
716	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
717	/** The page shift to get the EPT PTE index. */
718	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
719	/** The EPT PT index mask (apply to a shifted page address). */
720	#define EPT_PT_MASK X86_PT_PAE_MASK
721
722	/**
723	* EPT Page Table Entry.
724	*/
725	typedef union EPTPTE
726	{
727	/** Normal view. */
728	EPTPTEBITS n;
729	/** Unsigned integer view. */
730	X86PGPAEUINT u;
731	/** 64 bit unsigned integer view. */
732	uint64_t au64[1];
733	/** 32 bit unsigned integer view. */
734	uint32_t au32[2];
735	} EPTPTE;
736	AssertCompileSize(EPTPTE, 8);
737	/** Pointer to an EPT Page Directory Table Entry. */
738	typedef EPTPTE *PEPTPTE;
739	/** Pointer to a const EPT Page Directory Table Entry. */
740	typedef const EPTPTE *PCEPTPTE;
741
742	/**
743	* EPT Page Table.
744	*/
745	typedef struct EPTPT
746	{
747	EPTPTE a[EPT_PG_ENTRIES];
748	} EPTPT;
749	AssertCompileSize(EPTPT, 0x1000);
750	/** Pointer to an extended page table. */
751	typedef EPTPT *PEPTPT;
752	/** Pointer to a const extended table. */
753	typedef const EPTPT *PCEPTPT;
754
755	/** @} */
756
757	/**
758	* VMX VPID flush types.
759	* @note Valid enum members are in accordance to the VT-x spec.
760	*/
761	typedef enum
762	{
763	/** Invalidate a specific page. */
764	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
765	/** Invalidate one context (specific VPID). */
766	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
767	/** Invalidate all contexts (all VPIDs). */
768	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
769	/** Invalidate a single VPID context retaining global mappings. */
770	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
771	/** Unsupported by VirtualBox. */
772	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
773	/** Unsupported by CPU. */
774	VMXTLBFLUSHVPID_NONE = 0xbad1
775	} VMXTLBFLUSHVPID;
776	AssertCompileSize(VMXTLBFLUSHVPID, 4);
777
778	/**
779	* VMX EPT flush types.
780	* @note Valid enums values are in accordance to the VT-x spec.
781	*/
782	typedef enum
783	{
784	/** Invalidate one context (specific EPT). */
785	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
786	/* Invalidate all contexts (all EPTs) */
787	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
788	/** Unsupported by VirtualBox. */
789	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
790	/** Unsupported by CPU. */
791	VMXTLBFLUSHEPT_NONE = 0xbad1
792	} VMXTLBFLUSHEPT;
793	AssertCompileSize(VMXTLBFLUSHEPT, 4);
794
795	/**
796	* VMX Posted Interrupt Descriptor.
797	* In accordance to the VT-x spec.
798	*/
799	typedef struct VMXPOSTEDINTRDESC
800	{
801	uint32_t aVectorBitmap[8];
802	uint32_t fOutstandingNotification : 1;
803	uint32_t uReserved0 : 31;
804	uint8_t au8Reserved0[28];
805	} VMXPOSTEDINTRDESC;
806	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
807	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
808	/** Pointer to a posted interrupt descriptor. */
809	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
810	/** Pointer to a const posted interrupt descriptor. */
811	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
812
813	/**
814	* VMX VMCS revision identifier.
815	*/
816	typedef union
817	{
818	struct
819	{
820	/** Revision identifier. */
821	uint32_t u31RevisionId : 31;
822	/** Whether this is a shadow VMCS. */
823	uint32_t fIsShadowVmcs : 1;
824	} n;
825	/* The unsigned integer view. */
826	uint32_t u;
827	} VMXVMCSREVID;
828	AssertCompileSize(VMXVMCSREVID, 4);
829	/** Pointer to the VMXVMCSREVID union. */
830	typedef VMXVMCSREVID *PVMXVMCSREVID;
831	/** Pointer to a const VMXVVMCSREVID union. */
832	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
833
834	/**
835	* VMX VM-exit instruction information.
836	*/
837	typedef union
838	{
839	/** Plain unsigned int representation. */
840	uint32_t u;
841
842	/** INS and OUTS information. */
843	struct
844	{
845	uint32_t u7Reserved0 : 7;
846	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
847	uint32_t u3AddrSize : 3;
848	uint32_t u5Reserved1 : 5;
849	/** The segment register (X86_SREG_XXX). */
850	uint32_t iSegReg : 3;
851	uint32_t uReserved2 : 14;
852	} StrIo;
853
854	struct
855	{
856	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
857	uint32_t u2Scaling : 2;
858	uint32_t u5Undef0 : 5;
859	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
860	uint32_t u3AddrSize : 3;
861	/** Cleared to 0. */
862	uint32_t u1Cleared0 : 1;
863	uint32_t u4Undef0 : 4;
864	/** The segment register (X86_SREG_XXX). */
865	uint32_t iSegReg : 3;
866	/** The index register (X86_GREG_XXX). */
867	uint32_t iIdxReg : 4;
868	/** Set if index register is invalid. */
869	uint32_t fIdxRegInvalid : 1;
870	/** The base register (X86_GREG_XXX). */
871	uint32_t iBaseReg : 4;
872	/** Set if base register is invalid. */
873	uint32_t fBaseRegInvalid : 1;
874	/** Register 2 (X86_GREG_XXX). */
875	uint32_t iReg2 : 4;
876	} Inv;
877
878	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
879	struct
880	{
881	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
882	uint32_t u2Scaling : 2;
883	uint32_t u5Reserved0 : 5;
884	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
885	uint32_t u3AddrSize : 3;
886	/** Cleared to 0. */
887	uint32_t u1Cleared0 : 1;
888	uint32_t u4Reserved0 : 4;
889	/** The segment register (X86_SREG_XXX). */
890	uint32_t iSegReg : 3;
891	/** The index register (X86_GREG_XXX). */
892	uint32_t iIdxReg : 4;
893	/** Set if index register is invalid. */
894	uint32_t fIdxRegInvalid : 1;
895	/** The base register (X86_GREG_XXX). */
896	uint32_t iBaseReg : 4;
897	/** Set if base register is invalid. */
898	uint32_t fBaseRegInvalid : 1;
899	/** Register 2 (X86_GREG_XXX). */
900	uint32_t iReg2 : 4;
901	} VmxXsave;
902
903	/** LIDT, LGDT, SIDT, SGDT information. */
904	struct
905	{
906	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
907	uint32_t u2Scaling : 2;
908	uint32_t u5Undef0 : 5;
909	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
910	uint32_t u3AddrSize : 3;
911	/** Always cleared to 0. */
912	uint32_t u1Cleared0 : 1;
913	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
914	uint32_t uOperandSize : 1;
915	uint32_t u3Undef0 : 3;
916	/** The segment register (X86_SREG_XXX). */
917	uint32_t iSegReg : 3;
918	/** The index register (X86_GREG_XXX). */
919	uint32_t iIdxReg : 4;
920	/** Set if index register is invalid. */
921	uint32_t fIdxRegInvalid : 1;
922	/** The base register (X86_GREG_XXX). */
923	uint32_t iBaseReg : 4;
924	/** Set if base register is invalid. */
925	uint32_t fBaseRegInvalid : 1;
926	/** Instruction identity (VMX_INSTR_ID_XXX). */
927	uint32_t u2InstrId : 2;
928	uint32_t u2Undef0 : 2;
929	} GdtIdt;
930
931	/** LLDT, LTR, SLDT, STR information. */
932	struct
933	{
934	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
935	uint32_t u2Scaling : 2;
936	uint32_t u1Undef0 : 1;
937	/** Register 1 (X86_GREG_XXX). */
938	uint32_t iReg1 : 4;
939	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
940	uint32_t u3AddrSize : 3;
941	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
942	uint32_t fIsRegOperand : 1;
943	uint32_t u4Undef0 : 4;
944	/** The segment register (X86_SREG_XXX). */
945	uint32_t iSegReg : 3;
946	/** The index register (X86_GREG_XXX). */
947	uint32_t iIdxReg : 4;
948	/** Set if index register is invalid. */
949	uint32_t fIdxRegInvalid : 1;
950	/** The base register (X86_GREG_XXX). */
951	uint32_t iBaseReg : 4;
952	/** Set if base register is invalid. */
953	uint32_t fBaseRegInvalid : 1;
954	/** Instruction identity (VMX_INSTR_ID_XXX). */
955	uint32_t u2InstrId : 2;
956	uint32_t u2Undef0 : 2;
957	} LdtTr;
958
959	/** RDRAND, RDSEED information. */
960	struct
961	{
962	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
963	uint32_t u2Undef0 : 2;
964	/** Destination register (X86_GREG_XXX). */
965	uint32_t iReg1 : 4;
966	uint32_t u4Undef0 : 4;
967	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
968	uint32_t u2OperandSize : 2;
969	uint32_t u19Def0 : 20;
970	} RdrandRdseed;
971
972	struct
973	{
974	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
975	uint32_t u2Scaling : 2;
976	uint32_t u1Undef0 : 1;
977	/** Register 1 (X86_GREG_XXX). */
978	uint32_t iReg1 : 4;
979	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
980	uint32_t u3AddrSize : 3;
981	/** Memory or register operand. */
982	uint32_t fIsRegOperand : 1;
983	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
984	uint32_t u4Undef0 : 4;
985	/** The segment register (X86_SREG_XXX). */
986	uint32_t iSegReg : 3;
987	/** The index register (X86_GREG_XXX). */
988	uint32_t iIdxReg : 4;
989	/** Set if index register is invalid. */
990	uint32_t fIdxRegInvalid : 1;
991	/** The base register (X86_GREG_XXX). */
992	uint32_t iBaseReg : 4;
993	/** Set if base register is invalid. */
994	uint32_t fBaseRegInvalid : 1;
995	/** Register 2 (X86_GREG_XXX). */
996	uint32_t iReg2 : 4;
997	} VmreadVmwrite;
998
999	/** This is a combination field of all instruction information. Note! Not all field
1000	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1001	* specialized fields are overwritten by their generic counterparts (e.g. no
1002	* instruction identity field). */
1003	struct
1004	{
1005	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1006	uint32_t u2Scaling : 2;
1007	uint32_t u1Undef0 : 1;
1008	/** Register 1 (X86_GREG_XXX). */
1009	uint32_t iReg1 : 4;
1010	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1011	uint32_t u3AddrSize : 3;
1012	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1013	uint32_t fIsRegOperand : 1;
1014	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1015	uint32_t uOperandSize : 2;
1016	uint32_t u2Undef0 : 2;
1017	/** The segment register (X86_SREG_XXX). */
1018	uint32_t iSegReg : 3;
1019	/** The index register (X86_GREG_XXX). */
1020	uint32_t iIdxReg : 4;
1021	/** Set if index register is invalid. */
1022	uint32_t fIdxRegInvalid : 1;
1023	/** The base register (X86_GREG_XXX). */
1024	uint32_t iBaseReg : 4;
1025	/** Set if base register is invalid. */
1026	uint32_t fBaseRegInvalid : 1;
1027	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1028	uint32_t iReg2 : 4;
1029	} All;
1030	} VMXEXITINSTRINFO;
1031	AssertCompileSize(VMXEXITINSTRINFO, 4);
1032	/** Pointer to a VMX VM-exit instruction info. struct. */
1033	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1034	/** Pointer to a const VMX VM-exit instruction info. struct. */
1035	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1036
1037
1038	/** @name VM-entry failure reported in VM-exit qualification.
1039	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1040	*/
1041	/** No errors during VM-entry. */
1042	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1043	/** Not used. */
1044	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1045	/** Error while loading PDPTEs. */
1046	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1047	/** NMI injection when blocking-by-STI is set. */
1048	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1049	/** Invalid VMCS link pointer. */
1050	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1051	/** @} */
1052
1053
1054	/**
1055	* VMX MSR autoload/store element.
1056	* In accordance to the VT-x spec.
1057	*/
1058	typedef struct VMXAUTOMSR
1059	{
1060	/** The MSR Id. */
1061	uint32_t u32Msr;
1062	/** Reserved (MBZ). */
1063	uint32_t u32Reserved;
1064	/** The MSR value. */
1065	uint64_t u64Value;
1066	} VMXAUTOMSR;
1067	AssertCompileSize(VMXAUTOMSR, 16);
1068	/** Pointer to an MSR load/store element. */
1069	typedef VMXAUTOMSR *PVMXAUTOMSR;
1070	/** Pointer to a const MSR load/store element. */
1071	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1072
1073	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1074	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1075
1076	/**
1077	* VMX tagged-TLB flush types.
1078	*/
1079	typedef enum
1080	{
1081	VMXTLBFLUSHTYPE_EPT,
1082	VMXTLBFLUSHTYPE_VPID,
1083	VMXTLBFLUSHTYPE_EPT_VPID,
1084	VMXTLBFLUSHTYPE_NONE
1085	} VMXTLBFLUSHTYPE;
1086	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1087	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1088	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1089	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1090
1091	/**
1092	* VMX controls MSR.
1093	*/
1094	typedef union
1095	{
1096	struct
1097	{
1098	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1099	uint32_t disallowed0;
1100	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1101	* controls. */
1102	uint32_t allowed1;
1103	} n;
1104	uint64_t u;
1105	} VMXCTLSMSR;
1106	AssertCompileSize(VMXCTLSMSR, 8);
1107	/** Pointer to a VMXCTLSMSR union. */
1108	typedef VMXCTLSMSR *PVMXCTLSMSR;
1109	/** Pointer to a const VMXCTLSMSR union. */
1110	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1111
1112	/**
1113	* VMX MSRs.
1114	* @remarks Although treated as a plain-old data (POD) in several places, please
1115	* update HMVmxGetHostMsr() if new MSRs are added here.
1116	*/
1117	typedef struct VMXMSRS
1118	{
1119	uint64_t u64FeatCtrl;
1120	uint64_t u64Basic;
1121	VMXCTLSMSR PinCtls;
1122	VMXCTLSMSR ProcCtls;
1123	VMXCTLSMSR ProcCtls2;
1124	VMXCTLSMSR ExitCtls;
1125	VMXCTLSMSR EntryCtls;
1126	VMXCTLSMSR TruePinCtls;
1127	VMXCTLSMSR TrueProcCtls;
1128	VMXCTLSMSR TrueEntryCtls;
1129	VMXCTLSMSR TrueExitCtls;
1130	uint64_t u64Misc;
1131	uint64_t u64Cr0Fixed0;
1132	uint64_t u64Cr0Fixed1;
1133	uint64_t u64Cr4Fixed0;
1134	uint64_t u64Cr4Fixed1;
1135	uint64_t u64VmcsEnum;
1136	uint64_t u64VmFunc;
1137	uint64_t u64EptVpidCaps;
1138	uint64_t a_u64Reserved[2];
1139	} VMXMSRS;
1140	AssertCompileSizeAlignment(VMXMSRS, 8);
1141	AssertCompileSize(VMXMSRS, 168);
1142	/** Pointer to a VMXMSRS struct. */
1143	typedef VMXMSRS *PVMXMSRS;
1144	/** Pointer to a const VMXMSRS struct. */
1145	typedef const VMXMSRS *PCVMXMSRS;
1146
1147
1148	/** @name VMX Basic Exit Reasons.
1149	* @{
1150	*/
1151	/** -1 Invalid exit code */
1152	#define VMX_EXIT_INVALID (-1)
1153	/** 0 Exception or non-maskable interrupt (NMI). */
1154	#define VMX_EXIT_XCPT_OR_NMI 0
1155	/** 1 External interrupt. */
1156	#define VMX_EXIT_EXT_INT 1
1157	/** 2 Triple fault. */
1158	#define VMX_EXIT_TRIPLE_FAULT 2
1159	/** 3 INIT signal. */
1160	#define VMX_EXIT_INIT_SIGNAL 3
1161	/** 4 Start-up IPI (SIPI). */
1162	#define VMX_EXIT_SIPI 4
1163	/** 5 I/O system-management interrupt (SMI). */
1164	#define VMX_EXIT_IO_SMI 5
1165	/** 6 Other SMI. */
1166	#define VMX_EXIT_SMI 6
1167	/** 7 Interrupt window exiting. */
1168	#define VMX_EXIT_INT_WINDOW 7
1169	/** 8 NMI window exiting. */
1170	#define VMX_EXIT_NMI_WINDOW 8
1171	/** 9 Task switch. */
1172	#define VMX_EXIT_TASK_SWITCH 9
1173	/** 10 Guest software attempted to execute CPUID. */
1174	#define VMX_EXIT_CPUID 10
1175	/** 11 Guest software attempted to execute GETSEC. */
1176	#define VMX_EXIT_GETSEC 11
1177	/** 12 Guest software attempted to execute HLT. */
1178	#define VMX_EXIT_HLT 12
1179	/** 13 Guest software attempted to execute INVD. */
1180	#define VMX_EXIT_INVD 13
1181	/** 14 Guest software attempted to execute INVLPG. */
1182	#define VMX_EXIT_INVLPG 14
1183	/** 15 Guest software attempted to execute RDPMC. */
1184	#define VMX_EXIT_RDPMC 15
1185	/** 16 Guest software attempted to execute RDTSC. */
1186	#define VMX_EXIT_RDTSC 16
1187	/** 17 Guest software attempted to execute RSM in SMM. */
1188	#define VMX_EXIT_RSM 17
1189	/** 18 Guest software executed VMCALL. */
1190	#define VMX_EXIT_VMCALL 18
1191	/** 19 Guest software executed VMCLEAR. */
1192	#define VMX_EXIT_VMCLEAR 19
1193	/** 20 Guest software executed VMLAUNCH. */
1194	#define VMX_EXIT_VMLAUNCH 20
1195	/** 21 Guest software executed VMPTRLD. */
1196	#define VMX_EXIT_VMPTRLD 21
1197	/** 22 Guest software executed VMPTRST. */
1198	#define VMX_EXIT_VMPTRST 22
1199	/** 23 Guest software executed VMREAD. */
1200	#define VMX_EXIT_VMREAD 23
1201	/** 24 Guest software executed VMRESUME. */
1202	#define VMX_EXIT_VMRESUME 24
1203	/** 25 Guest software executed VMWRITE. */
1204	#define VMX_EXIT_VMWRITE 25
1205	/** 26 Guest software executed VMXOFF. */
1206	#define VMX_EXIT_VMXOFF 26
1207	/** 27 Guest software executed VMXON. */
1208	#define VMX_EXIT_VMXON 27
1209	/** 28 Control-register accesses. */
1210	#define VMX_EXIT_MOV_CRX 28
1211	/** 29 Debug-register accesses. */
1212	#define VMX_EXIT_MOV_DRX 29
1213	/** 30 I/O instruction. */
1214	#define VMX_EXIT_IO_INSTR 30
1215	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
1216	#define VMX_EXIT_RDMSR 31
1217	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
1218	#define VMX_EXIT_WRMSR 32
1219	/** 33 VM-entry failure due to invalid guest state. */
1220	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1221	/** 34 VM-entry failure due to MSR loading. */
1222	#define VMX_EXIT_ERR_MSR_LOAD 34
1223	/** 36 Guest software executed MWAIT. */
1224	#define VMX_EXIT_MWAIT 36
1225	/** 37 VM-exit due to monitor trap flag. */
1226	#define VMX_EXIT_MTF 37
1227	/** 39 Guest software attempted to execute MONITOR. */
1228	#define VMX_EXIT_MONITOR 39
1229	/** 40 Guest software attempted to execute PAUSE. */
1230	#define VMX_EXIT_PAUSE 40
1231	/** 41 VM-entry failure due to machine-check. */
1232	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1233	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
1234	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1235	/** 44 APIC access. Guest software attempted to access memory at a physical
1236	* address on the APIC-access page. */
1237	#define VMX_EXIT_APIC_ACCESS 44
1238	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual
1239	* interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
1240	#define VMX_EXIT_VIRTUALIZED_EOI 45
1241	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
1242	* SGDT, or SIDT. */
1243	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1244	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
1245	* SLDT, or STR. */
1246	#define VMX_EXIT_LDTR_TR_ACCESS 47
1247	/** 48 EPT violation. An attempt to access memory with a guest-physical address
1248	* was disallowed by the configuration of the EPT paging structures. */
1249	#define VMX_EXIT_EPT_VIOLATION 48
1250	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
1251	* address encountered a misconfigured EPT paging-structure entry. */
1252	#define VMX_EXIT_EPT_MISCONFIG 49
1253	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
1254	#define VMX_EXIT_INVEPT 50
1255	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1256	#define VMX_EXIT_RDTSCP 51
1257	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1258	#define VMX_EXIT_PREEMPT_TIMER 52
1259	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1260	#define VMX_EXIT_INVVPID 53
1261	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1262	#define VMX_EXIT_WBINVD 54
1263	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1264	#define VMX_EXIT_XSETBV 55
1265	/** 56 APIC write. Guest completed write to virtual-APIC. */
1266	#define VMX_EXIT_APIC_WRITE 56
1267	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1268	#define VMX_EXIT_RDRAND 57
1269	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1270	#define VMX_EXIT_INVPCID 58
1271	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1272	#define VMX_EXIT_VMFUNC 59
1273	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1274	#define VMX_EXIT_ENCLS 60
1275	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1276	* enabled. */
1277	#define VMX_EXIT_RDSEED 61
1278	/** 62 - Page-modification log full. */
1279	#define VMX_EXIT_PML_FULL 62
1280	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
1281	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1282	#define VMX_EXIT_XSAVES 63
1283	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
1284	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1285	#define VMX_EXIT_XRSTORS 64
1286	/** The maximum exit value (inclusive). */
1287	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1288	/** @} */
1289
1290
1291	/** @name VM Instruction Errors.
1292	* See Intel spec. "30.4 VM Instruction Error Numbers"
1293	* @{
1294	*/
1295	typedef enum
1296	{
1297	/** VMCALL executed in VMX root operation. */
1298	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1299	/** VMCLEAR with invalid physical address. */
1300	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1301	/** VMCLEAR with VMXON pointer. */
1302	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1303	/** VMLAUNCH with non-clear VMCS. */
1304	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1305	/** VMRESUME with non-launched VMCS. */
1306	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1307	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1308	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1309	/** VM-entry with invalid control field(s). */
1310	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1311	/** VM-entry with invalid host-state field(s). */
1312	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1313	/** VMPTRLD with invalid physical address. */
1314	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1315	/** VMPTRLD with VMXON pointer. */
1316	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1317	/** VMPTRLD with incorrect VMCS revision identifier. */
1318	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1319	/** VMREAD from unsupported VMCS component. */
1320	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1321	/** VMWRITE to unsupported VMCS component. */
1322	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1323	/** VMWRITE to read-only VMCS component. */
1324	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1325	/** VMXON executed in VMX root operation. */
1326	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1327	/** VM-entry with invalid executive-VMCS pointer. */
1328	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1329	/** VM-entry with non-launched executive VMCS. */
1330	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1331	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1332	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1333	/** VMCALL with non-clear VMCS. */
1334	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1335	/** VMCALL with invalid VM-exit control fields. */
1336	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1337	/** VMCALL with incorrect MSEG revision identifier. */
1338	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1339	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1340	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1341	/** VMCALL with invalid SMM-monitor features. */
1342	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1343	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1344	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1345	/** VM-entry with events blocked by MOV SS. */
1346	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1347	/** Invalid operand to INVEPT/INVVPID. */
1348	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1349	} VMXINSTRERR;
1350	/** @} */
1351
1352
1353	/** @name VMX abort reasons.
1354	* See Intel spec. "27.7 VMX Aborts".
1355	* Update HMVmxGetAbortDesc() if new reasons are added.
1356	* @{
1357	*/
1358	typedef enum
1359	{
1360	/** None - don't use this / uninitialized value. */
1361	VMXABORT_NONE = 0,
1362	/** VMX abort caused during saving of guest MSRs. */
1363	VMXABORT_SAVE_GUEST_MSRS = 1,
1364	/** VMX abort caused during host PDPTE checks. */
1365	VMXBOART_HOST_PDPTE = 2,
1366	/** VMX abort caused due to current VMCS being corrupted. */
1367	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1368	/** VMX abort caused during loading of host MSRs. */
1369	VMXABORT_LOAD_HOST_MSR = 4,
1370	/** VMX abort caused due to a machine-check exception during VM-exit. */
1371	VMXABORT_MACHINE_CHECK_XCPT = 5,
1372	/** VMX abort caused due to invalid return from long mode. */
1373	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1374	/* Type size hack. */
1375	VMXABORT_32BIT_HACK = 0x7fffffff
1376	} VMXABORT;
1377	AssertCompileSize(VMXABORT, 4);
1378	/** @} */
1379
1380
1381	/** @name VMX MSR - Basic VMX information.
1382	* @{
1383	*/
1384	/** VMCS (and related regions) memory type - Uncacheable. */
1385	#define VMX_BASIC_MEM_TYPE_UC 0
1386	/** VMCS (and related regions) memory type - Write back. */
1387	#define VMX_BASIC_MEM_TYPE_WB 6
1388
1389	/** Bit fields for MSR_IA32_VMX_BASIC. */
1390	/** VMCS revision identifier used by the processor. */
1391	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1392	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1393	/** Bit 31 is reserved and RAZ. */
1394	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1395	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1396	/** VMCS size in bytes. */
1397	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1398	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1399	/** Bits 45:47 are reserved. */
1400	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1401	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1402	/** Width of physical addresses used for the VMCS and associated memory regions
1403	* (always 0 on CPUs that support Intel 64 architecture). */
1404	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1405	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1406	/** Dual-monitor treatment of SMI and SMM supported. */
1407	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1408	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1409	/** Memory type that must be used for the VMCS and associated memory regions. */
1410	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1411	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1412	/** VM-exit instruction information for INS/OUTS. */
1413	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1414	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1415	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1416	* bits in VMX control MSRs. */
1417	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1418	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1419	/** Bits 56:63 are reserved and RAZ. */
1420	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 56
1421	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xff00000000000000)
1422	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1423	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1424	VMCS_INS_OUTS, TRUE_CTLS, RSVD_56_63));
1425	/** @} */
1426
1427
1428	/** @name VMX MSR - Miscellaneous data.
1429	* Bit fields for MSR_IA32_VMX_MISC.
1430	* @{
1431	*/
1432	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1433	#define VMX_MISC_EXIT_STORE_EFER_LMA RT_BIT(5)
1434	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1435	* VMWRITE cannot modify read-only VM-exit information fields. */
1436	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1437	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1438	* instructions. */
1439	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1440	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1441	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1442	/** Maximum CR3-target count supported by the CPU. */
1443	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1444	/** Relationship between the preemption timer and tsc. */
1445	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1446	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1447	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1448	#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_SHIFT 5
1449	#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1450	/** Activity states supported by the implementation. */
1451	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1452	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1453	/** Bits 9:13 is reserved and RAZ. */
1454	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1455	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1456	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1457	#define VMX_BF_MISC_PT_SHIFT 14
1458	#define VMX_BF_MISC_PT_MASK UINT64_C(0x0000000000004000)
1459	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1460	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1461	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1462	/** Number of CR3 target values supported by the processor. (0-256) */
1463	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1464	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1465	/** Maximum number of MSRs in the VMCS. */
1466	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1467	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1468	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1469	* SMIs. */
1470	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1471	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1472	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1473	* VMWRITE cannot modify read-only VM-exit information fields. */
1474	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1475	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1476	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1477	* instructions. */
1478	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1479	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1480	/** Bit 31 is reserved and RAZ. */
1481	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1482	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1483	/** 32-bit MSEG revision ID used by the processor. */
1484	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1485	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1486	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1487	(PREEMPT_TIMER_TSC, EXIT_STORE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, PT, SMM_READ_SMBASE_MSR,
1488	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1489	/** @} */
1490
1491	/** @name VMX MSR - VMCS enumeration.
1492	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1493	* @{
1494	*/
1495	/** Bit 0 is reserved and RAZ. */
1496	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1497	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1498	/** Highest index value used in VMCS field encoding. */
1499	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1500	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1501	/** Bit 10:63 is reserved and RAZ. */
1502	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1503	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1504	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1505	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1506	/** @} */
1507
1508
1509	/** @name VMX MSR - VM Functions.
1510	* Bit fields for MSR_IA32_VMX_VMFUNC.
1511	* @{
1512	*/
1513	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1514	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1515	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1516	/** Bits 1:63 are reserved and RAZ. */
1517	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1518	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1519	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1520	(EPTP_SWITCHING, RSVD_1_63));
1521	/** @} */
1522
1523
1524	/** @name VMX MSR - EPT/VPID capabilities.
1525	* @{
1526	*/
1527	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1528	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1529	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1530	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1531	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1532	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1533	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1534	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1535	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1536	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1537	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1538	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1539	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1540	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1541	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1542	/** @} */
1543
1544
1545	/** @name Extended Page Table Pointer (EPTP)
1546	* @{
1547	*/
1548	/** Uncachable EPT paging structure memory type. */
1549	#define VMX_EPT_MEMTYPE_UC 0
1550	/** Write-back EPT paging structure memory type. */
1551	#define VMX_EPT_MEMTYPE_WB 6
1552	/** Shift value to get the EPT page walk length (bits 5-3) */
1553	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1554	/** Mask value to get the EPT page walk length (bits 5-3) */
1555	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1556	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1557	* length) */
1558	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1559	/** @} */
1560
1561
1562	/** @name VMCS field encoding: 16-bit guest fields.
1563	* @{
1564	*/
1565	#define VMX_VMCS16_VPID 0x0000
1566	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1567	#define VMX_VMCS16_EPTP_INDEX 0x0004
1568	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1569	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1570	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1571	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1572	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1573	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1574	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1575	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1576	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1577	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1578	/** @} */
1579
1580
1581	/** @name VMCS field encoding: 16-bits host fields.
1582	* @{
1583	*/
1584	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1585	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1586	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1587	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1588	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1589	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1590	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1591	/** @} */
1592
1593
1594	/** @name VMCS field encoding: 64-bit control fields.
1595	* @{
1596	*/
1597	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1598	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1599	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1600	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1601	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1602	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1603	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1604	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1605	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1606	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1607	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1608	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1609	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1610	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1611	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1612	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1613	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1614	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1615	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1616	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1617	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1618	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1619	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1620	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1621	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1622	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1623	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1624	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1625	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1626	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1627	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1628	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1629	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1630	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1631	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1632	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1633	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1634	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1635	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1636	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1637	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1638	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1639	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202a
1640	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202b
1641	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
1642	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
1643	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
1644	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
1645	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1646	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1647	/** @} */
1648
1649
1650	/** @name VMCS field encoding: 64-bit read-only data fields.
1651	* @{
1652	*/
1653	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
1654	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
1655	/** @} */
1656
1657
1658	/** @name VMCS field encoding: 64-bit guest fields.
1659	* @{
1660	*/
1661	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1662	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1663	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
1664	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
1665	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1666	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1667	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1668	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1669	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
1670	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
1671	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
1672	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
1673	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
1674	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
1675	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
1676	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
1677	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1678	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1679	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
1680	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
1681	/** @} */
1682
1683
1684	/** @name VMCS field encoding: 64-bit host fields.
1685	* @{
1686	*/
1687	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
1688	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
1689	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
1690	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
1691	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
1692	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
1693	/** @} */
1694
1695
1696	/** @name VMCS field encoding: 32-bit control fields.
1697	* @{
1698	*/
1699	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1700	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1701	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1702	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1703	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1704	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
1705	#define VMX_VMCS32_CTRL_EXIT 0x400c
1706	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
1707	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1708	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1709	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1710	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1711	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1712	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
1713	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
1714	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
1715	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1716	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1717	/** @} */
1718
1719
1720	/** @name VMCS field encoding: 32-bits read-only fields.
1721	* @{
1722	*/
1723	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1724	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1725	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1726	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1727	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
1728	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
1729	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
1730	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
1731	/** @} */
1732
1733
1734	/** @name VMCS field encoding: 32-bit guest-state fields.
1735	* @{
1736	*/
1737	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1738	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1739	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1740	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1741	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1742	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
1743	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
1744	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
1745	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1746	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1747	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1748	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1749	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1750	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
1751	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
1752	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
1753	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1754	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1755	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
1756	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1757	#define VMX_VMCS32_GUEST_SMBASE 0x4828
1758	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
1759	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
1760	/** @} */
1761
1762
1763	/** @name VMCS field encoding: 32-bit host-state fields.
1764	* @{
1765	*/
1766	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1767	/** @} */
1768
1769
1770	/** @name Natural width control fields.
1771	* @{
1772	*/
1773	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1774	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1775	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1776	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1777	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1778	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
1779	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
1780	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
1781	/** @} */
1782
1783
1784	/** @name Natural width read-only data fields.
1785	* @{
1786	*/
1787	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1788	#define VMX_VMCS_RO_IO_RCX 0x6402
1789	#define VMX_VMCS_RO_IO_RSX 0x6404
1790	#define VMX_VMCS_RO_IO_RDI 0x6406
1791	#define VMX_VMCS_RO_IO_RIP 0x6408
1792	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640a
1793	/** @} */
1794
1795
1796	/** @name VMCS field encoding: Natural width guest-state fields.
1797	* @{
1798	*/
1799	#define VMX_VMCS_GUEST_CR0 0x6800
1800	#define VMX_VMCS_GUEST_CR3 0x6802
1801	#define VMX_VMCS_GUEST_CR4 0x6804
1802	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1803	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1804	#define VMX_VMCS_GUEST_SS_BASE 0x680a
1805	#define VMX_VMCS_GUEST_DS_BASE 0x680c
1806	#define VMX_VMCS_GUEST_FS_BASE 0x680e
1807	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1808	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1809	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1810	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1811	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1812	#define VMX_VMCS_GUEST_DR7 0x681a
1813	#define VMX_VMCS_GUEST_RSP 0x681c
1814	#define VMX_VMCS_GUEST_RIP 0x681e
1815	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1816	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
1817	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
1818	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
1819	/** @} */
1820
1821
1822	/** @name VMCS field encoding: Natural width host-state fields.
1823	* @{
1824	*/
1825	#define VMX_VMCS_HOST_CR0 0x6c00
1826	#define VMX_VMCS_HOST_CR3 0x6c02
1827	#define VMX_VMCS_HOST_CR4 0x6c04
1828	#define VMX_VMCS_HOST_FS_BASE 0x6c06
1829	#define VMX_VMCS_HOST_GS_BASE 0x6c08
1830	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
1831	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
1832	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
1833	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
1834	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
1835	#define VMX_VMCS_HOST_RSP 0x6c14
1836	#define VMX_VMCS_HOST_RIP 0x6c16
1837	/** @} */
1838
1839
1840	/** @name VMCS field encoding: Access.
1841	* @{ */
1842	typedef enum
1843	{
1844	VMXVMCSFIELDACCESS_FULL = 0,
1845	VMXVMCSFIELDACCESS_HIGH
1846	} VMXVMCSFIELDACCESS;
1847	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
1848	/** @} */
1849
1850
1851	/** @name VMCS field encoding: Type.
1852	* @{ */
1853	typedef enum
1854	{
1855	VMXVMCSFIELDTYPE_CONTROL = 0,
1856	VMXVMCSFIELDTYPE_VMEXIT_INFO,
1857	VMXVMCSFIELDTYPE_GUEST_STATE,
1858	VMXVMCSFIELDTYPE_HOST_STATE
1859	} VMXVMCSFIELDTYPE;
1860	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
1861	/** @} */
1862
1863
1864	/** @name VMCS field encoding: Width.
1865	* @{ */
1866	typedef enum
1867	{
1868	VMXVMCSFIELDWIDTH_16BIT = 0,
1869	VMXVMCSFIELDWIDTH_64BIT,
1870	VMXVMCSFIELDWIDTH_32BIT,
1871	VMXVMCSFIELDWIDTH_NATURAL
1872	} VMXVMCSFIELDWIDTH;
1873	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
1874	/** @} */
1875
1876	/** @name VM-entry instruction length.
1877	* @{ */
1878	/** The maximum valid value for VM-entry instruction length while injecting a
1879	* software interrupt, software exception or privileged software exception. */
1880	#define VMX_ENTRY_INSTR_LEN_MAX 15
1881	/** @} */
1882
1883
1884	/** @name VM-entry register masks.
1885	* @{ */
1886	/** CR0 bits ignored on VM-entry (ET, NW, CD and reserved bits bits 6:15, bit 17,
1887	* bits 19:28). */
1888	#define VMX_ENTRY_CR0_IGNORE_MASK UINT64_C(0x7ffaffc0)
1889	/** DR7 bits set here are always cleared on VM-entry (bit 12, bits 14:15). */
1890	#define VMX_ENTRY_DR7_MBZ_MASK UINT64_C(0xd000)
1891	/** DR7 bits set here are always set on VM-entry (bit 10). */
1892	#define VMX_ENTRY_DR7_MB1_MASK UINT64_C(0x400)
1893	/** @} */
1894
1895
1896	/** @name Pin-based VM-execution controls.
1897	* @{
1898	*/
1899	/** External interrupt exiting. */
1900	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
1901	/** NMI exiting. */
1902	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
1903	/** Virtual NMIs. */
1904	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
1905	/** Activate VMX preemption timer. */
1906	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
1907	/** Process interrupts with the posted-interrupt notification vector. */
1908	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
1909	/** Default1 class when true capability MSRs are not supported. */
1910	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
1911
1912	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
1913	* controls field in the VMCS. */
1914	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
1915	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
1916	#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT 1
1917	#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK UINT32_C(0x00000006)
1918	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
1919	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
1920	#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT 4
1921	#define VMX_BF_PIN_CTLS_UNDEF_4_MASK UINT32_C(0x00000010)
1922	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
1923	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
1924	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
1925	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
1926	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
1927	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
1928	#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT 8
1929	#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK UINT32_C(0xffffff00)
1930	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
1931	(EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
1932	/** @} */
1933
1934
1935	/** @name Processor-based VM-execution controls.
1936	* @{
1937	*/
1938	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1939	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
1940	/** Use timestamp counter offset. */
1941	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
1942	/** VM-exit when executing the HLT instruction. */
1943	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
1944	/** VM-exit when executing the INVLPG instruction. */
1945	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
1946	/** VM-exit when executing the MWAIT instruction. */
1947	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
1948	/** VM-exit when executing the RDPMC instruction. */
1949	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
1950	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1951	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
1952	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
1953	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1954	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
1955	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
1956	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1957	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
1958	/** VM-exit on CR8 loads. */
1959	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
1960	/** VM-exit on CR8 stores. */
1961	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
1962	/** Use TPR shadow. */
1963	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
1964	/** VM-exit when virtual NMI blocking is disabled. */
1965	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
1966	/** VM-exit when executing a MOV DRx instruction. */
1967	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
1968	/** VM-exit when executing IO instructions. */
1969	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
1970	/** Use IO bitmaps. */
1971	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
1972	/** Monitor trap flag. */
1973	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
1974	/** Use MSR bitmaps. */
1975	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
1976	/** VM-exit when executing the MONITOR instruction. */
1977	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
1978	/** VM-exit when executing the PAUSE instruction. */
1979	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
1980	/** Whether the secondary processor based VM-execution controls are used. */
1981	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
1982	/** Default1 class when true-capability MSRs are not supported. */
1983	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
1984
1985	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
1986	* controls field in the VMCS. */
1987	#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT 0
1988	#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
1989	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
1990	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
1991	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
1992	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
1993	#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT 4
1994	#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK UINT32_C(0x00000070)
1995	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
1996	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
1997	#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT 8
1998	#define VMX_BF_PROC_CTLS_UNDEF_8_MASK UINT32_C(0x00000100)
1999	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2000	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2001	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2002	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2003	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2004	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2005	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2006	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2007	#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT 13
2008	#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2009	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2010	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2011	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2012	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2013	#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT 17
2014	#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK UINT32_C(0x00060000)
2015	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2016	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2017	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2018	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2019	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2020	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2021	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2022	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2023	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2024	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2025	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2026	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2027	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2028	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2029	#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT 26
2030	#define VMX_BF_PROC_CTLS_UNDEF_26_MASK UINT32_C(0x4000000)
2031	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2032	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2033	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2034	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2035	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2036	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2037	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2038	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2039	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2040	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2041	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2042	(UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
2043	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
2044	CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2045	USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2046	USE_SECONDARY_CTLS));
2047	/** @} */
2048
2049
2050	/** @name Secondary Processor-based VM-execution controls.
2051	* @{
2052	*/
2053	/** Virtualize APIC access. */
2054	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2055	/** EPT supported/enabled. */
2056	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2057	/** Descriptor table instructions cause VM-exits. */
2058	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2059	/** RDTSCP supported/enabled. */
2060	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2061	/** Virtualize x2APIC mode. */
2062	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2063	/** VPID supported/enabled. */
2064	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2065	/** VM-exit when executing the WBINVD instruction. */
2066	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2067	/** Unrestricted guest execution. */
2068	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2069	/** APIC register virtualization. */
2070	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2071	/** Virtual-interrupt delivery. */
2072	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2073	/** A specified number of pause loops cause a VM-exit. */
2074	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2075	/** VM-exit when executing RDRAND instructions. */
2076	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2077	/** Enables INVPCID instructions. */
2078	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2079	/** Enables VMFUNC instructions. */
2080	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2081	/** Enables VMCS shadowing. */
2082	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2083	/** Enables ENCLS VM-exits. */
2084	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2085	/** VM-exit when executing RDSEED. */
2086	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2087	/** Enables page-modification logging. */
2088	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2089	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2090	#define VMX_PROC_CTLS2_EPT_VE RT_BIT(18)
2091	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2092	#define VMX_PROC_CTLS2_CONCEAL_FROM_PT RT_BIT(19)
2093	/** Enables XSAVES/XRSTORS instructions. */
2094	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2095	/** Use TSC scaling. */
2096	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2097
2098	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2099	* VM-execution controls field in the VMCS. */
2100	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2101	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2102	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2103	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2104	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2105	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2106	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2107	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2108	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2109	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2110	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2111	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2112	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2113	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2114	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2115	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2116	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2117	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2118	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2119	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2120	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2121	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2122	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2123	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2124	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2125	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2126	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2127	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2128	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2129	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2130	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2131	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2132	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2133	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2134	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2135	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2136	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2137	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2138	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_SHIFT 19
2139	#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_MASK UINT32_C(0x00080000)
2140	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2141	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2142	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_SHIFT 21
2143	#define VMX_BF_PROC_CTLS2_UNDEF_21_24_MASK UINT32_C(0x01e00000)
2144	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2145	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2146	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_SHIFT 26
2147	#define VMX_BF_PROC_CTLS2_UNDEF_26_31_MASK UINT32_C(0xfc000000)
2148	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2149	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2150	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2151	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_FROM_PT, XSAVES_XRSTORS, UNDEF_21_24,
2152	TSC_SCALING, UNDEF_26_31));
2153	/** @} */
2154
2155
2156	/** @name VM-entry controls.
2157	* @{
2158	*/
2159	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2160	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2161	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2162	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2163	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2164	/** In SMM mode after VM-entry. */
2165	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2166	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2167	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2168	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2169	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2170	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2171	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2172	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2173	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2174	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2175	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2176	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2177	#define VMX_ENTRY_CTLS_CONCEAL_VMX_PT RT_BIT(17)
2178	/** Default1 class when true-capability MSRs are not supported. */
2179	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2180
2181	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2182	* VMCS. */
2183	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT 0
2184	#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2185	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2186	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2187	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT 3
2188	#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2189	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2190	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2191	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2192	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2193	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2194	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2195	#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT 12
2196	#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK UINT32_C(0x00001000)
2197	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2198	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2199	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2200	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2201	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2202	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2203	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2204	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2205	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_SHIFT 17
2206	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_MASK UINT32_C(0x00020000)
2207	#define VMX_BF_ENTRY_CTLS_UNDEF_18_31_SHIFT 18
2208	#define VMX_BF_ENTRY_CTLS_UNDEF_18_31_MASK UINT32_C(0xfffc0000)
2209	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2210	(UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
2211	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_PT, UNDEF_18_31));
2212	/** @} */
2213
2214
2215	/** @name VM-exit controls.
2216	* @{
2217	*/
2218	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2219	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2220	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2221	/** Return to long mode after a VM-exit. */
2222	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2223	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2224	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2225	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2226	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2227	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2228	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2229	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2230	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2231	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2232	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2233	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2234	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2235	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2236	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2237	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2238	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2239	/** Default1 class when true-capability MSRs are not supported. */
2240	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2241
2242	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2243	* VMCS. */
2244	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT 0
2245	#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK UINT32_C(0x00000003)
2246	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2247	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2248	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT 3
2249	#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK UINT32_C(0x000001f8)
2250	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2251	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2252	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT 10
2253	#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK UINT32_C(0x00000c00)
2254	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2255	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2256	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT 13
2257	#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK UINT32_C(0x00006000)
2258	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2259	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2260	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT 16
2261	#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK UINT32_C(0x00030000)
2262	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2263	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2264	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2265	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2266	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2267	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2268	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2269	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2270	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2271	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2272	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_SHIFT 23
2273	#define VMX_BF_EXIT_CTLS_UNDEF_23_31_MASK UINT32_C(0xff800000)
2274	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2275	(UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
2276	ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2277	SAVE_PREEMPT_TIMER, UNDEF_23_31));
2278	/** @} */
2279
2280
2281	/** @name VM-exit reason.
2282	* @{
2283	*/
2284	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2285	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2286
2287	/** Bit fields for VM-exit reason. */
2288	/** The exit reason. */
2289	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2290	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2291	/** Bits 16:26 are reseved and MBZ. */
2292	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2293	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2294	/** Whether the VM-exit was incident to enclave mode. */
2295	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2296	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2297	/** Pending MTF (Monitor Trap Flag) VM-exit. */
2298	#define VMX_BF_EXIT_REASON_PENDING_MTF_SHIFT 28
2299	#define VMX_BF_EXIT_REASON_PENDING_MTF_MASK UINT32_C(0x10000000)
2300	/** VM-exit from VMX root operation (only possible with SMM). */
2301	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2302	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2303	/** Bit 30 is reserved and MBZ. */
2304	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2305	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2306	/** Whether VM-entry failed (currently only happens during loading guest-state
2307	* or MSRs or machine check exceptions). */
2308	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2309	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2310	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2311	(BASIC, RSVD_16_26, ENCLAVE_MODE, PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2312	/** @} */
2313
2314
2315	/** @name VM-entry interruption information.
2316	* @{
2317	*/
2318	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2319	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2320	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2321	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2322	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2323	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2324	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2325	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2326	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2327	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2328	/** Construct an VM-entry interruption information field from a VM-exit interruption
2329	* info value (same except that bit 12 is reserved). */
2330	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2331	/** Construct a VM-entry interruption information field from an IDT-vectoring
2332	* information field (same except that bit 12 is reserved). */
2333	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2334
2335	/** Bit fields for VM-entry interruption information. */
2336	/** The VM-entry interruption vector. */
2337	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2338	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2339	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2340	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2341	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2342	/** Whether this event has an error code. */
2343	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2344	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2345	/** Bits 12:30 are reserved and MBZ. */
2346	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2347	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2348	/** Whether this VM-entry interruption info is valid. */
2349	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2350	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2351	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2352	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2353	/** @} */
2354
2355	/** @name VM-entry exception error code.
2356	* @{ */
2357	/** Error code valid mask. */
2358	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2359	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2360	* stack aligned for doubleword pushes, the upper half of the error code is
2361	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2362	* use below. */
2363	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2364	/** @} */
2365
2366	/** @name VM-entry interruption information types.
2367	* @{
2368	*/
2369	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2370	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2371	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2372	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2373	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2374	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2375	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2376	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2377	/** @} */
2378
2379
2380	/** @name VM-entry interruption information vector types for
2381	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2382	* @{ */
2383	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2384	/** @} */
2385
2386
2387	/** @name VM-exit interruption information.
2388	* @{
2389	*/
2390	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2391	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2392	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2393	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2394	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2395	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2396	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2397	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2398	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2399
2400	/** Bit fields for VM-exit interruption infomration. */
2401	/** The VM-exit interruption vector. */
2402	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2403	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2404	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2405	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2406	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2407	/** Whether this event has an error code. */
2408	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2409	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2410	/** Whether NMI-unblocking due to IRET is active. */
2411	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2412	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2413	/** Bits 13:30 is reserved (MBZ). */
2414	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2415	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2416	/** Whether this VM-exit interruption info is valid. */
2417	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2418	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2419	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2420	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2421	/** @} */
2422
2423
2424	/** @name VM-exit interruption information types.
2425	* @{
2426	*/
2427	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2428	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2429	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2430	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2431	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2432	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2433	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2434	/** @} */
2435
2436
2437	/** @name VM-exit instruction identity.
2438	*
2439	* These are found in VM-exit instruction information fields for certain
2440	* instructions.
2441	* @{ */
2442	typedef uint8_t VMXINSTRID;
2443	#define VMXINSTRID_VALID RT_BIT(7)
2444	#define VMXINSTRID_IS_VALID(a) (((a) >> 7) & 1)
2445	#define VMXINSTRID_GET_ID(a) ((a) & ~VMXINSTRID_VALID)
2446	#define VMXINSTRID_NONE 0
2447	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
2448	#define VMXINSTRID_SGDT ((VMXINSTRID_VALID) \| 0)
2449	#define VMXINSTRID_SIDT ((VMXINSTRID_VALID) \| 1)
2450	#define VMXINSTRID_LGDT ((VMXINSTRID_VALID) \| 2)
2451	#define VMXINSTRID_LIDT ((VMXINSTRID_VALID) \| 3)
2452
2453	#define VMXINSTRID_SLDT ((VMXINSTRID_VALID) \| 0)
2454	#define VMXINSTRID_STR ((VMXINSTRID_VALID) \| 1)
2455	#define VMXINSTRID_LLDT ((VMXINSTRID_VALID) \| 2)
2456	#define VMXINSTRID_LTR ((VMXINSTRID_VALID) \| 3)
2457
2458	/** The following are used internally and are not based on the VT-x spec: */
2459	#define VMXINSTRID_VMLAUNCH ((VMXINSTRID_VALID) \| 50)
2460	#define VMXINSTRID_VMRESUME ((VMXINSTRID_VALID) \| 51)
2461	/** @} */
2462
2463
2464	/** @name IDT-vectoring information.
2465	* @{
2466	*/
2467	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
2468	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
2469	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2470	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
2471
2472	/** Construct an IDT-vectoring information field from an VM-entry interruption
2473	* information field (same except that bit 12 is reserved). */
2474	#define VMX_EXIT_IDT_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
2475
2476	/** Bit fields for IDT-vectoring information. */
2477	/** The IDT-vectoring info vector. */
2478	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
2479	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2480	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
2481	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
2482	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
2483	/** Whether the event has an error code. */
2484	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
2485	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2486	/** Bit 12 is undefined. */
2487	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
2488	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
2489	/** Bits 13:30 is reserved (MBZ). */
2490	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
2491	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2492	/** Whether this IDT-vectoring info is valid. */
2493	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
2494	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
2495	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
2496	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
2497	/** @} */
2498
2499
2500	/** @name IDT-vectoring information vector types.
2501	* @{
2502	*/
2503	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
2504	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
2505	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
2506	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
2507	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
2508	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
2509	#define VMX_IDT_VECTORING_INFO_TYPE_SW_UNUSED 7
2510	/** @} */
2511
2512
2513	/** @name TPR threshold.
2514	* @{ */
2515	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
2516	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
2517
2518	/** Bit fields for TPR threshold. */
2519	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
2520	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
2521	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
2522	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
2523	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
2524	(TPR, RSVD_4_31));
2525	/** @} */
2526
2527
2528	/** @name Guest-activity states.
2529	* @{
2530	*/
2531	/** The logical processor is active. */
2532	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
2533	/** The logical processor is inactive, because it executed a HLT instruction. */
2534	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
2535	/** The logical processor is inactive, because of a triple fault or other serious error. */
2536	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
2537	/** The logical processor is inactive, because it's waiting for a startup-IPI */
2538	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
2539	/** @} */
2540
2541
2542	/** @name Guest-interruptibility states.
2543	* @{
2544	*/
2545	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
2546	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
2547	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
2548	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
2549	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
2550
2551	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
2552	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
2553	/** @} */
2554
2555
2556	/** @name Exit qualification for Mov DRx.
2557	* @{
2558	*/
2559	/** 0-2: Debug register number */
2560	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
2561	/** 3: Reserved; cleared to 0. */
2562	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
2563	/** 4: Direction of move (0 = write, 1 = read) */
2564	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
2565	/** 5-7: Reserved; cleared to 0. */
2566	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
2567	/** 8-11: General purpose register number. */
2568	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
2569	/** Rest: reserved. */
2570	/** @} */
2571
2572
2573	/** @name Exit qualification for debug exceptions types.
2574	* @{
2575	*/
2576	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
2577	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
2578	/** @} */
2579
2580
2581	/** @name Exit qualification for control-register accesses.
2582	* @{
2583	*/
2584	/** 0-3: Control register number (0 for CLTS & LMSW) */
2585	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
2586	/** 4-5: Access type. */
2587	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
2588	/** 6: LMSW operand type */
2589	#define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1)
2590	/** 7: Reserved; cleared to 0. */
2591	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
2592	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
2593	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
2594	/** 12-15: Reserved; cleared to 0. */
2595	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
2596	/** 16-31: LMSW source data (else 0). */
2597	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
2598	/* Rest: reserved. */
2599	/** @} */
2600
2601
2602	/** @name Exit qualification for control-register access types.
2603	* @{
2604	*/
2605	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
2606	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
2607	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
2608	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
2609	/** @} */
2610
2611
2612	/** @name Exit qualification for task switch.
2613	* @{
2614	*/
2615	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
2616	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
2617	/** Task switch caused by a call instruction. */
2618	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
2619	/** Task switch caused by an iret instruction. */
2620	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
2621	/** Task switch caused by a jmp instruction. */
2622	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
2623	/** Task switch caused by an interrupt gate. */
2624	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
2625	/** @} */
2626
2627
2628	/** @name Exit qualification for EPT violations.
2629	* @{
2630	*/
2631	/** Set if the violation was caused by a data read. */
2632	#define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)
2633	/** Set if the violation was caused by a data write. */
2634	#define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)
2635	/** Set if the violation was caused by an instruction fetch. */
2636	#define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)
2637	/** AND of the present bit of all EPT structures. */
2638	#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)
2639	/** AND of the write bit of all EPT structures. */
2640	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)
2641	/** AND of the execute bit of all EPT structures. */
2642	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)
2643	/** Set if the guest linear address field contains the faulting address. */
2644	#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)
2645	/** If bit 7 is one: (reserved otherwise)
2646	* 1 - violation due to physical address access.
2647	* 0 - violation caused by page walk or access/dirty bit updates
2648	*/
2649	#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)
2650	/** @} */
2651
2652
2653	/** @name Exit qualification for I/O instructions.
2654	* @{
2655	*/
2656	/** 0-2: IO operation width. */
2657	#define VMX_EXIT_QUAL_IO_WIDTH(a) ((a) & 7)
2658	/** 3: IO operation direction. */
2659	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
2660	/** 4: String IO operation (INS / OUTS). */
2661	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
2662	/** 5: Repeated IO operation. */
2663	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
2664	/** 6: Operand encoding. */
2665	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
2666	/** 16-31: IO Port (0-0xffff). */
2667	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
2668	/* Rest reserved. */
2669	/** @} */
2670
2671
2672	/** @name Exit qualification for I/O instruction types.
2673	* @{
2674	*/
2675	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
2676	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
2677	/** @} */
2678
2679
2680	/** @name Exit qualification for I/O instruction encoding.
2681	* @{
2682	*/
2683	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
2684	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
2685	/** @} */
2686
2687
2688	/** @name Exit qualification for APIC-access VM-exits from linear and
2689	* guest-physical accesses.
2690	* @{
2691	*/
2692	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
2693	* access within the APIC page. */
2694	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
2695	/** 12-15: Access type. */
2696	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
2697	/* Rest reserved. */
2698	/** @} */
2699
2700
2701	/** @name Exit qualification for linear address APIC-access types.
2702	* @{
2703	*/
2704	/** Linear read access. */
2705	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
2706	/** Linear write access. */
2707	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
2708	/** Linear instruction fetch access. */
2709	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
2710	/** Linear read/write access during event delivery. */
2711	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
2712	/** Physical read/write access during event delivery. */
2713	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
2714	/** Physical access for an instruction fetch or during instruction execution. */
2715	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
2716	/** @} */
2717
2718
2719	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
2720	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2721	* @{
2722	*/
2723	/** Address calculation scaling field (powers of two). */
2724	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
2725	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2726	/** Bits 2 thru 6 are undefined. */
2727	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
2728	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
2729	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2730	* @remarks anyone's guess why this is a 3 bit field... */
2731	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
2732	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2733	/** Bit 10 is defined as zero. */
2734	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
2735	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
2736	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
2737	* for exits from 64-bit code as the operand size there is fixed. */
2738	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
2739	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
2740	/** Bits 12 thru 14 are undefined. */
2741	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
2742	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
2743	/** Applicable segment register (X86_SREG_XXX values). */
2744	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
2745	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2746	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2747	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
2748	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2749	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2750	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2751	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2752	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2753	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
2754	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2755	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2756	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
2757	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2758	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
2759	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
2760	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2761	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
2762	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
2763	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
2764	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
2765	/** Bits 30 & 31 are undefined. */
2766	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
2767	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2768	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2769	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
2770	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2771	/** @} */
2772
2773
2774	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
2775	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
2776	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
2777	* @{
2778	*/
2779	/** Address calculation scaling field (powers of two). */
2780	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
2781	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
2782	/** Bit 2 is undefined. */
2783	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
2784	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
2785	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
2786	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
2787	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
2788	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
2789	* @remarks anyone's guess why this is a 3 bit field... */
2790	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
2791	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
2792	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
2793	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
2794	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
2795	/** Bits 11 thru 14 are undefined. */
2796	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
2797	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
2798	/** Applicable segment register (X86_SREG_XXX values). */
2799	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
2800	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
2801	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
2802	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
2803	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
2804	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
2805	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
2806	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
2807	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
2808	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
2809	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
2810	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
2811	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
2812	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
2813	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
2814	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
2815	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
2816	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
2817	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
2818	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
2819	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
2820	/** Bits 30 & 31 are undefined. */
2821	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
2822	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
2823	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
2824	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
2825	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
2826	/** @} */
2827
2828
2829	/** @name Format of Pending-Debug-Exceptions.
2830	* Bits 4-11, 13, 15 and 17-63 are reserved.
2831	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
2832	* possibly valid here but not in DR6.
2833	* @{
2834	*/
2835	/** Hardware breakpoint 0 was met. */
2836	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
2837	/** Hardware breakpoint 1 was met. */
2838	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
2839	/** Hardware breakpoint 2 was met. */
2840	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
2841	/** Hardware breakpoint 3 was met. */
2842	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
2843	/** At least one data or IO breakpoint was hit. */
2844	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
2845	/** A debug exception would have been triggered by single-step execution mode. */
2846	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
2847	/** A debug exception occurred inside an RTM region. */
2848	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
2849	/** Mask of valid bits. */
2850	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
2851	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
2852	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
2853	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
2854	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
2855	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
2856	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
2857	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
2858	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
2859	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
2860	/** Bit fields for Pending debug exceptions. */
2861	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
2862	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
2863	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
2864	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
2865	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
2866	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
2867	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
2868	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
2869	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
2870	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
2871	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
2872	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
2873	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
2874	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
2875	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
2876	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
2877	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
2878	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
2879	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
2880	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
2881	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
2882	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
2883	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
2884	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
2885	/** @} */
2886
2887
2888	/** @name VMCS field encoding.
2889	* @{ */
2890	typedef union
2891	{
2892	struct
2893	{
2894	/** The access type; 0=full, 1=high of 64-bit fields. */
2895	uint32_t fAccessType : 1;
2896	/** The index. */
2897	uint32_t u8Index : 8;
2898	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
2899	uint32_t u2Type : 2;
2900	/** Reserved (MBZ). */
2901	uint32_t u1Reserved0 : 1;
2902	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
2903	uint32_t u2Width : 2;
2904	/** Reserved (MBZ). */
2905	uint32_t u18Reserved0 : 18;
2906	} n;
2907	/* The unsigned integer view. */
2908	uint32_t u;
2909	} VMXVMCSFIELDENC;
2910	AssertCompileSize(VMXVMCSFIELDENC, 4);
2911	/** Pointer to a VMCS field encoding. */
2912	typedef VMXVMCSFIELDENC *PVMXVMCSFIELDENC;
2913	/** Pointer to a const VMCS field encoding. */
2914	typedef const VMXVMCSFIELDENC *PCVMXVMCSFIELDENC;
2915
2916	/** VMCS field encoding type: Full. */
2917	#define VMX_VMCS_ENC_ACCESS_TYPE_FULL 0
2918	/** VMCS field encoding type: High. */
2919	#define VMX_VMCS_ENC_ACCESS_TYPE_HIGH 1
2920
2921	/** VMCS field encoding type: Control. */
2922	#define VMX_VMCS_ENC_TYPE_CONTROL 0
2923	/** VMCS field encoding type: VM-exit information / read-only fields. */
2924	#define VMX_VMCS_ENC_TYPE_VMEXIT_INFO 1
2925	/** VMCS field encoding type: Guest-state. */
2926	#define VMX_VMCS_ENC_TYPE_GUEST_STATE 2
2927	/** VMCS field encoding type: Host-state. */
2928	#define VMX_VMCS_ENC_TYPE_HOST_STATE 3
2929
2930	/** VMCS field encoding width: 16-bit. */
2931	#define VMX_VMCS_ENC_WIDTH_16BIT 0
2932	/** VMCS field encoding width: 64-bit. */
2933	#define VMX_VMCS_ENC_WIDTH_64BIT 1
2934	/** VMCS field encoding width: 32-bit. */
2935	#define VMX_VMCS_ENC_WIDTH_32BIT 2
2936	/** VMCS field encoding width: Natural width. */
2937	#define VMX_VMCS_ENC_WIDTH_NATURAL 3
2938
2939	/** Bits fields for VMCS field encoding. */
2940	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_SHIFT 0
2941	#define VMX_BF_VMCS_ENC_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2942	#define VMX_BF_VMCS_ENC_INDEX_SHIFT 1
2943	#define VMX_BF_VMCS_ENC_INDEX_MASK UINT32_C(0x000003fe)
2944	#define VMX_BF_VMCS_ENC_TYPE_SHIFT 10
2945	#define VMX_BF_VMCS_ENC_TYPE_MASK UINT32_C(0x00000c00)
2946	#define VMX_BF_VMCS_ENC_RSVD_12_SHIFT 12
2947	#define VMX_BF_VMCS_ENC_RSVD_12_MASK UINT32_C(0x00001000)
2948	#define VMX_BF_VMCS_ENC_WIDTH_SHIFT 13
2949	#define VMX_BF_VMCS_ENC_WIDTH_MASK UINT32_C(0x00006000)
2950	#define VMX_BF_VMCS_ENC_RSVD_15_31_SHIFT 15
2951	#define VMX_BF_VMCS_ENC_RSVD_15_31_MASK UINT32_C(0xffff8000)
2952	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENC_, UINT32_C(0), UINT32_MAX,
2953	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2954	/** @} */
2955
2956
2957	/** @defgroup grp_hm_vmx_virt VMX virtualization.
2958	* @{
2959	*/
2960
2961	/** @name Virtual VMX MSR - Miscellaneous data.
2962	* @{ */
2963	/** Number of CR3-target values supported. */
2964	#define VMX_V_CR3_TARGET_COUNT 4
2965	/** Activity states supported. */
2966	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
2967	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
2968	#define VMX_V_PREEMPT_TIMER_SHIFT 5
2969	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
2970	#define VMX_V_AUTOMSR_COUNT_MAX 0
2971	/** SMM MSEG revision ID. */
2972	#define VMX_V_MSEG_REV_ID 0
2973	/** @} */
2974
2975	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS state.
2976	* @{ */
2977	/** VMCS state clear. */
2978	#define VMX_V_VMCS_STATE_CLEAR RT_BIT(1)
2979	/** VMCS state launched. */
2980	#define VMX_V_VMCS_STATE_LAUNCHED RT_BIT(2)
2981	/** @} */
2982
2983	/** CR0 bits set here must always be set when in VMX operation. */
2984	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
2985	/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
2986	#define VMX_V_CR0_FIXED0_UX (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE \| X86_CR0_PG))
2987	/** CR4 bits set here must always be set when in VMX operation. */
2988	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
2989
2990	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
2991	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
2992	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x1d000001)
2993	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
2994
2995	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
2996	* complications when teleporation may be implemented). */
2997	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
2998	/** The size of the virtual VMCS region (in pages). */
2999	#define VMX_V_VMCS_PAGES 1
3000
3001	/** The size of the Virtual-APIC page (in bytes). */
3002	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3003	/** The size of the Virtual-APIC page (in pages). */
3004	#define VMX_V_VIRT_APIC_PAGES 1
3005
3006	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3007	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3008	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3009	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3010
3011	/** The size of the auto-load/store MSR area (in bytes). */
3012	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3013	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3014	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3015	/** The size of the auto-load/store MSR area (in pages). */
3016	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3017
3018	/** The highest index value used for supported virtual VMCS field encoding. */
3019	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCS_ENC_INDEX)
3020
3021	/**
3022	* Virtual VM-Exit information.
3023	*
3024	* This is a convenience structure that bundles some VM-exit information related
3025	* fields together.
3026	*/
3027	typedef struct
3028	{
3029	/** The VM-exit reason. */
3030	uint32_t uReason;
3031	/** The VM-exit instruction length. */
3032	uint32_t cbInstr;
3033	/** The VM-exit instruction information. */
3034	VMXEXITINSTRINFO InstrInfo;
3035	/** Padding. */
3036	uint32_t u32Padding0;
3037
3038	/** The VM-exit qualification field. */
3039	uint64_t u64Qual;
3040	/** The guest-linear address field. */
3041	uint64_t u64GuestLinearAddr;
3042	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3043	* instruction VM-exit. */
3044	RTGCPTR GCPtrEffAddr;
3045
3046	/** The VM-exit instruction ID. */
3047	VMXINSTRID uInstrId;
3048	} VMXVEXITINFO;
3049	/** Pointer to the VMXVEXITINFO struct. */
3050	typedef VMXVEXITINFO *PVMXVEXITINFO;
3051	/** Pointer to a const VMXVEXITINFO struct. */
3052	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3053
3054	/**
3055	* Virtual VMCS.
3056	* This is our custom format and merged into the actual VMCS (/shadow) when we
3057	* execute nested-guest code using hardware-assisted VMX.
3058	*
3059	* The first 8 bytes are as per Intel spec. 24.2 "Format of the VMCS Region".
3060	*
3061	* The offset and size of the VMCS state field (fVmcsState) is also fixed (not by
3062	* Intel but for our own requirements) as we use it to offset into guest memory.
3063	*
3064	* We always treat natural-width fields as 64-bit in our implementation since
3065	* it's easier, allows for teleporation in the future and does not affect guest
3066	* software.
3067	*
3068	* Although the guest is supposed to access the VMCS only through the execution of
3069	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3070	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3071	* for teleportation (when implemented) any newly added fields should be added to
3072	* the appropriate reserved sections or at the end of the structure.
3073	*/
3074	#pragma pack(1)
3075	typedef struct
3076	{
3077	/** 0x0 - VMX VMCS revision identifier. */
3078	VMXVMCSREVID u32VmcsRevId;
3079	/** 0x4 - VMX-abort indicator. */
3080	uint32_t u32VmxAbortId;
3081	/** 0x8 - VMCS state, see VMX_V_VMCS_STATE_XXX. */
3082	uint8_t fVmcsState;
3083	/** 0x9 - Reserved for future. */
3084	uint8_t au8Padding0[3];
3085	/** 0xc - Reserved for future. */
3086	uint32_t au32Reserved0[7];
3087
3088	/** @name 16-bit control fields.
3089	* @{ */
3090	/** 0x28 - Virtual processor ID. */
3091	uint16_t u16Vpid;
3092	/** 0x2a - Posted interrupt notify vector. */
3093	uint16_t u16PostIntNotifyVector;
3094	/** 0x2c - EPTP index. */
3095	uint16_t u16EptpIndex;
3096	/** 0x2e - Reserved for future. */
3097	uint16_t au16Reserved0[8];
3098	/** @} */
3099
3100	/** @name 16-bit Guest-state fields.
3101	* Order of [ES..GS] is important, must match X86_SREG_XXX.
3102	* @{ */
3103	/** 0x3e - Guest ES selector. */
3104	RTSEL GuestEs;
3105	/** 0x40 - Guest ES selector. */
3106	RTSEL GuestCs;
3107	/** 0x42 - Guest ES selector. */
3108	RTSEL GuestSs;
3109	/** 0x44 - Guest ES selector. */
3110	RTSEL GuestDs;
3111	/** 0x46 - Guest ES selector. */
3112	RTSEL GuestFs;
3113	/** 0x48 - Guest ES selector. */
3114	RTSEL GuestGs;
3115	/** 0x4a - Guest LDTR selector. */
3116	RTSEL GuestLdtr;
3117	/** 0x4c - Guest TR selector. */
3118	RTSEL GuestTr;
3119	/** 0x4e - Guest interrupt status (virtual-interrupt delivery). */
3120	uint16_t u16GuestIntStatus;
3121	/** 0x50 - PML index. */
3122	uint16_t u16PmlIndex;
3123	/** 0x52 - Reserved for future. */
3124	uint16_t au16Reserved1[8];
3125	/** @} */
3126
3127	/** @name 16-bit Host-state fields.
3128	* @{ */
3129	/** 0x62 - Host ES selector. */
3130	RTSEL HostEs;
3131	/** 0x64 - Host CS selector. */
3132	RTSEL HostCs;
3133	/** 0x66 - Host SS selector. */
3134	RTSEL HostSs;
3135	/** 0x68 - Host DS selector. */
3136	RTSEL HostDs;
3137	/** 0x6a - Host FS selector. */
3138	RTSEL HostFs;
3139	/** 0x6c - Host GS selector. */
3140	RTSEL HostGs;
3141	/** 0x6e - Host TR selector. */
3142	RTSEL HostTr;
3143	/** 0x70 - Reserved for future. */
3144	uint16_t au16Reserved2[10];
3145	/** @} */
3146
3147	/** @name 32-bit Control fields.
3148	* @{ */
3149	/** 0x84 - Pin-based VM-execution controls. */
3150	uint32_t u32PinCtls;
3151	/** 0x88 - Processor-based VM-execution controls. */
3152	uint32_t u32ProcCtls;
3153	/** 0x8c - Exception bitmap. */
3154	uint32_t u32XcptBitmap;
3155	/** 0x90 - Page-fault exception error mask. */
3156	uint32_t u32XcptPFMask;
3157	/** 0x94 - Page-fault exception error match. */
3158	uint32_t u32XcptPFMatch;
3159	/** 0x98 - CR3-target count. */
3160	uint32_t u32Cr3TargetCount;
3161	/** 0x9c - VM-exit controls. */
3162	uint32_t u32ExitCtls;
3163	/** 0xa0 - VM-exit MSR store count. */
3164	uint32_t u32ExitMsrStoreCount;
3165	/** 0xa4 - VM-exit MSR load count. */
3166	uint32_t u32ExitMsrLoadCount;
3167	/** 0xa8 - VM-entry controls. */
3168	uint32_t u32EntryCtls;
3169	/** 0xac - VM-entry MSR load count. */
3170	uint32_t u32EntryMsrLoadCount;
3171	/** 0xb0 - VM-entry interruption information. */
3172	uint32_t u32EntryIntInfo;
3173	/** 0xb4 - VM-entry exception error code. */
3174	uint32_t u32EntryXcptErrCode;
3175	/** 0xb8 - VM-entry instruction length. */
3176	uint32_t u32EntryInstrLen;
3177	/** 0xbc - TPR-threshold. */
3178	uint32_t u32TprThreshold;
3179	/** 0xc0 - Secondary-processor based VM-execution controls. */
3180	uint32_t u32ProcCtls2;
3181	/** 0xc4 - Pause-loop exiting Gap. */
3182	uint32_t u32PleGap;
3183	/** 0xc8 - Pause-loop exiting Window. */
3184	uint32_t u32PleWindow;
3185	/** 0xcc - Reserved for future. */
3186	uint32_t au32Reserved1[8];
3187	/** @} */
3188
3189	/** @name 32-bit Read-only Data fields.
3190	* @{ */
3191	/** 0xec - VM-instruction error. */
3192	uint32_t u32RoVmInstrError;
3193	/** 0xf0 - VM-exit reason. */
3194	uint32_t u32RoExitReason;
3195	/** 0xf4 - VM-exit interruption information. */
3196	uint32_t u32RoExitIntInfo;
3197	/** 0xf8 - VM-exit interruption error code. */
3198	uint32_t u32RoExitErrCode;
3199	/** 0xfc - IDT-vectoring information. */
3200	uint32_t u32RoIdtVectoringInfo;
3201	/** 0x100 - IDT-vectoring error code. */
3202	uint32_t u32RoIdtVectoringErrCode;
3203	/** 0x104 - VM-exit instruction length. */
3204	uint32_t u32RoExitInstrLen;
3205	/** 0x108 - VM-exit instruction information. */
3206	uint32_t u32RoExitInstrInfo;
3207	/** 0x10c - Reserved for future. */
3208	uint32_t au32RoReserved2[8];
3209	/** @} */
3210
3211	/** @name 32-bit Guest-state fields.
3212	* Order of [ES..GS] limit and attributes are important, must match X86_SREG_XXX.
3213	* @{ */
3214	/** 0x12c - Guest ES limit. */
3215	uint32_t u32GuestEsLimit;
3216	/** 0x130 - Guest CS limit. */
3217	uint32_t u32GuestCsLimit;
3218	/** 0x134 - Guest SS limit. */
3219	uint32_t u32GuestSsLimit;
3220	/** 0x138 - Guest DS limit. */
3221	uint32_t u32GuestDsLimit;
3222	/** 0x13c - Guest FS limit. */
3223	uint32_t u32GuestFsLimit;
3224	/** 0x140 - Guest GS limit. */
3225	uint32_t u32GuestGsLimit;
3226	/** 0x144 - Guest LDTR limit. */
3227	uint32_t u32GuestLdtrLimit;
3228	/** 0x148 - Guest TR limit. */
3229	uint32_t u32GuestTrLimit;
3230	/** 0x14c - Guest GDTR limit. */
3231	uint32_t u32GuestGdtrLimit;
3232	/** 0x150 - Guest IDTR limit. */
3233	uint32_t u32GuestIdtrLimit;
3234	/** 0x154 - Guest ES attributes. */
3235	uint32_t u32GuestEsAttr;
3236	/** 0x158 - Guest CS attributes. */
3237	uint32_t u32GuestCsAttr;
3238	/** 0x15c - Guest SS attributes. */
3239	uint32_t u32GuestSsAttr;
3240	/** 0x160 - Guest DS attributes. */
3241	uint32_t u32GuestDsAttr;
3242	/** 0x164 - Guest FS attributes. */
3243	uint32_t u32GuestFsAttr;
3244	/** 0x168 - Guest GS attributes. */
3245	uint32_t u32GuestGsAttr;
3246	/** 0x16c - Guest LDTR attributes. */
3247	uint32_t u32GuestLdtrAttr;
3248	/** 0x170 - Guest TR attributes. */
3249	uint32_t u32GuestTrAttr;
3250	/** 0x174 - Guest interruptibility state. */
3251	uint32_t u32GuestIntrState;
3252	/** 0x178 - Guest activity state. */
3253	uint32_t u32GuestActivityState;
3254	/** 0x17c - Guest SMBASE. */
3255	uint32_t u32GuestSmBase;
3256	/** 0x180 - Guest SYSENTER CS. */
3257	uint32_t u32GuestSysenterCS;
3258	/** 0x184 - Preemption timer value. */
3259	uint32_t u32PreemptTimer;
3260	/** 0x188 - Reserved for future. */
3261	uint32_t au32Reserved3[8];
3262	/** @} */
3263
3264	/** @name 32-bit Host-state fields.
3265	* @{ */
3266	/** 0x1a8 - Host SYSENTER CS. */
3267	uint32_t u32HostSysenterCs;
3268	/** 0x1ac - Reserved for future. */
3269	uint32_t au32Reserved4[11];
3270	/** @} */
3271
3272	/** @name 64-bit Control fields.
3273	* @{ */
3274	/** 0x1d8 - I/O bitmap A address. */
3275	RTUINT64U u64AddrIoBitmapA;
3276	/** 0x1e0 - I/O bitmap B address. */
3277	RTUINT64U u64AddrIoBitmapB;
3278	/** 0x1e8 - MSR bitmap address. */
3279	RTUINT64U u64AddrMsrBitmap;
3280	/** 0x1f0 - VM-exit MSR-store area address. */
3281	RTUINT64U u64AddrExitMsrStore;
3282	/** 0x1f8 - VM-exit MSR-load area address. */
3283	RTUINT64U u64AddrExitMsrLoad;
3284	/** 0x200 - VM-entry MSR-load area address. */
3285	RTUINT64U u64AddrEntryMsrLoad;
3286	/** 0x208 - Executive-VMCS pointer. */
3287	RTUINT64U u64ExecVmcsPtr;
3288	/** 0x210 - PML address. */
3289	RTUINT64U u64AddrPml;
3290	/** 0x218 - TSC offset. */
3291	RTUINT64U u64TscOffset;
3292	/** 0x220 - Virtual-APIC address. */
3293	RTUINT64U u64AddrVirtApic;
3294	/** 0x228 - APIC-access address. */
3295	RTUINT64U u64AddrApicAccess;
3296	/** 0x230 - Posted-interrupt descriptor address. */
3297	RTUINT64U u64AddrPostedIntDesc;
3298	/** 0x238 - VM-functions control. */
3299	RTUINT64U u64VmFuncCtls;
3300	/** 0x240 - EPTP pointer. */
3301	RTUINT64U u64EptpPtr;
3302	/** 0x248 - EOI-exit bitmap 0. */
3303	RTUINT64U u64EoiExitBitmap0;
3304	/** 0x250 - EOI-exit bitmap 1. */
3305	RTUINT64U u64EoiExitBitmap1;
3306	/** 0x258 - EOI-exit bitmap 2. */
3307	RTUINT64U u64EoiExitBitmap2;
3308	/** 0x260 - EOI-exit bitmap 3. */
3309	RTUINT64U u64EoiExitBitmap3;
3310	/** 0x268 - EPTP-list address. */
3311	RTUINT64U u64AddrEptpList;
3312	/** 0x270 - VMREAD-bitmap address. */
3313	RTUINT64U u64AddrVmreadBitmap;
3314	/** 0x278 - VMWRITE-bitmap address. */
3315	RTUINT64U u64AddrVmwriteBitmap;
3316	/** 0x280 - Virtualization-exception information address. */
3317	RTUINT64U u64AddrXcptVeInfo;
3318	/** 0x288 - XSS-exiting bitmap address. */
3319	RTUINT64U u64AddrXssBitmap;
3320	/** 0x290 - ENCLS-exiting bitmap address. */
3321	RTUINT64U u64AddrEnclsBitmap;
3322	/** 0x298 - TSC multiplier. */
3323	RTUINT64U u64TscMultiplier;
3324	/** 0x2a0 - Reserved for future. */
3325	RTUINT64U au64Reserved0[16];
3326	/** @} */
3327
3328	/** @name 64-bit Read-only Data fields.
3329	* @{ */
3330	/** 0x320 - Guest-physical address. */
3331	RTUINT64U u64GuestPhysAddr;
3332	/** 0x328 - Reserved for future. */
3333	RTUINT64U au64Reserved1[8];
3334	/** @} */
3335
3336	/** @name 64-bit Guest-state fields.
3337	* @{ */
3338	/** 0x368 - VMCS link pointer. */
3339	RTUINT64U u64VmcsLinkPtr;
3340	/** 0x370 - Guest debug-control MSR. */
3341	RTUINT64U u64GuestDebugCtlMsr;
3342	/** 0x378 - Guest PAT MSR. */
3343	RTUINT64U u64GuestPatMsr;
3344	/** 0x380 - Guest EFER MSR. */
3345	RTUINT64U u64GuestEferMsr;
3346	/** 0x388 - Guest global performance-control MSR. */
3347	RTUINT64U u64GuestPerfGlobalCtlMsr;
3348	/** 0x390 - Guest PDPTE 0. */
3349	RTUINT64U u64GuestPdpte0;
3350	/** 0x398 - Guest PDPTE 0. */
3351	RTUINT64U u64GuestPdpte1;
3352	/** 0x3a0 - Guest PDPTE 1. */
3353	RTUINT64U u64GuestPdpte2;
3354	/** 0x3a8 - Guest PDPTE 2. */
3355	RTUINT64U u64GuestPdpte3;
3356	/** 0x3b0 - Guest Bounds-config MSR (Intel MPX - Memory Protection Extensions). */
3357	RTUINT64U u64GuestBndcfgsMsr;
3358	/** 0x3b8 - Reserved for future. */
3359	RTUINT64U au64Reserved2[16];
3360	/** @} */
3361
3362	/** @name 64-bit Host-state Fields.
3363	* @{ */
3364	/** 0x438 - Host PAT MSR. */
3365	RTUINT64U u64HostPatMsr;
3366	/** 0x440 - Host EFER MSR. */
3367	RTUINT64U u64HostEferMsr;
3368	/** 0x448 - Host global performance-control MSR. */
3369	RTUINT64U u64HostPerfGlobalCtlMsr;
3370	/** 0x450 - Reserved for future. */
3371	RTUINT64U au64Reserved3[16];
3372	/** @} */
3373
3374	/** @name Natural-width Control fields.
3375	* @{ */
3376	/** 0x4d0 - CR0 guest/host Mask. */
3377	RTUINT64U u64Cr0Mask;
3378	/** 0x4d8 - CR4 guest/host Mask. */
3379	RTUINT64U u64Cr4Mask;
3380	/** 0x4e0 - CR0 read shadow. */
3381	RTUINT64U u64Cr0ReadShadow;
3382	/** 0x4e8 - CR4 read shadow. */
3383	RTUINT64U u64Cr4ReadShadow;
3384	/** 0x4f0 - CR3-target value 0. */
3385	RTUINT64U u64Cr3Target0;
3386	/** 0x4f8 - CR3-target value 1. */
3387	RTUINT64U u64Cr3Target1;
3388	/** 0x500 - CR3-target value 2. */
3389	RTUINT64U u64Cr3Target2;
3390	/** 0x508 - CR3-target value 3. */
3391	RTUINT64U u64Cr3Target3;
3392	/** 0x510 - Reserved for future. */
3393	RTUINT64U au64Reserved4[32];
3394	/** @} */
3395
3396	/** @name Natural-width Read-only Data fields. */
3397	/** 0x610 - Exit qualification. */
3398	RTUINT64U u64ExitQual;
3399	/** 0x618 - I/O RCX. */
3400	RTUINT64U u64IoRcx;
3401	/** 0x620 - I/O RSI. */
3402	RTUINT64U u64IoRsi;
3403	/** 0x628 - I/O RDI. */
3404	RTUINT64U u64IoRdi;
3405	/** 0x630 - I/O RIP. */
3406	RTUINT64U u64IoRip;
3407	/** 0x638 - Guest-linear address. */
3408	RTUINT64U u64GuestLinearAddr;
3409	/** 0x640 - Reserved for future. */
3410	RTUINT64U au64Reserved5[16];
3411	/** @} */
3412
3413	/** @name Natural-width Guest-state Fields.
3414	* Order of [ES..GS] base is important, must match X86_SREG_XXX.
3415	* @{ */
3416	/** 0x6c0 - Guest CR0. */
3417	RTUINT64U u64GuestCr0;
3418	/** 0x6c8 - Guest CR3. */
3419	RTUINT64U u64GuestCr3;
3420	/** 0x6d0 - Guest CR4. */
3421	RTUINT64U u64GuestCr4;
3422	/** 0x6d8 - Guest ES base. */
3423	RTUINT64U u64GuestEsBase;
3424	/** 0x6e0 - Guest CS base. */
3425	RTUINT64U u64GuestCsBase;
3426	/** 0x6e8 - Guest SS base. */
3427	RTUINT64U u64GuestSsBase;
3428	/** 0x6f0 - Guest DS base. */
3429	RTUINT64U u64GuestDsBase;
3430	/** 0x6f8 - Guest FS base. */
3431	RTUINT64U u64GuestFsBase;
3432	/** 0x700 - Guest GS base. */
3433	RTUINT64U u64GuestGsBase;
3434	/** 0x708 - Guest LDTR base. */
3435	RTUINT64U u64GuestLdtrBase;
3436	/** 0x710 - Guest TR base. */
3437	RTUINT64U u64GuestTrBase;
3438	/** 0x718 - Guest GDTR base. */
3439	RTUINT64U u64GuestGdtrBase;
3440	/** 0x720 - Guest IDTR base. */
3441	RTUINT64U u64GuestIdtrBase;
3442	/** 0x728 - Guest DR7. */
3443	RTUINT64U u64GuestDr7;
3444	/** 0x730 - Guest RSP. */
3445	RTUINT64U u64GuestRsp;
3446	/** 0x738 - Guest RIP. */
3447	RTUINT64U u64GuestRip;
3448	/** 0x740 - Guest RFLAGS. */
3449	RTUINT64U u64GuestRFlags;
3450	/** 0x748 - Guest pending debug exception. */
3451	RTUINT64U u64GuestPendingDbgXcpt;
3452	/** 0x750 - Guest SYSENTER ESP. */
3453	RTUINT64U u64GuestSysenterEsp;
3454	/** 0x758 - Guest SYSENTER EIP. */
3455	RTUINT64U u64GuestSysenterEip;
3456	/** 0x760 - Reserved for future. */
3457	RTUINT64U au64Reserved6[32];
3458	/** @} */
3459
3460	/** @name Natural-width Host-state fields.
3461	* @{ */
3462	/** 0x860 - Host CR0. */
3463	RTUINT64U u64HostCr0;
3464	/** 0x868 - Host CR3. */
3465	RTUINT64U u64HostCr3;
3466	/** 0x870 - Host CR4. */
3467	RTUINT64U u64HostCr4;
3468	/** 0x878 - Host FS base. */
3469	RTUINT64U u64HostFsBase;
3470	/** 0x880 - Host GS base. */
3471	RTUINT64U u64HostGsBase;
3472	/** 0x888 - Host TR base. */
3473	RTUINT64U u64HostTrBase;
3474	/** 0x890 - Host GDTR base. */
3475	RTUINT64U u64HostGdtrBase;
3476	/** 0x898 - Host IDTR base. */
3477	RTUINT64U u64HostIdtrBase;
3478	/** 0x8a0 - Host SYSENTER ESP base. */
3479	RTUINT64U u64HostSysenterEsp;
3480	/** 0x8a8 - Host SYSENTER ESP base. */
3481	RTUINT64U u64HostSysenterEip;
3482	/** 0x8b0 - Host RSP. */
3483	RTUINT64U u64HostRsp;
3484	/** 0x8b8 - Host RIP. */
3485	RTUINT64U u64HostRip;
3486	/** 0x8c0 - Reserved for future. */
3487	RTUINT64U au64Reserved7[32];
3488	/** @} */
3489
3490	/** 0x9c0 - Padding. */
3491	uint8_t abPadding[X86_PAGE_4K_SIZE - 0x9c0];
3492	} VMXVVMCS;
3493	#pragma pack()
3494	/** Pointer to the VMXVVMCS struct. */
3495	typedef VMXVVMCS *PVMXVVMCS;
3496	/** Pointer to a const VMXVVMCS struct. */
3497	typedef const VMXVVMCS *PCVMXVVMCS;
3498	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
3499	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
3500	AssertCompileMemberOffset(VMXVVMCS, u32VmxAbortId, 0x004);
3501	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
3502	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x028);
3503	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x03e);
3504	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x062);
3505	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x084);
3506	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x0ec);
3507	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x12c);
3508	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x1a8);
3509	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x1d8);
3510	AssertCompileMemberOffset(VMXVVMCS, u64GuestPhysAddr, 0x320);
3511	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x368);
3512	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x438);
3513	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x4d0);
3514	AssertCompileMemberOffset(VMXVVMCS, u64ExitQual, 0x610);
3515	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x6c0);
3516	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x860);
3517	/** @} */
3518
3519	/**
3520	* Virtual VMX-instruction and VM-exit diagnostics.
3521	*
3522	* These are not the same as VM instruction errors that are enumerated in the Intel
3523	* spec. These are purely internal, fine-grained definitions used for diagnostic
3524	* purposes and are not reported to guest software under the VM-instruction error
3525	* field in its VMCS.
3526	*
3527	* @note Members of this enum are used as array indices, so no gaps are allowed.
3528	* Please update g_apszVmxInstrDiagDesc when you add new fields to this
3529	* enum.
3530	*/
3531	typedef enum
3532	{
3533	/* Internal processing errors. */
3534	kVmxVDiag_None = 0,
3535	kVmxVDiag_Ipe_1,
3536	kVmxVDiag_Ipe_2,
3537	kVmxVDiag_Ipe_3,
3538	kVmxVDiag_Ipe_4,
3539	kVmxVDiag_Ipe_5,
3540	kVmxVDiag_Ipe_6,
3541	kVmxVDiag_Ipe_7,
3542	kVmxVDiag_Ipe_8,
3543	kVmxVDiag_Ipe_9,
3544	kVmxVDiag_Ipe_10,
3545	kVmxVDiag_Ipe_11,
3546	kVmxVDiag_Ipe_12,
3547	kVmxVDiag_Ipe_13,
3548	kVmxVDiag_Ipe_14,
3549	kVmxVDiag_Ipe_15,
3550	kVmxVDiag_Ipe_16,
3551	/* VMXON. */
3552	kVmxVDiag_Vmxon_A20M,
3553	kVmxVDiag_Vmxon_Cpl,
3554	kVmxVDiag_Vmxon_Cr0Fixed0,
3555	kVmxVDiag_Vmxon_Cr4Fixed0,
3556	kVmxVDiag_Vmxon_Intercept,
3557	kVmxVDiag_Vmxon_LongModeCS,
3558	kVmxVDiag_Vmxon_MsrFeatCtl,
3559	kVmxVDiag_Vmxon_PtrAbnormal,
3560	kVmxVDiag_Vmxon_PtrAlign,
3561	kVmxVDiag_Vmxon_PtrMap,
3562	kVmxVDiag_Vmxon_PtrReadPhys,
3563	kVmxVDiag_Vmxon_PtrWidth,
3564	kVmxVDiag_Vmxon_RealOrV86Mode,
3565	kVmxVDiag_Vmxon_ShadowVmcs,
3566	kVmxVDiag_Vmxon_VmxAlreadyRoot,
3567	kVmxVDiag_Vmxon_Vmxe,
3568	kVmxVDiag_Vmxon_VmcsRevId,
3569	kVmxVDiag_Vmxon_VmxRootCpl,
3570	/* VMXOFF. */
3571	kVmxVDiag_Vmxoff_Cpl,
3572	kVmxVDiag_Vmxoff_Intercept,
3573	kVmxVDiag_Vmxoff_LongModeCS,
3574	kVmxVDiag_Vmxoff_RealOrV86Mode,
3575	kVmxVDiag_Vmxoff_Vmxe,
3576	kVmxVDiag_Vmxoff_VmxRoot,
3577	/* VMPTRLD. */
3578	kVmxVDiag_Vmptrld_Cpl,
3579	kVmxVDiag_Vmptrld_LongModeCS,
3580	kVmxVDiag_Vmptrld_PtrAbnormal,
3581	kVmxVDiag_Vmptrld_PtrAlign,
3582	kVmxVDiag_Vmptrld_PtrMap,
3583	kVmxVDiag_Vmptrld_PtrReadPhys,
3584	kVmxVDiag_Vmptrld_PtrVmxon,
3585	kVmxVDiag_Vmptrld_PtrWidth,
3586	kVmxVDiag_Vmptrld_RealOrV86Mode,
3587	kVmxVDiag_Vmptrld_ShadowVmcs,
3588	kVmxVDiag_Vmptrld_VmcsRevId,
3589	kVmxVDiag_Vmptrld_VmxRoot,
3590	/* VMPTRST. */
3591	kVmxVDiag_Vmptrst_Cpl,
3592	kVmxVDiag_Vmptrst_LongModeCS,
3593	kVmxVDiag_Vmptrst_PtrMap,
3594	kVmxVDiag_Vmptrst_RealOrV86Mode,
3595	kVmxVDiag_Vmptrst_VmxRoot,
3596	/* VMCLEAR. */
3597	kVmxVDiag_Vmclear_Cpl,
3598	kVmxVDiag_Vmclear_LongModeCS,
3599	kVmxVDiag_Vmclear_PtrAbnormal,
3600	kVmxVDiag_Vmclear_PtrAlign,
3601	kVmxVDiag_Vmclear_PtrMap,
3602	kVmxVDiag_Vmclear_PtrReadPhys,
3603	kVmxVDiag_Vmclear_PtrVmxon,
3604	kVmxVDiag_Vmclear_PtrWidth,
3605	kVmxVDiag_Vmclear_RealOrV86Mode,
3606	kVmxVDiag_Vmclear_VmxRoot,
3607	/* VMWRITE. */
3608	kVmxVDiag_Vmwrite_Cpl,
3609	kVmxVDiag_Vmwrite_FieldInvalid,
3610	kVmxVDiag_Vmwrite_FieldRo,
3611	kVmxVDiag_Vmwrite_LinkPtrInvalid,
3612	kVmxVDiag_Vmwrite_LongModeCS,
3613	kVmxVDiag_Vmwrite_PtrInvalid,
3614	kVmxVDiag_Vmwrite_PtrMap,
3615	kVmxVDiag_Vmwrite_RealOrV86Mode,
3616	kVmxVDiag_Vmwrite_VmxRoot,
3617	/* VMREAD. */
3618	kVmxVDiag_Vmread_Cpl,
3619	kVmxVDiag_Vmread_FieldInvalid,
3620	kVmxVDiag_Vmread_LinkPtrInvalid,
3621	kVmxVDiag_Vmread_LongModeCS,
3622	kVmxVDiag_Vmread_PtrInvalid,
3623	kVmxVDiag_Vmread_PtrMap,
3624	kVmxVDiag_Vmread_RealOrV86Mode,
3625	kVmxVDiag_Vmread_VmxRoot,
3626	/* VMLAUNCH/VMRESUME. */
3627	kVmxVDiag_Vmentry_AddrApicAccess,
3628	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
3629	kVmxVDiag_Vmentry_AddrExitMsrLoad,
3630	kVmxVDiag_Vmentry_AddrExitMsrStore,
3631	kVmxVDiag_Vmentry_AddrIoBitmapA,
3632	kVmxVDiag_Vmentry_AddrIoBitmapB,
3633	kVmxVDiag_Vmentry_AddrMsrBitmap,
3634	kVmxVDiag_Vmentry_AddrVirtApicPage,
3635	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
3636	kVmxVDiag_Vmentry_AddrVmreadBitmap,
3637	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
3638	kVmxVDiag_Vmentry_ApicRegVirt,
3639	kVmxVDiag_Vmentry_BlocKMovSS,
3640	kVmxVDiag_Vmentry_Cpl,
3641	kVmxVDiag_Vmentry_Cr3TargetCount,
3642	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
3643	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
3644	kVmxVDiag_Vmentry_EntryInstrLen,
3645	kVmxVDiag_Vmentry_EntryInstrLenZero,
3646	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
3647	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
3648	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
3649	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
3650	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
3651	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
3652	kVmxVDiag_Vmentry_GuestActStateHlt,
3653	kVmxVDiag_Vmentry_GuestActStateRsvd,
3654	kVmxVDiag_Vmentry_GuestActStateShutdown,
3655	kVmxVDiag_Vmentry_GuestActStateSsDpl,
3656	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
3657	kVmxVDiag_Vmentry_GuestCr0Fixed0,
3658	kVmxVDiag_Vmentry_GuestCr0Fixed1,
3659	kVmxVDiag_Vmentry_GuestCr0PgPe,
3660	kVmxVDiag_Vmentry_GuestCr3,
3661	kVmxVDiag_Vmentry_GuestCr4Fixed0,
3662	kVmxVDiag_Vmentry_GuestCr4Fixed1,
3663	kVmxVDiag_Vmentry_GuestDebugCtl,
3664	kVmxVDiag_Vmentry_GuestDr7,
3665	kVmxVDiag_Vmentry_GuestEferMsr,
3666	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
3667	kVmxVDiag_Vmentry_GuestGdtrBase,
3668	kVmxVDiag_Vmentry_GuestGdtrLimit,
3669	kVmxVDiag_Vmentry_GuestIdtrBase,
3670	kVmxVDiag_Vmentry_GuestIdtrLimit,
3671	kVmxVDiag_Vmentry_GuestIntStateEnclave,
3672	kVmxVDiag_Vmentry_GuestIntStateExtInt,
3673	kVmxVDiag_Vmentry_GuestIntStateNmi,
3674	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
3675	kVmxVDiag_Vmentry_GuestIntStateRsvd,
3676	kVmxVDiag_Vmentry_GuestIntStateSmi,
3677	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
3678	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
3679	kVmxVDiag_Vmentry_GuestPae,
3680	kVmxVDiag_Vmentry_GuestPatMsr,
3681	kVmxVDiag_Vmentry_GuestPcide,
3682	kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys,
3683	kVmxVDiag_Vmentry_GuestPdpte0Rsvd,
3684	kVmxVDiag_Vmentry_GuestPdpte1Rsvd,
3685	kVmxVDiag_Vmentry_GuestPdpte2Rsvd,
3686	kVmxVDiag_Vmentry_GuestPdpte3Rsvd,
3687	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
3688	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
3689	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
3690	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
3691	kVmxVDiag_Vmentry_GuestRip,
3692	kVmxVDiag_Vmentry_GuestRipRsvd,
3693	kVmxVDiag_Vmentry_GuestRFlagsIf,
3694	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
3695	kVmxVDiag_Vmentry_GuestRFlagsVm,
3696	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
3697	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
3698	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
3699	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
3700	kVmxVDiag_Vmentry_GuestSegAttrCsType,
3701	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
3702	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
3703	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
3704	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
3705	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
3706	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
3707	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
3708	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
3709	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
3710	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
3711	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
3712	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
3713	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
3714	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
3715	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
3716	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
3717	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
3718	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
3719	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
3720	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
3721	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
3722	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
3723	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
3724	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
3725	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
3726	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
3727	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
3728	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
3729	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
3730	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
3731	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
3732	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
3733	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
3734	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
3735	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
3736	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
3737	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
3738	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
3739	kVmxVDiag_Vmentry_GuestSegAttrSsType,
3740	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
3741	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
3742	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
3743	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
3744	kVmxVDiag_Vmentry_GuestSegAttrTrType,
3745	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
3746	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
3747	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
3748	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
3749	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
3750	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
3751	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
3752	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
3753	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
3754	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
3755	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
3756	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
3757	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
3758	kVmxVDiag_Vmentry_GuestSegBaseCs,
3759	kVmxVDiag_Vmentry_GuestSegBaseDs,
3760	kVmxVDiag_Vmentry_GuestSegBaseEs,
3761	kVmxVDiag_Vmentry_GuestSegBaseFs,
3762	kVmxVDiag_Vmentry_GuestSegBaseGs,
3763	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
3764	kVmxVDiag_Vmentry_GuestSegBaseSs,
3765	kVmxVDiag_Vmentry_GuestSegBaseTr,
3766	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
3767	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
3768	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
3769	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
3770	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
3771	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
3772	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
3773	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
3774	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
3775	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
3776	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
3777	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
3778	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
3779	kVmxVDiag_Vmentry_GuestSegSelLdtr,
3780	kVmxVDiag_Vmentry_GuestSegSelTr,
3781	kVmxVDiag_Vmentry_GuestSysenterEspEip,
3782	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
3783	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
3784	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
3785	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
3786	kVmxVDiag_Vmentry_HostCr0Fixed0,
3787	kVmxVDiag_Vmentry_HostCr0Fixed1,
3788	kVmxVDiag_Vmentry_HostCr3,
3789	kVmxVDiag_Vmentry_HostCr4Fixed0,
3790	kVmxVDiag_Vmentry_HostCr4Fixed1,
3791	kVmxVDiag_Vmentry_HostCr4Pae,
3792	kVmxVDiag_Vmentry_HostCr4Pcide,
3793	kVmxVDiag_Vmentry_HostCsTr,
3794	kVmxVDiag_Vmentry_HostEferMsr,
3795	kVmxVDiag_Vmentry_HostEferMsrRsvd,
3796	kVmxVDiag_Vmentry_HostGuestLongMode,
3797	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
3798	kVmxVDiag_Vmentry_HostLongMode,
3799	kVmxVDiag_Vmentry_HostPatMsr,
3800	kVmxVDiag_Vmentry_HostRip,
3801	kVmxVDiag_Vmentry_HostRipRsvd,
3802	kVmxVDiag_Vmentry_HostSel,
3803	kVmxVDiag_Vmentry_HostSegBase,
3804	kVmxVDiag_Vmentry_HostSs,
3805	kVmxVDiag_Vmentry_HostSysenterEspEip,
3806	kVmxVDiag_Vmentry_LongModeCS,
3807	kVmxVDiag_Vmentry_MsrLoad,
3808	kVmxVDiag_Vmentry_MsrLoadCount,
3809	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
3810	kVmxVDiag_Vmentry_MsrLoadRing3,
3811	kVmxVDiag_Vmentry_MsrLoadRsvd,
3812	kVmxVDiag_Vmentry_NmiWindowExit,
3813	kVmxVDiag_Vmentry_PinCtlsAllowed1,
3814	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
3815	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
3816	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
3817	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
3818	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
3819	kVmxVDiag_Vmentry_PtrInvalid,
3820	kVmxVDiag_Vmentry_PtrReadPhys,
3821	kVmxVDiag_Vmentry_RealOrV86Mode,
3822	kVmxVDiag_Vmentry_SavePreemptTimer,
3823	kVmxVDiag_Vmentry_TprThresholdRsvd,
3824	kVmxVDiag_Vmentry_TprThresholdVTpr,
3825	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
3826	kVmxVDiag_Vmentry_VirtIntDelivery,
3827	kVmxVDiag_Vmentry_VirtNmi,
3828	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
3829	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
3830	kVmxVDiag_Vmentry_VmcsClear,
3831	kVmxVDiag_Vmentry_VmcsLaunch,
3832	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
3833	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
3834	kVmxVDiag_Vmentry_VmxRoot,
3835	kVmxVDiag_Vmentry_Vpid,
3836	kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys,
3837	kVmxVDiag_Vmexit_HostPdpte0Rsvd,
3838	kVmxVDiag_Vmexit_HostPdpte1Rsvd,
3839	kVmxVDiag_Vmexit_HostPdpte2Rsvd,
3840	kVmxVDiag_Vmexit_HostPdpte3Rsvd,
3841	kVmxVDiag_Vmexit_MsrLoad,
3842	kVmxVDiag_Vmexit_MsrLoadCount,
3843	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
3844	kVmxVDiag_Vmexit_MsrLoadRing3,
3845	kVmxVDiag_Vmexit_MsrLoadRsvd,
3846	kVmxVDiag_Vmexit_MsrStore,
3847	kVmxVDiag_Vmexit_MsrStoreCount,
3848	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
3849	kVmxVDiag_Vmexit_MsrStoreRing3,
3850	kVmxVDiag_Vmexit_MsrStoreRsvd,
3851	/* Last member for determining array index limit. */
3852	kVmxVDiag_End
3853	} VMXVDIAG;
3854	AssertCompileSize(VMXVDIAG, 4);
3855
3856
3857	/** @defgroup grp_hm_vmx_inline VMX Inline Helpers
3858	* @{
3859	*/
3860	/**
3861	* Gets the effective width of a VMCS field given it's encoding adjusted for
3862	* HIGH/FULL access for 64-bit fields.
3863	*
3864	* @returns The effective VMCS field width.
3865	* @param uFieldEnc The VMCS field encoding.
3866	*
3867	* @remarks Warning! This function does not verify the encoding is for a valid and
3868	* supported VMCS field.
3869	*/
3870	DECLINLINE(uint8_t) HMVmxGetVmcsFieldWidthEff(uint32_t uFieldEnc)
3871	{
3872	/* Only the "HIGH" parts of all 64-bit fields have bit 0 set. */
3873	if (uFieldEnc & RT_BIT(0))
3874	return VMXVMCSFIELDWIDTH_32BIT;
3875
3876	/* Bits 13:14 contains the width of the VMCS field, see VMXVMCSFIELDWIDTH_XXX. */
3877	return (uFieldEnc >> 13) & 0x3;
3878	}
3879
3880	/**
3881	* Returns whether the given VMCS field is a read-only VMCS field or not.
3882	*
3883	* @returns @c true if it's a read-only field, @c false otherwise.
3884	* @param uFieldEnc The VMCS field encoding.
3885	*
3886	* @remarks Warning! This function does not verify the encoding is for a valid and
3887	* supported VMCS field.
3888	*/
3889	DECLINLINE(bool) HMVmxIsVmcsFieldReadOnly(uint32_t uFieldEnc)
3890	{
3891	/* See Intel spec. B.4.2 "Natural-Width Read-Only Data Fields". */
3892	return (RT_BF_GET(uFieldEnc, VMX_BF_VMCS_ENC_TYPE) == VMXVMCSFIELDTYPE_VMEXIT_INFO);
3893	}
3894
3895	/**
3896	* Returns whether the given VM-entry interruption-information type is valid or not.
3897	*
3898	* @returns @c true if it's a valid type, @c false otherwise.
3899	* @param fSupportsMTF Whether the Monitor-Trap Flag CPU feature is supported.
3900	* @param uType The VM-entry interruption-information type.
3901	*/
3902	DECLINLINE(bool) HMVmxIsEntryIntInfoTypeValid(bool fSupportsMTF, uint8_t uType)
3903	{
3904	/* See Intel spec. 26.2.1.3 "VM-Entry Control Fields". */
3905	switch (uType)
3906	{
3907	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
3908	case VMX_ENTRY_INT_INFO_TYPE_NMI:
3909	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
3910	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
3911	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
3912	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: return true;
3913	case VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT: return fSupportsMTF;
3914	default:
3915	return false;
3916	}
3917	}
3918
3919	/**
3920	* Returns whether the given VM-entry interruption-information vector and type
3921	* combination is valid or not.
3922	*
3923	* @returns @c true if it's a valid vector/type combination, @c false otherwise.
3924	* @param uVector The VM-entry interruption-information vector.
3925	* @param uType The VM-entry interruption-information type.
3926	*
3927	* @remarks Warning! This function does not validate the type field individually.
3928	* Use it after verifying type is valid using HMVmxIsEntryIntInfoTypeValid.
3929	*/
3930	DECLINLINE(bool) HMVmxIsEntryIntInfoVectorValid(uint8_t uVector, uint8_t uType)
3931	{
3932	/* See Intel spec. 26.2.1.3 "VM-Entry Control Fields". */
3933	if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
3934	&& uVector != X86_XCPT_NMI)
3935	return false;
3936	if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
3937	&& uVector > X86_XCPT_LAST)
3938	return false;
3939	if ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
3940	&& uVector != VMX_ENTRY_INT_INFO_VECTOR_MTF)
3941	return false;
3942	return true;
3943	}
3944
3945
3946	/**
3947	* Returns whether or not the VM-exit is trap-like or fault-like.
3948	*
3949	* @returns @c true if it's a trap-like VM-exit, @c false otehrwise.
3950	* @param uExitReason The VM-exit reason.
3951	*
3952	* @remarks Warning! This does not validate the VM-exit reason.
3953	*/
3954	DECLINLINE(bool) HMVmxIsTrapLikeVmexit(uint32_t uExitReason)
3955	{
3956	/*
3957	* Trap-like VM-exits - The instruction causing the VM-exit completes before the
3958	* VM-exit occurs.
3959	*
3960	* Fault-like VM-exits - The instruction causing the VM-exit is not completed before
3961	* the VM-exit occurs.
3962	*
3963	* See Intel spec. 25.5.2 "Monitor Trap Flag".
3964	* See Intel spec. 29.1.4 "EOI Virtualization".
3965	* See Intel spec. 29.4.3.3 "APIC-Write VM Exits".
3966	* See Intel spec. 29.1.2 "TPR Virtualization".
3967	*/
3968	switch (uExitReason)
3969	{
3970	case VMX_EXIT_MTF:
3971	case VMX_EXIT_VIRTUALIZED_EOI:
3972	case VMX_EXIT_APIC_WRITE:
3973	case VMX_EXIT_TPR_BELOW_THRESHOLD:
3974	return true;
3975	}
3976	return false;
3977	}
3978	/** @} */
3979
3980
3981	/** @defgroup grp_hm_vmx_asm VMX Assembly Helpers
3982	* @{
3983	*/
3984
3985	/**
3986	* Restores some host-state fields that need not be done on every VM-exit.
3987	*
3988	* @returns VBox status code.
3989	* @param fRestoreHostFlags Flags of which host registers needs to be
3990	* restored.
3991	* @param pRestoreHost Pointer to the host-restore structure.
3992	*/
3993	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
3994
3995
3996	/**
3997	* Dispatches an NMI to the host.
3998	*/
3999	DECLASM(int) VMXDispatchHostNmi(void);
4000
4001
4002	/**
4003	* Executes VMXON.
4004	*
4005	* @returns VBox status code.
4006	* @param HCPhysVmxOn Physical address of VMXON structure.
4007	*/
4008	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
4009	DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
4010	#else
4011	DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
4012	{
4013	# if RT_INLINE_ASM_GNU_STYLE
4014	int rc = VINF_SUCCESS;
4015	__asm__ __volatile__ (
4016	"push %3 \n\t"
4017	"push %2 \n\t"
4018	".byte 0xf3, 0x0f, 0xc7, 0x34, 0x24 # VMXON [esp] \n\t"
4019	"ja 2f \n\t"
4020	"je 1f \n\t"
4021	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
4022	"jmp 2f \n\t"
4023	"1: \n\t"
4024	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
4025	"2: \n\t"
4026	"add $8, %%esp \n\t"
4027	:"=rm"(rc)
4028	:"0"(VINF_SUCCESS),
4029	"ir"((uint32_t)HCPhysVmxOn), /* don't allow direct memory reference here, */
4030	"ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
4031	:"memory"
4032	);
4033	return rc;
4034
4035	# elif VMX_USE_MSC_INTRINSICS
4036	unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
4037	if (RT_LIKELY(rcMsc == 0))
4038	return VINF_SUCCESS;
4039	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
4040
4041	# else
4042	int rc = VINF_SUCCESS;
4043	__asm
4044	{
4045	push dword ptr [HCPhysVmxOn + 4]
4046	push dword ptr [HCPhysVmxOn]
4047	_emit 0xf3
4048	_emit 0x0f
4049	_emit 0xc7
4050	_emit 0x34
4051	_emit 0x24 /* VMXON [esp] */
4052	jnc vmxon_good
4053	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
4054	jmp the_end
4055
4056	vmxon_good:
4057	jnz the_end
4058	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
4059	the_end:
4060	add esp, 8
4061	}
4062	return rc;
4063	# endif
4064	}
4065	#endif
4066
4067
4068	/**
4069	* Executes VMXOFF.
4070	*/
4071	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
4072	DECLASM(void) VMXDisable(void);
4073	#else
4074	DECLINLINE(void) VMXDisable(void)
4075	{
4076	# if RT_INLINE_ASM_GNU_STYLE
4077	__asm__ __volatile__ (
4078	".byte 0x0f, 0x01, 0xc4 # VMXOFF \n\t"
4079	);
4080
4081	# elif VMX_USE_MSC_INTRINSICS
4082	__vmx_off();
4083
4084	# else
4085	__asm
4086	{
4087	_emit 0x0f
4088	_emit 0x01
4089	_emit 0xc4 /* VMXOFF */
4090	}
4091	# endif
4092	}
4093	#endif
4094
4095
4096	/**
4097	* Executes VMCLEAR.
4098	*
4099	* @returns VBox status code.
4100	* @param HCPhysVmcs Physical address of VM control structure.
4101	*/
4102	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
4103	DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
4104	#else
4105	DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
4106	{
4107	# if RT_INLINE_ASM_GNU_STYLE
4108	int rc = VINF_SUCCESS;
4109	__asm__ __volatile__ (
4110	"push %3 \n\t"
4111	"push %2 \n\t"
4112	".byte 0x66, 0x0f, 0xc7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
4113	"jnc 1f \n\t"
4114	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
4115	"1: \n\t"
4116	"add $8, %%esp \n\t"
4117	:"=rm"(rc)
4118	:"0"(VINF_SUCCESS),
4119	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
4120	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
4121	:"memory"
4122	);
4123	return rc;
4124
4125	# elif VMX_USE_MSC_INTRINSICS
4126	unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
4127	if (RT_LIKELY(rcMsc == 0))
4128	return VINF_SUCCESS;
4129	return VERR_VMX_INVALID_VMCS_PTR;
4130
4131	# else
4132	int rc = VINF_SUCCESS;
4133	__asm
4134	{
4135	push dword ptr [HCPhysVmcs + 4]
4136	push dword ptr [HCPhysVmcs]
4137	_emit 0x66
4138	_emit 0x0f
4139	_emit 0xc7
4140	_emit 0x34
4141	_emit 0x24 /* VMCLEAR [esp] */
4142	jnc success
4143	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
4144	success:
4145	add esp, 8
4146	}
4147	return rc;
4148	# endif
4149	}
4150	#endif
4151
4152
4153	/**
4154	* Executes VMPTRLD.
4155	*
4156	* @returns VBox status code.
4157	* @param HCPhysVmcs Physical address of VMCS structure.
4158	*/
4159	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
4160	DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
4161	#else
4162	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
4163	{
4164	# if RT_INLINE_ASM_GNU_STYLE
4165	int rc = VINF_SUCCESS;
4166	__asm__ __volatile__ (
4167	"push %3 \n\t"
4168	"push %2 \n\t"
4169	".byte 0x0f, 0xc7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
4170	"jnc 1f \n\t"
4171	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
4172	"1: \n\t"
4173	"add $8, %%esp \n\t"
4174	:"=rm"(rc)
4175	:"0"(VINF_SUCCESS),
4176	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
4177	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
4178	);
4179	return rc;
4180
4181	# elif VMX_USE_MSC_INTRINSICS
4182	unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
4183	if (RT_LIKELY(rcMsc == 0))
4184	return VINF_SUCCESS;
4185	return VERR_VMX_INVALID_VMCS_PTR;
4186
4187	# else
4188	int rc = VINF_SUCCESS;
4189	__asm
4190	{
4191	push dword ptr [HCPhysVmcs + 4]
4192	push dword ptr [HCPhysVmcs]
4193	_emit 0x0f
4194	_emit 0xc7
4195	_emit 0x34
4196	_emit 0x24 /* VMPTRLD [esp] */
4197	jnc success
4198	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
4199
4200	success:
4201	add esp, 8
4202	}
4203	return rc;
4204	# endif
4205	}
4206	#endif
4207
4208
4209	/**
4210	* Executes VMPTRST.
4211	*
4212	* @returns VBox status code.
4213	* @param pHCPhysVmcs Where to store the physical address of the current
4214	* VMCS.
4215	*/
4216	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
4217
4218
4219	/**
4220	* Executes VMWRITE.
4221	*
4222	* @returns VBox status code.
4223	* @retval VINF_SUCCESS.
4224	* @retval VERR_VMX_INVALID_VMCS_PTR.
4225	* @retval VERR_VMX_INVALID_VMCS_FIELD.
4226	*
4227	* @param uFieldEnc VMCS field encoding.
4228	* @param u32Val The 32-bit value to set.
4229	*
4230	* @remarks The values of the two status codes can be OR'ed together, the result
4231	* will be VERR_VMX_INVALID_VMCS_PTR.
4232	*/
4233	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
4234	DECLASM(int) VMXWriteVmcs32(uint32_t uFieldEnc, uint32_t u32Val);
4235	#else
4236	DECLINLINE(int) VMXWriteVmcs32(uint32_t uFieldEnc, uint32_t u32Val)
4237	{
4238	# if RT_INLINE_ASM_GNU_STYLE
4239	int rc = VINF_SUCCESS;
4240	__asm__ __volatile__ (
4241	".byte 0x0f, 0x79, 0xc2 # VMWRITE eax, edx \n\t"
4242	"ja 2f \n\t"
4243	"je 1f \n\t"
4244	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
4245	"jmp 2f \n\t"
4246	"1: \n\t"
4247	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
4248	"2: \n\t"
4249	:"=rm"(rc)
4250	:"0"(VINF_SUCCESS),
4251	"a"(uFieldEnc),
4252	"d"(u32Val)
4253	);
4254	return rc;
4255
4256	# elif VMX_USE_MSC_INTRINSICS
4257	unsigned char rcMsc = __vmx_vmwrite(uFieldEnc, u32Val);
4258	if (RT_LIKELY(rcMsc == 0))
4259	return VINF_SUCCESS;
4260	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
4261
4262	#else
4263	int rc = VINF_SUCCESS;
4264	__asm
4265	{
4266	push dword ptr [u32Val]
4267	mov eax, [uFieldEnc]
4268	_emit 0x0f
4269	_emit 0x79
4270	_emit 0x04
4271	_emit 0x24 /* VMWRITE eax, [esp] */
4272	jnc valid_vmcs
4273	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
4274	jmp the_end
4275
4276	valid_vmcs:
4277	jnz the_end
4278	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
4279	the_end:
4280	add esp, 4
4281	}
4282	return rc;
4283	# endif
4284	}
4285	#endif
4286
4287	/**
4288	* Executes VMWRITE.
4289	*
4290	* @returns VBox status code.
4291	* @retval VINF_SUCCESS.
4292	* @retval VERR_VMX_INVALID_VMCS_PTR.
4293	* @retval VERR_VMX_INVALID_VMCS_FIELD.
4294	*
4295	* @param uFieldEnc The VMCS field encoding.
4296	* @param u64Val The 16, 32 or 64-bit value to set.
4297	*
4298	* @remarks The values of the two status codes can be OR'ed together, the result
4299	* will be VERR_VMX_INVALID_VMCS_PTR.
4300	*/
4301	#if !defined(RT_ARCH_X86)
4302	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
4303	DECLASM(int) VMXWriteVmcs64(uint32_t uFieldEnc, uint64_t u64Val);
4304	# else /* VMX_USE_MSC_INTRINSICS */
4305	DECLINLINE(int) VMXWriteVmcs64(uint32_t uFieldEnc, uint64_t u64Val)
4306	{
4307	unsigned char rcMsc = __vmx_vmwrite(uFieldEnc, u64Val);
4308	if (RT_LIKELY(rcMsc == 0))
4309	return VINF_SUCCESS;
4310	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
4311	}
4312	# endif /* VMX_USE_MSC_INTRINSICS */
4313	#else
4314	# define VMXWriteVmcs64(uFieldEnc, u64Val) VMXWriteVmcs64Ex(pVCpu, uFieldEnc, u64Val) /** @todo dead ugly, picking up pVCpu like this */
4315	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t uFieldEnc, uint64_t u64Val);
4316	#endif
4317
4318	#if ARCH_BITS == 32
4319	# define VMXWriteVmcsHstN VMXWriteVmcs32
4320	# define VMXWriteVmcsGstN(uFieldEnc, u64Val) VMXWriteVmcs64Ex(pVCpu, uFieldEnc, u64Val)
4321	#else /* ARCH_BITS == 64 */
4322	# define VMXWriteVmcsHstN VMXWriteVmcs64
4323	# define VMXWriteVmcsGstN VMXWriteVmcs64
4324	#endif
4325
4326
4327	/**
4328	* Invalidate a page using INVEPT.
4329	*
4330	* @returns VBox status code.
4331	* @param enmFlush Type of flush.
4332	* @param pDescriptor Pointer to the descriptor.
4333	*/
4334	DECLASM(int) VMXR0InvEPT(VMXTLBFLUSHEPT enmFlush, uint64_t *pDescriptor);
4335
4336
4337	/**
4338	* Invalidate a page using INVVPID.
4339	*
4340	* @returns VBox status code.
4341	* @param enmFlush Type of flush.
4342	* @param pDescriptor Pointer to the descriptor.
4343	*/
4344	DECLASM(int) VMXR0InvVPID(VMXTLBFLUSHVPID enmFlush, uint64_t *pDescriptor);
4345
4346
4347	/**
4348	* Executes VMREAD for a 32-bit field.
4349	*
4350	* @returns VBox status code.
4351	* @retval VINF_SUCCESS.
4352	* @retval VERR_VMX_INVALID_VMCS_PTR.
4353	* @retval VERR_VMX_INVALID_VMCS_FIELD.
4354	*
4355	* @param uFieldEnc The VMCS field encoding.
4356	* @param pData Where to store VMCS field value.
4357	*
4358	* @remarks The values of the two status codes can be OR'ed together, the result
4359	* will be VERR_VMX_INVALID_VMCS_PTR.
4360	*/
4361	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
4362	DECLASM(int) VMXReadVmcs32(uint32_t uFieldEnc, uint32_t *pData);
4363	#else
4364	DECLINLINE(int) VMXReadVmcs32(uint32_t uFieldEnc, uint32_t *pData)
4365	{
4366	# if RT_INLINE_ASM_GNU_STYLE
4367	int rc = VINF_SUCCESS;
4368	__asm__ __volatile__ (
4369	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
4370	".byte 0x0f, 0x78, 0xc2 # VMREAD eax, edx \n\t"
4371	"ja 2f \n\t"
4372	"je 1f \n\t"
4373	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
4374	"jmp 2f \n\t"
4375	"1: \n\t"
4376	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
4377	"2: \n\t"
4378	:"=&r"(rc),
4379	"=d"(*pData)
4380	:"a"(uFieldEnc),
4381	"d"(0)
4382	);
4383	return rc;
4384
4385	# elif VMX_USE_MSC_INTRINSICS
4386	unsigned char rcMsc;
4387	# if ARCH_BITS == 32
4388	rcMsc = __vmx_vmread(uFieldEnc, pData);
4389	# else
4390	uint64_t u64Tmp;
4391	rcMsc = __vmx_vmread(uFieldEnc, &u64Tmp);
4392	*pData = (uint32_t)u64Tmp;
4393	# endif
4394	if (RT_LIKELY(rcMsc == 0))
4395	return VINF_SUCCESS;
4396	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
4397
4398	#else
4399	int rc = VINF_SUCCESS;
4400	__asm
4401	{
4402	sub esp, 4
4403	mov dword ptr [esp], 0
4404	mov eax, [uFieldEnc]
4405	_emit 0x0f
4406	_emit 0x78
4407	_emit 0x04
4408	_emit 0x24 /* VMREAD eax, [esp] */
4409	mov edx, pData
4410	pop dword ptr [edx]
4411	jnc valid_vmcs
4412	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
4413	jmp the_end
4414
4415	valid_vmcs:
4416	jnz the_end
4417	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
4418	the_end:
4419	}
4420	return rc;
4421	# endif
4422	}
4423	#endif
4424
4425	/**
4426	* Executes VMREAD for a 64-bit field.
4427	*
4428	* @returns VBox status code.
4429	* @retval VINF_SUCCESS.
4430	* @retval VERR_VMX_INVALID_VMCS_PTR.
4431	* @retval VERR_VMX_INVALID_VMCS_FIELD.
4432	*
4433	* @param uFieldEnc The VMCS field encoding.
4434	* @param pData Where to store VMCS field value.
4435	*
4436	* @remarks The values of the two status codes can be OR'ed together, the result
4437	* will be VERR_VMX_INVALID_VMCS_PTR.
4438	*/
4439	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
4440	DECLASM(int) VMXReadVmcs64(uint32_t uFieldEnc, uint64_t *pData);
4441	#else
4442	DECLINLINE(int) VMXReadVmcs64(uint32_t uFieldEnc, uint64_t *pData)
4443	{
4444	# if VMX_USE_MSC_INTRINSICS
4445	unsigned char rcMsc;
4446	# if ARCH_BITS == 32
4447	size_t uLow;
4448	size_t uHigh;
4449	rcMsc = __vmx_vmread(uFieldEnc, &uLow);
4450	rcMsc \|= __vmx_vmread(uFieldEnc + 1, &uHigh);
4451	*pData = RT_MAKE_U64(uLow, uHigh);
4452	# else
4453	rcMsc = __vmx_vmread(uFieldEnc, pData);
4454	# endif
4455	if (RT_LIKELY(rcMsc == 0))
4456	return VINF_SUCCESS;
4457	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
4458
4459	# elif ARCH_BITS == 32
4460	int rc;
4461	uint32_t val_hi, val;
4462	rc = VMXReadVmcs32(uFieldEnc, &val);
4463	rc \|= VMXReadVmcs32(uFieldEnc + 1, &val_hi);
4464	AssertRC(rc);
4465	*pData = RT_MAKE_U64(val, val_hi);
4466	return rc;
4467
4468	# else
4469	# error "Shouldn't be here..."
4470	# endif
4471	}
4472	#endif
4473
4474
4475	/**
4476	* Gets the last instruction error value from the current VMCS.
4477	*
4478	* @returns VBox status code.
4479	*/
4480	DECLINLINE(uint32_t) VMXGetLastError(void)
4481	{
4482	#if ARCH_BITS == 64
4483	uint64_t uLastError = 0;
4484	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
4485	AssertRC(rc);
4486	return (uint32_t)uLastError;
4487
4488	#else /* 32-bit host: */
4489	uint32_t uLastError = 0;
4490	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
4491	AssertRC(rc);
4492	return uLastError;
4493	#endif
4494	}
4495
4496	/** @} */
4497
4498	/** @} */
4499
4500	#endif
4501

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 74429

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