hm_vmx.h@ 63648

Last change on this file since 63648 was 62634, checked in by vboxsync, 8 years ago
includes: Workaround for C4668 & C4255 warnings in MSC and WDK headers.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2016 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vmx_h
27	#define ___VBox_vmm_vmx_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/x86.h>
32	#include <iprt/assert.h>
33
34	/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35	when targeting AMD64. */
36	#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37	# pragma warning(push)
38	# pragma warning(disable:4668) /* Several incorrect __cplusplus uses. */
39	# pragma warning(disable:4255) /* Incorrect __slwpcb prototype. */
40	# include <intrin.h>
41	# pragma warning(pop)
42	/* We always want them as intrinsics, no functions. */
43	# pragma intrinsic(__vmx_on)
44	# pragma intrinsic(__vmx_off)
45	# pragma intrinsic(__vmx_vmclear)
46	# pragma intrinsic(__vmx_vmptrld)
47	# pragma intrinsic(__vmx_vmread)
48	# pragma intrinsic(__vmx_vmwrite)
49	# define VMX_USE_MSC_INTRINSICS 1
50	#else
51	# define VMX_USE_MSC_INTRINSICS 0
52	#endif
53
54
55	/** @defgroup grp_hm_vmx VMX Types and Definitions
56	* @ingroup grp_hm
57	* @{
58	*/
59
60	/** @def HMVMXCPU_GST_SET_UPDATED
61	* Sets a guest-state-updated flag.
62	*
63	* @param pVCpu The cross context virtual CPU structure.
64	* @param fFlag The flag to set.
65	*/
66	#define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
67
68	/** @def HMVMXCPU_GST_IS_SET
69	* Checks if all the flags in the specified guest-state-updated set is pending.
70	*
71	* @param pVCpu The cross context virtual CPU structure.
72	* @param fFlag The flag to check.
73	*/
74	#define HMVMXCPU_GST_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
75
76	/** @def HMVMXCPU_GST_IS_UPDATED
77	* Checks if one or more of the flags in the specified guest-state-updated set
78	* is updated.
79	*
80	* @param pVCpu The cross context virtual CPU structure.
81	* @param fFlags The flags to check for.
82	*/
83	#define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
84
85	/** @def HMVMXCPU_GST_RESET_TO
86	* Resets the guest-state-updated flags to the specified value.
87	*
88	* @param pVCpu The cross context virtual CPU structure.
89	* @param fFlags The new value.
90	*/
91	#define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
92
93	/** @def HMVMXCPU_GST_VALUE
94	* Returns the current guest-state-updated flags value.
95	*
96	* @param pVCpu The cross context virtual CPU structure.
97	*/
98	#define HMVMXCPU_GST_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState))
99
100	/** @name Host-state restoration flags.
101	* @note If you change these values don't forget to update the assembly
102	* defines as well!
103	* @{
104	*/
105	#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
106	#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
107	#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
108	#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
109	#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
110	#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
111	#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
112	#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
113	#define VMX_RESTORE_HOST_REQUIRED RT_BIT(8)
114	/** @} */
115
116	/**
117	* Host-state restoration structure.
118	* This holds host-state fields that require manual restoration.
119	* Assembly version found in hm_vmx.mac (should be automatically verified).
120	*/
121	typedef struct VMXRESTOREHOST
122	{
123	RTSEL uHostSelDS; /* 0x00 */
124	RTSEL uHostSelES; /* 0x02 */
125	RTSEL uHostSelFS; /* 0x04 */
126	RTSEL uHostSelGS; /* 0x06 */
127	RTSEL uHostSelTR; /* 0x08 */
128	uint8_t abPadding0[4];
129	X86XDTR64 HostGdtr; /*< 0x0e - should be aligned by it's 64-bit member. /
130	uint8_t abPadding1[6];
131	X86XDTR64 HostIdtr; /*< 0x1e - should be aligned by it's 64-bit member. /
132	uint64_t uHostFSBase; /* 0x28 */
133	uint64_t uHostGSBase; /* 0x30 */
134	} VMXRESTOREHOST;
135	/** Pointer to VMXRESTOREHOST. */
136	typedef VMXRESTOREHOST *PVMXRESTOREHOST;
137	AssertCompileSize(X86XDTR64, 10);
138	AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
139	AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
140	AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
141	AssertCompileSize(VMXRESTOREHOST, 56);
142	AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
143
144	/** @name Host-state MSR lazy-restoration flags.
145	* @{
146	*/
147	/** The host MSRs have been saved. */
148	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
149	/** The guest MSRs are loaded and in effect. */
150	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
151	/** @} */
152
153	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
154	* UFC = Unsupported Feature Combination.
155	* @{
156	*/
157	/** Unsupported pin-based VM-execution controls combo. */
158	#define VMX_UFC_CTRL_PIN_EXEC 1
159	/** Unsupported processor-based VM-execution controls combo. */
160	#define VMX_UFC_CTRL_PROC_EXEC 2
161	/** Unsupported move debug register VM-exit combo. */
162	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
163	/** Unsupported VM-entry controls combo. */
164	#define VMX_UFC_CTRL_ENTRY 4
165	/** Unsupported VM-exit controls combo. */
166	#define VMX_UFC_CTRL_EXIT 5
167	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
168	* for storing host MSRs. */
169	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
170	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
171	* for storing guest MSRs. */
172	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
173	/** Invalid VMCS size. */
174	#define VMX_UFC_INVALID_VMCS_SIZE 8
175	/** Unsupported secondary processor-based VM-execution controls combo. */
176	#define VMX_UFC_CTRL_PROC_EXEC2 9
177	/** Invalid unrestricted-guest execution controls combo. */
178	#define VMX_UFC_INVALID_UX_COMBO 10
179	/** EPT flush type not supported. */
180	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
181	/** EPT paging structure memory type is not write-back. */
182	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
183	/** EPT requires INVEPT instr. support but it's not available. */
184	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
185	/** EPT requires page-walk length of 4. */
186	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
187	/** @} */
188
189	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
190	* IGS = Invalid Guest State.
191	* @{
192	*/
193	/** An error occurred while checking invalid-guest-state. */
194	#define VMX_IGS_ERROR 500
195	/** The invalid guest-state checks did not find any reason why. */
196	#define VMX_IGS_REASON_NOT_FOUND 501
197	/** CR0 fixed1 bits invalid. */
198	#define VMX_IGS_CR0_FIXED1 502
199	/** CR0 fixed0 bits invalid. */
200	#define VMX_IGS_CR0_FIXED0 503
201	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
202	#define VMX_IGS_CR0_PG_PE_COMBO 504
203	/** CR4 fixed1 bits invalid. */
204	#define VMX_IGS_CR4_FIXED1 505
205	/** CR4 fixed0 bits invalid. */
206	#define VMX_IGS_CR4_FIXED0 506
207	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
208	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
209	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
210	/** CR0.PG not set for long-mode when not using unrestricted guest. */
211	#define VMX_IGS_CR0_PG_LONGMODE 508
212	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
213	#define VMX_IGS_CR4_PAE_LONGMODE 509
214	/** CR4.PCIDE set for 32-bit guest. */
215	#define VMX_IGS_CR4_PCIDE 510
216	/** VMCS' DR7 reserved bits not set to 0. */
217	#define VMX_IGS_DR7_RESERVED 511
218	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
219	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
220	/** VMCS' EFER MSR reserved bits not set to 0. */
221	#define VMX_IGS_EFER_MSR_RESERVED 513
222	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
223	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
224	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
225	* without unrestricted guest. */
226	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
227	/** CS.Attr.P bit invalid. */
228	#define VMX_IGS_CS_ATTR_P_INVALID 516
229	/** CS.Attr reserved bits not set to 0. */
230	#define VMX_IGS_CS_ATTR_RESERVED 517
231	/** CS.Attr.G bit invalid. */
232	#define VMX_IGS_CS_ATTR_G_INVALID 518
233	/** CS is unusable. */
234	#define VMX_IGS_CS_ATTR_UNUSABLE 519
235	/** CS and SS DPL unequal. */
236	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
237	/** CS and SS DPL mismatch. */
238	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
239	/** CS Attr.Type invalid. */
240	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
241	/** CS and SS RPL unequal. */
242	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
243	/** SS.Attr.DPL and SS RPL unequal. */
244	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
245	/** SS.Attr.DPL invalid for segment type. */
246	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
247	/** SS.Attr.Type invalid. */
248	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
249	/** SS.Attr.P bit invalid. */
250	#define VMX_IGS_SS_ATTR_P_INVALID 527
251	/** SS.Attr reserved bits not set to 0. */
252	#define VMX_IGS_SS_ATTR_RESERVED 528
253	/** SS.Attr.G bit invalid. */
254	#define VMX_IGS_SS_ATTR_G_INVALID 529
255	/** DS.Attr.A bit invalid. */
256	#define VMX_IGS_DS_ATTR_A_INVALID 530
257	/** DS.Attr.P bit invalid. */
258	#define VMX_IGS_DS_ATTR_P_INVALID 531
259	/** DS.Attr.DPL and DS RPL unequal. */
260	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
261	/** DS.Attr reserved bits not set to 0. */
262	#define VMX_IGS_DS_ATTR_RESERVED 533
263	/** DS.Attr.G bit invalid. */
264	#define VMX_IGS_DS_ATTR_G_INVALID 534
265	/** DS.Attr.Type invalid. */
266	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
267	/** ES.Attr.A bit invalid. */
268	#define VMX_IGS_ES_ATTR_A_INVALID 536
269	/** ES.Attr.P bit invalid. */
270	#define VMX_IGS_ES_ATTR_P_INVALID 537
271	/** ES.Attr.DPL and DS RPL unequal. */
272	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
273	/** ES.Attr reserved bits not set to 0. */
274	#define VMX_IGS_ES_ATTR_RESERVED 539
275	/** ES.Attr.G bit invalid. */
276	#define VMX_IGS_ES_ATTR_G_INVALID 540
277	/** ES.Attr.Type invalid. */
278	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
279	/** FS.Attr.A bit invalid. */
280	#define VMX_IGS_FS_ATTR_A_INVALID 542
281	/** FS.Attr.P bit invalid. */
282	#define VMX_IGS_FS_ATTR_P_INVALID 543
283	/** FS.Attr.DPL and DS RPL unequal. */
284	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
285	/** FS.Attr reserved bits not set to 0. */
286	#define VMX_IGS_FS_ATTR_RESERVED 545
287	/** FS.Attr.G bit invalid. */
288	#define VMX_IGS_FS_ATTR_G_INVALID 546
289	/** FS.Attr.Type invalid. */
290	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
291	/** GS.Attr.A bit invalid. */
292	#define VMX_IGS_GS_ATTR_A_INVALID 548
293	/** GS.Attr.P bit invalid. */
294	#define VMX_IGS_GS_ATTR_P_INVALID 549
295	/** GS.Attr.DPL and DS RPL unequal. */
296	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
297	/** GS.Attr reserved bits not set to 0. */
298	#define VMX_IGS_GS_ATTR_RESERVED 551
299	/** GS.Attr.G bit invalid. */
300	#define VMX_IGS_GS_ATTR_G_INVALID 552
301	/** GS.Attr.Type invalid. */
302	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
303	/** V86 mode CS.Base invalid. */
304	#define VMX_IGS_V86_CS_BASE_INVALID 554
305	/** V86 mode CS.Limit invalid. */
306	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
307	/** V86 mode CS.Attr invalid. */
308	#define VMX_IGS_V86_CS_ATTR_INVALID 556
309	/** V86 mode SS.Base invalid. */
310	#define VMX_IGS_V86_SS_BASE_INVALID 557
311	/** V86 mode SS.Limit invalid. */
312	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
313	/** V86 mode SS.Attr invalid. */
314	#define VMX_IGS_V86_SS_ATTR_INVALID 559
315	/** V86 mode DS.Base invalid. */
316	#define VMX_IGS_V86_DS_BASE_INVALID 560
317	/** V86 mode DS.Limit invalid. */
318	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
319	/** V86 mode DS.Attr invalid. */
320	#define VMX_IGS_V86_DS_ATTR_INVALID 562
321	/** V86 mode ES.Base invalid. */
322	#define VMX_IGS_V86_ES_BASE_INVALID 563
323	/** V86 mode ES.Limit invalid. */
324	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
325	/** V86 mode ES.Attr invalid. */
326	#define VMX_IGS_V86_ES_ATTR_INVALID 565
327	/** V86 mode FS.Base invalid. */
328	#define VMX_IGS_V86_FS_BASE_INVALID 566
329	/** V86 mode FS.Limit invalid. */
330	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
331	/** V86 mode FS.Attr invalid. */
332	#define VMX_IGS_V86_FS_ATTR_INVALID 568
333	/** V86 mode GS.Base invalid. */
334	#define VMX_IGS_V86_GS_BASE_INVALID 569
335	/** V86 mode GS.Limit invalid. */
336	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
337	/** V86 mode GS.Attr invalid. */
338	#define VMX_IGS_V86_GS_ATTR_INVALID 571
339	/** Longmode CS.Base invalid. */
340	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
341	/** Longmode SS.Base invalid. */
342	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
343	/** Longmode DS.Base invalid. */
344	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
345	/** Longmode ES.Base invalid. */
346	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
347	/** SYSENTER ESP is not canonical. */
348	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
349	/** SYSENTER EIP is not canonical. */
350	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
351	/** PAT MSR invalid. */
352	#define VMX_IGS_PAT_MSR_INVALID 578
353	/** PAT MSR reserved bits not set to 0. */
354	#define VMX_IGS_PAT_MSR_RESERVED 579
355	/** GDTR.Base is not canonical. */
356	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
357	/** IDTR.Base is not canonical. */
358	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
359	/** GDTR.Limit invalid. */
360	#define VMX_IGS_GDTR_LIMIT_INVALID 582
361	/** IDTR.Limit invalid. */
362	#define VMX_IGS_IDTR_LIMIT_INVALID 583
363	/** Longmode RIP is invalid. */
364	#define VMX_IGS_LONGMODE_RIP_INVALID 584
365	/** RFLAGS reserved bits not set to 0. */
366	#define VMX_IGS_RFLAGS_RESERVED 585
367	/** RFLAGS RA1 reserved bits not set to 1. */
368	#define VMX_IGS_RFLAGS_RESERVED1 586
369	/** RFLAGS.VM (V86 mode) invalid. */
370	#define VMX_IGS_RFLAGS_VM_INVALID 587
371	/** RFLAGS.IF invalid. */
372	#define VMX_IGS_RFLAGS_IF_INVALID 588
373	/** Activity state invalid. */
374	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
375	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
376	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
377	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
378	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
379	/** Activity state SIPI WAIT invalid. */
380	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
381	/** Interruptibility state reserved bits not set to 0. */
382	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
383	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
384	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
385	/** Interruptibility state block-by-STI invalid for EFLAGS. */
386	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
387	/** Interruptibility state invalid while trying to deliver external
388	* interrupt. */
389	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
390	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
391	* NMI. */
392	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
393	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
394	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
395	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
396	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
397	/** Interruptibility state block-by-STI (maybe) invalid when trying to
398	* deliver an NMI. */
399	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
400	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
401	* active. */
402	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
403	/** Pending debug exceptions reserved bits not set to 0. */
404	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
405	/** Longmode pending debug exceptions reserved bits not set to 0. */
406	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
407	/** Pending debug exceptions.BS bit is not set when it should be. */
408	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
409	/** Pending debug exceptions.BS bit is not clear when it should be. */
410	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
411	/** VMCS link pointer reserved bits not set to 0. */
412	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
413	/** TR cannot index into LDT, TI bit MBZ. */
414	#define VMX_IGS_TR_TI_INVALID 607
415	/** LDTR cannot index into LDT. TI bit MBZ. */
416	#define VMX_IGS_LDTR_TI_INVALID 608
417	/** TR.Base is not canonical. */
418	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
419	/** FS.Base is not canonical. */
420	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
421	/** GS.Base is not canonical. */
422	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
423	/** LDTR.Base is not canonical. */
424	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
425	/** TR is unusable. */
426	#define VMX_IGS_TR_ATTR_UNUSABLE 613
427	/** TR.Attr.S bit invalid. */
428	#define VMX_IGS_TR_ATTR_S_INVALID 614
429	/** TR is not present. */
430	#define VMX_IGS_TR_ATTR_P_INVALID 615
431	/** TR.Attr reserved bits not set to 0. */
432	#define VMX_IGS_TR_ATTR_RESERVED 616
433	/** TR.Attr.G bit invalid. */
434	#define VMX_IGS_TR_ATTR_G_INVALID 617
435	/** Longmode TR.Attr.Type invalid. */
436	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
437	/** TR.Attr.Type invalid. */
438	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
439	/** CS.Attr.S invalid. */
440	#define VMX_IGS_CS_ATTR_S_INVALID 620
441	/** CS.Attr.DPL invalid. */
442	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
443	/** PAE PDPTE reserved bits not set to 0. */
444	#define VMX_IGS_PAE_PDPTE_RESERVED 623
445	/** @} */
446
447	/** @name VMX VMCS-Read cache indices.
448	* @{
449	*/
450	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
451	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
452	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
453	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
454	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
455	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
456	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
457	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
458	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
459	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
460	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
461	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
462	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
463	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
464	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
465	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
466	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
467	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
468	/** @} */
469
470	/** @name VMX EPT paging structures
471	* @{
472	*/
473
474	/**
475	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
476	*/
477	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
478
479	/**
480	* EPT Page Directory Pointer Entry. Bit view.
481	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
482	* this did cause trouble with one compiler/version).
483	*/
484	typedef struct EPTPML4EBITS
485	{
486	/** Present bit. */
487	uint64_t u1Present : 1;
488	/** Writable bit. */
489	uint64_t u1Write : 1;
490	/** Executable bit. */
491	uint64_t u1Execute : 1;
492	/** Reserved (must be 0). */
493	uint64_t u5Reserved : 5;
494	/** Available for software. */
495	uint64_t u4Available : 4;
496	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
497	uint64_t u40PhysAddr : 40;
498	/** Available for software. */
499	uint64_t u12Available : 12;
500	} EPTPML4EBITS;
501	AssertCompileSize(EPTPML4EBITS, 8);
502
503	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
504	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
505	/** The page shift to get the PML4 index. */
506	#define EPT_PML4_SHIFT X86_PML4_SHIFT
507	/** The PML4 index mask (apply to a shifted page address). */
508	#define EPT_PML4_MASK X86_PML4_MASK
509
510	/**
511	* EPT PML4E.
512	*/
513	typedef union EPTPML4E
514	{
515	/** Normal view. */
516	EPTPML4EBITS n;
517	/** Unsigned integer view. */
518	X86PGPAEUINT u;
519	/** 64 bit unsigned integer view. */
520	uint64_t au64[1];
521	/** 32 bit unsigned integer view. */
522	uint32_t au32[2];
523	} EPTPML4E;
524	AssertCompileSize(EPTPML4E, 8);
525	/** Pointer to a PML4 table entry. */
526	typedef EPTPML4E *PEPTPML4E;
527	/** Pointer to a const PML4 table entry. */
528	typedef const EPTPML4E *PCEPTPML4E;
529
530	/**
531	* EPT PML4 Table.
532	*/
533	typedef struct EPTPML4
534	{
535	EPTPML4E a[EPT_PG_ENTRIES];
536	} EPTPML4;
537	AssertCompileSize(EPTPML4, 0x1000);
538	/** Pointer to an EPT PML4 Table. */
539	typedef EPTPML4 *PEPTPML4;
540	/** Pointer to a const EPT PML4 Table. */
541	typedef const EPTPML4 *PCEPTPML4;
542
543	/**
544	* EPT Page Directory Pointer Entry. Bit view.
545	*/
546	typedef struct EPTPDPTEBITS
547	{
548	/** Present bit. */
549	uint64_t u1Present : 1;
550	/** Writable bit. */
551	uint64_t u1Write : 1;
552	/** Executable bit. */
553	uint64_t u1Execute : 1;
554	/** Reserved (must be 0). */
555	uint64_t u5Reserved : 5;
556	/** Available for software. */
557	uint64_t u4Available : 4;
558	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
559	uint64_t u40PhysAddr : 40;
560	/** Available for software. */
561	uint64_t u12Available : 12;
562	} EPTPDPTEBITS;
563	AssertCompileSize(EPTPDPTEBITS, 8);
564
565	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
566	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
567	/** The page shift to get the PDPT index. */
568	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
569	/** The PDPT index mask (apply to a shifted page address). */
570	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
571
572	/**
573	* EPT Page Directory Pointer.
574	*/
575	typedef union EPTPDPTE
576	{
577	/** Normal view. */
578	EPTPDPTEBITS n;
579	/** Unsigned integer view. */
580	X86PGPAEUINT u;
581	/** 64 bit unsigned integer view. */
582	uint64_t au64[1];
583	/** 32 bit unsigned integer view. */
584	uint32_t au32[2];
585	} EPTPDPTE;
586	AssertCompileSize(EPTPDPTE, 8);
587	/** Pointer to an EPT Page Directory Pointer Entry. */
588	typedef EPTPDPTE *PEPTPDPTE;
589	/** Pointer to a const EPT Page Directory Pointer Entry. */
590	typedef const EPTPDPTE *PCEPTPDPTE;
591
592	/**
593	* EPT Page Directory Pointer Table.
594	*/
595	typedef struct EPTPDPT
596	{
597	EPTPDPTE a[EPT_PG_ENTRIES];
598	} EPTPDPT;
599	AssertCompileSize(EPTPDPT, 0x1000);
600	/** Pointer to an EPT Page Directory Pointer Table. */
601	typedef EPTPDPT *PEPTPDPT;
602	/** Pointer to a const EPT Page Directory Pointer Table. */
603	typedef const EPTPDPT *PCEPTPDPT;
604
605
606	/**
607	* EPT Page Directory Table Entry. Bit view.
608	*/
609	typedef struct EPTPDEBITS
610	{
611	/** Present bit. */
612	uint64_t u1Present : 1;
613	/** Writable bit. */
614	uint64_t u1Write : 1;
615	/** Executable bit. */
616	uint64_t u1Execute : 1;
617	/** Reserved (must be 0). */
618	uint64_t u4Reserved : 4;
619	/** Big page (must be 0 here). */
620	uint64_t u1Size : 1;
621	/** Available for software. */
622	uint64_t u4Available : 4;
623	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
624	uint64_t u40PhysAddr : 40;
625	/** Available for software. */
626	uint64_t u12Available : 12;
627	} EPTPDEBITS;
628	AssertCompileSize(EPTPDEBITS, 8);
629
630	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
631	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
632	/** The page shift to get the PD index. */
633	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
634	/** The PD index mask (apply to a shifted page address). */
635	#define EPT_PD_MASK X86_PD_PAE_MASK
636
637	/**
638	* EPT 2MB Page Directory Table Entry. Bit view.
639	*/
640	typedef struct EPTPDE2MBITS
641	{
642	/** Present bit. */
643	uint64_t u1Present : 1;
644	/** Writable bit. */
645	uint64_t u1Write : 1;
646	/** Executable bit. */
647	uint64_t u1Execute : 1;
648	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
649	uint64_t u3EMT : 3;
650	/** Ignore PAT memory type */
651	uint64_t u1IgnorePAT : 1;
652	/** Big page (must be 1 here). */
653	uint64_t u1Size : 1;
654	/** Available for software. */
655	uint64_t u4Available : 4;
656	/** Reserved (must be 0). */
657	uint64_t u9Reserved : 9;
658	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
659	uint64_t u31PhysAddr : 31;
660	/** Available for software. */
661	uint64_t u12Available : 12;
662	} EPTPDE2MBITS;
663	AssertCompileSize(EPTPDE2MBITS, 8);
664
665	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
666	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
667
668	/**
669	* EPT Page Directory Table Entry.
670	*/
671	typedef union EPTPDE
672	{
673	/** Normal view. */
674	EPTPDEBITS n;
675	/** 2MB view (big). */
676	EPTPDE2MBITS b;
677	/** Unsigned integer view. */
678	X86PGPAEUINT u;
679	/** 64 bit unsigned integer view. */
680	uint64_t au64[1];
681	/** 32 bit unsigned integer view. */
682	uint32_t au32[2];
683	} EPTPDE;
684	AssertCompileSize(EPTPDE, 8);
685	/** Pointer to an EPT Page Directory Table Entry. */
686	typedef EPTPDE *PEPTPDE;
687	/** Pointer to a const EPT Page Directory Table Entry. */
688	typedef const EPTPDE *PCEPTPDE;
689
690	/**
691	* EPT Page Directory Table.
692	*/
693	typedef struct EPTPD
694	{
695	EPTPDE a[EPT_PG_ENTRIES];
696	} EPTPD;
697	AssertCompileSize(EPTPD, 0x1000);
698	/** Pointer to an EPT Page Directory Table. */
699	typedef EPTPD *PEPTPD;
700	/** Pointer to a const EPT Page Directory Table. */
701	typedef const EPTPD *PCEPTPD;
702
703
704	/**
705	* EPT Page Table Entry. Bit view.
706	*/
707	typedef struct EPTPTEBITS
708	{
709	/** 0 - Present bit.
710	* @remark This is a convenience "misnomer". The bit actually indicates
711	* read access and the CPU will consider an entry with any of the
712	* first three bits set as present. Since all our valid entries
713	* will have this bit set, it can be used as a present indicator
714	* and allow some code sharing. */
715	uint64_t u1Present : 1;
716	/** 1 - Writable bit. */
717	uint64_t u1Write : 1;
718	/** 2 - Executable bit. */
719	uint64_t u1Execute : 1;
720	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
721	uint64_t u3EMT : 3;
722	/** 6 - Ignore PAT memory type */
723	uint64_t u1IgnorePAT : 1;
724	/** 11:7 - Available for software. */
725	uint64_t u5Available : 5;
726	/** 51:12 - Physical address of page. Restricted by maximum physical
727	* address width of the cpu. */
728	uint64_t u40PhysAddr : 40;
729	/** 63:52 - Available for software. */
730	uint64_t u12Available : 12;
731	} EPTPTEBITS;
732	AssertCompileSize(EPTPTEBITS, 8);
733
734	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
735	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
736	/** The page shift to get the EPT PTE index. */
737	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
738	/** The EPT PT index mask (apply to a shifted page address). */
739	#define EPT_PT_MASK X86_PT_PAE_MASK
740
741	/**
742	* EPT Page Table Entry.
743	*/
744	typedef union EPTPTE
745	{
746	/** Normal view. */
747	EPTPTEBITS n;
748	/** Unsigned integer view. */
749	X86PGPAEUINT u;
750	/** 64 bit unsigned integer view. */
751	uint64_t au64[1];
752	/** 32 bit unsigned integer view. */
753	uint32_t au32[2];
754	} EPTPTE;
755	AssertCompileSize(EPTPTE, 8);
756	/** Pointer to an EPT Page Directory Table Entry. */
757	typedef EPTPTE *PEPTPTE;
758	/** Pointer to a const EPT Page Directory Table Entry. */
759	typedef const EPTPTE *PCEPTPTE;
760
761	/**
762	* EPT Page Table.
763	*/
764	typedef struct EPTPT
765	{
766	EPTPTE a[EPT_PG_ENTRIES];
767	} EPTPT;
768	AssertCompileSize(EPTPT, 0x1000);
769	/** Pointer to an extended page table. */
770	typedef EPTPT *PEPTPT;
771	/** Pointer to a const extended table. */
772	typedef const EPTPT *PCEPTPT;
773
774	/** @} */
775
776	/** VMX VPID flush types.
777	* @note Valid enum members are in accordance to the VT-x spec.
778	*/
779	typedef enum
780	{
781	/** Invalidate a specific page. */
782	VMXFLUSHVPID_INDIV_ADDR = 0,
783	/** Invalidate one context (specific VPID). */
784	VMXFLUSHVPID_SINGLE_CONTEXT = 1,
785	/** Invalidate all contexts (all VPIDs). */
786	VMXFLUSHVPID_ALL_CONTEXTS = 2,
787	/** Invalidate a single VPID context retaining global mappings. */
788	VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
789	/** Unsupported by VirtualBox. */
790	VMXFLUSHVPID_NOT_SUPPORTED = 0xbad0,
791	/** Unsupported by CPU. */
792	VMXFLUSHVPID_NONE = 0xbad1
793	} VMXFLUSHVPID;
794	AssertCompileSize(VMXFLUSHVPID, 4);
795
796	/** VMX EPT flush types.
797	* @note Valid enums values are in accordance to the VT-x spec.
798	*/
799	typedef enum
800	{
801	/** Invalidate one context (specific EPT). */
802	VMXFLUSHEPT_SINGLE_CONTEXT = 1,
803	/* Invalidate all contexts (all EPTs) */
804	VMXFLUSHEPT_ALL_CONTEXTS = 2,
805	/** Unsupported by VirtualBox. */
806	VMXFLUSHEPT_NOT_SUPPORTED = 0xbad0,
807	/** Unsupported by CPU. */
808	VMXFLUSHEPT_NONE = 0xbad1
809	} VMXFLUSHEPT;
810	AssertCompileSize(VMXFLUSHEPT, 4);
811
812	/** VMX Posted Interrupt Descriptor.
813	* In accordance to the VT-x spec.
814	*/
815	typedef struct VMXPOSTEDINTRDESC
816	{
817	uint32_t aVectorBitmap[8];
818	uint32_t fOutstandingNotification : 1;
819	uint32_t uReserved0 : 31;
820	uint8_t au8Reserved0[28];
821	} VMXPOSTEDINTRDESC;
822	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
823	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
824	/** Pointer to a posted interrupt descriptor. */
825	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
826	/** Pointer to a const posted interrupt descriptor. */
827	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
828
829	/** VMX MSR autoload/store element.
830	* In accordance to the VT-x spec.
831	*/
832	typedef struct VMXAUTOMSR
833	{
834	/** The MSR Id. */
835	uint32_t u32Msr;
836	/** Reserved (MBZ). */
837	uint32_t u32Reserved;
838	/** The MSR value. */
839	uint64_t u64Value;
840	} VMXAUTOMSR;
841	AssertCompileSize(VMXAUTOMSR, 16);
842	/** Pointer to an MSR load/store element. */
843	typedef VMXAUTOMSR *PVMXAUTOMSR;
844	/** Pointer to a const MSR load/store element. */
845	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
846
847	/**
848	* VMX-capability qword
849	*/
850	typedef union
851	{
852	struct
853	{
854	/** Bits set here -must- be set in the corresponding VM-execution controls. */
855	uint32_t disallowed0;
856	/** Bits cleared here -must- be cleared in the corresponding VM-execution
857	* controls. */
858	uint32_t allowed1;
859	} n;
860	uint64_t u;
861	} VMXCAPABILITY;
862	AssertCompileSize(VMXCAPABILITY, 8);
863
864	/**
865	* VMX MSRs.
866	*/
867	typedef struct VMXMSRS
868	{
869	uint64_t u64FeatureCtrl;
870	uint64_t u64BasicInfo;
871	VMXCAPABILITY VmxPinCtls;
872	VMXCAPABILITY VmxProcCtls;
873	VMXCAPABILITY VmxProcCtls2;
874	VMXCAPABILITY VmxExit;
875	VMXCAPABILITY VmxEntry;
876	uint64_t u64Misc;
877	uint64_t u64Cr0Fixed0;
878	uint64_t u64Cr0Fixed1;
879	uint64_t u64Cr4Fixed0;
880	uint64_t u64Cr4Fixed1;
881	uint64_t u64VmcsEnum;
882	uint64_t u64Vmfunc;
883	uint64_t u64EptVpidCaps;
884	} VMXMSRS;
885	AssertCompileSizeAlignment(VMXMSRS, 8);
886	/** Pointer to a VMXMSRS struct. */
887	typedef VMXMSRS *PVMXMSRS;
888
889	/** @name VMX EFLAGS reserved bits.
890	* @{
891	*/
892	/** And-mask for setting reserved bits to zero */
893	#define VMX_EFLAGS_RESERVED_0 (X86_EFL_1 \| X86_EFL_LIVE_MASK)
894	/** Or-mask for setting reserved bits to 1 */
895	#define VMX_EFLAGS_RESERVED_1 X86_EFL_1
896	/** @} */
897
898	/** @name VMX Basic Exit Reasons.
899	* @{
900	*/
901	/** -1 Invalid exit code */
902	#define VMX_EXIT_INVALID -1
903	/** 0 Exception or non-maskable interrupt (NMI). */
904	#define VMX_EXIT_XCPT_OR_NMI 0
905	/** 1 External interrupt. */
906	#define VMX_EXIT_EXT_INT 1
907	/** 2 Triple fault. */
908	#define VMX_EXIT_TRIPLE_FAULT 2
909	/** 3 INIT signal. */
910	#define VMX_EXIT_INIT_SIGNAL 3
911	/** 4 Start-up IPI (SIPI). */
912	#define VMX_EXIT_SIPI 4
913	/** 5 I/O system-management interrupt (SMI). */
914	#define VMX_EXIT_IO_SMI 5
915	/** 6 Other SMI. */
916	#define VMX_EXIT_SMI 6
917	/** 7 Interrupt window exiting. */
918	#define VMX_EXIT_INT_WINDOW 7
919	/** 8 NMI window exiting. */
920	#define VMX_EXIT_NMI_WINDOW 8
921	/** 9 Task switch. */
922	#define VMX_EXIT_TASK_SWITCH 9
923	/** 10 Guest software attempted to execute CPUID. */
924	#define VMX_EXIT_CPUID 10
925	/** 11 Guest software attempted to execute GETSEC. */
926	#define VMX_EXIT_GETSEC 11
927	/** 12 Guest software attempted to execute HLT. */
928	#define VMX_EXIT_HLT 12
929	/** 13 Guest software attempted to execute INVD. */
930	#define VMX_EXIT_INVD 13
931	/** 14 Guest software attempted to execute INVLPG. */
932	#define VMX_EXIT_INVLPG 14
933	/** 15 Guest software attempted to execute RDPMC. */
934	#define VMX_EXIT_RDPMC 15
935	/** 16 Guest software attempted to execute RDTSC. */
936	#define VMX_EXIT_RDTSC 16
937	/** 17 Guest software attempted to execute RSM in SMM. */
938	#define VMX_EXIT_RSM 17
939	/** 18 Guest software executed VMCALL. */
940	#define VMX_EXIT_VMCALL 18
941	/** 19 Guest software executed VMCLEAR. */
942	#define VMX_EXIT_VMCLEAR 19
943	/** 20 Guest software executed VMLAUNCH. */
944	#define VMX_EXIT_VMLAUNCH 20
945	/** 21 Guest software executed VMPTRLD. */
946	#define VMX_EXIT_VMPTRLD 21
947	/** 22 Guest software executed VMPTRST. */
948	#define VMX_EXIT_VMPTRST 22
949	/** 23 Guest software executed VMREAD. */
950	#define VMX_EXIT_VMREAD 23
951	/** 24 Guest software executed VMRESUME. */
952	#define VMX_EXIT_VMRESUME 24
953	/** 25 Guest software executed VMWRITE. */
954	#define VMX_EXIT_VMWRITE 25
955	/** 26 Guest software executed VMXOFF. */
956	#define VMX_EXIT_VMXOFF 26
957	/** 27 Guest software executed VMXON. */
958	#define VMX_EXIT_VMXON 27
959	/** 28 Control-register accesses. */
960	#define VMX_EXIT_MOV_CRX 28
961	/** 29 Debug-register accesses. */
962	#define VMX_EXIT_MOV_DRX 29
963	/** 30 I/O instruction. */
964	#define VMX_EXIT_IO_INSTR 30
965	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
966	#define VMX_EXIT_RDMSR 31
967	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
968	#define VMX_EXIT_WRMSR 32
969	/** 33 VM-entry failure due to invalid guest state. */
970	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
971	/** 34 VM-entry failure due to MSR loading. */
972	#define VMX_EXIT_ERR_MSR_LOAD 34
973	/** 36 Guest software executed MWAIT. */
974	#define VMX_EXIT_MWAIT 36
975	/** 37 VM-exit due to monitor trap flag. */
976	#define VMX_EXIT_MTF 37
977	/** 39 Guest software attempted to execute MONITOR. */
978	#define VMX_EXIT_MONITOR 39
979	/** 40 Guest software attempted to execute PAUSE. */
980	#define VMX_EXIT_PAUSE 40
981	/** 41 VM-entry failure due to machine-check. */
982	#define VMX_EXIT_ERR_MACHINE_CHECK 41
983	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
984	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
985	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
986	#define VMX_EXIT_APIC_ACCESS 44
987	/** 45 Virtualized EOI. EOI virtualization was performed for a virtual interrupt
988	whose vector indexed a bit set in the EOI-exit bitmap. */
989	#define VMX_EXIT_VIRTUALIZED_EOI 45
990	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
991	#define VMX_EXIT_XDTR_ACCESS 46
992	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
993	#define VMX_EXIT_TR_ACCESS 47
994	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
995	#define VMX_EXIT_EPT_VIOLATION 48
996	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
997	#define VMX_EXIT_EPT_MISCONFIG 49
998	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
999	#define VMX_EXIT_INVEPT 50
1000	/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
1001	#define VMX_EXIT_RDTSCP 51
1002	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
1003	#define VMX_EXIT_PREEMPT_TIMER 52
1004	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1005	#define VMX_EXIT_INVVPID 53
1006	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1007	#define VMX_EXIT_WBINVD 54
1008	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1009	#define VMX_EXIT_XSETBV 55
1010	/** 56 APIC write. Guest completed write to virtual-APIC. */
1011	#define VMX_EXIT_APIC_WRITE 56
1012	/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1013	#define VMX_EXIT_RDRAND 57
1014	/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1015	#define VMX_EXIT_INVPCID 58
1016	/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1017	#define VMX_EXIT_VMFUNC 59
1018	/** 60 ENCLS. Guest software attempted to execute ENCLS. */
1019	#define VMX_EXIT_ENCLS 60
1020	/** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
1021	* enabled. */
1022	#define VMX_EXIT_RDSEED 61
1023	/** 62 - Page-modification log full. */
1024	#define VMX_EXIT_PML_FULL 62
1025	/** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
1026	* enabled (XSAVES/XRSTORS was enabled too, of course). */
1027	#define VMX_EXIT_XSAVES 63
1028	/** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
1029	* was enabled (XSAVES/XRSTORS was enabled too, of course). */
1030	#define VMX_EXIT_XRSTORS 64
1031	/** The maximum exit value (inclusive). */
1032	#define VMX_EXIT_MAX (VMX_EXIT_XRSTORS)
1033	/** @} */
1034
1035
1036	/** @name VM Instruction Errors
1037	* @{
1038	*/
1039	/** VMCALL executed in VMX root operation. */
1040	#define VMX_ERROR_VMCALL 1
1041	/** VMCLEAR with invalid physical address. */
1042	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1043	/** VMCLEAR with VMXON pointer. */
1044	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1045	/** VMLAUNCH with non-clear VMCS. */
1046	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1047	/** VMRESUME with non-launched VMCS. */
1048	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1049	/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1050	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1051	/** VM-entry with invalid control field(s). */
1052	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1053	/** VM-entry with invalid host-state field(s). */
1054	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1055	/** VMPTRLD with invalid physical address. */
1056	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1057	/** VMPTRLD with VMXON pointer. */
1058	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1059	/** VMPTRLD with incorrect VMCS revision identifier. */
1060	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1061	/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1062	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1063	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1064	/** VMWRITE to read-only VMCS component. */
1065	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1066	/** VMXON executed in VMX root operation. */
1067	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1068	/** VM-entry with invalid executive-VMCS pointer. */
1069	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1070	/** VM-entry with non-launched executive VMCS. */
1071	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1072	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1073	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1074	/** VMCALL with non-clear VMCS. */
1075	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1076	/** VMCALL with invalid VM-exit control fields. */
1077	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1078	/** VMCALL with incorrect MSEG revision identifier. */
1079	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1080	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1081	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1082	/** VMCALL with invalid SMM-monitor features. */
1083	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1084	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1085	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1086	/** VM-entry with events blocked by MOV SS. */
1087	#define VMX_ERROR_VMENTRY_MOV_SS 26
1088	/** Invalid operand to INVEPT/INVVPID. */
1089	#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1090	/** @} */
1091
1092
1093	/** @name VMX MSRs - Basic VMX information.
1094	* @{
1095	*/
1096	/** VMCS revision identifier used by the processor. */
1097	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) ((a) & 0x7FFFFFFF)
1098	/** Size of the VMCS. */
1099	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0x1FFF)
1100	/** Width of physical address used for the VMCS.
1101	* 0 -> limited to the available amount of physical ram
1102	* 1 -> within the first 4 GB
1103	*/
1104	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1105	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1106	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1107	/** Memory type that must be used for the VMCS. */
1108	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1109	/** Whether the processor provides additional information for exits due to INS/OUTS. */
1110	#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1111	/** @} */
1112
1113
1114	/** @name VMX MSRs - Misc VMX info.
1115	* @{
1116	*/
1117	/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1118	#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1119	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1120	#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1121	/** Activity states supported by the implementation. */
1122	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1123	/** Number of CR3 target values supported by the processor. (0-256) */
1124	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1125	/** Maximum number of MSRs in the VMCS. (N+1)512. /
1126	#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1127	/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1128	#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1129	/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1130	#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1131	/** Whether VMWRITE can be used to write VM-exit information fields. */
1132	#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1133	/** MSEG revision identifier used by the processor. */
1134	#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1135	/** @} */
1136
1137
1138	/** @name VMX MSRs - VMCS enumeration field info
1139	* @{
1140	*/
1141	/** Highest field index. */
1142	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1143	/** @} */
1144
1145
1146	/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1147	* @{
1148	*/
1149	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1150	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1151	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1152	#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1153	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1154	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1155	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1156	#define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21)
1157	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1158	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1159	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1160	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1161	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1162	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1163	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1164	/** @} */
1165
1166	/** @name Extended Page Table Pointer (EPTP)
1167	* @{
1168	*/
1169	/** Uncachable EPT paging structure memory type. */
1170	#define VMX_EPT_MEMTYPE_UC 0
1171	/** Write-back EPT paging structure memory type. */
1172	#define VMX_EPT_MEMTYPE_WB 6
1173	/** Shift value to get the EPT page walk length (bits 5-3) */
1174	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1175	/** Mask value to get the EPT page walk length (bits 5-3) */
1176	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1177	/** Default EPT page-walk length (1 less than the actual EPT page-walk
1178	* length) */
1179	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1180	/** @} */
1181
1182
1183	/** @name VMCS field encoding - 16 bits guest fields
1184	* @{
1185	*/
1186	#define VMX_VMCS16_VPID 0x000
1187	#define VMX_VMCS16_POSTED_INTR_NOTIFY_VECTOR 0x002
1188	#define VMX_VMCS16_EPTP_INDEX 0x004
1189	#define VMX_VMCS16_GUEST_ES_SEL 0x800
1190	#define VMX_VMCS16_GUEST_CS_SEL 0x802
1191	#define VMX_VMCS16_GUEST_SS_SEL 0x804
1192	#define VMX_VMCS16_GUEST_DS_SEL 0x806
1193	#define VMX_VMCS16_GUEST_FS_SEL 0x808
1194	#define VMX_VMCS16_GUEST_GS_SEL 0x80A
1195	#define VMX_VMCS16_GUEST_LDTR_SEL 0x80C
1196	#define VMX_VMCS16_GUEST_TR_SEL 0x80E
1197	#define VMX_VMCS16_GUEST_INTR_STATUS 0x810
1198	/** @} */
1199
1200	/** @name VMCS field encoding - 16 bits host fields
1201	* @{
1202	*/
1203	#define VMX_VMCS16_HOST_ES_SEL 0xC00
1204	#define VMX_VMCS16_HOST_CS_SEL 0xC02
1205	#define VMX_VMCS16_HOST_SS_SEL 0xC04
1206	#define VMX_VMCS16_HOST_DS_SEL 0xC06
1207	#define VMX_VMCS16_HOST_FS_SEL 0xC08
1208	#define VMX_VMCS16_HOST_GS_SEL 0xC0A
1209	#define VMX_VMCS16_HOST_TR_SEL 0xC0C
1210	/** @} */
1211
1212	/** @name VMCS field encoding - 64 bits host fields
1213	* @{
1214	*/
1215	#define VMX_VMCS64_HOST_PAT_FULL 0x2C00
1216	#define VMX_VMCS64_HOST_PAT_HIGH 0x2C01
1217	#define VMX_VMCS64_HOST_EFER_FULL 0x2C02
1218	#define VMX_VMCS64_HOST_EFER_HIGH 0x2C03
1219	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
1220	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
1221	/** @} */
1222
1223
1224	/** @name VMCS field encoding - 64 Bits control fields
1225	* @{
1226	*/
1227	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1228	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1229	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1230	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1231
1232	/* Optional */
1233	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1234	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1235
1236	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1237	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1238	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1239	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1240
1241	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1242	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1243
1244	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1245	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1246
1247	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1248	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1249
1250	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1251	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1252	#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1253
1254	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1255	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1256	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1257
1258	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1259	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1260	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1261
1262	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1263	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1264	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1265
1266	/** Extended page table pointer. */
1267	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201A
1268	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201B
1269
1270	/** EOI-exit bitmap 0. */
1271	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201C
1272	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201D
1273
1274	/** EOI-exit bitmap 1. */
1275	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201E
1276	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201F
1277
1278	/** EOI-exit bitmap 2. */
1279	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1280	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1281
1282	/** EOI-exit bitmap 3. */
1283	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1284	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1285
1286	/** Extended page table pointer lists. */
1287	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1288	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1289
1290	/** VM-read bitmap. */
1291	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1292	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
1293
1294	/** VM-write bitmap. */
1295	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
1296	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
1297
1298	/** Virtualization-exception information address. */
1299	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL 0x202A
1300	#define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH 0x202B
1301
1302	/** XSS-exiting bitmap. */
1303	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202C
1304	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202D
1305
1306	/** TSC multiplier. */
1307	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
1308	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
1309
1310	/** VM-exit guest physical address. */
1311	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1312	#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1313	/** @} */
1314
1315
1316	/** @name VMCS field encoding - 64 Bits guest fields
1317	* @{
1318	*/
1319	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1320	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1321	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
1322	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
1323	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1324	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1325	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1326	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1327	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
1328	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
1329	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1330	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1331	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1332	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1333	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1334	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1335	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1336	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1337	/** @} */
1338
1339
1340	/** @name VMCS field encoding - 32 Bits control fields
1341	* @{
1342	*/
1343	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1344	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1345	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1346	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1347	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1348	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1349	#define VMX_VMCS32_CTRL_EXIT 0x400C
1350	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1351	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1352	#define VMX_VMCS32_CTRL_ENTRY 0x4012
1353	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1354	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1355	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1356	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1357	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1358	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1359	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
1360	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
1361	/** @} */
1362
1363
1364	/** @name VMX_VMCS_CTRL_PIN_EXEC
1365	* @{
1366	*/
1367	/** External interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1368	#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1369	/** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through the guest's IDT. */
1370	#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1371	/** Virtual NMIs. */
1372	#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1373	/** Activate VMX preemption timer. */
1374	#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1375	/** Process interrupts with the posted-interrupt notification vector. */
1376	#define VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR RT_BIT(7)
1377	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1378	/** @} */
1379
1380	/** @name VMX_VMCS_CTRL_PROC_EXEC
1381	* @{
1382	*/
1383	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
1384	#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1385	/** Use timestamp counter offset. */
1386	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1387	/** VM-exit when executing the HLT instruction. */
1388	#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1389	/** VM-exit when executing the INVLPG instruction. */
1390	#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1391	/** VM-exit when executing the MWAIT instruction. */
1392	#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1393	/** VM-exit when executing the RDPMC instruction. */
1394	#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1395	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
1396	#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1397	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1398	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1399	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1400	#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1401	/** VM-exit on CR8 loads. */
1402	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1403	/** VM-exit on CR8 stores. */
1404	#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1405	/** Use TPR shadow. */
1406	#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1407	/** VM-exit when virtual NMI blocking is disabled. */
1408	#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1409	/** VM-exit when executing a MOV DRx instruction. */
1410	#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1411	/** VM-exit when executing IO instructions. */
1412	#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1413	/** Use IO bitmaps. */
1414	#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1415	/** Monitor trap flag. */
1416	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1417	/** Use MSR bitmaps. */
1418	#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1419	/** VM-exit when executing the MONITOR instruction. */
1420	#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1421	/** VM-exit when executing the PAUSE instruction. */
1422	#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1423	/** Determines whether the secondary processor based VM-execution controls are used. */
1424	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1425	/** @} */
1426
1427	/** @name VMX_VMCS_CTRL_PROC_EXEC2
1428	* @{
1429	*/
1430	/** Virtualize APIC access. */
1431	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1432	/** EPT supported/enabled. */
1433	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1434	/** Descriptor table instructions cause VM-exits. */
1435	#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1436	/** RDTSCP supported/enabled. */
1437	#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1438	/** Virtualize x2APIC mode. */
1439	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1440	/** VPID supported/enabled. */
1441	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1442	/** VM-exit when executing the WBINVD instruction. */
1443	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1444	/** Unrestricted guest execution. */
1445	#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1446	/** APIC register virtualization. */
1447	#define VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT RT_BIT(8)
1448	/** Virtual-interrupt delivery. */
1449	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY RT_BIT(9)
1450	/** A specified number of pause loops cause a VM-exit. */
1451	#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1452	/** VM-exit when executing RDRAND instructions. */
1453	#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1454	/** Enables INVPCID instructions. */
1455	#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1456	/** Enables VMFUNC instructions. */
1457	#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1458	/** Enables VMCS shadowing. */
1459	#define VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING RT_BIT(14)
1460	/** Enables ENCLS VM-exits. */
1461	#define VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT RT_BIT(15)
1462	/** VM-exit when executing RDSEED. */
1463	#define VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT RT_BIT(16)
1464	/** Enables page-modification logging. */
1465	#define VMX_VMCS_CTRL_PROC_EXEC2_PML RT_BIT(17)
1466	/** Controls whether EPT-violations may cause \#VE instead of exits. */
1467	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE RT_BIT(18)
1468	/** Conceal VMX non-root operation from Intel processor trace (PT). */
1469	#define VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT RT_BIT(19)
1470	/** Enables XSAVES/XRSTORS instructions. */
1471	#define VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS RT_BIT(20)
1472	/** Use TSC scaling. */
1473	#define VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING RT_BIT(25)
1474
1475	/** @} */
1476
1477
1478	/** @name VMX_VMCS_CTRL_ENTRY
1479	* @{
1480	*/
1481	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1482	#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1483	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1484	#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1485	/** In SMM mode after VM-entry. */
1486	#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1487	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1488	#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1489	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
1490	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1491	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
1492	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1493	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
1494	#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1495	/** @} */
1496
1497
1498	/** @name VMX_VMCS_CTRL_EXIT
1499	* @{
1500	*/
1501	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1502	#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1503	/** Return to long mode after a VM-exit. */
1504	#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1505	/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
1506	#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1507	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1508	#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1509	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
1510	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1511	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
1512	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1513	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
1514	#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1515	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
1516	#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1517	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
1518	#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1519	/** @} */
1520
1521
1522	/** @name VMX_VMCS_CTRL_VMFUNC
1523	* @{
1524	*/
1525	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1526	#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1527	/** @} */
1528
1529
1530	/** @name VMCS field encoding - 32 Bits read-only fields
1531	* @{
1532	*/
1533	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1534	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1535	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1536	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1537	#define VMX_VMCS32_RO_IDT_INFO 0x4408
1538	#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1539	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1540	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1541	/** @} */
1542
1543	/** @name VMX_VMCS32_RO_EXIT_REASON
1544	* @{
1545	*/
1546	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
1547	/** @} */
1548
1549	/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1550	* @{
1551	*/
1552	#define VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1553	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1554	#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1555	/** @} */
1556
1557
1558	/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1559	* @{
1560	*/
1561	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff)
1562	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1563	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1564	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1565	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1566	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(a) ((a) & RT_BIT(12))
1567	#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1568	#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) RT_BOOL((a) & RT_BIT(31))
1569	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1570	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
1571	/** @} */
1572
1573	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1574	* @{
1575	*/
1576	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1577	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1578	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1579	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4
1580	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT 5
1581	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1582	/** @} */
1583
1584	/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1585	* @{
1586	*/
1587	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
1588	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1589	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1590	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1591	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) RT_BOOL((a) & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1592	#define VMX_IDT_VECTORING_INFO_VALID(a) ((a) & RT_BIT(31))
1593	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
1594	/** @} */
1595
1596	/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1597	* @{
1598	*/
1599	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1600	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1601	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1602	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1603	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1604	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1605	/** @} */
1606
1607
1608	/** @name VMCS field encoding - 32 Bits guest state fields
1609	* @{
1610	*/
1611	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1612	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1613	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1614	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1615	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1616	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1617	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1618	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1619	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1620	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1621	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1622	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1623	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1624	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1625	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1626	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1627	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1628	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1629	#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1630	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1631	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
1632	#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1633	/** @} */
1634
1635
1636	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1637	* @{
1638	*/
1639	/** The logical processor is active. */
1640	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1641	/** The logical processor is inactive, because executed a HLT instruction. */
1642	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1643	/** The logical processor is inactive, because of a triple fault or other serious error. */
1644	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1645	/** The logical processor is inactive, because it's waiting for a startup-IPI */
1646	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1647	/** @} */
1648
1649
1650	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1651	* @{
1652	*/
1653	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1654	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1655	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1656	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1657	/** @} */
1658
1659
1660	/** @name VMCS field encoding - 32 Bits host state fields
1661	* @{
1662	*/
1663	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1664	/** @} */
1665
1666	/** @name Natural width control fields
1667	* @{
1668	*/
1669	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1670	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1671	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1672	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1673	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1674	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1675	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1676	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1677	/** @} */
1678
1679
1680	/** @name Natural width read-only data fields
1681	* @{
1682	*/
1683	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1684	#define VMX_VMCS_RO_IO_RCX 0x6402
1685	#define VMX_VMCS_RO_IO_RSX 0x6404
1686	#define VMX_VMCS_RO_IO_RDI 0x6406
1687	#define VMX_VMCS_RO_IO_RIP 0x6408
1688	#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1689	/** @} */
1690
1691
1692	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1693	* @{
1694	*/
1695	/** 0-2: Debug register number */
1696	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) ((a) & 7)
1697	/** 3: Reserved; cleared to 0. */
1698	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) (((a) >> 3) & 1)
1699	/** 4: Direction of move (0 = write, 1 = read) */
1700	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) (((a) >> 4) & 1)
1701	/** 5-7: Reserved; cleared to 0. */
1702	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) (((a) >> 5) & 7)
1703	/** 8-11: General purpose register number. */
1704	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) (((a) >> 8) & 0xF)
1705	/** Rest: reserved. */
1706	/** @} */
1707
1708	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1709	* @{
1710	*/
1711	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1712	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1713	/** @} */
1714
1715
1716
1717	/** @name CRx accesses
1718	* @{
1719	*/
1720	/** 0-3: Control register number (0 for CLTS & LMSW) */
1721	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) ((a) & 0xF)
1722	/** 4-5: Access type. */
1723	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) (((a) >> 4) & 3)
1724	/** 6: LMSW operand type */
1725	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) (((a) >> 6) & 1)
1726	/** 7: Reserved; cleared to 0. */
1727	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) (((a) >> 7) & 1)
1728	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1729	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) (((a) >> 8) & 0xF)
1730	/** 12-15: Reserved; cleared to 0. */
1731	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) (((a) >> 12) & 0xF)
1732	/** 16-31: LMSW source data (else 0). */
1733	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) (((a) >> 16) & 0xFFFF)
1734	/* Rest: reserved. */
1735	/** @} */
1736
1737	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1738	* @{
1739	*/
1740	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1741	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1742	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1743	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1744	/** @} */
1745
1746	/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1747	* @{
1748	*/
1749	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
1750	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
1751	/** Task switch caused by a call instruction. */
1752	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1753	/** Task switch caused by an iret instruction. */
1754	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1755	/** Task switch caused by a jmp instruction. */
1756	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1757	/** Task switch caused by an interrupt gate. */
1758	#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1759	/** @} */
1760
1761
1762	/** @name VMX_EXIT_EPT_VIOLATION
1763	* @{
1764	*/
1765	/** Set if the violation was caused by a data read. */
1766	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1767	/** Set if the violation was caused by a data write. */
1768	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1769	/** Set if the violation was caused by an instruction fetch. */
1770	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1771	/** AND of the present bit of all EPT structures. */
1772	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1773	/** AND of the write bit of all EPT structures. */
1774	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1775	/** AND of the execute bit of all EPT structures. */
1776	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1777	/** Set if the guest linear address field contains the faulting address. */
1778	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1779	/** If bit 7 is one: (reserved otherwise)
1780	* 1 - violation due to physical address access.
1781	* 0 - violation caused by page walk or access/dirty bit updates
1782	*/
1783	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1784	/** @} */
1785
1786
1787	/** @name VMX_EXIT_PORT_IO
1788	* @{
1789	*/
1790	/** 0-2: IO operation width. */
1791	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1792	/** 3: IO operation direction. */
1793	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1794	/** 4: String IO operation (INS / OUTS). */
1795	#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1796	/** 5: Repeated IO operation. */
1797	#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1798	/** 6: Operand encoding. */
1799	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1800	/** 16-31: IO Port (0-0xffff). */
1801	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1802	/* Rest reserved. */
1803	/** @} */
1804
1805	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1806	* @{
1807	*/
1808	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1809	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1810	/** @} */
1811
1812
1813	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1814	* @{
1815	*/
1816	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1817	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1818	/** @} */
1819
1820	/** @name VMX_EXIT_APIC_ACCESS
1821	* @{
1822	*/
1823	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of access within the APIC page. */
1824	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1825	/** 12-15: Access type. */
1826	#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
1827	/* Rest reserved. */
1828	/** @} */
1829
1830
1831	/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE return values
1832	* @{
1833	*/
1834	/** Linear read access. */
1835	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1836	/** Linear write access. */
1837	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1838	/** Linear instruction fetch access. */
1839	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1840	/** Linear read/write access during event delivery. */
1841	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1842	/** Physical read/write access during event delivery. */
1843	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1844	/** Physical access for an instruction fetch or during instruction execution. */
1845	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1846	/** @} */
1847
1848	/** @name VMX_XDTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information
1849	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1850	* @{
1851	*/
1852	/** Address calculation scaling field (powers of two). */
1853	#define VMX_XDTR_INSINFO_SCALE_SHIFT 0
1854	#define VMX_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1855	/** Bits 2 thru 6 are undefined. */
1856	#define VMX_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
1857	#define VMX_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
1858	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1859	* @remarks anyone's guess why this is a 3 bit field... */
1860	#define VMX_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
1861	#define VMX_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1862	/** Bit 10 is defined as zero. */
1863	#define VMX_XDTR_INSINFO_ZERO_10_SHIFT 10
1864	#define VMX_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
1865	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
1866	* for exits from 64-bit code as the operand size there is fixed. */
1867	#define VMX_XDTR_INSINFO_OP_SIZE_SHIFT 11
1868	#define VMX_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
1869	/** Bits 12 thru 14 are undefined. */
1870	#define VMX_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
1871	#define VMX_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
1872	/** Applicable segment register (X86_SREG_XXX values). */
1873	#define VMX_XDTR_INSINFO_SREG_SHIFT 15
1874	#define VMX_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1875	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1876	#define VMX_XDTR_INSINFO_INDEX_REG_SHIFT 18
1877	#define VMX_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1878	/** Is VMX_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1879	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1880	#define VMX_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1881	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1882	#define VMX_XDTR_INSINFO_BASE_REG_SHIFT 23
1883	#define VMX_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1884	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
1885	#define VMX_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
1886	#define VMX_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
1887	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values) */
1888	#define VMX_XDTR_INSINFO_INSTR_ID_SHIFT 28
1889	#define VMX_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
1890	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
1891	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
1892	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
1893	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
1894	/** Bits 30 & 31 are undefined. */
1895	#define VMX_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
1896	#define VMX_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
1897	RT_BF_ASSERT_COMPILE_CHECKS(VMX_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
1898	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
1899	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
1900	/** @} */
1901
1902
1903	/** @name VMX_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information
1904	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
1905	* This is similar to VMX_XDTR_INSINFO_XXX.
1906	* @{
1907	*/
1908	/** Address calculation scaling field (powers of two). */
1909	#define VMX_YYTR_INSINFO_SCALE_SHIFT 0
1910	#define VMX_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
1911	/** Bit 2 is undefined. */
1912	#define VMX_YYTR_INSINFO_UNDEF_2_SHIFT 2
1913	#define VMX_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
1914	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
1915	#define VMX_YYTR_INSINFO_REG1_SHIFT 3
1916	#define VMX_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
1917	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
1918	* @remarks anyone's guess why this is a 3 bit field... */
1919	#define VMX_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
1920	#define VMX_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
1921	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
1922	#define VMX_YYTR_INSINFO_HAS_REG1_SHIFT 10
1923	#define VMX_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
1924	/** Bits 11 thru 14 are undefined. */
1925	#define VMX_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
1926	#define VMX_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
1927	/** Applicable segment register (X86_SREG_XXX values). */
1928	#define VMX_YYTR_INSINFO_SREG_SHIFT 15
1929	#define VMX_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
1930	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
1931	#define VMX_YYTR_INSINFO_INDEX_REG_SHIFT 18
1932	#define VMX_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
1933	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
1934	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
1935	#define VMX_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
1936	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
1937	#define VMX_YYTR_INSINFO_BASE_REG_SHIFT 23
1938	#define VMX_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
1939	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
1940	#define VMX_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
1941	#define VMX_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
1942	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
1943	#define VMX_YYTR_INSINFO_INSTR_ID_SHIFT 28
1944	#define VMX_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
1945	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
1946	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
1947	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
1948	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
1949	/** Bits 30 & 31 are undefined. */
1950	#define VMX_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
1951	#define VMX_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
1952	RT_BF_ASSERT_COMPILE_CHECKS(VMX_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
1953	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
1954	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
1955	/** @} */
1956
1957
1958	/** @name VMCS field encoding - Natural width guest state fields
1959	* @{
1960	*/
1961	#define VMX_VMCS_GUEST_CR0 0x6800
1962	#define VMX_VMCS_GUEST_CR3 0x6802
1963	#define VMX_VMCS_GUEST_CR4 0x6804
1964	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1965	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1966	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1967	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1968	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1969	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1970	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1971	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1972	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1973	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1974	#define VMX_VMCS_GUEST_DR7 0x681A
1975	#define VMX_VMCS_GUEST_RSP 0x681C
1976	#define VMX_VMCS_GUEST_RIP 0x681E
1977	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1978	#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1979	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1980	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1981	/** @} */
1982
1983
1984	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1985	* Bits 4-11, 13 and 15-63 are reserved.
1986	* @{
1987	*/
1988	/** Hardware breakpoint 0 was met. */
1989	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1990	/** Hardware breakpoint 1 was met. */
1991	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1992	/** Hardware breakpoint 2 was met. */
1993	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1994	/** Hardware breakpoint 3 was met. */
1995	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1996	/** At least one data or IO breakpoint was hit. */
1997	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1998	/** A debug exception would have been triggered by single-step execution mode. */
1999	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
2000	/** @} */
2001
2002	/** @name VMCS field encoding - Natural width host state fields
2003	* @{
2004	*/
2005	#define VMX_VMCS_HOST_CR0 0x6C00
2006	#define VMX_VMCS_HOST_CR3 0x6C02
2007	#define VMX_VMCS_HOST_CR4 0x6C04
2008	#define VMX_VMCS_HOST_FS_BASE 0x6C06
2009	#define VMX_VMCS_HOST_GS_BASE 0x6C08
2010	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
2011	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
2012	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
2013	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
2014	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
2015	#define VMX_VMCS_HOST_RSP 0x6C14
2016	#define VMX_VMCS_HOST_RIP 0x6C16
2017	/** @} */
2018
2019
2020	/** @defgroup grp_hm_vmx_asm VMX Assembly Helpers
2021	* @{
2022	*/
2023
2024	/**
2025	* Restores some host-state fields that need not be done on every VM-exit.
2026	*
2027	* @returns VBox status code.
2028	* @param fRestoreHostFlags Flags of which host registers needs to be
2029	* restored.
2030	* @param pRestoreHost Pointer to the host-restore structure.
2031	*/
2032	DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
2033
2034
2035	/**
2036	* Dispatches an NMI to the host.
2037	*/
2038	DECLASM(int) VMXDispatchHostNmi(void);
2039
2040
2041	/**
2042	* Executes VMXON.
2043	*
2044	* @returns VBox status code.
2045	* @param HCPhysVmxOn Physical address of VMXON structure.
2046	*/
2047	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2048	DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
2049	#else
2050	DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
2051	{
2052	# if RT_INLINE_ASM_GNU_STYLE
2053	int rc = VINF_SUCCESS;
2054	__asm__ __volatile__ (
2055	"push %3 \n\t"
2056	"push %2 \n\t"
2057	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
2058	"ja 2f \n\t"
2059	"je 1f \n\t"
2060	"movl $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
2061	"jmp 2f \n\t"
2062	"1: \n\t"
2063	"movl $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
2064	"2: \n\t"
2065	"add $8, %%esp \n\t"
2066	:"=rm"(rc)
2067	:"0"(VINF_SUCCESS),
2068	"ir"((uint32_t)HCPhysVmxOn), /* don't allow direct memory reference here, */
2069	"ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
2070	:"memory"
2071	);
2072	return rc;
2073
2074	# elif VMX_USE_MSC_INTRINSICS
2075	unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
2076	if (RT_LIKELY(rcMsc == 0))
2077	return VINF_SUCCESS;
2078	return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
2079
2080	# else
2081	int rc = VINF_SUCCESS;
2082	__asm
2083	{
2084	push dword ptr [HCPhysVmxOn + 4]
2085	push dword ptr [HCPhysVmxOn]
2086	_emit 0xF3
2087	_emit 0x0F
2088	_emit 0xC7
2089	_emit 0x34
2090	_emit 0x24 /* VMXON [esp] */
2091	jnc vmxon_good
2092	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
2093	jmp the_end
2094
2095	vmxon_good:
2096	jnz the_end
2097	mov dword ptr [rc], VERR_VMX_VMXON_FAILED
2098	the_end:
2099	add esp, 8
2100	}
2101	return rc;
2102	# endif
2103	}
2104	#endif
2105
2106
2107	/**
2108	* Executes VMXOFF.
2109	*/
2110	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2111	DECLASM(void) VMXDisable(void);
2112	#else
2113	DECLINLINE(void) VMXDisable(void)
2114	{
2115	# if RT_INLINE_ASM_GNU_STYLE
2116	__asm__ __volatile__ (
2117	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
2118	);
2119
2120	# elif VMX_USE_MSC_INTRINSICS
2121	__vmx_off();
2122
2123	# else
2124	__asm
2125	{
2126	_emit 0x0F
2127	_emit 0x01
2128	_emit 0xC4 /* VMXOFF */
2129	}
2130	# endif
2131	}
2132	#endif
2133
2134
2135	/**
2136	* Executes VMCLEAR.
2137	*
2138	* @returns VBox status code.
2139	* @param HCPhysVmcs Physical address of VM control structure.
2140	*/
2141	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2142	DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
2143	#else
2144	DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
2145	{
2146	# if RT_INLINE_ASM_GNU_STYLE
2147	int rc = VINF_SUCCESS;
2148	__asm__ __volatile__ (
2149	"push %3 \n\t"
2150	"push %2 \n\t"
2151	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
2152	"jnc 1f \n\t"
2153	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2154	"1: \n\t"
2155	"add $8, %%esp \n\t"
2156	:"=rm"(rc)
2157	:"0"(VINF_SUCCESS),
2158	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2159	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
2160	:"memory"
2161	);
2162	return rc;
2163
2164	# elif VMX_USE_MSC_INTRINSICS
2165	unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
2166	if (RT_LIKELY(rcMsc == 0))
2167	return VINF_SUCCESS;
2168	return VERR_VMX_INVALID_VMCS_PTR;
2169
2170	# else
2171	int rc = VINF_SUCCESS;
2172	__asm
2173	{
2174	push dword ptr [HCPhysVmcs + 4]
2175	push dword ptr [HCPhysVmcs]
2176	_emit 0x66
2177	_emit 0x0F
2178	_emit 0xC7
2179	_emit 0x34
2180	_emit 0x24 /* VMCLEAR [esp] */
2181	jnc success
2182	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2183	success:
2184	add esp, 8
2185	}
2186	return rc;
2187	# endif
2188	}
2189	#endif
2190
2191
2192	/**
2193	* Executes VMPTRLD.
2194	*
2195	* @returns VBox status code.
2196	* @param HCPhysVmcs Physical address of VMCS structure.
2197	*/
2198	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2199	DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
2200	#else
2201	DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
2202	{
2203	# if RT_INLINE_ASM_GNU_STYLE
2204	int rc = VINF_SUCCESS;
2205	__asm__ __volatile__ (
2206	"push %3 \n\t"
2207	"push %2 \n\t"
2208	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2209	"jnc 1f \n\t"
2210	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2211	"1: \n\t"
2212	"add $8, %%esp \n\t"
2213	:"=rm"(rc)
2214	:"0"(VINF_SUCCESS),
2215	"ir"((uint32_t)HCPhysVmcs), /* don't allow direct memory reference here, */
2216	"ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
2217	);
2218	return rc;
2219
2220	# elif VMX_USE_MSC_INTRINSICS
2221	unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
2222	if (RT_LIKELY(rcMsc == 0))
2223	return VINF_SUCCESS;
2224	return VERR_VMX_INVALID_VMCS_PTR;
2225
2226	# else
2227	int rc = VINF_SUCCESS;
2228	__asm
2229	{
2230	push dword ptr [HCPhysVmcs + 4]
2231	push dword ptr [HCPhysVmcs]
2232	_emit 0x0F
2233	_emit 0xC7
2234	_emit 0x34
2235	_emit 0x24 /* VMPTRLD [esp] */
2236	jnc success
2237	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2238
2239	success:
2240	add esp, 8
2241	}
2242	return rc;
2243	# endif
2244	}
2245	#endif
2246
2247	/**
2248	* Executes VMPTRST.
2249	*
2250	* @returns VBox status code.
2251	* @param pHCPhysVmcs Where to store the physical address of the current
2252	* VMCS.
2253	*/
2254	DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
2255
2256	/**
2257	* Executes VMWRITE.
2258	*
2259	* @returns VBox status code.
2260	* @retval VINF_SUCCESS.
2261	* @retval VERR_VMX_INVALID_VMCS_PTR.
2262	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2263	*
2264	* @param idxField VMCS index.
2265	* @param u32Val 32-bit value.
2266	*
2267	* @remarks The values of the two status codes can be OR'ed together, the result
2268	* will be VERR_VMX_INVALID_VMCS_PTR.
2269	*/
2270	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2271	DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2272	#else
2273	DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2274	{
2275	# if RT_INLINE_ASM_GNU_STYLE
2276	int rc = VINF_SUCCESS;
2277	__asm__ __volatile__ (
2278	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2279	"ja 2f \n\t"
2280	"je 1f \n\t"
2281	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2282	"jmp 2f \n\t"
2283	"1: \n\t"
2284	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2285	"2: \n\t"
2286	:"=rm"(rc)
2287	:"0"(VINF_SUCCESS),
2288	"a"(idxField),
2289	"d"(u32Val)
2290	);
2291	return rc;
2292
2293	# elif VMX_USE_MSC_INTRINSICS
2294	unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2295	if (RT_LIKELY(rcMsc == 0))
2296	return VINF_SUCCESS;
2297	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2298
2299	#else
2300	int rc = VINF_SUCCESS;
2301	__asm
2302	{
2303	push dword ptr [u32Val]
2304	mov eax, [idxField]
2305	_emit 0x0F
2306	_emit 0x79
2307	_emit 0x04
2308	_emit 0x24 /* VMWRITE eax, [esp] */
2309	jnc valid_vmcs
2310	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2311	jmp the_end
2312
2313	valid_vmcs:
2314	jnz the_end
2315	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2316	the_end:
2317	add esp, 4
2318	}
2319	return rc;
2320	# endif
2321	}
2322	#endif
2323
2324	/**
2325	* Executes VMWRITE.
2326	*
2327	* @returns VBox status code.
2328	* @retval VINF_SUCCESS.
2329	* @retval VERR_VMX_INVALID_VMCS_PTR.
2330	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2331	*
2332	* @param idxField VMCS index.
2333	* @param u64Val 16, 32 or 64-bit value.
2334	*
2335	* @remarks The values of the two status codes can be OR'ed together, the result
2336	* will be VERR_VMX_INVALID_VMCS_PTR.
2337	*/
2338	#if !defined(RT_ARCH_X86)
2339	# if !VMX_USE_MSC_INTRINSICS \|\| ARCH_BITS != 64
2340	DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2341	# else /* VMX_USE_MSC_INTRINSICS */
2342	DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2343	{
2344	unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2345	if (RT_LIKELY(rcMsc == 0))
2346	return VINF_SUCCESS;
2347	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2348	}
2349	# endif /* VMX_USE_MSC_INTRINSICS */
2350	#else
2351	# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2352	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2353	#endif
2354
2355	#if ARCH_BITS == 32
2356	# define VMXWriteVmcsHstN VMXWriteVmcs32
2357	# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2358	#else /* ARCH_BITS == 64 */
2359	# define VMXWriteVmcsHstN VMXWriteVmcs64
2360	# define VMXWriteVmcsGstN VMXWriteVmcs64
2361	#endif
2362
2363
2364	/**
2365	* Invalidate a page using INVEPT.
2366	*
2367	* @returns VBox status code.
2368	* @param enmFlush Type of flush.
2369	* @param pDescriptor Pointer to the descriptor.
2370	*/
2371	DECLASM(int) VMXR0InvEPT(VMXFLUSHEPT enmFlush, uint64_t *pDescriptor);
2372
2373	/**
2374	* Invalidate a page using INVVPID.
2375	*
2376	* @returns VBox status code.
2377	* @param enmFlush Type of flush.
2378	* @param pDescriptor Pointer to the descriptor.
2379	*/
2380	DECLASM(int) VMXR0InvVPID(VMXFLUSHVPID enmFlush, uint64_t *pDescriptor);
2381
2382	/**
2383	* Executes VMREAD.
2384	*
2385	* @returns VBox status code.
2386	* @retval VINF_SUCCESS.
2387	* @retval VERR_VMX_INVALID_VMCS_PTR.
2388	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2389	*
2390	* @param idxField VMCS index.
2391	* @param pData Where to store VM field value.
2392	*
2393	* @remarks The values of the two status codes can be OR'ed together, the result
2394	* will be VERR_VMX_INVALID_VMCS_PTR.
2395	*/
2396	#if ((RT_INLINE_ASM_EXTERNAL \|\| !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
2397	DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2398	#else
2399	DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2400	{
2401	# if RT_INLINE_ASM_GNU_STYLE
2402	int rc = VINF_SUCCESS;
2403	__asm__ __volatile__ (
2404	"movl $" RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2405	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2406	"ja 2f \n\t"
2407	"je 1f \n\t"
2408	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2409	"jmp 2f \n\t"
2410	"1: \n\t"
2411	"movl $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2412	"2: \n\t"
2413	:"=&r"(rc),
2414	"=d"(*pData)
2415	:"a"(idxField),
2416	"d"(0)
2417	);
2418	return rc;
2419
2420	# elif VMX_USE_MSC_INTRINSICS
2421	unsigned char rcMsc;
2422	# if ARCH_BITS == 32
2423	rcMsc = __vmx_vmread(idxField, pData);
2424	# else
2425	uint64_t u64Tmp;
2426	rcMsc = __vmx_vmread(idxField, &u64Tmp);
2427	*pData = (uint32_t)u64Tmp;
2428	# endif
2429	if (RT_LIKELY(rcMsc == 0))
2430	return VINF_SUCCESS;
2431	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2432
2433	#else
2434	int rc = VINF_SUCCESS;
2435	__asm
2436	{
2437	sub esp, 4
2438	mov dword ptr [esp], 0
2439	mov eax, [idxField]
2440	_emit 0x0F
2441	_emit 0x78
2442	_emit 0x04
2443	_emit 0x24 /* VMREAD eax, [esp] */
2444	mov edx, pData
2445	pop dword ptr [edx]
2446	jnc valid_vmcs
2447	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2448	jmp the_end
2449
2450	valid_vmcs:
2451	jnz the_end
2452	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2453	the_end:
2454	}
2455	return rc;
2456	# endif
2457	}
2458	#endif
2459
2460	/**
2461	* Executes VMREAD.
2462	*
2463	* @returns VBox status code.
2464	* @retval VINF_SUCCESS.
2465	* @retval VERR_VMX_INVALID_VMCS_PTR.
2466	* @retval VERR_VMX_INVALID_VMCS_FIELD.
2467	*
2468	* @param idxField VMCS index.
2469	* @param pData Where to store VM field value.
2470	*
2471	* @remarks The values of the two status codes can be OR'ed together, the result
2472	* will be VERR_VMX_INVALID_VMCS_PTR.
2473	*/
2474	#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
2475	DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2476	#else
2477	DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2478	{
2479	# if VMX_USE_MSC_INTRINSICS
2480	unsigned char rcMsc;
2481	# if ARCH_BITS == 32
2482	size_t uLow;
2483	size_t uHigh;
2484	rcMsc = __vmx_vmread(idxField, &uLow);
2485	rcMsc \|= __vmx_vmread(idxField + 1, &uHigh);
2486	*pData = RT_MAKE_U64(uLow, uHigh);
2487	# else
2488	rcMsc = __vmx_vmread(idxField, pData);
2489	# endif
2490	if (RT_LIKELY(rcMsc == 0))
2491	return VINF_SUCCESS;
2492	return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2493
2494	# elif ARCH_BITS == 32
2495	int rc;
2496	uint32_t val_hi, val;
2497	rc = VMXReadVmcs32(idxField, &val);
2498	rc \|= VMXReadVmcs32(idxField + 1, &val_hi);
2499	AssertRC(rc);
2500	*pData = RT_MAKE_U64(val, val_hi);
2501	return rc;
2502
2503	# else
2504	# error "Shouldn't be here..."
2505	# endif
2506	}
2507	#endif
2508
2509	/**
2510	* Gets the last instruction error value from the current VMCS.
2511	*
2512	* @returns VBox status code.
2513	*/
2514	DECLINLINE(uint32_t) VMXGetLastError(void)
2515	{
2516	#if ARCH_BITS == 64
2517	uint64_t uLastError = 0;
2518	int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2519	AssertRC(rc);
2520	return (uint32_t)uLastError;
2521
2522	#else /* 32-bit host: */
2523	uint32_t uLastError = 0;
2524	int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2525	AssertRC(rc);
2526	return uLastError;
2527	#endif
2528	}
2529
2530	#ifdef IN_RING0
2531	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2532	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2533	#endif /* IN_RING0 */
2534
2535	/** @} */
2536
2537	/** @} */
2538
2539	#endif
2540

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 63648

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