VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 48248

Last change on this file since 48248 was 48216, checked in by vboxsync, 11 years ago

VMM/HM: Cleanup.
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File size: 98.2 KB
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1/** @file
2 * HM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2013 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vmx_h
27#define ___VBox_vmm_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/x86.h>
32#include <iprt/assert.h>
33
34/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
35 when targeting AMD64. */
36#if RT_INLINE_ASM_USES_INTRIN >= 16 && defined(RT_ARCH_AMD64)
37# include <intrin.h>
38/* We always want them as intrinsics, no functions. */
39# pragma intrinsic(__vmx_on)
40# pragma intrinsic(__vmx_off)
41# pragma intrinsic(__vmx_vmclear)
42# pragma intrinsic(__vmx_vmptrld)
43# pragma intrinsic(__vmx_vmread)
44# pragma intrinsic(__vmx_vmwrite)
45# define VMX_USE_MSC_INTRINSICS 1
46#else
47# define VMX_USE_MSC_INTRINSICS 0
48#endif
49
50
51/** @defgroup grp_vmx vmx Types and Definitions
52 * @ingroup grp_hm
53 * @{
54 */
55
56/** @name Host-state restoration flags.
57 * @{
58 */
59/* If you change these values don't forget to update the assembly defines as well! */
60#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
61#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
62#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
63#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
64#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
65#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
66#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
67#define VMX_RESTORE_HOST_REQUIRED RT_BIT(7)
68/** @} */
69
70/**
71 * Host-state restoration structure.
72 * This holds host-state fields that require manual restoration.
73 * Assembly version found in hm_vmx.mac (should be automatically verified).
74 */
75typedef struct VMXRESTOREHOST
76{
77 RTSEL uHostSelDS; /* 0x00 */
78 RTSEL uHostSelES; /* 0x02 */
79 RTSEL uHostSelFS; /* 0x04 */
80 RTSEL uHostSelGS; /* 0x06 */
81 RTSEL uHostSelTR; /* 0x08 */
82 uint8_t abPadding0[4];
83 X86XDTR64 HostGdtr; /**< 0x0e - should be aligned by it's 64-bit member. */
84 uint8_t abPadding1[6];
85 X86XDTR64 HostIdtr; /**< 0x1e - should be aligned by it's 64-bit member. */
86 uint64_t uHostFSBase; /* 0x28 */
87 uint64_t uHostGSBase; /* 0x30 */
88} VMXRESTOREHOST;
89/** Pointer to VMXRESTOREHOST. */
90typedef VMXRESTOREHOST *PVMXRESTOREHOST;
91AssertCompileSize(X86XDTR64, 10);
92AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 16);
93AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 32);
94AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 40);
95AssertCompileSize(VMXRESTOREHOST, 56);
96
97/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
98 * UFC = Unsupported Feature Combination.
99 * @{
100 */
101/** Unsupported pin-based VM-execution controls combo. */
102#define VMX_UFC_CTRL_PIN_EXEC 0
103/** Unsupported processor-based VM-execution controls combo. */
104#define VMX_UFC_CTRL_PROC_EXEC 1
105/** Unsupported pin-based VM-execution controls combo. */
106#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 2
107/** Unsupported VM-entry controls combo. */
108#define VMX_UFC_CTRL_ENTRY 3
109/** Unsupported VM-exit controls combo. */
110#define VMX_UFC_CTRL_EXIT 4
111/** MSR storage capacity of the VMCS autoload/store area is not sufficient
112 * for storing host MSRs. */
113#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 5
114/** MSR storage capacity of the VMCS autoload/store area is not sufficient
115 * for storing guest MSRs. */
116#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 6
117/** @} */
118
119/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
120 * IGS = Invalid Guest State.
121 * @{
122 */
123/** An error occurred while checking invalid-guest-state. */
124#define VMX_IGS_ERROR 0
125/** The invalid guest-state checks did not find any reason why. */
126#define VMX_IGS_REASON_NOT_FOUND 1
127/** CR0 fixed1 bits invalid. */
128#define VMX_IGS_CR0_FIXED1 2
129/** CR0 fixed0 bits invalid. */
130#define VMX_IGS_CR0_FIXED0 3
131/** CR0.PE and CR0.PE invalid VT-x/host combination. */
132#define VMX_IGS_CR0_PG_PE_COMBO 4
133/** CR4 fixed1 bits invalid. */
134#define VMX_IGS_CR4_FIXED1 5
135/** CR4 fixed0 bits invalid. */
136#define VMX_IGS_CR4_FIXED0 6
137/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
138 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
139#define VMX_IGS_DEBUGCTL_MSR_RESERVED 7
140/** CR0.PG not set for long-mode when not using unrestricted guest. */
141#define VMX_IGS_CR0_PG_LONGMODE 8
142/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
143#define VMX_IGS_CR4_PAE_LONGMODE 9
144/** CR4.PCIDE set for 32-bit guest. */
145#define VMX_IGS_CR4_PCIDE 10
146/** VMCS' DR7 reserved bits not set to 0. */
147#define VMX_IGS_DR7_RESERVED 11
148/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
149#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12
150/** VMCS' EFER MSR reserved bits not set to 0. */
151#define VMX_IGS_EFER_MSR_RESERVED 13
152/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
153#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14
154/** VMCS' EFER MSR.LMA does not match CR0.PG of the guest when not using
155 * unrestricted guest. */
156#define VMX_IGS_EFER_LMA_PG_MISMATCH 15
157/** CS.Attr.P bit invalid. */
158#define VMX_IGS_CS_ATTR_P_INVALID 16
159/** CS.Attr reserved bits not set to 0. */
160#define VMX_IGS_CS_ATTR_RESERVED 17
161/** CS.Attr.G bit invalid. */
162#define VMX_IGS_CS_ATTR_G_INVALID 18
163/** CS is unusable. */
164#define VMX_IGS_CS_ATTR_UNUSABLE 19
165/** CS and SS DPL unequal. */
166#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20
167/** CS and SS DPL mismatch. */
168#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21
169/** CS Attr.Type invalid. */
170#define VMX_IGS_CS_ATTR_TYPE_INVALID 22
171/** CS and SS RPL unequal. */
172#define VMX_IGS_SS_CS_RPL_UNEQUAL 23
173/** SS.Attr.DPL and SS RPL unequal. */
174#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24
175/** SS.Attr.DPL invalid for segment type. */
176#define VMX_IGS_SS_ATTR_DPL_INVALID 25
177/** SS.Attr.Type invalid. */
178#define VMX_IGS_SS_ATTR_TYPE_INVALID 26
179/** SS.Attr.P bit invalid. */
180#define VMX_IGS_SS_ATTR_P_INVALID 27
181/** SS.Attr reserved bits not set to 0. */
182#define VMX_IGS_SS_ATTR_RESERVED 28
183/** SS.Attr.G bit invalid. */
184#define VMX_IGS_SS_ATTR_G_INVALID 29
185/** DS.Attr.A bit invalid. */
186#define VMX_IGS_DS_ATTR_A_INVALID 30
187/** DS.Attr.P bit invalid. */
188#define VMX_IGS_DS_ATTR_P_INVALID 31
189/** DS.Attr.DPL and DS RPL unequal. */
190#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32
191/** DS.Attr reserved bits not set to 0. */
192#define VMX_IGS_DS_ATTR_RESERVED 33
193/** DS.Attr.G bit invalid. */
194#define VMX_IGS_DS_ATTR_G_INVALID 34
195/** DS.Attr.Type invalid. */
196#define VMX_IGS_DS_ATTR_TYPE_INVALID 35
197/** ES.Attr.A bit invalid. */
198#define VMX_IGS_ES_ATTR_A_INVALID 36
199/** ES.Attr.P bit invalid. */
200#define VMX_IGS_ES_ATTR_P_INVALID 37
201/** ES.Attr.DPL and DS RPL unequal. */
202#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38
203/** ES.Attr reserved bits not set to 0. */
204#define VMX_IGS_ES_ATTR_RESERVED 39
205/** ES.Attr.G bit invalid. */
206#define VMX_IGS_ES_ATTR_G_INVALID 40
207/** ES.Attr.Type invalid. */
208#define VMX_IGS_ES_ATTR_TYPE_INVALID 41
209/** FS.Attr.A bit invalid. */
210#define VMX_IGS_FS_ATTR_A_INVALID 42
211/** FS.Attr.P bit invalid. */
212#define VMX_IGS_FS_ATTR_P_INVALID 43
213/** FS.Attr.DPL and DS RPL unequal. */
214#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44
215/** FS.Attr reserved bits not set to 0. */
216#define VMX_IGS_FS_ATTR_RESERVED 45
217/** FS.Attr.G bit invalid. */
218#define VMX_IGS_FS_ATTR_G_INVALID 46
219/** FS.Attr.Type invalid. */
220#define VMX_IGS_FS_ATTR_TYPE_INVALID 47
221/** GS.Attr.A bit invalid. */
222#define VMX_IGS_GS_ATTR_A_INVALID 48
223/** GS.Attr.P bit invalid. */
224#define VMX_IGS_GS_ATTR_P_INVALID 49
225/** GS.Attr.DPL and DS RPL unequal. */
226#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 50
227/** GS.Attr reserved bits not set to 0. */
228#define VMX_IGS_GS_ATTR_RESERVED 51
229/** GS.Attr.G bit invalid. */
230#define VMX_IGS_GS_ATTR_G_INVALID 52
231/** GS.Attr.Type invalid. */
232#define VMX_IGS_GS_ATTR_TYPE_INVALID 53
233/** V86 mode CS.Base invalid. */
234#define VMX_IGS_V86_CS_BASE_INVALID 54
235/** V86 mode CS.Limit invalid. */
236#define VMX_IGS_V86_CS_LIMIT_INVALID 55
237/** V86 mode CS.Attr invalid. */
238#define VMX_IGS_V86_CS_ATTR_INVALID 56
239/** V86 mode SS.Base invalid. */
240#define VMX_IGS_V86_SS_BASE_INVALID 57
241/** V86 mode SS.Limit invalid. */
242#define VMX_IGS_V86_SS_LIMIT_INVALID 59
243/** V86 mode SS.Attr invalid. */
244#define VMX_IGS_V86_SS_ATTR_INVALID 59
245/** V86 mode DS.Base invalid. */
246#define VMX_IGS_V86_DS_BASE_INVALID 60
247/** V86 mode DS.Limit invalid. */
248#define VMX_IGS_V86_DS_LIMIT_INVALID 61
249/** V86 mode DS.Attr invalid. */
250#define VMX_IGS_V86_DS_ATTR_INVALID 62
251/** V86 mode ES.Base invalid. */
252#define VMX_IGS_V86_ES_BASE_INVALID 63
253/** V86 mode ES.Limit invalid. */
254#define VMX_IGS_V86_ES_LIMIT_INVALID 64
255/** V86 mode ES.Attr invalid. */
256#define VMX_IGS_V86_ES_ATTR_INVALID 65
257/** V86 mode FS.Base invalid. */
258#define VMX_IGS_V86_FS_BASE_INVALID 66
259/** V86 mode FS.Limit invalid. */
260#define VMX_IGS_V86_FS_LIMIT_INVALID 67
261/** V86 mode FS.Attr invalid. */
262#define VMX_IGS_V86_FS_ATTR_INVALID 68
263/** V86 mode GS.Base invalid. */
264#define VMX_IGS_V86_GS_BASE_INVALID 69
265/** V86 mode GS.Limit invalid. */
266#define VMX_IGS_V86_GS_LIMIT_INVALID 70
267/** V86 mode GS.Attr invalid. */
268#define VMX_IGS_V86_GS_ATTR_INVALID 71
269/** Longmode CS.Base invalid. */
270#define VMX_IGS_LONGMODE_CS_BASE_INVALID 72
271/** Longmode SS.Base invalid. */
272#define VMX_IGS_LONGMODE_SS_BASE_INVALID 73
273/** Longmode DS.Base invalid. */
274#define VMX_IGS_LONGMODE_DS_BASE_INVALID 74
275/** Longmode ES.Base invalid. */
276#define VMX_IGS_LONGMODE_ES_BASE_INVALID 75
277/** SYSENTER ESP is not canonical. */
278#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76
279/** SYSENTER EIP is not canonical. */
280#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77
281/** PAT MSR invalid. */
282#define VMX_IGS_PAT_MSR_INVALID 78
283/** PAT MSR reserved bits not set to 0. */
284#define VMX_IGS_PAT_MSR_RESERVED 79
285/** GDTR.Base is not canonical. */
286#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80
287/** IDTR.Base is not canonical. */
288#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81
289/** GDTR.Limit invalid. */
290#define VMX_IGS_GDTR_LIMIT_INVALID 82
291/** IDTR.Limit invalid. */
292#define VMX_IGS_IDTR_LIMIT_INVALID 83
293/** Longmode RIP is invalid. */
294#define VMX_IGS_LONGMODE_RIP_INVALID 84
295/** RFLAGS reserved bits not set to 0. */
296#define VMX_IGS_RFLAGS_RESERVED 85
297/** RFLAGS RA1 reserved bits not set to 1. */
298#define VMX_IGS_RFLAGS_RESERVED1 86
299/** RFLAGS.VM (V86 mode) invalid. */
300#define VMX_IGS_RFLAGS_VM_INVALID 87
301/** RFLAGS.IF invalid. */
302#define VMX_IGS_RFLAGS_IF_INVALID 88
303/** Activity state invalid. */
304#define VMX_IGS_ACTIVITY_STATE_INVALID 89
305/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
306#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90
307/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
308#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91
309/** Activity state SIPI WAIT invalid. */
310#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92
311/** Interruptibility state reserved bits not set to 0. */
312#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93
313/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
314#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94
315/** Interruptibility state block-by-STI invalid for EFLAGS. */
316#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95
317/** Interruptibility state invalid while trying to deliver external
318 * interrupt. */
319#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96
320/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
321 * NMI. */
322#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97
323/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
324#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98
325/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
326#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99
327/** Interruptibilty state block-by-STI (maybe) invalid when trying to deliver
328 * an NMI. */
329#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100
330/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
331 * active. */
332#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101
333/** Pending debug exceptions reserved bits not set to 0. */
334#define VMX_IGS_PENDING_DEBUG_RESERVED 102
335/** Longmode pending debug exceptions reserved bits not set to 0. */
336#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103
337/** Pending debug exceptions.BS bit is not set when it should be. */
338#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104
339/** Pending debug exceptions.BS bit is not clear when it should be. */
340#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105
341/** VMCS link pointer reserved bits not set to 0. */
342#define VMX_IGS_VMCS_LINK_PTR_RESERVED 106
343/** TR cannot index into LDT, TI bit MBZ. */
344#define VMX_IGS_TR_TI_INVALID 107
345/** LDTR cannot index into LDT. TI bit MBZ. */
346#define VMX_IGS_LDTR_TI_INVALID 108
347/** TR.Base is not canonical. */
348#define VMX_IGS_TR_BASE_NOT_CANONICAL 109
349/** FS.Base is not canonical. */
350#define VMX_IGS_FS_BASE_NOT_CANONICAL 110
351/** GS.Base is not canonical. */
352#define VMX_IGS_GS_BASE_NOT_CANONICAL 111
353/** LDTR.Base is not canonical. */
354#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112
355/** TR is unusable. */
356#define VMX_IGS_TR_ATTR_UNUSABLE 113
357/** TR.Attr.S bit invalid. */
358#define VMX_IGS_TR_ATTR_S_INVALID 114
359/** TR is not present. */
360#define VMX_IGS_TR_ATTR_P_INVALID 115
361/** TR.Attr reserved bits not set to 0. */
362#define VMX_IGS_TR_ATTR_RESERVED 116
363/** TR.Attr.G bit invalid. */
364#define VMX_IGS_TR_ATTR_G_INVALID 117
365/** Longmode TR.Attr.Type invalid. */
366#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118
367/** TR.Attr.Type invalid. */
368#define VMX_IGS_TR_ATTR_TYPE_INVALID 119
369/** CS.Attr.S invalid. */
370#define VMX_IGS_CS_ATTR_S_INVALID 120
371/** CS.Attr.DPL invalid. */
372#define VMX_IGS_CS_ATTR_DPL_INVALID 121
373/** @} */
374
375/** @name VMX VMCS-Read cache indices.
376 * @{
377 */
378#ifndef VBOX_WITH_OLD_VTX_CODE
379# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
380# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
381# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
382# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
383# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
384# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
385# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
386# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
387# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
388# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
389# define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
390# define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
391# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
392# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
393# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
394# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
395# define VMX_VMCS_GUEST_CR3_CACHE_IDX 15
396# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
397#else /* VBOX_WITH_OLD_VTX_CODE */
398# define VMX_VMCS_GUEST_RIP_CACHE_IDX 0
399# define VMX_VMCS_GUEST_RSP_CACHE_IDX 1
400# define VMX_VMCS_GUEST_RFLAGS_CACHE_IDX 2
401# define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE_CACHE_IDX 3
402# define VMX_VMCS_CTRL_CR0_READ_SHADOW_CACHE_IDX 4
403# define VMX_VMCS_GUEST_CR0_CACHE_IDX 5
404# define VMX_VMCS_CTRL_CR4_READ_SHADOW_CACHE_IDX 6
405# define VMX_VMCS_GUEST_CR4_CACHE_IDX 7
406# define VMX_VMCS_GUEST_DR7_CACHE_IDX 8
407# define VMX_VMCS32_GUEST_SYSENTER_CS_CACHE_IDX 9
408# define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 10
409# define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 11
410# define VMX_VMCS32_GUEST_GDTR_LIMIT_CACHE_IDX 12
411# define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 13
412# define VMX_VMCS32_GUEST_IDTR_LIMIT_CACHE_IDX 14
413# define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 15
414# define VMX_VMCS16_GUEST_FIELD_CS_CACHE_IDX 16
415# define VMX_VMCS32_GUEST_CS_LIMIT_CACHE_IDX 17
416# define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 18
417# define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS_CACHE_IDX 19
418# define VMX_VMCS16_GUEST_FIELD_DS_CACHE_IDX 20
419# define VMX_VMCS32_GUEST_DS_LIMIT_CACHE_IDX 21
420# define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 22
421# define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS_CACHE_IDX 23
422# define VMX_VMCS16_GUEST_FIELD_ES_CACHE_IDX 24
423# define VMX_VMCS32_GUEST_ES_LIMIT_CACHE_IDX 25
424# define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 26
425# define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS_CACHE_IDX 27
426# define VMX_VMCS16_GUEST_FIELD_FS_CACHE_IDX 28
427# define VMX_VMCS32_GUEST_FS_LIMIT_CACHE_IDX 29
428# define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 30
429# define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS_CACHE_IDX 31
430# define VMX_VMCS16_GUEST_FIELD_GS_CACHE_IDX 32
431# define VMX_VMCS32_GUEST_GS_LIMIT_CACHE_IDX 33
432# define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 34
433# define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS_CACHE_IDX 35
434# define VMX_VMCS16_GUEST_FIELD_SS_CACHE_IDX 36
435# define VMX_VMCS32_GUEST_SS_LIMIT_CACHE_IDX 37
436# define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 38
437# define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS_CACHE_IDX 39
438# define VMX_VMCS16_GUEST_FIELD_TR_CACHE_IDX 40
439# define VMX_VMCS32_GUEST_TR_LIMIT_CACHE_IDX 41
440# define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 42
441# define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS_CACHE_IDX 43
442# define VMX_VMCS16_GUEST_FIELD_LDTR_CACHE_IDX 44
443# define VMX_VMCS32_GUEST_LDTR_LIMIT_CACHE_IDX 45
444# define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 46
445# define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS_CACHE_IDX 47
446# define VMX_VMCS32_RO_EXIT_REASON_CACHE_IDX 48
447# define VMX_VMCS32_RO_VM_INSTR_ERROR_CACHE_IDX 49
448# define VMX_VMCS32_RO_EXIT_INSTR_LENGTH_CACHE_IDX 50
449# define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE_CACHE_IDX 51
450# define VMX_VMCS32_RO_EXIT_INSTR_INFO_CACHE_IDX 52
451# define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO_CACHE_IDX 53
452# define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 54
453# define VMX_VMCS32_RO_IDT_INFO_CACHE_IDX 55
454# define VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX 56
455# define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS32_RO_IDT_ERROR_CODE_CACHE_IDX + 1)
456# define VMX_VMCS_GUEST_CR3_CACHE_IDX 57
457# define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX 58
458# define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL_CACHE_IDX + 1)
459#endif /* VBOX_WITH_OLD_VTX_CODE */
460/** @} */
461
462/** @name VMX EPT paging structures
463 * @{
464 */
465
466/**
467 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
468 */
469#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
470
471/**
472 * EPT Page Directory Pointer Entry. Bit view.
473 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
474 * this did cause trouble with one compiler/version).
475 */
476#pragma pack(1)
477typedef struct EPTPML4EBITS
478{
479 /** Present bit. */
480 uint64_t u1Present : 1;
481 /** Writable bit. */
482 uint64_t u1Write : 1;
483 /** Executable bit. */
484 uint64_t u1Execute : 1;
485 /** Reserved (must be 0). */
486 uint64_t u5Reserved : 5;
487 /** Available for software. */
488 uint64_t u4Available : 4;
489 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
490 uint64_t u40PhysAddr : 40;
491 /** Availabe for software. */
492 uint64_t u12Available : 12;
493} EPTPML4EBITS;
494#pragma pack()
495AssertCompileSize(EPTPML4EBITS, 8);
496
497/** Bits 12-51 - - EPT - Physical Page number of the next level. */
498#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
499/** The page shift to get the PML4 index. */
500#define EPT_PML4_SHIFT X86_PML4_SHIFT
501/** The PML4 index mask (apply to a shifted page address). */
502#define EPT_PML4_MASK X86_PML4_MASK
503
504/**
505 * EPT PML4E.
506 */
507#pragma pack(1)
508typedef union EPTPML4E
509{
510 /** Normal view. */
511 EPTPML4EBITS n;
512 /** Unsigned integer view. */
513 X86PGPAEUINT u;
514 /** 64 bit unsigned integer view. */
515 uint64_t au64[1];
516 /** 32 bit unsigned integer view. */
517 uint32_t au32[2];
518} EPTPML4E;
519#pragma pack()
520/** Pointer to a PML4 table entry. */
521typedef EPTPML4E *PEPTPML4E;
522/** Pointer to a const PML4 table entry. */
523typedef const EPTPML4E *PCEPTPML4E;
524AssertCompileSize(EPTPML4E, 8);
525
526/**
527 * EPT PML4 Table.
528 */
529#pragma pack(1)
530typedef struct EPTPML4
531{
532 EPTPML4E a[EPT_PG_ENTRIES];
533} EPTPML4;
534#pragma pack()
535/** Pointer to an EPT PML4 Table. */
536typedef EPTPML4 *PEPTPML4;
537/** Pointer to a const EPT PML4 Table. */
538typedef const EPTPML4 *PCEPTPML4;
539
540/**
541 * EPT Page Directory Pointer Entry. Bit view.
542 */
543#pragma pack(1)
544typedef struct EPTPDPTEBITS
545{
546 /** Present bit. */
547 uint64_t u1Present : 1;
548 /** Writable bit. */
549 uint64_t u1Write : 1;
550 /** Executable bit. */
551 uint64_t u1Execute : 1;
552 /** Reserved (must be 0). */
553 uint64_t u5Reserved : 5;
554 /** Available for software. */
555 uint64_t u4Available : 4;
556 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
557 uint64_t u40PhysAddr : 40;
558 /** Availabe for software. */
559 uint64_t u12Available : 12;
560} EPTPDPTEBITS;
561#pragma pack()
562AssertCompileSize(EPTPDPTEBITS, 8);
563
564/** Bits 12-51 - - EPT - Physical Page number of the next level. */
565#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
566/** The page shift to get the PDPT index. */
567#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
568/** The PDPT index mask (apply to a shifted page address). */
569#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
570
571/**
572 * EPT Page Directory Pointer.
573 */
574#pragma pack(1)
575typedef union EPTPDPTE
576{
577 /** Normal view. */
578 EPTPDPTEBITS n;
579 /** Unsigned integer view. */
580 X86PGPAEUINT u;
581 /** 64 bit unsigned integer view. */
582 uint64_t au64[1];
583 /** 32 bit unsigned integer view. */
584 uint32_t au32[2];
585} EPTPDPTE;
586#pragma pack()
587/** Pointer to an EPT Page Directory Pointer Entry. */
588typedef EPTPDPTE *PEPTPDPTE;
589/** Pointer to a const EPT Page Directory Pointer Entry. */
590typedef const EPTPDPTE *PCEPTPDPTE;
591AssertCompileSize(EPTPDPTE, 8);
592
593/**
594 * EPT Page Directory Pointer Table.
595 */
596#pragma pack(1)
597typedef struct EPTPDPT
598{
599 EPTPDPTE a[EPT_PG_ENTRIES];
600} EPTPDPT;
601#pragma pack()
602/** Pointer to an EPT Page Directory Pointer Table. */
603typedef EPTPDPT *PEPTPDPT;
604/** Pointer to a const EPT Page Directory Pointer Table. */
605typedef const EPTPDPT *PCEPTPDPT;
606
607
608/**
609 * EPT Page Directory Table Entry. Bit view.
610 */
611#pragma pack(1)
612typedef struct EPTPDEBITS
613{
614 /** Present bit. */
615 uint64_t u1Present : 1;
616 /** Writable bit. */
617 uint64_t u1Write : 1;
618 /** Executable bit. */
619 uint64_t u1Execute : 1;
620 /** Reserved (must be 0). */
621 uint64_t u4Reserved : 4;
622 /** Big page (must be 0 here). */
623 uint64_t u1Size : 1;
624 /** Available for software. */
625 uint64_t u4Available : 4;
626 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
627 uint64_t u40PhysAddr : 40;
628 /** Availabe for software. */
629 uint64_t u12Available : 12;
630} EPTPDEBITS;
631#pragma pack()
632AssertCompileSize(EPTPDEBITS, 8);
633
634/** Bits 12-51 - - EPT - Physical Page number of the next level. */
635#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
636/** The page shift to get the PD index. */
637#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
638/** The PD index mask (apply to a shifted page address). */
639#define EPT_PD_MASK X86_PD_PAE_MASK
640
641/**
642 * EPT 2MB Page Directory Table Entry. Bit view.
643 */
644#pragma pack(1)
645typedef struct EPTPDE2MBITS
646{
647 /** Present bit. */
648 uint64_t u1Present : 1;
649 /** Writable bit. */
650 uint64_t u1Write : 1;
651 /** Executable bit. */
652 uint64_t u1Execute : 1;
653 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
654 uint64_t u3EMT : 3;
655 /** Ignore PAT memory type */
656 uint64_t u1IgnorePAT : 1;
657 /** Big page (must be 1 here). */
658 uint64_t u1Size : 1;
659 /** Available for software. */
660 uint64_t u4Available : 4;
661 /** Reserved (must be 0). */
662 uint64_t u9Reserved : 9;
663 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
664 uint64_t u31PhysAddr : 31;
665 /** Availabe for software. */
666 uint64_t u12Available : 12;
667} EPTPDE2MBITS;
668#pragma pack()
669AssertCompileSize(EPTPDE2MBITS, 8);
670
671/** Bits 21-51 - - EPT - Physical Page number of the next level. */
672#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
673
674/**
675 * EPT Page Directory Table Entry.
676 */
677#pragma pack(1)
678typedef union EPTPDE
679{
680 /** Normal view. */
681 EPTPDEBITS n;
682 /** 2MB view (big). */
683 EPTPDE2MBITS b;
684 /** Unsigned integer view. */
685 X86PGPAEUINT u;
686 /** 64 bit unsigned integer view. */
687 uint64_t au64[1];
688 /** 32 bit unsigned integer view. */
689 uint32_t au32[2];
690} EPTPDE;
691#pragma pack()
692/** Pointer to an EPT Page Directory Table Entry. */
693typedef EPTPDE *PEPTPDE;
694/** Pointer to a const EPT Page Directory Table Entry. */
695typedef const EPTPDE *PCEPTPDE;
696AssertCompileSize(EPTPDE, 8);
697
698/**
699 * EPT Page Directory Table.
700 */
701#pragma pack(1)
702typedef struct EPTPD
703{
704 EPTPDE a[EPT_PG_ENTRIES];
705} EPTPD;
706#pragma pack()
707/** Pointer to an EPT Page Directory Table. */
708typedef EPTPD *PEPTPD;
709/** Pointer to a const EPT Page Directory Table. */
710typedef const EPTPD *PCEPTPD;
711
712
713/**
714 * EPT Page Table Entry. Bit view.
715 */
716#pragma pack(1)
717typedef struct EPTPTEBITS
718{
719 /** 0 - Present bit.
720 * @remark This is a convenience "misnomer". The bit actually indicates
721 * read access and the CPU will consider an entry with any of the
722 * first three bits set as present. Since all our valid entries
723 * will have this bit set, it can be used as a present indicator
724 * and allow some code sharing. */
725 uint64_t u1Present : 1;
726 /** 1 - Writable bit. */
727 uint64_t u1Write : 1;
728 /** 2 - Executable bit. */
729 uint64_t u1Execute : 1;
730 /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
731 uint64_t u3EMT : 3;
732 /** 6 - Ignore PAT memory type */
733 uint64_t u1IgnorePAT : 1;
734 /** 11:7 - Available for software. */
735 uint64_t u5Available : 5;
736 /** 51:12 - Physical address of page. Restricted by maximum physical
737 * address width of the cpu. */
738 uint64_t u40PhysAddr : 40;
739 /** 63:52 - Available for software. */
740 uint64_t u12Available : 12;
741} EPTPTEBITS;
742#pragma pack()
743AssertCompileSize(EPTPTEBITS, 8);
744
745/** Bits 12-51 - - EPT - Physical Page number of the next level. */
746#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
747/** The page shift to get the EPT PTE index. */
748#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
749/** The EPT PT index mask (apply to a shifted page address). */
750#define EPT_PT_MASK X86_PT_PAE_MASK
751
752/**
753 * EPT Page Table Entry.
754 */
755#pragma pack(1)
756typedef union EPTPTE
757{
758 /** Normal view. */
759 EPTPTEBITS n;
760 /** Unsigned integer view. */
761 X86PGPAEUINT u;
762 /** 64 bit unsigned integer view. */
763 uint64_t au64[1];
764 /** 32 bit unsigned integer view. */
765 uint32_t au32[2];
766} EPTPTE;
767#pragma pack()
768/** Pointer to an EPT Page Directory Table Entry. */
769typedef EPTPTE *PEPTPTE;
770/** Pointer to a const EPT Page Directory Table Entry. */
771typedef const EPTPTE *PCEPTPTE;
772AssertCompileSize(EPTPTE, 8);
773
774/**
775 * EPT Page Table.
776 */
777#pragma pack(1)
778typedef struct EPTPT
779{
780 EPTPTE a[EPT_PG_ENTRIES];
781} EPTPT;
782#pragma pack()
783/** Pointer to an extended page table. */
784typedef EPTPT *PEPTPT;
785/** Pointer to a const extended table. */
786typedef const EPTPT *PCEPTPT;
787
788/**
789 * VPID flush types.
790 */
791typedef enum
792{
793 /** Invalidate a specific page. */
794 VMX_FLUSH_VPID_INDIV_ADDR = 0,
795 /** Invalidate one context (specific VPID). */
796 VMX_FLUSH_VPID_SINGLE_CONTEXT = 1,
797 /** Invalidate all contexts (all VPIDs). */
798 VMX_FLUSH_VPID_ALL_CONTEXTS = 2,
799 /** Invalidate a single VPID context retaining global mappings. */
800 VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
801 /** Unsupported by VirtualBox. */
802 VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
803 /** Unsupported by CPU. */
804 VMX_FLUSH_VPID_NONE = 0xb00,
805 /** 32bit hackishness. */
806 VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
807} VMX_FLUSH_VPID;
808
809/**
810 * EPT flush types.
811 */
812typedef enum
813{
814 /** Invalidate one context (specific EPT). */
815 VMX_FLUSH_EPT_SINGLE_CONTEXT = 1,
816 /* Invalidate all contexts (all EPTs) */
817 VMX_FLUSH_EPT_ALL_CONTEXTS = 2,
818 /** Unsupported by VirtualBox. */
819 VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
820 /** Unsupported by CPU. */
821 VMX_FLUSH_EPT_NONE = 0xb00,
822 /** 32bit hackishness. */
823 VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
824} VMX_FLUSH_EPT;
825/** @} */
826
827/** @name MSR autoload/store elements
828 * @{
829 */
830#pragma pack(1)
831typedef struct
832{
833 uint32_t u32Msr;
834 uint32_t u32Reserved;
835 uint64_t u64Value;
836} VMXAUTOMSR;
837#pragma pack()
838/** Pointer to an MSR load/store element. */
839typedef VMXAUTOMSR *PVMXAUTOMSR;
840/** Pointer to a const MSR load/store element. */
841typedef const VMXAUTOMSR *PCVMXAUTOMSR;
842/** @} */
843
844/** @name VMX-capability qword
845 * @{
846 */
847#pragma pack(1)
848typedef union
849{
850 struct
851 {
852 /** Bits set here -must- be set in the correpsonding VM-execution controls. */
853 uint32_t disallowed0;
854 /** Bits cleared here -must- be cleared in the corresponding VM-execution
855 * controls. */
856 uint32_t allowed1;
857 } n;
858 uint64_t u;
859} VMX_CAPABILITY;
860#pragma pack()
861/** @} */
862
863/** @name VMX MSRs.
864 * @{
865 */
866typedef struct VMXMSRS
867{
868 uint64_t u64FeatureCtrl;
869 uint64_t u64BasicInfo;
870 VMX_CAPABILITY VmxPinCtls;
871 VMX_CAPABILITY VmxProcCtls;
872 VMX_CAPABILITY VmxProcCtls2;
873 VMX_CAPABILITY VmxExit;
874 VMX_CAPABILITY VmxEntry;
875 uint64_t u64Misc;
876 uint64_t u64Cr0Fixed0;
877 uint64_t u64Cr0Fixed1;
878 uint64_t u64Cr4Fixed0;
879 uint64_t u64Cr4Fixed1;
880 uint64_t u64VmcsEnum;
881 uint64_t u64Vmfunc;
882 uint64_t u64EptVpidCaps;
883} VMXMSRS;
884/** Pointer to a VMXMSRS struct. */
885typedef VMXMSRS *PVMXMSRS;
886/** @} */
887
888/** @name VMX EFLAGS reserved bits.
889 * @{
890 */
891/** And-mask for setting reserved bits to zero */
892#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
893/** Or-mask for setting reserved bits to 1 */
894#define VMX_EFLAGS_RESERVED_1 0x00000002
895/** @} */
896
897/** @name VMX Basic Exit Reasons.
898 * @{
899 */
900/** -1 Invalid exit code */
901#define VMX_EXIT_INVALID -1
902/** 0 Exception or non-maskable interrupt (NMI). */
903#define VMX_EXIT_XCPT_OR_NMI 0
904/** 1 External interrupt. */
905#define VMX_EXIT_EXT_INT 1
906/** 2 Triple fault. */
907#define VMX_EXIT_TRIPLE_FAULT 2
908/** 3 INIT signal. */
909#define VMX_EXIT_INIT_SIGNAL 3
910/** 4 Start-up IPI (SIPI). */
911#define VMX_EXIT_SIPI 4
912/** 5 I/O system-management interrupt (SMI). */
913#define VMX_EXIT_IO_SMI 5
914/** 6 Other SMI. */
915#define VMX_EXIT_SMI 6
916/** 7 Interrupt window exiting. */
917#define VMX_EXIT_INT_WINDOW 7
918/** 8 NMI window exiting. */
919#define VMX_EXIT_NMI_WINDOW 8
920/** 9 Task switch. */
921#define VMX_EXIT_TASK_SWITCH 9
922/** 10 Guest software attempted to execute CPUID. */
923#define VMX_EXIT_CPUID 10
924/** 10 Guest software attempted to execute GETSEC. */
925#define VMX_EXIT_GETSEC 11
926/** 12 Guest software attempted to execute HLT. */
927#define VMX_EXIT_HLT 12
928/** 13 Guest software attempted to execute INVD. */
929#define VMX_EXIT_INVD 13
930/** 14 Guest software attempted to execute INVLPG. */
931#define VMX_EXIT_INVLPG 14
932/** 15 Guest software attempted to execute RDPMC. */
933#define VMX_EXIT_RDPMC 15
934/** 16 Guest software attempted to execute RDTSC. */
935#define VMX_EXIT_RDTSC 16
936/** 17 Guest software attempted to execute RSM in SMM. */
937#define VMX_EXIT_RSM 17
938/** 18 Guest software executed VMCALL. */
939#define VMX_EXIT_VMCALL 18
940/** 19 Guest software executed VMCLEAR. */
941#define VMX_EXIT_VMCLEAR 19
942/** 20 Guest software executed VMLAUNCH. */
943#define VMX_EXIT_VMLAUNCH 20
944/** 21 Guest software executed VMPTRLD. */
945#define VMX_EXIT_VMPTRLD 21
946/** 22 Guest software executed VMPTRST. */
947#define VMX_EXIT_VMPTRST 22
948/** 23 Guest software executed VMREAD. */
949#define VMX_EXIT_VMREAD 23
950/** 24 Guest software executed VMRESUME. */
951#define VMX_EXIT_VMRESUME 24
952/** 25 Guest software executed VMWRITE. */
953#define VMX_EXIT_VMWRITE 25
954/** 26 Guest software executed VMXOFF. */
955#define VMX_EXIT_VMXOFF 26
956/** 27 Guest software executed VMXON. */
957#define VMX_EXIT_VMXON 27
958/** 28 Control-register accesses. */
959#define VMX_EXIT_MOV_CRX 28
960/** 29 Debug-register accesses. */
961#define VMX_EXIT_MOV_DRX 29
962/** 30 I/O instruction. */
963#define VMX_EXIT_IO_INSTR 30
964/** 31 RDMSR. Guest software attempted to execute RDMSR. */
965#define VMX_EXIT_RDMSR 31
966/** 32 WRMSR. Guest software attempted to execute WRMSR. */
967#define VMX_EXIT_WRMSR 32
968/** 33 VM-entry failure due to invalid guest state. */
969#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
970/** 34 VM-entry failure due to MSR loading. */
971#define VMX_EXIT_ERR_MSR_LOAD 34
972/** 36 Guest software executed MWAIT. */
973#define VMX_EXIT_MWAIT 36
974/** 37 VM exit due to monitor trap flag. */
975#define VMX_EXIT_MTF 37
976/** 39 Guest software attempted to execute MONITOR. */
977#define VMX_EXIT_MONITOR 39
978/** 40 Guest software attempted to execute PAUSE. */
979#define VMX_EXIT_PAUSE 40
980/** 41 VM-entry failure due to machine-check. */
981#define VMX_EXIT_ERR_MACHINE_CHECK 41
982/** 43 TPR below threshold. Guest software executed MOV to CR8. */
983#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
984/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
985#define VMX_EXIT_APIC_ACCESS 44
986/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
987#define VMX_EXIT_XDTR_ACCESS 46
988/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
989#define VMX_EXIT_TR_ACCESS 47
990/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
991#define VMX_EXIT_EPT_VIOLATION 48
992/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
993#define VMX_EXIT_EPT_MISCONFIG 49
994/** 50 INVEPT. Guest software attempted to execute INVEPT. */
995#define VMX_EXIT_INVEPT 50
996/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
997#define VMX_EXIT_RDTSCP 51
998/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
999#define VMX_EXIT_PREEMPT_TIMER 52
1000/** 53 INVVPID. Guest software attempted to execute INVVPID. */
1001#define VMX_EXIT_INVVPID 53
1002/** 54 WBINVD. Guest software attempted to execute WBINVD. */
1003#define VMX_EXIT_WBINVD 54
1004/** 55 XSETBV. Guest software attempted to execute XSETBV. */
1005#define VMX_EXIT_XSETBV 55
1006/** 57 RDRAND. Guest software attempted to execute RDRAND. */
1007#define VMX_EXIT_RDRAND 57
1008/** 58 INVPCID. Guest software attempted to execute INVPCID. */
1009#define VMX_EXIT_INVPCID 58
1010/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
1011#define VMX_EXIT_VMFUNC 59
1012/** The maximum exit value (inclusive). */
1013#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
1014/** @} */
1015
1016
1017/** @name VM Instruction Errors
1018 * @{
1019 */
1020/** VMCALL executed in VMX root operation. */
1021#define VMX_ERROR_VMCALL 1
1022/** VMCLEAR with invalid physical address. */
1023#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
1024/** VMCLEAR with VMXON pointer. */
1025#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
1026/** VMLAUNCH with non-clear VMCS. */
1027#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
1028/** VMRESUME with non-launched VMCS. */
1029#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
1030/** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
1031#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
1032/** VM-entry with invalid control field(s). */
1033#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
1034/** VM-entry with invalid host-state field(s). */
1035#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
1036/** VMPTRLD with invalid physical address. */
1037#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
1038/** VMPTRLD with VMXON pointer. */
1039#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
1040/** VMPTRLD with incorrect VMCS revision identifier. */
1041#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
1042/** VMREAD/VMWRITE from/to unsupported VMCS component. */
1043#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
1044#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
1045/** VMWRITE to read-only VMCS component. */
1046#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
1047/** VMXON executed in VMX root operation. */
1048#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
1049/** VM entry with invalid executive-VMCS pointer. */
1050#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
1051/** VM entry with non-launched executive VMCS. */
1052#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
1053/** VM entry with executive-VMCS pointer not VMXON pointer. */
1054#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
1055/** VMCALL with non-clear VMCS. */
1056#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
1057/** VMCALL with invalid VM-exit control fields. */
1058#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
1059/** VMCALL with incorrect MSEG revision identifier. */
1060#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
1061/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1062#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
1063/** VMCALL with invalid SMM-monitor features. */
1064#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
1065/** VM entry with invalid VM-execution control fields in executive VMCS. */
1066#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
1067/** VM entry with events blocked by MOV SS. */
1068#define VMX_ERROR_VMENTRY_MOV_SS 26
1069/** Invalid operand to INVEPT/INVVPID. */
1070#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
1071
1072/** @} */
1073
1074
1075/** @name VMX MSRs - Basic VMX information.
1076 * @{
1077 */
1078/** VMCS revision identifier used by the processor. */
1079#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
1080/** Size of the VMCS. */
1081#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) (((a) >> 32) & 0xFFF)
1082/** Width of physical address used for the VMCS.
1083 * 0 -> limited to the available amount of physical ram
1084 * 1 -> within the first 4 GB
1085 */
1086#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)
1087/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
1088#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) (((a) >> 49) & 1)
1089/** Memory type that must be used for the VMCS. */
1090#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xF)
1091/** Whether the processor provides additional information for exits due to INS/OUTS. */
1092#define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a) RT_BOOL((a) & RT_BIT_64(54))
1093/** @} */
1094
1095
1096/** @name VMX MSRs - Misc VMX info.
1097 * @{
1098 */
1099/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
1100#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
1101/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1102#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a) (((a) >> 5) & 1)
1103/** Activity states supported by the implementation. */
1104#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) (((a) >> 6) & 0x7)
1105/** Number of CR3 target values supported by the processor. (0-256) */
1106#define MSR_IA32_VMX_MISC_CR3_TARGET(a) (((a) >> 16) & 0x1FF)
1107/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
1108#define MSR_IA32_VMX_MISC_MAX_MSR(a) (((((a) >> 25) & 0x7) + 1) * 512)
1109/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
1110#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a) (((a) >> 15) & 1)
1111/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
1112#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a) (((a) >> 28) & 1)
1113/** Whether VMWRITE can be used to write VM-exit information fields. */
1114#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a) (((a) >> 29) & 1)
1115/** MSEG revision identifier used by the processor. */
1116#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
1117/** @} */
1118
1119
1120/** @name VMX MSRs - VMCS enumeration field info
1121 * @{
1122 */
1123/** Highest field index. */
1124#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) (((a) >> 1) & 0x1FF)
1125/** @} */
1126
1127
1128/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
1129 * @{
1130 */
1131#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1132#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY RT_BIT_64(1)
1133#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY RT_BIT_64(2)
1134#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS RT_BIT_64(3)
1135#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS RT_BIT_64(4)
1136#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS RT_BIT_64(5)
1137#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS RT_BIT_64(6)
1138#define MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS RT_BIT_64(7)
1139#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8)
1140#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC RT_BIT_64(9)
1141#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT RT_BIT_64(12)
1142#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP RT_BIT_64(13)
1143#define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14)
1144#define MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS RT_BIT_64(16)
1145#define MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS RT_BIT_64(17)
1146#define MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS RT_BIT_64(18)
1147#define MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS RT_BIT_64(19)
1148#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1149#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1150#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1151#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1152#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1153#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1154#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1155#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1156
1157/** @} */
1158
1159/** @name Extended Page Table Pointer (EPTP)
1160 * @{
1161 */
1162/** Uncachable EPT paging structure memory type. */
1163#define VMX_EPT_MEMTYPE_UC 0
1164/** Write-back EPT paging structure memory type. */
1165#define VMX_EPT_MEMTYPE_WB 6
1166/** Shift value to get the EPT page walk length (bits 5-3) */
1167#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
1168/** Mask value to get the EPT page walk length (bits 5-3) */
1169#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
1170/** Default EPT page-walk length (1 less than the actual EPT page-walk
1171 * length) */
1172#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
1173/** @} */
1174
1175
1176/** @name VMCS field encoding - 16 bits guest fields
1177 * @{
1178 */
1179#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
1180#define VMX_VMCS16_GUEST_FIELD_ES 0x800
1181#define VMX_VMCS16_GUEST_FIELD_CS 0x802
1182#define VMX_VMCS16_GUEST_FIELD_SS 0x804
1183#define VMX_VMCS16_GUEST_FIELD_DS 0x806
1184#define VMX_VMCS16_GUEST_FIELD_FS 0x808
1185#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
1186#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
1187#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
1188/** @} */
1189
1190/** @name VMCS field encoding - 16 bits host fields
1191 * @{
1192 */
1193#define VMX_VMCS16_HOST_FIELD_ES 0xC00
1194#define VMX_VMCS16_HOST_FIELD_CS 0xC02
1195#define VMX_VMCS16_HOST_FIELD_SS 0xC04
1196#define VMX_VMCS16_HOST_FIELD_DS 0xC06
1197#define VMX_VMCS16_HOST_FIELD_FS 0xC08
1198#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
1199#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
1200/** @} */
1201
1202/** @name VMCS field encoding - 64 bits host fields
1203 * @{
1204 */
1205#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
1206#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
1207#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
1208#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
1209#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
1210#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
1211/** @} */
1212
1213
1214/** @name VMCS field encoding - 64 Bits control fields
1215 * @{
1216 */
1217#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1218#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1219#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1220#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1221
1222/* Optional */
1223#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1224#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1225
1226#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1227#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1228#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1229#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1230
1231#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
1232#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
1233
1234#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
1235#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
1236
1237#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1238#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1239
1240/** Optional (VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW) */
1241#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
1242#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
1243
1244/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
1245#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1246#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1247
1248/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
1249#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1250#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1251
1252/** Extended page table pointer. */
1253#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1254#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1255
1256/** Extended page table pointer lists. */
1257#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1258#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1259
1260/** VM-exit guest phyiscal address. */
1261#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
1262#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
1263/** @} */
1264
1265
1266/** @name VMCS field encoding - 64 Bits guest fields
1267 * @{
1268 */
1269#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
1270#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
1271#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
1272#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
1273#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
1274#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
1275#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
1276#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
1277#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
1278#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
1279#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
1280#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
1281#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
1282#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
1283#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
1284#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
1285#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
1286#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
1287/** @} */
1288
1289
1290/** @name VMCS field encoding - 32 Bits control fields
1291 * @{
1292 */
1293#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
1294#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
1295#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
1296#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
1297#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
1298#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
1299#define VMX_VMCS32_CTRL_EXIT 0x400C
1300#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
1301#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
1302#define VMX_VMCS32_CTRL_ENTRY 0x4012
1303#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
1304#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
1305#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
1306#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
1307#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
1308#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401E
1309/** @} */
1310
1311
1312/** @name VMX_VMCS_CTRL_PIN_EXEC
1313 * @{
1314 */
1315/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1316#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT RT_BIT(0)
1317/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
1318#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT RT_BIT(3)
1319/** Virtual NMIs. */
1320#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI RT_BIT(5)
1321/** Activate VMX preemption timer. */
1322#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER RT_BIT(6)
1323/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
1324/** @} */
1325
1326/** @name VMX_VMCS_CTRL_PROC_EXEC
1327 * @{
1328 */
1329/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
1330#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT RT_BIT(2)
1331/** Use timestamp counter offset. */
1332#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING RT_BIT(3)
1333/** VM Exit when executing the HLT instruction. */
1334#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT RT_BIT(7)
1335/** VM Exit when executing the INVLPG instruction. */
1336#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT RT_BIT(9)
1337/** VM Exit when executing the MWAIT instruction. */
1338#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT RT_BIT(10)
1339/** VM Exit when executing the RDPMC instruction. */
1340#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT RT_BIT(11)
1341/** VM Exit when executing the RDTSC/RDTSCP instruction. */
1342#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT RT_BIT(12)
1343/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1344#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT RT_BIT(15)
1345/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1346#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT RT_BIT(16)
1347/** VM Exit on CR8 loads. */
1348#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT RT_BIT(19)
1349/** VM Exit on CR8 stores. */
1350#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT RT_BIT(20)
1351/** Use TPR shadow. */
1352#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW RT_BIT(21)
1353/** VM Exit when virtual nmi blocking is disabled. */
1354#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT RT_BIT(22)
1355/** VM Exit when executing a MOV DRx instruction. */
1356#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT RT_BIT(23)
1357/** VM Exit when executing IO instructions. */
1358#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT RT_BIT(24)
1359/** Use IO bitmaps. */
1360#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS RT_BIT(25)
1361/** Monitor trap flag. */
1362#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG RT_BIT(27)
1363/** Use MSR bitmaps. */
1364#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS RT_BIT(28)
1365/** VM Exit when executing the MONITOR instruction. */
1366#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT RT_BIT(29)
1367/** VM Exit when executing the PAUSE instruction. */
1368#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT RT_BIT(30)
1369/** Determines whether the secondary processor based VM-execution controls are used. */
1370#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
1371/** @} */
1372
1373/** @name VMX_VMCS_CTRL_PROC_EXEC2
1374 * @{
1375 */
1376/** Virtualize APIC access. */
1377#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
1378/** EPT supported/enabled. */
1379#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
1380/** Descriptor table instructions cause VM-exits. */
1381#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT RT_BIT(2)
1382/** RDTSCP supported/enabled. */
1383#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP RT_BIT(3)
1384/** Virtualize x2APIC mode. */
1385#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC RT_BIT(4)
1386/** VPID supported/enabled. */
1387#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
1388/** VM Exit when executing the WBINVD instruction. */
1389#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
1390/** Unrestricted guest execution. */
1391#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST RT_BIT(7)
1392/** A specified nr of pause loops cause a VM-exit. */
1393#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
1394/** VM Exit when executing RDRAND instructions. */
1395#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT RT_BIT(11)
1396/** Enables INVPCID instructions. */
1397#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID RT_BIT(12)
1398/** Enables VMFUNC instructions. */
1399#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC RT_BIT(13)
1400/** @} */
1401
1402
1403/** @name VMX_VMCS_CTRL_ENTRY
1404 * @{
1405 */
1406/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1407#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG RT_BIT(2)
1408/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
1409#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST RT_BIT(9)
1410/** In SMM mode after VM-entry. */
1411#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM RT_BIT(10)
1412/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
1413#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON RT_BIT(11)
1414/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
1415#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR RT_BIT(13)
1416/** Whether the guest IA32_PAT MSR is loaded on VM entry. */
1417#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR RT_BIT(14)
1418/** Whether the guest IA32_EFER MSR is loaded on VM entry. */
1419#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR RT_BIT(15)
1420/** @} */
1421
1422
1423/** @name VMX_VMCS_CTRL_EXIT
1424 * @{
1425 */
1426/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1427#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG RT_BIT(2)
1428/** Return to long mode after a VM-exit. */
1429#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE RT_BIT(9)
1430/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
1431#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR RT_BIT(12)
1432/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
1433#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT RT_BIT(15)
1434/** Whether the guest IA32_PAT MSR is saved on VM exit. */
1435#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR RT_BIT(18)
1436/** Whether the host IA32_PAT MSR is loaded on VM exit. */
1437#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR RT_BIT(19)
1438/** Whether the guest IA32_EFER MSR is saved on VM exit. */
1439#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR RT_BIT(20)
1440/** Whether the host IA32_EFER MSR is loaded on VM exit. */
1441#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR RT_BIT(21)
1442/** Whether the value of the VMX preemption timer is saved on every VM exit. */
1443#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
1444/** @} */
1445
1446
1447/** @name VMX_VMCS_CTRL_VMFUNC
1448 * @{
1449 */
1450/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1451#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING RT_BIT_64(0)
1452/** @} */
1453
1454
1455/** @name VMCS field encoding - 32 Bits read-only fields
1456 * @{
1457 */
1458#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
1459#define VMX_VMCS32_RO_EXIT_REASON 0x4402
1460#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
1461#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
1462#define VMX_VMCS32_RO_IDT_INFO 0x4408
1463#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
1464#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
1465#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
1466/** @} */
1467
1468/** @name VMX_VMCS32_RO_EXIT_REASON
1469 * @{
1470 */
1471#define VMX_EXIT_REASON_BASIC(a) (a & 0xffff)
1472/** @} */
1473
1474/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
1475 * @{
1476 */
1477#define VMX_ENTRY_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
1478#define VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT 8
1479#define VMX_ENTRY_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1480/** @} */
1481
1482
1483/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
1484 * @{
1485 */
1486#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
1487#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
1488#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
1489#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
1490#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
1491#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
1492#ifdef VBOX_WITH_OLD_VTX_CODE
1493# define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
1494#endif
1495#define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31)
1496#define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) (a & RT_BIT(31))
1497/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
1498#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
1499/** @} */
1500
1501/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
1502 * @{
1503 */
1504#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
1505#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
1506#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
1507#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT 4 /**< int xx */
1508#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DB_XCPT 5 /**< Why are we getting this one?? */
1509#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
1510/** @} */
1511
1512/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
1513 * @{
1514 */
1515#define VMX_IDT_VECTORING_INFO_VECTOR(a) (a & 0xff)
1516#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
1517#define VMX_IDT_VECTORING_INFO_TYPE(a) ((a >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
1518#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
1519#define VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID)
1520#define VMX_IDT_VECTORING_INFO_VALID(a) (a & RT_BIT(31))
1521#define VMX_ENTRY_INTR_INFO_FROM_EXIT_IDT_INFO(a) (a & ~RT_BIT(12))
1522/** @} */
1523
1524/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
1525 * @{
1526 */
1527#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
1528#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
1529#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
1530#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
1531#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
1532#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
1533/** @} */
1534
1535
1536/** @name VMCS field encoding - 32 Bits guest state fields
1537 * @{
1538 */
1539#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
1540#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
1541#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
1542#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
1543#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
1544#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
1545#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
1546#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
1547#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
1548#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
1549#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
1550#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
1551#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
1552#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
1553#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
1554#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
1555#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
1556#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
1557#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
1558#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
1559#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
1560#define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482E
1561/** @} */
1562
1563
1564/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1565 * @{
1566 */
1567/** The logical processor is active. */
1568#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
1569/** The logical processor is inactive, because executed a HLT instruction. */
1570#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
1571/** The logical processor is inactive, because of a triple fault or other serious error. */
1572#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
1573/** The logical processor is inactive, because it's waiting for a startup-IPI */
1574#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1575/** @} */
1576
1577
1578/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1579 * @{
1580 */
1581#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1582#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1583#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1584#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1585/** @} */
1586
1587
1588/** @name VMCS field encoding - 32 Bits host state fields
1589 * @{
1590 */
1591#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1592/** @} */
1593
1594/** @name Natural width control fields
1595 * @{
1596 */
1597#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1598#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1599#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1600#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1601#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1602#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1603#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1604#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1605/** @} */
1606
1607
1608/** @name Natural width read-only data fields
1609 * @{
1610 */
1611#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1612#define VMX_VMCS_RO_IO_RCX 0x6402
1613#define VMX_VMCS_RO_IO_RSX 0x6404
1614#define VMX_VMCS_RO_IO_RDI 0x6406
1615#define VMX_VMCS_RO_IO_RIP 0x6408
1616#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
1617/** @} */
1618
1619
1620/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1621 * @{
1622 */
1623/** 0-2: Debug register number */
1624#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1625/** 3: Reserved; cleared to 0. */
1626#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1627/** 4: Direction of move (0 = write, 1 = read) */
1628#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1629/** 5-7: Reserved; cleared to 0. */
1630#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1631/** 8-11: General purpose register number. */
1632#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1633/** Rest: reserved. */
1634/** @} */
1635
1636/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1637 * @{
1638 */
1639#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1640#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1641/** @} */
1642
1643
1644
1645/** @name CRx accesses
1646 * @{
1647 */
1648/** 0-3: Control register number (0 for CLTS & LMSW) */
1649#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1650/** 4-5: Access type. */
1651#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1652/** 6: LMSW operand type */
1653#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1654/** 7: Reserved; cleared to 0. */
1655#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1656/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1657#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1658/** 12-15: Reserved; cleared to 0. */
1659#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1660/** 16-31: LMSW source data (else 0). */
1661#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1662/** Rest: reserved. */
1663/** @} */
1664
1665/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1666 * @{
1667 */
1668#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1669#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1670#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1671#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1672/** @} */
1673
1674/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1675 * @{
1676 */
1677#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1678#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1679/** Task switch caused by a call instruction. */
1680#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1681/** Task switch caused by an iret instruction. */
1682#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1683/** Task switch caused by a jmp instruction. */
1684#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1685/** Task switch caused by an interrupt gate. */
1686#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1687/** @} */
1688
1689
1690/** @name VMX_EXIT_EPT_VIOLATION
1691 * @{
1692 */
1693/** Set if the violation was caused by a data read. */
1694#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1695/** Set if the violation was caused by a data write. */
1696#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1697/** Set if the violation was caused by an insruction fetch. */
1698#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1699/** AND of the present bit of all EPT structures. */
1700#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1701/** AND of the write bit of all EPT structures. */
1702#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1703/** AND of the execute bit of all EPT structures. */
1704#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1705/** Set if the guest linear address field contains the faulting address. */
1706#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1707/** If bit 7 is one: (reserved otherwise)
1708 * 1 - violation due to physical address access.
1709 * 0 - violation caused by page walk or access/dirty bit updates
1710 */
1711#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1712/** @} */
1713
1714
1715/** @name VMX_EXIT_PORT_IO
1716 * @{
1717 */
1718/** 0-2: IO operation width. */
1719#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) ((a) & 7)
1720/** 3: IO operation direction. */
1721#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) (((a) >> 3) & 1)
1722/** 4: String IO operation (INS / OUTS). */
1723#define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))
1724/** 5: Repeated IO operation. */
1725#define VMX_EXIT_QUALIFICATION_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))
1726/** 6: Operand encoding. */
1727#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) (((a) >> 6) & 1)
1728/** 16-31: IO Port (0-0xffff). */
1729#define VMX_EXIT_QUALIFICATION_IO_PORT(a) (((a) >> 16) & 0xffff)
1730/* Rest reserved. */
1731/** @} */
1732
1733/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1734 * @{
1735 */
1736#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1737#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1738/** @} */
1739
1740
1741/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1742 * @{
1743 */
1744#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1745#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1746/** @} */
1747
1748/** @name VMX_EXIT_APIC_ACCESS
1749 * @{
1750 */
1751/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1752#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
1753/** 12-15: Access type. */
1754#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a) & 0xf000)
1755/* Rest reserved. */
1756/** @} */
1757
1758
1759/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1760 * @{
1761 */
1762/** Linear read access. */
1763#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1764/** Linear write access. */
1765#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1766/** Linear instruction fetch access. */
1767#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1768/** Linear read/write access during event delivery. */
1769#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1770/** Physical read/write access during event delivery. */
1771#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1772/** Physical access for an instruction fetch or during instruction execution. */
1773#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1774/** @} */
1775
1776/** @} */
1777
1778/** @name VMCS field encoding - Natural width guest state fields
1779 * @{
1780 */
1781#define VMX_VMCS_GUEST_CR0 0x6800
1782#define VMX_VMCS_GUEST_CR3 0x6802
1783#define VMX_VMCS_GUEST_CR4 0x6804
1784#define VMX_VMCS_GUEST_ES_BASE 0x6806
1785#define VMX_VMCS_GUEST_CS_BASE 0x6808
1786#define VMX_VMCS_GUEST_SS_BASE 0x680A
1787#define VMX_VMCS_GUEST_DS_BASE 0x680C
1788#define VMX_VMCS_GUEST_FS_BASE 0x680E
1789#define VMX_VMCS_GUEST_GS_BASE 0x6810
1790#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1791#define VMX_VMCS_GUEST_TR_BASE 0x6814
1792#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1793#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1794#define VMX_VMCS_GUEST_DR7 0x681A
1795#define VMX_VMCS_GUEST_RSP 0x681C
1796#define VMX_VMCS_GUEST_RIP 0x681E
1797#define VMX_VMCS_GUEST_RFLAGS 0x6820
1798#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
1799#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1800#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1801/** @} */
1802
1803
1804/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1805 * @{
1806 */
1807/** Hardware breakpoint 0 was met. */
1808#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1809/** Hardware breakpoint 1 was met. */
1810#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1811/** Hardware breakpoint 2 was met. */
1812#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1813/** Hardware breakpoint 3 was met. */
1814#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1815/** At least one data or IO breakpoint was hit. */
1816#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1817/** A debug exception would have been triggered by single-step execution mode. */
1818#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1819/** Bits 4-11, 13 and 15-63 are reserved. */
1820
1821/** @} */
1822
1823/** @name VMCS field encoding - Natural width host state fields
1824 * @{
1825 */
1826#define VMX_VMCS_HOST_CR0 0x6C00
1827#define VMX_VMCS_HOST_CR3 0x6C02
1828#define VMX_VMCS_HOST_CR4 0x6C04
1829#define VMX_VMCS_HOST_FS_BASE 0x6C06
1830#define VMX_VMCS_HOST_GS_BASE 0x6C08
1831#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1832#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1833#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1834#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1835#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1836#define VMX_VMCS_HOST_RSP 0x6C14
1837#define VMX_VMCS_HOST_RIP 0x6C16
1838/** @} */
1839
1840/** @} */
1841
1842
1843/** @defgroup grp_vmx_asm vmx assembly helpers
1844 * @ingroup grp_vmx
1845 * @{
1846 */
1847
1848/**
1849 * Restores some host-state fields that need not be done on every VM-exit.
1850 *
1851 * @returns VBox status code.
1852 * @param fRestoreHostFlags Flags of which host registers needs to be
1853 * restored.
1854 * @param pRestoreHost Pointer to the host-restore structure.
1855 */
1856DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1857
1858
1859/**
1860 * Dispatches an NMI to the host.
1861 */
1862DECLASM(int) VMXDispatchHostNmi(void);
1863
1864
1865/**
1866 * Executes VMXON
1867 *
1868 * @returns VBox status code
1869 * @param pVMXOn Physical address of VMXON structure
1870 */
1871#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1872DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1873#else
1874DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1875{
1876# if RT_INLINE_ASM_GNU_STYLE
1877 int rc = VINF_SUCCESS;
1878 __asm__ __volatile__ (
1879 "push %3 \n\t"
1880 "push %2 \n\t"
1881 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1882 "ja 2f \n\t"
1883 "je 1f \n\t"
1884 "movl $"RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1885 "jmp 2f \n\t"
1886 "1: \n\t"
1887 "movl $"RT_XSTR(VERR_VMX_VMXON_FAILED)", %0 \n\t"
1888 "2: \n\t"
1889 "add $8, %%esp \n\t"
1890 :"=rm"(rc)
1891 :"0"(VINF_SUCCESS),
1892 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1893 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1894 :"memory"
1895 );
1896 return rc;
1897
1898# elif VMX_USE_MSC_INTRINSICS
1899 unsigned char rcMsc = __vmx_on(&pVMXOn);
1900 if (RT_LIKELY(rcMsc == 0))
1901 return VINF_SUCCESS;
1902 return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
1903
1904# else
1905 int rc = VINF_SUCCESS;
1906 __asm
1907 {
1908 push dword ptr [pVMXOn+4]
1909 push dword ptr [pVMXOn]
1910 _emit 0xF3
1911 _emit 0x0F
1912 _emit 0xC7
1913 _emit 0x34
1914 _emit 0x24 /* VMXON [esp] */
1915 jnc vmxon_good
1916 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1917 jmp the_end
1918
1919vmxon_good:
1920 jnz the_end
1921 mov dword ptr [rc], VERR_VMX_VMXON_FAILED
1922the_end:
1923 add esp, 8
1924 }
1925 return rc;
1926# endif
1927}
1928#endif
1929
1930
1931/**
1932 * Executes VMXOFF
1933 */
1934#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1935DECLASM(void) VMXDisable(void);
1936#else
1937DECLINLINE(void) VMXDisable(void)
1938{
1939# if RT_INLINE_ASM_GNU_STYLE
1940 __asm__ __volatile__ (
1941 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1942 );
1943
1944# elif VMX_USE_MSC_INTRINSICS
1945 __vmx_off();
1946
1947# else
1948 __asm
1949 {
1950 _emit 0x0F
1951 _emit 0x01
1952 _emit 0xC4 /* VMXOFF */
1953 }
1954# endif
1955}
1956#endif
1957
1958
1959/**
1960 * Executes VMCLEAR
1961 *
1962 * @returns VBox status code
1963 * @param pVMCS Physical address of VM control structure
1964 */
1965#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1966DECLASM(int) VMXClearVmcs(RTHCPHYS pVMCS);
1967#else
1968DECLINLINE(int) VMXClearVmcs(RTHCPHYS pVMCS)
1969{
1970# if RT_INLINE_ASM_GNU_STYLE
1971 int rc = VINF_SUCCESS;
1972 __asm__ __volatile__ (
1973 "push %3 \n\t"
1974 "push %2 \n\t"
1975 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1976 "jnc 1f \n\t"
1977 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1978 "1: \n\t"
1979 "add $8, %%esp \n\t"
1980 :"=rm"(rc)
1981 :"0"(VINF_SUCCESS),
1982 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1983 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1984 :"memory"
1985 );
1986 return rc;
1987
1988# elif VMX_USE_MSC_INTRINSICS
1989 unsigned char rcMsc = __vmx_vmclear(&pVMCS);
1990 if (RT_LIKELY(rcMsc == 0))
1991 return VINF_SUCCESS;
1992 return VERR_VMX_INVALID_VMCS_PTR;
1993
1994# else
1995 int rc = VINF_SUCCESS;
1996 __asm
1997 {
1998 push dword ptr [pVMCS+4]
1999 push dword ptr [pVMCS]
2000 _emit 0x66
2001 _emit 0x0F
2002 _emit 0xC7
2003 _emit 0x34
2004 _emit 0x24 /* VMCLEAR [esp] */
2005 jnc success
2006 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2007success:
2008 add esp, 8
2009 }
2010 return rc;
2011# endif
2012}
2013#endif
2014
2015
2016/**
2017 * Executes VMPTRLD
2018 *
2019 * @returns VBox status code
2020 * @param pVMCS Physical address of VMCS structure
2021 */
2022#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2023DECLASM(int) VMXActivateVmcs(RTHCPHYS pVMCS);
2024#else
2025DECLINLINE(int) VMXActivateVmcs(RTHCPHYS pVMCS)
2026{
2027# if RT_INLINE_ASM_GNU_STYLE
2028 int rc = VINF_SUCCESS;
2029 __asm__ __volatile__ (
2030 "push %3 \n\t"
2031 "push %2 \n\t"
2032 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
2033 "jnc 1f \n\t"
2034 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2035 "1: \n\t"
2036 "add $8, %%esp \n\t"
2037 :"=rm"(rc)
2038 :"0"(VINF_SUCCESS),
2039 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
2040 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
2041 );
2042 return rc;
2043
2044# elif VMX_USE_MSC_INTRINSICS
2045 unsigned char rcMsc = __vmx_vmptrld(&pVMCS);
2046 if (RT_LIKELY(rcMsc == 0))
2047 return VINF_SUCCESS;
2048 return VERR_VMX_INVALID_VMCS_PTR;
2049
2050# else
2051 int rc = VINF_SUCCESS;
2052 __asm
2053 {
2054 push dword ptr [pVMCS+4]
2055 push dword ptr [pVMCS]
2056 _emit 0x0F
2057 _emit 0xC7
2058 _emit 0x34
2059 _emit 0x24 /* VMPTRLD [esp] */
2060 jnc success
2061 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2062
2063success:
2064 add esp, 8
2065 }
2066 return rc;
2067# endif
2068}
2069#endif
2070
2071/**
2072 * Executes VMPTRST
2073 *
2074 * @returns VBox status code
2075 * @param pVMCS Address that will receive the current pointer
2076 */
2077DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pVMCS);
2078
2079/**
2080 * Executes VMWRITE
2081 *
2082 * @returns VBox status code
2083 * @retval VINF_SUCCESS
2084 * @retval VERR_VMX_INVALID_VMCS_PTR
2085 * @retval VERR_VMX_INVALID_VMCS_FIELD
2086 *
2087 * @param idxField VMCS index
2088 * @param u32Val 32 bits value
2089 *
2090 * @remarks The values of the two status codes can be ORed together, the result
2091 * will be VERR_VMX_INVALID_VMCS_PTR.
2092 */
2093#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2094DECLASM(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val);
2095#else
2096DECLINLINE(int) VMXWriteVmcs32(uint32_t idxField, uint32_t u32Val)
2097{
2098# if RT_INLINE_ASM_GNU_STYLE
2099 int rc = VINF_SUCCESS;
2100 __asm__ __volatile__ (
2101 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
2102 "ja 2f \n\t"
2103 "je 1f \n\t"
2104 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2105 "jmp 2f \n\t"
2106 "1: \n\t"
2107 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2108 "2: \n\t"
2109 :"=rm"(rc)
2110 :"0"(VINF_SUCCESS),
2111 "a"(idxField),
2112 "d"(u32Val)
2113 );
2114 return rc;
2115
2116# elif VMX_USE_MSC_INTRINSICS
2117 unsigned char rcMsc = __vmx_vmwrite(idxField, u32Val);
2118 if (RT_LIKELY(rcMsc == 0))
2119 return VINF_SUCCESS;
2120 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2121
2122#else
2123 int rc = VINF_SUCCESS;
2124 __asm
2125 {
2126 push dword ptr [u32Val]
2127 mov eax, [idxField]
2128 _emit 0x0F
2129 _emit 0x79
2130 _emit 0x04
2131 _emit 0x24 /* VMWRITE eax, [esp] */
2132 jnc valid_vmcs
2133 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2134 jmp the_end
2135
2136valid_vmcs:
2137 jnz the_end
2138 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2139the_end:
2140 add esp, 4
2141 }
2142 return rc;
2143# endif
2144}
2145#endif
2146
2147/**
2148 * Executes VMWRITE
2149 *
2150 * @returns VBox status code
2151 * @retval VINF_SUCCESS
2152 * @retval VERR_VMX_INVALID_VMCS_PTR
2153 * @retval VERR_VMX_INVALID_VMCS_FIELD
2154 *
2155 * @param idxField VMCS index
2156 * @param u64Val 16, 32 or 64 bits value
2157 *
2158 * @remarks The values of the two status codes can be ORed together, the result
2159 * will be VERR_VMX_INVALID_VMCS_PTR.
2160 */
2161#if !defined(RT_ARCH_X86) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2162# if !VMX_USE_MSC_INTRINSICS || ARCH_BITS != 64
2163DECLASM(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val);
2164# else /* VMX_USE_MSC_INTRINSICS */
2165DECLINLINE(int) VMXWriteVmcs64(uint32_t idxField, uint64_t u64Val)
2166{
2167 unsigned char rcMsc = __vmx_vmwrite(idxField, u64Val);
2168 if (RT_LIKELY(rcMsc == 0))
2169 return VINF_SUCCESS;
2170 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2171}
2172# endif /* VMX_USE_MSC_INTRINSICS */
2173#else
2174# define VMXWriteVmcs64(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val) /** @todo dead ugly, picking up pVCpu like this */
2175VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
2176#endif
2177
2178#ifdef VBOX_WITH_OLD_VTX_CODE
2179# if ARCH_BITS == 64
2180# define VMXWriteVmcs VMXWriteVmcs64
2181# else
2182# define VMXWriteVmcs VMXWriteVmcs32
2183# endif
2184#else /* !VBOX_WITH_OLD_VTX_CODE */
2185# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2186# define VMXWriteVmcsHstN(idxField, uVal) HMVMX_IS_64BIT_HOST_MODE() ? \
2187 VMXWriteVmcs64(idxField, uVal) \
2188 : VMXWriteVmcs32(idxField, uVal)
2189# define VMXWriteVmcsGstN(idxField, u64Val) (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests) ? \
2190 VMXWriteVmcs64(idxField, u64Val) \
2191 : VMXWriteVmcs32(idxField, u64Val)
2192# elif ARCH_BITS == 32
2193# define VMXWriteVmcsHstN VMXWriteVmcs32
2194# define VMXWriteVmcsGstN(idxField, u64Val) VMXWriteVmcs64Ex(pVCpu, idxField, u64Val)
2195# else /* ARCH_BITS == 64 */
2196# define VMXWriteVmcsHstN VMXWriteVmcs64
2197# define VMXWriteVmcsGstN VMXWriteVmcs64
2198# endif
2199#endif /* !VBOX_WITH_OLD_VTX_CODE */
2200
2201
2202/**
2203 * Invalidate a page using invept
2204 * @returns VBox status code
2205 * @param enmFlush Type of flush
2206 * @param pDescriptor Descriptor
2207 */
2208DECLASM(int) VMXR0InvEPT(VMX_FLUSH_EPT enmFlush, uint64_t *pDescriptor);
2209
2210/**
2211 * Invalidate a page using invvpid
2212 * @returns VBox status code
2213 * @param enmFlush Type of flush
2214 * @param pDescriptor Descriptor
2215 */
2216DECLASM(int) VMXR0InvVPID(VMX_FLUSH_VPID enmFlush, uint64_t *pDescriptor);
2217
2218/**
2219 * Executes VMREAD
2220 *
2221 * @returns VBox status code
2222 * @retval VINF_SUCCESS
2223 * @retval VERR_VMX_INVALID_VMCS_PTR
2224 * @retval VERR_VMX_INVALID_VMCS_FIELD
2225 *
2226 * @param idxField VMCS index
2227 * @param pData Ptr to store VM field value
2228 *
2229 * @remarks The values of the two status codes can be ORed together, the result
2230 * will be VERR_VMX_INVALID_VMCS_PTR.
2231 */
2232#if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2233DECLASM(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData);
2234#else
2235DECLINLINE(int) VMXReadVmcs32(uint32_t idxField, uint32_t *pData)
2236{
2237# if RT_INLINE_ASM_GNU_STYLE
2238 int rc = VINF_SUCCESS;
2239 __asm__ __volatile__ (
2240 "movl $"RT_XSTR(VINF_SUCCESS)", %0 \n\t"
2241 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
2242 "ja 2f \n\t"
2243 "je 1f \n\t"
2244 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
2245 "jmp 2f \n\t"
2246 "1: \n\t"
2247 "movl $"RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
2248 "2: \n\t"
2249 :"=&r"(rc),
2250 "=d"(*pData)
2251 :"a"(idxField),
2252 "d"(0)
2253 );
2254 return rc;
2255
2256# elif VMX_USE_MSC_INTRINSICS
2257 unsigned char rcMsc;
2258# if ARCH_BITS == 32
2259 rcMsc = __vmx_vmread(idxField, pData);
2260# else
2261 uint64_t u64Tmp;
2262 rcMsc = __vmx_vmread(idxField, &u64Tmp);
2263 *pData = (uint32_t)u64Tmp;
2264# endif
2265 if (RT_LIKELY(rcMsc == 0))
2266 return VINF_SUCCESS;
2267 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2268
2269#else
2270 int rc = VINF_SUCCESS;
2271 __asm
2272 {
2273 sub esp, 4
2274 mov dword ptr [esp], 0
2275 mov eax, [idxField]
2276 _emit 0x0F
2277 _emit 0x78
2278 _emit 0x04
2279 _emit 0x24 /* VMREAD eax, [esp] */
2280 mov edx, pData
2281 pop dword ptr [edx]
2282 jnc valid_vmcs
2283 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
2284 jmp the_end
2285
2286valid_vmcs:
2287 jnz the_end
2288 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
2289the_end:
2290 }
2291 return rc;
2292# endif
2293}
2294#endif
2295
2296/**
2297 * Executes VMREAD
2298 *
2299 * @returns VBox status code
2300 * @retval VINF_SUCCESS
2301 * @retval VERR_VMX_INVALID_VMCS_PTR
2302 * @retval VERR_VMX_INVALID_VMCS_FIELD
2303 *
2304 * @param idxField VMCS index
2305 * @param pData Ptr to store VM field value
2306 *
2307 * @remarks The values of the two status codes can be ORed together, the result
2308 * will be VERR_VMX_INVALID_VMCS_PTR.
2309 */
2310#if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS) || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2311DECLASM(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData);
2312#else
2313DECLINLINE(int) VMXReadVmcs64(uint32_t idxField, uint64_t *pData)
2314{
2315# if VMX_USE_MSC_INTRINSICS
2316 unsigned char rcMsc;
2317# if ARCH_BITS == 32
2318 size_t uLow;
2319 size_t uHigh;
2320 rcMsc = __vmx_vmread(idxField, &uLow);
2321 rcMsc |= __vmx_vmread(idxField + 1, &uHigh);
2322 *pData = RT_MAKE_U64(uLow, uHigh);
2323# else
2324 rcMsc = __vmx_vmread(idxField, pData);
2325# endif
2326 if (RT_LIKELY(rcMsc == 0))
2327 return VINF_SUCCESS;
2328 return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
2329
2330# elif ARCH_BITS == 32
2331 int rc;
2332 uint32_t val_hi, val;
2333 rc = VMXReadVmcs32(idxField, &val);
2334 rc |= VMXReadVmcs32(idxField + 1, &val_hi);
2335 AssertRC(rc);
2336 *pData = RT_MAKE_U64(val, val_hi);
2337 return rc;
2338
2339# else
2340# error "Shouldn't be here..."
2341# endif
2342}
2343#endif
2344
2345#ifdef VBOX_WITH_OLD_VTX_CODE
2346# if ARCH_BITS == 64
2347# define VMXReadVmcsField VMXReadVmcs64
2348# else
2349# define VMXReadVmcsField VMXReadVmcs32
2350# endif
2351#endif
2352
2353/**
2354 * Gets the last instruction error value from the current VMCS
2355 *
2356 * @returns error value
2357 */
2358DECLINLINE(uint32_t) VMXGetLastError(void)
2359{
2360#if ARCH_BITS == 64
2361 uint64_t uLastError = 0;
2362 int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2363 AssertRC(rc);
2364 return (uint32_t)uLastError;
2365
2366#else /* 32-bit host: */
2367 uint32_t uLastError = 0;
2368 int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
2369 AssertRC(rc);
2370 return uLastError;
2371#endif
2372}
2373
2374#ifdef IN_RING0
2375VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
2376VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
2377#endif /* IN_RING0 */
2378
2379/** @} */
2380
2381#endif
2382
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