VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 65904

Last change on this file since 65904 was 65904, checked in by vboxsync, 8 years ago

VMM: Nested Hw.virt: Started with tweaking the AMD bits and laying the groundwork.
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1/** @file
2 * HM - SVM (AMD-V) Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2016 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_svm_h
27#define ___VBox_vmm_svm_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/assert.h>
32#include <iprt/asm.h>
33
34
35/** @defgroup grp_hm_svm SVM (AMD-V) Types and Definitions
36 * @ingroup grp_hm
37 * @{
38 */
39
40/** @name SVM features for cpuid 0x8000000a
41 * @{
42 */
43/** Bit 0 - NP - Nested Paging supported. */
44#define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
45/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
46#define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
47/** Bit 2 - SVML - SVM locking bit supported. */
48#define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
49/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
50#define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
51/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
52#define AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
53/** Bit 5 - VmcbClean - Support VMCB clean bits. */
54#define AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
55/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
56 * VMCB.TLB_Control is supported. */
57#define AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
58/** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
59#define AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
60/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
61#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
62/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
63 * intercept filter cycle count threshold. */
64#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
65/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
66#define AMD_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
67/** @} */
68
69
70/** @name SVM Basic Exit Reasons.
71 * @{
72 */
73/** Invalid guest state in VMCB. */
74#define SVM_EXIT_INVALID (-1)
75/** Read from CR0-CR15. */
76#define SVM_EXIT_READ_CR0 0x0
77#define SVM_EXIT_READ_CR1 0x1
78#define SVM_EXIT_READ_CR2 0x2
79#define SVM_EXIT_READ_CR3 0x3
80#define SVM_EXIT_READ_CR4 0x4
81#define SVM_EXIT_READ_CR5 0x5
82#define SVM_EXIT_READ_CR6 0x6
83#define SVM_EXIT_READ_CR7 0x7
84#define SVM_EXIT_READ_CR8 0x8
85#define SVM_EXIT_READ_CR9 0x9
86#define SVM_EXIT_READ_CR10 0xA
87#define SVM_EXIT_READ_CR11 0xB
88#define SVM_EXIT_READ_CR12 0xC
89#define SVM_EXIT_READ_CR13 0xD
90#define SVM_EXIT_READ_CR14 0xE
91#define SVM_EXIT_READ_CR15 0xF
92/** Writes to CR0-CR15. */
93#define SVM_EXIT_WRITE_CR0 0x10
94#define SVM_EXIT_WRITE_CR1 0x11
95#define SVM_EXIT_WRITE_CR2 0x12
96#define SVM_EXIT_WRITE_CR3 0x13
97#define SVM_EXIT_WRITE_CR4 0x14
98#define SVM_EXIT_WRITE_CR5 0x15
99#define SVM_EXIT_WRITE_CR6 0x16
100#define SVM_EXIT_WRITE_CR7 0x17
101#define SVM_EXIT_WRITE_CR8 0x18
102#define SVM_EXIT_WRITE_CR9 0x19
103#define SVM_EXIT_WRITE_CR10 0x1A
104#define SVM_EXIT_WRITE_CR11 0x1B
105#define SVM_EXIT_WRITE_CR12 0x1C
106#define SVM_EXIT_WRITE_CR13 0x1D
107#define SVM_EXIT_WRITE_CR14 0x1E
108#define SVM_EXIT_WRITE_CR15 0x1F
109/** Read from DR0-DR15. */
110#define SVM_EXIT_READ_DR0 0x20
111#define SVM_EXIT_READ_DR1 0x21
112#define SVM_EXIT_READ_DR2 0x22
113#define SVM_EXIT_READ_DR3 0x23
114#define SVM_EXIT_READ_DR4 0x24
115#define SVM_EXIT_READ_DR5 0x25
116#define SVM_EXIT_READ_DR6 0x26
117#define SVM_EXIT_READ_DR7 0x27
118#define SVM_EXIT_READ_DR8 0x28
119#define SVM_EXIT_READ_DR9 0x29
120#define SVM_EXIT_READ_DR10 0x2A
121#define SVM_EXIT_READ_DR11 0x2B
122#define SVM_EXIT_READ_DR12 0x2C
123#define SVM_EXIT_READ_DR13 0x2D
124#define SVM_EXIT_READ_DR14 0x2E
125#define SVM_EXIT_READ_DR15 0x2F
126/** Writes to DR0-DR15. */
127#define SVM_EXIT_WRITE_DR0 0x30
128#define SVM_EXIT_WRITE_DR1 0x31
129#define SVM_EXIT_WRITE_DR2 0x32
130#define SVM_EXIT_WRITE_DR3 0x33
131#define SVM_EXIT_WRITE_DR4 0x34
132#define SVM_EXIT_WRITE_DR5 0x35
133#define SVM_EXIT_WRITE_DR6 0x36
134#define SVM_EXIT_WRITE_DR7 0x37
135#define SVM_EXIT_WRITE_DR8 0x38
136#define SVM_EXIT_WRITE_DR9 0x39
137#define SVM_EXIT_WRITE_DR10 0x3A
138#define SVM_EXIT_WRITE_DR11 0x3B
139#define SVM_EXIT_WRITE_DR12 0x3C
140#define SVM_EXIT_WRITE_DR13 0x3D
141#define SVM_EXIT_WRITE_DR14 0x3E
142#define SVM_EXIT_WRITE_DR15 0x3F
143/* Exception 0-31. */
144#define SVM_EXIT_EXCEPTION_0 0x40
145#define SVM_EXIT_EXCEPTION_1 0x41
146#define SVM_EXIT_EXCEPTION_2 0x42
147#define SVM_EXIT_EXCEPTION_3 0x43
148#define SVM_EXIT_EXCEPTION_4 0x44
149#define SVM_EXIT_EXCEPTION_5 0x45
150#define SVM_EXIT_EXCEPTION_6 0x46
151#define SVM_EXIT_EXCEPTION_7 0x47
152#define SVM_EXIT_EXCEPTION_8 0x48
153#define SVM_EXIT_EXCEPTION_9 0x49
154#define SVM_EXIT_EXCEPTION_A 0x4A
155#define SVM_EXIT_EXCEPTION_B 0x4B
156#define SVM_EXIT_EXCEPTION_C 0x4C
157#define SVM_EXIT_EXCEPTION_D 0x4D
158#define SVM_EXIT_EXCEPTION_E 0x4E
159#define SVM_EXIT_EXCEPTION_F 0x4F
160#define SVM_EXIT_EXCEPTION_10 0x50
161#define SVM_EXIT_EXCEPTION_11 0x51
162#define SVM_EXIT_EXCEPTION_12 0x52
163#define SVM_EXIT_EXCEPTION_13 0x53
164#define SVM_EXIT_EXCEPTION_14 0x54
165#define SVM_EXIT_EXCEPTION_15 0x55
166#define SVM_EXIT_EXCEPTION_16 0x56
167#define SVM_EXIT_EXCEPTION_17 0x57
168#define SVM_EXIT_EXCEPTION_18 0x58
169#define SVM_EXIT_EXCEPTION_19 0x59
170#define SVM_EXIT_EXCEPTION_1A 0x5A
171#define SVM_EXIT_EXCEPTION_1B 0x5B
172#define SVM_EXIT_EXCEPTION_1C 0x5C
173#define SVM_EXIT_EXCEPTION_1D 0x5D
174#define SVM_EXIT_EXCEPTION_1E 0x5E
175#define SVM_EXIT_EXCEPTION_1F 0x5F
176/** Physical maskable interrupt. */
177#define SVM_EXIT_INTR 0x60
178/** Non-maskable interrupt. */
179#define SVM_EXIT_NMI 0x61
180/** System Management interrupt. */
181#define SVM_EXIT_SMI 0x62
182/** Physical INIT signal. */
183#define SVM_EXIT_INIT 0x63
184/** Virtual interrupt. */
185#define SVM_EXIT_VINTR 0x64
186/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
187#define SVM_EXIT_CR0_SEL_WRITE 0x65
188/** IDTR read. */
189#define SVM_EXIT_IDTR_READ 0x66
190/** GDTR read. */
191#define SVM_EXIT_GDTR_READ 0x67
192/** LDTR read. */
193#define SVM_EXIT_LDTR_READ 0x68
194/** TR read. */
195#define SVM_EXIT_TR_READ 0x69
196/** IDTR write. */
197#define SVM_EXIT_IDTR_WRITE 0x6A
198/** GDTR write. */
199#define SVM_EXIT_GDTR_WRITE 0x6B
200/** LDTR write. */
201#define SVM_EXIT_LDTR_WRITE 0x6C
202/** TR write. */
203#define SVM_EXIT_TR_WRITE 0x6D
204/** RDTSC instruction. */
205#define SVM_EXIT_RDTSC 0x6E
206/** RDPMC instruction. */
207#define SVM_EXIT_RDPMC 0x6F
208/** PUSHF instruction. */
209#define SVM_EXIT_PUSHF 0x70
210/** POPF instruction. */
211#define SVM_EXIT_POPF 0x71
212/** CPUID instruction. */
213#define SVM_EXIT_CPUID 0x72
214/** RSM instruction. */
215#define SVM_EXIT_RSM 0x73
216/** IRET instruction. */
217#define SVM_EXIT_IRET 0x74
218/** software interrupt (INTn instructions). */
219#define SVM_EXIT_SWINT 0x75
220/** INVD instruction. */
221#define SVM_EXIT_INVD 0x76
222/** PAUSE instruction. */
223#define SVM_EXIT_PAUSE 0x77
224/** HLT instruction. */
225#define SVM_EXIT_HLT 0x78
226/** INVLPG instructions. */
227#define SVM_EXIT_INVLPG 0x79
228/** INVLPGA instruction. */
229#define SVM_EXIT_INVLPGA 0x7A
230/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
231#define SVM_EXIT_IOIO 0x7B
232/** RDMSR or WRMSR access to protected MSR. */
233#define SVM_EXIT_MSR 0x7C
234/** task switch. */
235#define SVM_EXIT_TASK_SWITCH 0x7D
236/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
237#define SVM_EXIT_FERR_FREEZE 0x7E
238/** Shutdown. */
239#define SVM_EXIT_SHUTDOWN 0x7F
240/** VMRUN instruction. */
241#define SVM_EXIT_VMRUN 0x80
242/** VMMCALL instruction. */
243#define SVM_EXIT_VMMCALL 0x81
244/** VMLOAD instruction. */
245#define SVM_EXIT_VMLOAD 0x82
246/** VMSAVE instruction. */
247#define SVM_EXIT_VMSAVE 0x83
248/** STGI instruction. */
249#define SVM_EXIT_STGI 0x84
250/** CLGI instruction. */
251#define SVM_EXIT_CLGI 0x85
252/** SKINIT instruction. */
253#define SVM_EXIT_SKINIT 0x86
254/** RDTSCP instruction. */
255#define SVM_EXIT_RDTSCP 0x87
256/** ICEBP instruction. */
257#define SVM_EXIT_ICEBP 0x88
258/** WBINVD instruction. */
259#define SVM_EXIT_WBINVD 0x89
260/** MONITOR instruction. */
261#define SVM_EXIT_MONITOR 0x8A
262/** MWAIT instruction. */
263#define SVM_EXIT_MWAIT 0x8B
264/** MWAIT instruction, when armed. */
265#define SVM_EXIT_MWAIT_ARMED 0x8C
266/** XSETBV instruction. */
267#define SVM_EXIT_XSETBV 0x8D
268/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
269#define SVM_EXIT_NPF 0x400
270/** AVIC: Virtual IPI delivery not completed. */
271#define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
272/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
273 * hardware. */
274#define SVM_EXIT_AVIC_NOACCEL 0x402
275
276/** The maximum possible exit value. */
277#define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
278/** @} */
279
280
281/** @name SVMVMCB.u64ExitInfo2 for task switches
282 * @{
283 */
284/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
285#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
286/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
287#define SVM_EXIT2_TASK_SWITCH_JMP RT_BIT_64(38)
288/** Set to 1 if the task switch has an error code; else cleared to 0. */
289#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
290/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
291#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
292/** @} */
293
294/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
295 * @{
296 */
297/** The access was a read MSR. */
298#define SVM_EXIT1_MSR_READ 0x0
299/** The access was a write MSR. */
300#define SVM_EXIT1_MSR_WRITE 0x1
301/** @} */
302
303
304/** @name SVMVMCB.ctrl.u64InterceptCtrl
305 * @{
306 */
307/** Intercept INTR (physical maskable interrupt). */
308#define SVM_CTRL_INTERCEPT_INTR RT_BIT_64(0)
309/** Intercept NMI. */
310#define SVM_CTRL_INTERCEPT_NMI RT_BIT_64(1)
311/** Intercept SMI. */
312#define SVM_CTRL_INTERCEPT_SMI RT_BIT_64(2)
313/** Intercept INIT. */
314#define SVM_CTRL_INTERCEPT_INIT RT_BIT_64(3)
315/** Intercept VINTR (virtual maskable interrupt). */
316#define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4)
317/** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
318#define SVM_CTRL_INTERCEPT_CR0 RT_BIT_64(5)
319/** Intercept reads of IDTR. */
320#define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6)
321/** Intercept reads of GDTR. */
322#define SVM_CTRL_INTERCEPT_GDTR_READS RT_BIT_64(7)
323/** Intercept reads of LDTR. */
324#define SVM_CTRL_INTERCEPT_LDTR_READS RT_BIT_64(8)
325/** Intercept reads of TR. */
326#define SVM_CTRL_INTERCEPT_TR_READS RT_BIT_64(9)
327/** Intercept writes of IDTR. */
328#define SVM_CTRL_INTERCEPT_IDTR_WRITES RT_BIT_64(10)
329/** Intercept writes of GDTR. */
330#define SVM_CTRL_INTERCEPT_GDTR_WRITES RT_BIT_64(11)
331/** Intercept writes of LDTR. */
332#define SVM_CTRL_INTERCEPT_LDTR_WRITES RT_BIT_64(12)
333/** Intercept writes of TR. */
334#define SVM_CTRL_INTERCEPT_TR_WRITES RT_BIT_64(13)
335/** Intercept RDTSC instruction. */
336#define SVM_CTRL_INTERCEPT_RDTSC RT_BIT_64(14)
337/** Intercept RDPMC instruction. */
338#define SVM_CTRL_INTERCEPT_RDPMC RT_BIT_64(15)
339/** Intercept PUSHF instruction. */
340#define SVM_CTRL_INTERCEPT_PUSHF RT_BIT_64(16)
341/** Intercept POPF instruction. */
342#define SVM_CTRL_INTERCEPT_POPF RT_BIT_64(17)
343/** Intercept CPUID instruction. */
344#define SVM_CTRL_INTERCEPT_CPUID RT_BIT_64(18)
345/** Intercept RSM instruction. */
346#define SVM_CTRL_INTERCEPT_RSM RT_BIT_64(19)
347/** Intercept IRET instruction. */
348#define SVM_CTRL_INTERCEPT_IRET RT_BIT_64(20)
349/** Intercept INTn instruction. */
350#define SVM_CTRL_INTERCEPT_INTN RT_BIT_64(21)
351/** Intercept INVD instruction. */
352#define SVM_CTRL_INTERCEPT_INVD RT_BIT_64(22)
353/** Intercept PAUSE instruction. */
354#define SVM_CTRL_INTERCEPT_PAUSE RT_BIT_64(23)
355/** Intercept HLT instruction. */
356#define SVM_CTRL_INTERCEPT_HLT RT_BIT_64(24)
357/** Intercept INVLPG instruction. */
358#define SVM_CTRL_INTERCEPT_INVLPG RT_BIT_64(25)
359/** Intercept INVLPGA instruction. */
360#define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26)
361/** IOIO_PROT Intercept IN/OUT accesses to selected ports. */
362#define SVM_CTRL_INTERCEPT_INOUT_BITMAP RT_BIT_64(27)
363/** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
364#define SVM_CTRL_INTERCEPT_MSR_SHADOW RT_BIT_64(28)
365/** Intercept task switches. */
366#define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29)
367/** FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
368#define SVM_CTRL_INTERCEPT_FERR_FREEZE RT_BIT_64(30)
369/** Intercept shutdown events. */
370#define SVM_CTRL_INTERCEPT_SHUTDOWN RT_BIT_64(31)
371/** Intercept VMRUN instruction. */
372#define SVM_CTRL_INTERCEPT_VMRUN RT_BIT_64(32 + 0)
373/** Intercept VMMCALL instruction. */
374#define SVM_CTRL_INTERCEPT_VMMCALL RT_BIT_64(32 + 1)
375/** Intercept VMLOAD instruction. */
376#define SVM_CTRL_INTERCEPT_VMLOAD RT_BIT_64(32 + 2)
377/** Intercept VMSAVE instruction. */
378#define SVM_CTRL_INTERCEPT_VMSAVE RT_BIT_64(32 + 3)
379/** Intercept STGI instruction. */
380#define SVM_CTRL_INTERCEPT_STGI RT_BIT_64(32 + 4)
381/** Intercept CLGI instruction. */
382#define SVM_CTRL_INTERCEPT_CLGI RT_BIT_64(32 + 5)
383/** Intercept SKINIT instruction. */
384#define SVM_CTRL_INTERCEPT_SKINIT RT_BIT_64(32 + 6)
385/** Intercept RDTSCP instruction. */
386#define SVM_CTRL_INTERCEPT_RDTSCP RT_BIT_64(32 + 7)
387/** Intercept ICEBP instruction. */
388#define SVM_CTRL_INTERCEPT_ICEBP RT_BIT_64(32 + 8)
389/** Intercept WBINVD instruction. */
390#define SVM_CTRL_INTERCEPT_WBINVD RT_BIT_64(32 + 9)
391/** Intercept MONITOR instruction. */
392#define SVM_CTRL_INTERCEPT_MONITOR RT_BIT_64(32 + 10)
393/** Intercept MWAIT instruction unconditionally. */
394#define SVM_CTRL_INTERCEPT_MWAIT RT_BIT_64(32 + 11)
395/** Intercept MWAIT instruction when armed. */
396#define SVM_CTRL_INTERCEPT_MWAIT_ARMED RT_BIT_64(32 + 12)
397/** Intercept XSETBV instruction. */
398#define SVM_CTRL_INTERCEPT_XSETBV RT_BIT_64(32 + 13)
399/* Bit 14 - Reserved, SBZ. */
400/** Intercept EFER writes after guest instruction finishes. */
401#define SVM_CTRL_INTERCEPT_EFER_WRITES_TRAP RT_BIT_64(32 + 15)
402/** Intercept CR0 writes after guest instruction finishes. */
403#define SVM_CTRL_INTERCEPT_CR0_WRITES_TRAP RT_BIT_64(32 + 16)
404/** Intercept CR0 writes after guest instruction finishes. */
405#define SVM_CTRL_INTERCEPT_CR1_WRITES_TRAP RT_BIT_64(32 + 17)
406/** Intercept CR0 writes after guest instruction finishes. */
407#define SVM_CTRL_INTERCEPT_CR2_WRITES_TRAP RT_BIT_64(32 + 18)
408/** Intercept CR0 writes after guest instruction finishes. */
409#define SVM_CTRL_INTERCEPT_CR3_WRITES_TRAP RT_BIT_64(32 + 19)
410/** Intercept CR0 writes after guest instruction finishes. */
411#define SVM_CTRL_INTERCEPT_CR4_WRITES_TRAP RT_BIT_64(32 + 20)
412/** Intercept CR0 writes after guest instruction finishes. */
413#define SVM_CTRL_INTERCEPT_CR5_WRITES_TRAP RT_BIT_64(32 + 21)
414/** Intercept CR0 writes after guest instruction finishes. */
415#define SVM_CTRL_INTERCEPT_CR6_WRITES_TRAP RT_BIT_64(32 + 22)
416/** Intercept CR0 writes after guest instruction finishes. */
417#define SVM_CTRL_INTERCEPT_CR7_WRITES_TRAP RT_BIT_64(32 + 23)
418/** Intercept CR0 writes after guest instruction finishes. */
419#define SVM_CTRL_INTERCEPT_CR8_WRITES_TRAP RT_BIT_64(32 + 24)
420/** Intercept CR0 writes after guest instruction finishes. */
421#define SVM_CTRL_INTERCEPT_CR9_WRITES_TRAP RT_BIT_64(32 + 25)
422/** Intercept CR0 writes after guest instruction finishes. */
423#define SVM_CTRL_INTERCEPT_CR10_WRITES_TRAP RT_BIT_64(32 + 26)
424/** Intercept CR0 writes after guest instruction finishes. */
425#define SVM_CTRL_INTERCEPT_CR11_WRITES_TRAP RT_BIT_64(32 + 27)
426/** Intercept CR0 writes after guest instruction finishes. */
427#define SVM_CTRL_INTERCEPT_CR12_WRITES_TRAP RT_BIT_64(32 + 28)
428/** Intercept CR0 writes after guest instruction finishes. */
429#define SVM_CTRL_INTERCEPT_CR13_WRITES_TRAP RT_BIT_64(32 + 29)
430/** Intercept CR0 writes after guest instruction finishes. */
431#define SVM_CTRL_INTERCEPT_CR14_WRITES_TRAP RT_BIT_64(32 + 30)
432/** Intercept CR0 writes after guest instruction finishes. */
433#define SVM_CTRL_INTERCEPT_CR15_WRITES_TRAP RT_BIT_64(32 + 31)
434/** @} */
435
436/** @name SVMVMCB.ctrl.u64NestedPaging
437 * @{
438 */
439#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
440/** @} */
441
442/** @name SVMVMCB.ctrl.u64IntShadow
443 * @{
444 */
445#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
446/** @} */
447
448
449/** @name SVMINTCTRL.u3Type
450 * @{
451 */
452/** External or virtual interrupt. */
453#define SVM_EVENT_EXTERNAL_IRQ 0
454/** Non-maskable interrupt. */
455#define SVM_EVENT_NMI 2
456/** Exception; fault or trap. */
457#define SVM_EVENT_EXCEPTION 3
458/** Software interrupt. */
459#define SVM_EVENT_SOFTWARE_INT 4
460/** @} */
461
462
463/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
464 * @{
465 */
466/** Flush nothing. */
467#define SVM_TLB_FLUSH_NOTHING 0
468/** Flush entire TLB (host+guest entries) */
469#define SVM_TLB_FLUSH_ENTIRE 1
470/** Flush this guest's TLB entries (by ASID) */
471#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
472/** Flush this guest's non-global TLB entries (by ASID) */
473#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
474/** @} */
475
476
477/**
478 * SVM Selector type; includes hidden parts.
479 */
480typedef struct
481{
482 uint16_t u16Sel;
483 uint16_t u16Attr;
484 uint32_t u32Limit;
485 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
486} SVMSEL;
487AssertCompileSize(SVMSEL, 16);
488
489/**
490 * SVM GDTR/IDTR type.
491 */
492typedef struct
493{
494 uint16_t u16Reserved1;
495 uint16_t u16Reserved2;
496 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
497 uint64_t u64Base;
498} SVMGDTR;
499AssertCompileSize(SVMGDTR, 16);
500typedef SVMGDTR SVMIDTR;
501
502/**
503 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
504 */
505typedef union
506{
507 struct
508 {
509 uint32_t u8Vector : 8;
510 uint32_t u3Type : 3;
511 uint32_t u1ErrorCodeValid : 1;
512 uint32_t u19Reserved : 19;
513 uint32_t u1Valid : 1;
514 uint32_t u32ErrorCode : 32;
515 } n;
516 uint64_t u;
517} SVMEVENT;
518/** Pointer to the SVMEVENT union. */
519typedef SVMEVENT *PSVMEVENT;
520
521/**
522 * SVM Interrupt control structure (Virtual Interrupt Control).
523 */
524typedef union
525{
526 struct
527 {
528 uint32_t u8VTPR : 8; /* V_TPR */
529 uint32_t u1VIrqValid : 1; /* V_IRQ */
530 uint32_t u7Reserved : 7;
531 uint32_t u4VIrqPriority : 4; /* V_INTR_PRIO */
532 uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
533 uint32_t u3Reserved : 3;
534 uint32_t u1VIrqMasking : 1; /* V_INTR_MASKING */
535 uint32_t u6Reserved : 6;
536 uint32_t u1AvicEnable : 1;
537 uint32_t u8VIrqVector : 8; /* V_INTR_VECTOR */
538 uint32_t u24Reserved : 24;
539 } n;
540 uint64_t u;
541} SVMINTCTRL;
542
543/**
544 * SVM TLB control structure.
545 */
546typedef union
547{
548 struct
549 {
550 uint32_t u32ASID : 32;
551 uint32_t u8TLBFlush : 8;
552 uint32_t u24Reserved : 24;
553 } n;
554 uint64_t u;
555} SVMTLBCTRL;
556
557/**
558 * SVM IOIO exit structure (EXITINFO1 for IOIO intercepts).
559 */
560typedef union
561{
562 struct
563 {
564 uint32_t u1Type : 1; /**< Bit 0: 0 = out, 1 = in */
565 uint32_t u1Reserved : 1; /**< Bit 1: Reserved */
566 uint32_t u1STR : 1; /**< Bit 2: String I/O (1) or not (0). */
567 uint32_t u1REP : 1; /**< Bit 3: Repeat prefixed string I/O. */
568 uint32_t u1OP8 : 1; /**< Bit 4: 8-bit operand. */
569 uint32_t u1OP16 : 1; /**< Bit 5: 16-bit operand. */
570 uint32_t u1OP32 : 1; /**< Bit 6: 32-bit operand. */
571 uint32_t u1ADDR16 : 1; /**< Bit 7: 16-bit operand. */
572 uint32_t u1ADDR32 : 1; /**< Bit 8: 32-bit operand. */
573 uint32_t u1ADDR64 : 1; /**< Bit 9: 64-bit operand. */
574 uint32_t u3SEG : 3; /**< BITS 12:10: Effective segment number. Added with decode assist in APM v3.17. */
575 uint32_t u3Reserved : 3;
576 uint32_t u16Port : 16; /**< Bits 31:16: Port number. */
577 } n;
578 uint32_t u;
579} SVMIOIOEXIT;
580
581/** @name SVMIOIOEXIT.u1Type
582 * @{ */
583/** IO write. */
584#define SVM_IOIO_WRITE 0
585/** IO read. */
586#define SVM_IOIO_READ 1
587/** @}*/
588
589/**
590 * SVM nested paging structure.
591 */
592typedef union
593{
594 struct
595 {
596 uint32_t u1NestedPaging : 1; /**< enabled/disabled */
597 } n;
598 uint64_t u;
599} SVMNPCTRL;
600
601/**
602 * SVM AVIC.
603 */
604typedef union
605{
606 struct
607 {
608 uint64_t u12Reserved1 : 12;
609 uint64_t u40Addr : 40;
610 uint64_t u12Reserved2 : 12;
611 } n;
612 uint64_t u;
613} SVMAVIC;
614AssertCompileSize(SVMAVIC, 8);
615
616/**
617 * SVM AVIC PHYSICAL_TABLE pointer.
618 */
619typedef union
620{
621 struct
622 {
623 uint64_t u8LastGuestCoreId : 8;
624 uint64_t u4Reserved : 4;
625 uint64_t u40Addr : 40;
626 uint64_t u12Reserved : 12;
627 } n;
628 uint64_t u;
629} SVMAVICPHYS;
630AssertCompileSize(SVMAVICPHYS, 8);
631
632/**
633 * SVM VM Control Block. (VMCB)
634 */
635#pragma pack(1)
636typedef struct SVMVMCB
637{
638 /** Control Area. */
639 struct
640 {
641 /** Offset 0x00 - Intercept reads of CR0-CR15. */
642 uint16_t u16InterceptRdCRx;
643 /** Offset 0x02 - Intercept writes to CR0-CR15. */
644 uint16_t u16InterceptWrCRx;
645 /** Offset 0x04 - Intercept reads of DR0-DR15. */
646 uint16_t u16InterceptRdDRx;
647 /** Offset 0x06 - Intercept writes to DR0-DR15. */
648 uint16_t u16InterceptWrDRx;
649 /** Offset 0x08 - Intercept exception vectors 0-31. */
650 uint32_t u32InterceptException;
651 /** Offset 0x0C - Intercept control. */
652 uint64_t u64InterceptCtrl;
653 /** Offset 0x14-0x3F - Reserved. */
654 uint8_t u8Reserved[0x3c - 0x14];
655 /** Offset 0x3c - PAUSE filter threshold. */
656 uint16_t u16PauseFilterThreshold;
657 /** Offset 0x3e - PAUSE intercept filter count. */
658 uint16_t u16PauseFilterCount;
659 /** Offset 0x40 - Physical address of IOPM. */
660 uint64_t u64IOPMPhysAddr;
661 /** Offset 0x48 - Physical address of MSRPM. */
662 uint64_t u64MSRPMPhysAddr;
663 /** Offset 0x50 - TSC Offset. */
664 uint64_t u64TSCOffset;
665 /** Offset 0x58 - TLB control field. */
666 SVMTLBCTRL TLBCtrl;
667 /** Offset 0x60 - Interrupt control field. */
668 SVMINTCTRL IntCtrl;
669 /** Offset 0x68 - Interrupt shadow. */
670 uint64_t u64IntShadow;
671 /** Offset 0x70 - Exit code. */
672 uint64_t u64ExitCode;
673 /** Offset 0x78 - Exit info 1. */
674 uint64_t u64ExitInfo1;
675 /** Offset 0x80 - Exit info 2. */
676 uint64_t u64ExitInfo2;
677 /** Offset 0x88 - Exit Interrupt info. */
678 SVMEVENT ExitIntInfo;
679 /** Offset 0x90 - Nested Paging. */
680 SVMNPCTRL NestedPaging;
681 /** Offset 0x98 - AVIC APIC BAR. */
682 SVMAVIC AvicBar;
683 /** Offset 0xA0-0xA7 - Reserved. */
684 uint8_t u8Reserved2[0xA8-0xA0];
685 /** Offset 0xA8 - Event injection. */
686 SVMEVENT EventInject;
687 /** Offset 0xB0 - Host CR3 for nested paging. */
688 uint64_t u64NestedPagingCR3;
689 /** Offset 0xB8 - LBR Virtualization. */
690 uint64_t u64LBRVirt;
691 /** Offset 0xC0 - VMCB Clean Bits. */
692 uint64_t u64VmcbCleanBits;
693 /** Offset 0xC8 - Next sequential instruction pointer. */
694 uint64_t u64NextRIP;
695 /** Offset 0xD0 - Number of bytes fetched. */
696 uint8_t cbInstrFetched;
697 /** Offset 0xD1 - Fetched bytes. */
698 uint8_t abInstr[15];
699 /** Offset 0xE0 - AVIC APIC_BACKING_PAGE pointer. */
700 SVMAVIC AvicBackingPagePtr;
701 /** Offset 0xE8-0xEF - Reserved. */
702 uint8_t u8Reserved3[0xF0 - 0xE8];
703 /** Offset 0xF0 - AVIC LOGICAL_TABLE pointer. */
704 SVMAVIC AvicLogicalTablePtr;
705 /** Offset 0xF8 - AVIC PHYSICAL_TABLE pointer. */
706 SVMAVICPHYS AvicPhysicalTablePtr;
707 } ctrl;
708
709 /** Offset 0x100-0x3FF - Reserved. */
710 uint8_t u8Reserved3[0x400-0x100];
711
712 /** State Save Area. Starts at offset 0x400. */
713 struct
714 {
715 /** Offset 0x400 - Guest ES register + hidden parts. */
716 SVMSEL ES;
717 /** Offset 0x410 - Guest CS register + hidden parts. */
718 SVMSEL CS;
719 /** Offset 0x420 - Guest SS register + hidden parts. */
720 SVMSEL SS;
721 /** Offset 0x430 - Guest DS register + hidden parts. */
722 SVMSEL DS;
723 /** Offset 0x440 - Guest FS register + hidden parts. */
724 SVMSEL FS;
725 /** Offset 0x450 - Guest GS register + hidden parts. */
726 SVMSEL GS;
727 /** Offset 0x460 - Guest GDTR register. */
728 SVMGDTR GDTR;
729 /** Offset 0x470 - Guest LDTR register + hidden parts. */
730 SVMSEL LDTR;
731 /** Offset 0x480 - Guest IDTR register. */
732 SVMIDTR IDTR;
733 /** Offset 0x490 - Guest TR register + hidden parts. */
734 SVMSEL TR;
735 /** Offset 0x4A0-0x4CA - Reserved. */
736 uint8_t u8Reserved4[0x4CB-0x4A0];
737 /** Offset 0x4CB - CPL. */
738 uint8_t u8CPL;
739 /** Offset 0x4CC-0x4CF - Reserved. */
740 uint8_t u8Reserved5[0x4D0-0x4CC];
741 /** Offset 0x4D0 - EFER. */
742 uint64_t u64EFER;
743 /** Offset 0x4D8-0x547 - Reserved. */
744 uint8_t u8Reserved6[0x548-0x4D8];
745 /** Offset 0x548 - CR4. */
746 uint64_t u64CR4;
747 /** Offset 0x550 - CR3. */
748 uint64_t u64CR3;
749 /** Offset 0x558 - CR0. */
750 uint64_t u64CR0;
751 /** Offset 0x560 - DR7. */
752 uint64_t u64DR7;
753 /** Offset 0x568 - DR6. */
754 uint64_t u64DR6;
755 /** Offset 0x570 - RFLAGS. */
756 uint64_t u64RFlags;
757 /** Offset 0x578 - RIP. */
758 uint64_t u64RIP;
759 /** Offset 0x580-0x5D7 - Reserved. */
760 uint8_t u8Reserved7[0x5D8-0x580];
761 /** Offset 0x5D8 - RSP. */
762 uint64_t u64RSP;
763 /** Offset 0x5E0-0x5F7 - Reserved. */
764 uint8_t u8Reserved8[0x5F8-0x5E0];
765 /** Offset 0x5F8 - RAX. */
766 uint64_t u64RAX;
767 /** Offset 0x600 - STAR. */
768 uint64_t u64STAR;
769 /** Offset 0x608 - LSTAR. */
770 uint64_t u64LSTAR;
771 /** Offset 0x610 - CSTAR. */
772 uint64_t u64CSTAR;
773 /** Offset 0x618 - SFMASK. */
774 uint64_t u64SFMASK;
775 /** Offset 0x620 - KernelGSBase. */
776 uint64_t u64KernelGSBase;
777 /** Offset 0x628 - SYSENTER_CS. */
778 uint64_t u64SysEnterCS;
779 /** Offset 0x630 - SYSENTER_ESP. */
780 uint64_t u64SysEnterESP;
781 /** Offset 0x638 - SYSENTER_EIP. */
782 uint64_t u64SysEnterEIP;
783 /** Offset 0x640 - CR2. */
784 uint64_t u64CR2;
785 /** Offset 0x648-0x667 - Reserved. */
786 uint8_t u8Reserved9[0x668-0x648];
787 /** Offset 0x668 - G_PAT. */
788 uint64_t u64GPAT;
789 /** Offset 0x670 - DBGCTL. */
790 uint64_t u64DBGCTL;
791 /** Offset 0x678 - BR_FROM. */
792 uint64_t u64BR_FROM;
793 /** Offset 0x680 - BR_TO. */
794 uint64_t u64BR_TO;
795 /** Offset 0x688 - LASTEXCPFROM. */
796 uint64_t u64LASTEXCPFROM;
797 /** Offset 0x690 - LASTEXCPTO. */
798 uint64_t u64LASTEXCPTO;
799 } guest;
800
801 /** Offset 0x698-0xFFF- Reserved. */
802 uint8_t u8Reserved10[0x1000-0x698];
803} SVMVMCB;
804#pragma pack()
805/** Pointer to the SVMVMCB structure. */
806typedef SVMVMCB *PSVMVMCB;
807AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
808AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptRdCRx, 0x00);
809AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptWrCRx, 0x02);
810AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptRdDRx, 0x04);
811AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptWrDRx, 0x06);
812AssertCompileMemberOffset(SVMVMCB, ctrl.u32InterceptException, 0x08);
813AssertCompileMemberOffset(SVMVMCB, ctrl.u64InterceptCtrl, 0x0C);
814AssertCompileMemberOffset(SVMVMCB, ctrl.u8Reserved, 0x14);
815AssertCompileMemberOffset(SVMVMCB, ctrl.u16PauseFilterThreshold, 0x3c);
816AssertCompileMemberOffset(SVMVMCB, ctrl.u16PauseFilterCount, 0x3e);
817AssertCompileMemberOffset(SVMVMCB, ctrl.u64IOPMPhysAddr, 0x40);
818AssertCompileMemberOffset(SVMVMCB, ctrl.u64MSRPMPhysAddr, 0x48);
819AssertCompileMemberOffset(SVMVMCB, ctrl.u64TSCOffset, 0x50);
820AssertCompileMemberOffset(SVMVMCB, ctrl.TLBCtrl, 0x58);
821AssertCompileMemberOffset(SVMVMCB, ctrl.IntCtrl, 0x60);
822AssertCompileMemberOffset(SVMVMCB, ctrl.u64IntShadow, 0x68);
823AssertCompileMemberOffset(SVMVMCB, ctrl.u64ExitCode, 0x70);
824AssertCompileMemberOffset(SVMVMCB, ctrl.u64ExitInfo1, 0x78);
825AssertCompileMemberOffset(SVMVMCB, ctrl.u64ExitInfo2, 0x80);
826AssertCompileMemberOffset(SVMVMCB, ctrl.ExitIntInfo, 0x88);
827AssertCompileMemberOffset(SVMVMCB, ctrl.NestedPaging, 0x90);
828AssertCompileMemberOffset(SVMVMCB, ctrl.AvicBar, 0x98);
829AssertCompileMemberOffset(SVMVMCB, ctrl.u8Reserved2, 0xA0);
830AssertCompileMemberOffset(SVMVMCB, ctrl.EventInject, 0xA8);
831AssertCompileMemberOffset(SVMVMCB, ctrl.u64NestedPagingCR3, 0xB0);
832AssertCompileMemberOffset(SVMVMCB, ctrl.u64LBRVirt, 0xB8);
833AssertCompileMemberOffset(SVMVMCB, ctrl.u64VmcbCleanBits, 0xC0);
834AssertCompileMemberOffset(SVMVMCB, ctrl.u64NextRIP, 0xC8);
835AssertCompileMemberOffset(SVMVMCB, ctrl.cbInstrFetched, 0xD0);
836AssertCompileMemberOffset(SVMVMCB, ctrl.abInstr, 0xD1);
837AssertCompileMemberOffset(SVMVMCB, ctrl.AvicBackingPagePtr, 0xE0);
838AssertCompileMemberOffset(SVMVMCB, ctrl.u8Reserved3, 0xE8);
839AssertCompileMemberOffset(SVMVMCB, ctrl.AvicLogicalTablePtr, 0xF0);
840AssertCompileMemberOffset(SVMVMCB, ctrl.AvicPhysicalTablePtr, 0xF8);
841AssertCompileMemberOffset(SVMVMCB, u8Reserved3, 0x100);
842AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
843AssertCompileMemberOffset(SVMVMCB, guest.ES, 0x400);
844AssertCompileMemberOffset(SVMVMCB, guest.CS, 0x410);
845AssertCompileMemberOffset(SVMVMCB, guest.SS, 0x420);
846AssertCompileMemberOffset(SVMVMCB, guest.DS, 0x430);
847AssertCompileMemberOffset(SVMVMCB, guest.FS, 0x440);
848AssertCompileMemberOffset(SVMVMCB, guest.GS, 0x450);
849AssertCompileMemberOffset(SVMVMCB, guest.GDTR, 0x460);
850AssertCompileMemberOffset(SVMVMCB, guest.LDTR, 0x470);
851AssertCompileMemberOffset(SVMVMCB, guest.IDTR, 0x480);
852AssertCompileMemberOffset(SVMVMCB, guest.TR, 0x490);
853AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved4, 0x4A0);
854AssertCompileMemberOffset(SVMVMCB, guest.u8CPL, 0x4CB);
855AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved5, 0x4CC);
856AssertCompileMemberOffset(SVMVMCB, guest.u64EFER, 0x4D0);
857AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved6, 0x4D8);
858AssertCompileMemberOffset(SVMVMCB, guest.u64CR4, 0x548);
859AssertCompileMemberOffset(SVMVMCB, guest.u64CR3, 0x550);
860AssertCompileMemberOffset(SVMVMCB, guest.u64CR0, 0x558);
861AssertCompileMemberOffset(SVMVMCB, guest.u64DR7, 0x560);
862AssertCompileMemberOffset(SVMVMCB, guest.u64DR6, 0x568);
863AssertCompileMemberOffset(SVMVMCB, guest.u64RFlags, 0x570);
864AssertCompileMemberOffset(SVMVMCB, guest.u64RIP, 0x578);
865AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved7, 0x580);
866AssertCompileMemberOffset(SVMVMCB, guest.u64RSP, 0x5D8);
867AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved8, 0x5E0);
868AssertCompileMemberOffset(SVMVMCB, guest.u64RAX, 0x5F8);
869AssertCompileMemberOffset(SVMVMCB, guest.u64STAR, 0x600);
870AssertCompileMemberOffset(SVMVMCB, guest.u64LSTAR, 0x608);
871AssertCompileMemberOffset(SVMVMCB, guest.u64CSTAR, 0x610);
872AssertCompileMemberOffset(SVMVMCB, guest.u64SFMASK, 0x618);
873AssertCompileMemberOffset(SVMVMCB, guest.u64KernelGSBase, 0x620);
874AssertCompileMemberOffset(SVMVMCB, guest.u64SysEnterCS, 0x628);
875AssertCompileMemberOffset(SVMVMCB, guest.u64SysEnterESP, 0x630);
876AssertCompileMemberOffset(SVMVMCB, guest.u64SysEnterEIP, 0x638);
877AssertCompileMemberOffset(SVMVMCB, guest.u64CR2, 0x640);
878AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved9, 0x648);
879AssertCompileMemberOffset(SVMVMCB, guest.u64GPAT, 0x668);
880AssertCompileMemberOffset(SVMVMCB, guest.u64DBGCTL, 0x670);
881AssertCompileMemberOffset(SVMVMCB, guest.u64BR_FROM, 0x678);
882AssertCompileMemberOffset(SVMVMCB, guest.u64BR_TO, 0x680);
883AssertCompileMemberOffset(SVMVMCB, guest.u64LASTEXCPFROM, 0x688);
884AssertCompileMemberOffset(SVMVMCB, guest.u64LASTEXCPTO, 0x690);
885AssertCompileMemberOffset(SVMVMCB, u8Reserved10, 0x698);
886AssertCompileSize(SVMVMCB, 0x1000);
887
888#ifdef IN_RING0
889VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
890#endif /* IN_RING0 */
891
892/** @} */
893
894#endif
895
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