VirtualBox

source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 104429

Last change on this file since 104429 was 103005, checked in by vboxsync, 9 months ago

iprt/asm.h,*: Split out the ASMMem* and related stuff into a separate header, asm-mem.h, so that we can get the RT_ASM_PAGE_SIZE stuff out of the way.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 46.5 KB
Line 
1/** @file
2 * HM - SVM (AMD-V) Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_vmm_hm_svm_h
37#define VBOX_INCLUDED_vmm_hm_svm_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <VBox/types.h>
43#include <iprt/assert.h>
44
45#ifdef RT_OS_SOLARIS
46# undef ES
47# undef CS
48# undef DS
49# undef SS
50# undef FS
51# undef GS
52#endif
53
54/** @defgroup grp_hm_svm SVM (AMD-V) Types and Definitions
55 * @ingroup grp_hm
56 * @{
57 */
58
59/** @name SVM generic / convenient defines.
60 * @{
61 */
62/** Number of pages required for the VMCB. */
63#define SVM_VMCB_PAGES 1
64/** Number of pages required for the MSR permission bitmap. */
65#define SVM_MSRPM_PAGES 2
66/** Number of pages required for the IO permission bitmap. */
67#define SVM_IOPM_PAGES 3
68/** @} */
69
70/*
71 * Ugly!
72 * When compiling the recompiler, its own svm.h defines clash with
73 * the following defines. Avoid just the duplicates here as we still
74 * require other definitions and structures in this header.
75 */
76#ifndef IN_REM_R3
77/** @name SVM_EXIT_XXX - SVM Basic Exit Reasons.
78 * @{
79 */
80/** Invalid guest state in VMCB. */
81# define SVM_EXIT_INVALID (uint64_t)(-1)
82/** Read from CR0-CR15. */
83# define SVM_EXIT_READ_CR0 0x0
84# define SVM_EXIT_READ_CR1 0x1
85# define SVM_EXIT_READ_CR2 0x2
86# define SVM_EXIT_READ_CR3 0x3
87# define SVM_EXIT_READ_CR4 0x4
88# define SVM_EXIT_READ_CR5 0x5
89# define SVM_EXIT_READ_CR6 0x6
90# define SVM_EXIT_READ_CR7 0x7
91# define SVM_EXIT_READ_CR8 0x8
92# define SVM_EXIT_READ_CR9 0x9
93# define SVM_EXIT_READ_CR10 0xa
94# define SVM_EXIT_READ_CR11 0xb
95# define SVM_EXIT_READ_CR12 0xc
96# define SVM_EXIT_READ_CR13 0xd
97# define SVM_EXIT_READ_CR14 0xe
98# define SVM_EXIT_READ_CR15 0xf
99/** Writes to CR0-CR15. */
100# define SVM_EXIT_WRITE_CR0 0x10
101# define SVM_EXIT_WRITE_CR1 0x11
102# define SVM_EXIT_WRITE_CR2 0x12
103# define SVM_EXIT_WRITE_CR3 0x13
104# define SVM_EXIT_WRITE_CR4 0x14
105# define SVM_EXIT_WRITE_CR5 0x15
106# define SVM_EXIT_WRITE_CR6 0x16
107# define SVM_EXIT_WRITE_CR7 0x17
108# define SVM_EXIT_WRITE_CR8 0x18
109# define SVM_EXIT_WRITE_CR9 0x19
110# define SVM_EXIT_WRITE_CR10 0x1a
111# define SVM_EXIT_WRITE_CR11 0x1b
112# define SVM_EXIT_WRITE_CR12 0x1c
113# define SVM_EXIT_WRITE_CR13 0x1d
114# define SVM_EXIT_WRITE_CR14 0x1e
115# define SVM_EXIT_WRITE_CR15 0x1f
116/** Read from DR0-DR15. */
117# define SVM_EXIT_READ_DR0 0x20
118# define SVM_EXIT_READ_DR1 0x21
119# define SVM_EXIT_READ_DR2 0x22
120# define SVM_EXIT_READ_DR3 0x23
121# define SVM_EXIT_READ_DR4 0x24
122# define SVM_EXIT_READ_DR5 0x25
123# define SVM_EXIT_READ_DR6 0x26
124# define SVM_EXIT_READ_DR7 0x27
125# define SVM_EXIT_READ_DR8 0x28
126# define SVM_EXIT_READ_DR9 0x29
127# define SVM_EXIT_READ_DR10 0x2a
128# define SVM_EXIT_READ_DR11 0x2b
129# define SVM_EXIT_READ_DR12 0x2c
130# define SVM_EXIT_READ_DR13 0x2d
131# define SVM_EXIT_READ_DR14 0x2e
132# define SVM_EXIT_READ_DR15 0x2f
133/** Writes to DR0-DR15. */
134# define SVM_EXIT_WRITE_DR0 0x30
135# define SVM_EXIT_WRITE_DR1 0x31
136# define SVM_EXIT_WRITE_DR2 0x32
137# define SVM_EXIT_WRITE_DR3 0x33
138# define SVM_EXIT_WRITE_DR4 0x34
139# define SVM_EXIT_WRITE_DR5 0x35
140# define SVM_EXIT_WRITE_DR6 0x36
141# define SVM_EXIT_WRITE_DR7 0x37
142# define SVM_EXIT_WRITE_DR8 0x38
143# define SVM_EXIT_WRITE_DR9 0x39
144# define SVM_EXIT_WRITE_DR10 0x3a
145# define SVM_EXIT_WRITE_DR11 0x3b
146# define SVM_EXIT_WRITE_DR12 0x3c
147# define SVM_EXIT_WRITE_DR13 0x3d
148# define SVM_EXIT_WRITE_DR14 0x3e
149# define SVM_EXIT_WRITE_DR15 0x3f
150/* Exception 0-31. */
151# define SVM_EXIT_XCPT_0 0x40
152# define SVM_EXIT_XCPT_1 0x41
153# define SVM_EXIT_XCPT_2 0x42
154# define SVM_EXIT_XCPT_3 0x43
155# define SVM_EXIT_XCPT_4 0x44
156# define SVM_EXIT_XCPT_5 0x45
157# define SVM_EXIT_XCPT_6 0x46
158# define SVM_EXIT_XCPT_7 0x47
159# define SVM_EXIT_XCPT_8 0x48
160# define SVM_EXIT_XCPT_9 0x49
161# define SVM_EXIT_XCPT_10 0x4a
162# define SVM_EXIT_XCPT_11 0x4b
163# define SVM_EXIT_XCPT_12 0x4c
164# define SVM_EXIT_XCPT_13 0x4d
165# define SVM_EXIT_XCPT_14 0x4e
166# define SVM_EXIT_XCPT_15 0x4f
167# define SVM_EXIT_XCPT_16 0x50
168# define SVM_EXIT_XCPT_17 0x51
169# define SVM_EXIT_XCPT_18 0x52
170# define SVM_EXIT_XCPT_19 0x53
171# define SVM_EXIT_XCPT_20 0x54
172# define SVM_EXIT_XCPT_21 0x55
173# define SVM_EXIT_XCPT_22 0x56
174# define SVM_EXIT_XCPT_23 0x57
175# define SVM_EXIT_XCPT_24 0x58
176# define SVM_EXIT_XCPT_25 0x59
177# define SVM_EXIT_XCPT_26 0x5a
178# define SVM_EXIT_XCPT_27 0x5b
179# define SVM_EXIT_XCPT_28 0x5c
180# define SVM_EXIT_XCPT_29 0x5d
181# define SVM_EXIT_XCPT_30 0x5e
182# define SVM_EXIT_XCPT_31 0x5f
183/* Exception (more readable) */
184# define SVM_EXIT_XCPT_DE SVM_EXIT_XCPT_0
185# define SVM_EXIT_XCPT_DB SVM_EXIT_XCPT_1
186# define SVM_EXIT_XCPT_NMI SVM_EXIT_XCPT_2
187# define SVM_EXIT_XCPT_BP SVM_EXIT_XCPT_3
188# define SVM_EXIT_XCPT_OF SVM_EXIT_XCPT_4
189# define SVM_EXIT_XCPT_BR SVM_EXIT_XCPT_5
190# define SVM_EXIT_XCPT_UD SVM_EXIT_XCPT_6
191# define SVM_EXIT_XCPT_NM SVM_EXIT_XCPT_7
192# define SVM_EXIT_XCPT_DF SVM_EXIT_XCPT_8
193# define SVM_EXIT_XCPT_CO_SEG_OVERRUN SVM_EXIT_XCPT_9
194# define SVM_EXIT_XCPT_TS SVM_EXIT_XCPT_10
195# define SVM_EXIT_XCPT_NP SVM_EXIT_XCPT_11
196# define SVM_EXIT_XCPT_SS SVM_EXIT_XCPT_12
197# define SVM_EXIT_XCPT_GP SVM_EXIT_XCPT_13
198# define SVM_EXIT_XCPT_PF SVM_EXIT_XCPT_14
199# define SVM_EXIT_XCPT_MF SVM_EXIT_XCPT_16
200# define SVM_EXIT_XCPT_AC SVM_EXIT_XCPT_17
201# define SVM_EXIT_XCPT_MC SVM_EXIT_XCPT_18
202# define SVM_EXIT_XCPT_XF SVM_EXIT_XCPT_19
203# define SVM_EXIT_XCPT_VE SVM_EXIT_XCPT_20
204# define SVM_EXIT_XCPT_SX SVM_EXIT_XCPT_30
205/** Physical maskable interrupt. */
206# define SVM_EXIT_INTR 0x60
207/** Non-maskable interrupt. */
208# define SVM_EXIT_NMI 0x61
209/** System Management interrupt. */
210# define SVM_EXIT_SMI 0x62
211/** Physical INIT signal. */
212# define SVM_EXIT_INIT 0x63
213/** Virtual interrupt. */
214# define SVM_EXIT_VINTR 0x64
215/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
216# define SVM_EXIT_CR0_SEL_WRITE 0x65
217/** IDTR read. */
218# define SVM_EXIT_IDTR_READ 0x66
219/** GDTR read. */
220# define SVM_EXIT_GDTR_READ 0x67
221/** LDTR read. */
222# define SVM_EXIT_LDTR_READ 0x68
223/** TR read. */
224# define SVM_EXIT_TR_READ 0x69
225/** IDTR write. */
226# define SVM_EXIT_IDTR_WRITE 0x6a
227/** GDTR write. */
228# define SVM_EXIT_GDTR_WRITE 0x6b
229/** LDTR write. */
230# define SVM_EXIT_LDTR_WRITE 0x6c
231/** TR write. */
232# define SVM_EXIT_TR_WRITE 0x6d
233/** RDTSC instruction. */
234# define SVM_EXIT_RDTSC 0x6e
235/** RDPMC instruction. */
236# define SVM_EXIT_RDPMC 0x6f
237/** PUSHF instruction. */
238# define SVM_EXIT_PUSHF 0x70
239/** POPF instruction. */
240# define SVM_EXIT_POPF 0x71
241/** CPUID instruction. */
242# define SVM_EXIT_CPUID 0x72
243/** RSM instruction. */
244# define SVM_EXIT_RSM 0x73
245/** IRET instruction. */
246# define SVM_EXIT_IRET 0x74
247/** Software interrupt (INTn instructions). */
248# define SVM_EXIT_SWINT 0x75
249/** INVD instruction. */
250# define SVM_EXIT_INVD 0x76
251/** PAUSE instruction. */
252# define SVM_EXIT_PAUSE 0x77
253/** HLT instruction. */
254# define SVM_EXIT_HLT 0x78
255/** INVLPG instructions. */
256# define SVM_EXIT_INVLPG 0x79
257/** INVLPGA instruction. */
258# define SVM_EXIT_INVLPGA 0x7a
259/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
260# define SVM_EXIT_IOIO 0x7b
261/** RDMSR or WRMSR access to protected MSR. */
262# define SVM_EXIT_MSR 0x7c
263/** task switch. */
264# define SVM_EXIT_TASK_SWITCH 0x7d
265/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
266# define SVM_EXIT_FERR_FREEZE 0x7e
267/** Shutdown. */
268# define SVM_EXIT_SHUTDOWN 0x7f
269/** VMRUN instruction. */
270# define SVM_EXIT_VMRUN 0x80
271/** VMMCALL instruction. */
272# define SVM_EXIT_VMMCALL 0x81
273/** VMLOAD instruction. */
274# define SVM_EXIT_VMLOAD 0x82
275/** VMSAVE instruction. */
276# define SVM_EXIT_VMSAVE 0x83
277/** STGI instruction. */
278# define SVM_EXIT_STGI 0x84
279/** CLGI instruction. */
280# define SVM_EXIT_CLGI 0x85
281/** SKINIT instruction. */
282# define SVM_EXIT_SKINIT 0x86
283/** RDTSCP instruction. */
284# define SVM_EXIT_RDTSCP 0x87
285/** ICEBP instruction. */
286# define SVM_EXIT_ICEBP 0x88
287/** WBINVD instruction. */
288# define SVM_EXIT_WBINVD 0x89
289/** MONITOR instruction. */
290# define SVM_EXIT_MONITOR 0x8a
291/** MWAIT instruction. */
292# define SVM_EXIT_MWAIT 0x8b
293/** MWAIT instruction, when armed. */
294# define SVM_EXIT_MWAIT_ARMED 0x8c
295/** XSETBV instruction. */
296# define SVM_EXIT_XSETBV 0x8d
297/** RDPRU instruction. */
298# define SVM_EXIT_RDPRU 0x8e
299/** Write to EFER (after guest instruction completes). */
300# define SVM_EXIT_WRITE_EFER_TRAP 0x8f
301/** Write to CR0-CR15 (after guest instruction completes). */
302# define SVM_EXIT_WRITE_CR0_TRAP 0x90
303# define SVM_EXIT_WRITE_CR1_TRAP 0x91
304# define SVM_EXIT_WRITE_CR2_TRAP 0x92
305# define SVM_EXIT_WRITE_CR3_TRAP 0x93
306# define SVM_EXIT_WRITE_CR4_TRAP 0x94
307# define SVM_EXIT_WRITE_CR5_TRAP 0x95
308# define SVM_EXIT_WRITE_CR6_TRAP 0x96
309# define SVM_EXIT_WRITE_CR7_TRAP 0x97
310# define SVM_EXIT_WRITE_CR8_TRAP 0x98
311# define SVM_EXIT_WRITE_CR9_TRAP 0x99
312# define SVM_EXIT_WRITE_CR10_TRAP 0x9a
313# define SVM_EXIT_WRITE_CR11_TRAP 0x9b
314# define SVM_EXIT_WRITE_CR12_TRAP 0x9c
315# define SVM_EXIT_WRITE_CR13_TRAP 0x9d
316# define SVM_EXIT_WRITE_CR14_TRAP 0x9e
317# define SVM_EXIT_WRITE_CR15_TRAP 0x9f
318/** MCOMMIT instruction. */
319# define SVM_EXIT_MCOMMIT 0xa3
320
321/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
322# define SVM_EXIT_NPF 0x400
323/** AVIC: Virtual IPI delivery not completed. */
324# define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
325/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
326 * hardware. */
327# define SVM_EXIT_AVIC_NOACCEL 0x402
328/** The maximum possible exit value. */
329# define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
330/** @} */
331#endif /* !IN_REM_R3*/
332
333
334/** @name SVMVMCB.u64ExitInfo2 for task switches
335 * @{
336 */
337/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
338#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
339/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
340#define SVM_EXIT2_TASK_SWITCH_JUMP RT_BIT_64(38)
341/** Set to 1 if the task switch has an error code; else cleared to 0. */
342#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
343/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
344#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
345/** @} */
346
347/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
348 * @{
349 */
350/** The access was a read MSR. */
351#define SVM_EXIT1_MSR_READ 0x0
352/** The access was a write MSR. */
353#define SVM_EXIT1_MSR_WRITE 0x1
354/** @} */
355
356/** @name SVMVMCB.u64ExitInfo1 for Mov CRx accesses.
357 * @{
358 */
359/** The mask of whether the access was via a Mov CRx instruction. */
360#define SVM_EXIT1_MOV_CRX_MASK RT_BIT_64(63)
361/** The mask for the GPR number of the Mov CRx instruction. */
362#define SVM_EXIT1_MOV_CRX_GPR_NUMBER 0xf
363/** @} */
364
365/** @name SVMVMCB.u64ExitInfo1 for Mov DRx accesses.
366 * @{
367 */
368/** The mask for the GPR number of the Mov DRx instruction. */
369#define SVM_EXIT1_MOV_DRX_GPR_NUMBER 0xf
370/** @} */
371
372/** @name SVMVMCB.ctrl.u64InterceptCtrl
373 * @{
374 */
375/** Intercept INTR (physical maskable interrupt). */
376#define SVM_CTRL_INTERCEPT_INTR RT_BIT_64(0)
377/** Intercept NMI. */
378#define SVM_CTRL_INTERCEPT_NMI RT_BIT_64(1)
379/** Intercept SMI. */
380#define SVM_CTRL_INTERCEPT_SMI RT_BIT_64(2)
381/** Intercept INIT. */
382#define SVM_CTRL_INTERCEPT_INIT RT_BIT_64(3)
383/** Intercept VINTR (virtual maskable interrupt). */
384#define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4)
385/** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
386#define SVM_CTRL_INTERCEPT_CR0_SEL_WRITE RT_BIT_64(5)
387/** Intercept reads of IDTR. */
388#define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6)
389/** Intercept reads of GDTR. */
390#define SVM_CTRL_INTERCEPT_GDTR_READS RT_BIT_64(7)
391/** Intercept reads of LDTR. */
392#define SVM_CTRL_INTERCEPT_LDTR_READS RT_BIT_64(8)
393/** Intercept reads of TR. */
394#define SVM_CTRL_INTERCEPT_TR_READS RT_BIT_64(9)
395/** Intercept writes of IDTR. */
396#define SVM_CTRL_INTERCEPT_IDTR_WRITES RT_BIT_64(10)
397/** Intercept writes of GDTR. */
398#define SVM_CTRL_INTERCEPT_GDTR_WRITES RT_BIT_64(11)
399/** Intercept writes of LDTR. */
400#define SVM_CTRL_INTERCEPT_LDTR_WRITES RT_BIT_64(12)
401/** Intercept writes of TR. */
402#define SVM_CTRL_INTERCEPT_TR_WRITES RT_BIT_64(13)
403/** Intercept RDTSC instruction. */
404#define SVM_CTRL_INTERCEPT_RDTSC RT_BIT_64(14)
405/** Intercept RDPMC instruction. */
406#define SVM_CTRL_INTERCEPT_RDPMC RT_BIT_64(15)
407/** Intercept PUSHF instruction. */
408#define SVM_CTRL_INTERCEPT_PUSHF RT_BIT_64(16)
409/** Intercept POPF instruction. */
410#define SVM_CTRL_INTERCEPT_POPF RT_BIT_64(17)
411/** Intercept CPUID instruction. */
412#define SVM_CTRL_INTERCEPT_CPUID RT_BIT_64(18)
413/** Intercept RSM instruction. */
414#define SVM_CTRL_INTERCEPT_RSM RT_BIT_64(19)
415/** Intercept IRET instruction. */
416#define SVM_CTRL_INTERCEPT_IRET RT_BIT_64(20)
417/** Intercept INTn instruction. */
418#define SVM_CTRL_INTERCEPT_INTN RT_BIT_64(21)
419/** Intercept INVD instruction. */
420#define SVM_CTRL_INTERCEPT_INVD RT_BIT_64(22)
421/** Intercept PAUSE instruction. */
422#define SVM_CTRL_INTERCEPT_PAUSE RT_BIT_64(23)
423/** Intercept HLT instruction. */
424#define SVM_CTRL_INTERCEPT_HLT RT_BIT_64(24)
425/** Intercept INVLPG instruction. */
426#define SVM_CTRL_INTERCEPT_INVLPG RT_BIT_64(25)
427/** Intercept INVLPGA instruction. */
428#define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26)
429/** IOIO_PROT Intercept IN/OUT accesses to selected ports. */
430#define SVM_CTRL_INTERCEPT_IOIO_PROT RT_BIT_64(27)
431/** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
432#define SVM_CTRL_INTERCEPT_MSR_PROT RT_BIT_64(28)
433/** Intercept task switches. */
434#define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29)
435/** FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
436#define SVM_CTRL_INTERCEPT_FERR_FREEZE RT_BIT_64(30)
437/** Intercept shutdown events. */
438#define SVM_CTRL_INTERCEPT_SHUTDOWN RT_BIT_64(31)
439/** Intercept VMRUN instruction. */
440#define SVM_CTRL_INTERCEPT_VMRUN RT_BIT_64(32 + 0)
441/** Intercept VMMCALL instruction. */
442#define SVM_CTRL_INTERCEPT_VMMCALL RT_BIT_64(32 + 1)
443/** Intercept VMLOAD instruction. */
444#define SVM_CTRL_INTERCEPT_VMLOAD RT_BIT_64(32 + 2)
445/** Intercept VMSAVE instruction. */
446#define SVM_CTRL_INTERCEPT_VMSAVE RT_BIT_64(32 + 3)
447/** Intercept STGI instruction. */
448#define SVM_CTRL_INTERCEPT_STGI RT_BIT_64(32 + 4)
449/** Intercept CLGI instruction. */
450#define SVM_CTRL_INTERCEPT_CLGI RT_BIT_64(32 + 5)
451/** Intercept SKINIT instruction. */
452#define SVM_CTRL_INTERCEPT_SKINIT RT_BIT_64(32 + 6)
453/** Intercept RDTSCP instruction. */
454#define SVM_CTRL_INTERCEPT_RDTSCP RT_BIT_64(32 + 7)
455/** Intercept ICEBP instruction. */
456#define SVM_CTRL_INTERCEPT_ICEBP RT_BIT_64(32 + 8)
457/** Intercept WBINVD instruction. */
458#define SVM_CTRL_INTERCEPT_WBINVD RT_BIT_64(32 + 9)
459/** Intercept MONITOR instruction. */
460#define SVM_CTRL_INTERCEPT_MONITOR RT_BIT_64(32 + 10)
461/** Intercept MWAIT instruction unconditionally. */
462#define SVM_CTRL_INTERCEPT_MWAIT RT_BIT_64(32 + 11)
463/** Intercept MWAIT instruction when armed. */
464#define SVM_CTRL_INTERCEPT_MWAIT_ARMED RT_BIT_64(32 + 12)
465/** Intercept XSETBV instruction. */
466#define SVM_CTRL_INTERCEPT_XSETBV RT_BIT_64(32 + 13)
467/** Intercept RDPRU instruction. */
468#define SVM_CTRL_INTERCEPT_RDPRU RT_BIT_64(32 + 14)
469/** Intercept EFER writes after guest instruction finishes. */
470#define SVM_CTRL_INTERCEPT_EFER_WRITES_TRAP RT_BIT_64(32 + 15)
471/** Intercept CR0 writes after guest instruction finishes. */
472#define SVM_CTRL_INTERCEPT_CR0_WRITES_TRAP RT_BIT_64(32 + 16)
473/** Intercept CR0 writes after guest instruction finishes. */
474#define SVM_CTRL_INTERCEPT_CR1_WRITES_TRAP RT_BIT_64(32 + 17)
475/** Intercept CR0 writes after guest instruction finishes. */
476#define SVM_CTRL_INTERCEPT_CR2_WRITES_TRAP RT_BIT_64(32 + 18)
477/** Intercept CR0 writes after guest instruction finishes. */
478#define SVM_CTRL_INTERCEPT_CR3_WRITES_TRAP RT_BIT_64(32 + 19)
479/** Intercept CR0 writes after guest instruction finishes. */
480#define SVM_CTRL_INTERCEPT_CR4_WRITES_TRAP RT_BIT_64(32 + 20)
481/** Intercept CR0 writes after guest instruction finishes. */
482#define SVM_CTRL_INTERCEPT_CR5_WRITES_TRAP RT_BIT_64(32 + 21)
483/** Intercept CR0 writes after guest instruction finishes. */
484#define SVM_CTRL_INTERCEPT_CR6_WRITES_TRAP RT_BIT_64(32 + 22)
485/** Intercept CR0 writes after guest instruction finishes. */
486#define SVM_CTRL_INTERCEPT_CR7_WRITES_TRAP RT_BIT_64(32 + 23)
487/** Intercept CR0 writes after guest instruction finishes. */
488#define SVM_CTRL_INTERCEPT_CR8_WRITES_TRAP RT_BIT_64(32 + 24)
489/** Intercept CR0 writes after guest instruction finishes. */
490#define SVM_CTRL_INTERCEPT_CR9_WRITES_TRAP RT_BIT_64(32 + 25)
491/** Intercept CR0 writes after guest instruction finishes. */
492#define SVM_CTRL_INTERCEPT_CR10_WRITES_TRAP RT_BIT_64(32 + 26)
493/** Intercept CR0 writes after guest instruction finishes. */
494#define SVM_CTRL_INTERCEPT_CR11_WRITES_TRAP RT_BIT_64(32 + 27)
495/** Intercept CR0 writes after guest instruction finishes. */
496#define SVM_CTRL_INTERCEPT_CR12_WRITES_TRAP RT_BIT_64(32 + 28)
497/** Intercept CR0 writes after guest instruction finishes. */
498#define SVM_CTRL_INTERCEPT_CR13_WRITES_TRAP RT_BIT_64(32 + 29)
499/** Intercept CR0 writes after guest instruction finishes. */
500#define SVM_CTRL_INTERCEPT_CR14_WRITES_TRAP RT_BIT_64(32 + 30)
501/** Intercept CR0 writes after guest instruction finishes. */
502#define SVM_CTRL_INTERCEPT_CR15_WRITES_TRAP RT_BIT_64(32 + 31)
503/** @} */
504
505/** @name SVMINTCTRL.u3Type
506 * @{
507 */
508/** External or virtual interrupt. */
509#define SVM_EVENT_EXTERNAL_IRQ 0
510/** Non-maskable interrupt. */
511#define SVM_EVENT_NMI 2
512/** Exception; fault or trap. */
513#define SVM_EVENT_EXCEPTION 3
514/** Software interrupt. */
515#define SVM_EVENT_SOFTWARE_INT 4
516/** @} */
517
518/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
519 * @{
520 */
521/** Flush nothing. */
522#define SVM_TLB_FLUSH_NOTHING 0
523/** Flush entire TLB (host+guest entries) */
524#define SVM_TLB_FLUSH_ENTIRE 1
525/** Flush this guest's TLB entries (by ASID) */
526#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
527/** Flush this guest's non-global TLB entries (by ASID) */
528#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
529/** @} */
530
531/**
532 * SVM selector/segment register type.
533 */
534typedef struct
535{
536 uint16_t u16Sel;
537 uint16_t u16Attr;
538 uint32_t u32Limit;
539 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
540} SVMSELREG;
541AssertCompileSize(SVMSELREG, 16);
542/** Pointer to the SVMSELREG struct. */
543typedef SVMSELREG *PSVMSELREG;
544/** Pointer to a const SVMSELREG struct. */
545typedef const SVMSELREG *PCSVMSELREG;
546
547/**
548 * SVM GDTR/IDTR type.
549 */
550typedef struct
551{
552 uint16_t u16Reserved0;
553 uint16_t u16Reserved1;
554 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
555 uint64_t u64Base;
556} SVMXDTR;
557AssertCompileSize(SVMXDTR, 16);
558typedef SVMXDTR SVMIDTR;
559typedef SVMXDTR SVMGDTR;
560/** Pointer to the SVMXDTR struct. */
561typedef SVMXDTR *PSVMXDTR;
562/** Pointer to a const SVMXDTR struct. */
563typedef const SVMXDTR *PCSVMXDTR;
564
565/**
566 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
567 */
568typedef union
569{
570 struct
571 {
572 uint32_t u8Vector : 8;
573 uint32_t u3Type : 3;
574 uint32_t u1ErrorCodeValid : 1;
575 uint32_t u19Reserved : 19;
576 uint32_t u1Valid : 1;
577 uint32_t u32ErrorCode : 32;
578 } n;
579 uint64_t u;
580} SVMEVENT;
581/** Pointer to the SVMEVENT union. */
582typedef SVMEVENT *PSVMEVENT;
583/** Pointer to a const SVMEVENT union. */
584typedef const SVMEVENT *PCSVMEVENT;
585
586/** Gets the event type given an SVMEVENT parameter. */
587#define SVM_EVENT_GET_TYPE(a_SvmEvent) (((a_SvmEvent) >> 8) & 7)
588
589/**
590 * SVM Interrupt control structure (Virtual Interrupt Control).
591 */
592typedef union
593{
594 struct
595 {
596 uint32_t u8VTPR : 8; /* V_TPR */
597 uint32_t u1VIrqPending : 1; /* V_IRQ */
598 uint32_t u1VGif : 1; /* VGIF */
599 uint32_t u6Reserved : 6;
600 uint32_t u4VIntrPrio : 4; /* V_INTR_PRIO */
601 uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
602 uint32_t u3Reserved : 3;
603 uint32_t u1VIntrMasking : 1; /* V_INTR_MASKING */
604 uint32_t u1VGifEnable : 1; /* VGIF enable */
605 uint32_t u5Reserved : 5;
606 uint32_t u1AvicEnable : 1; /* AVIC enable */
607 uint32_t u8VIntrVector : 8; /* V_INTR_VECTOR */
608 uint32_t u24Reserved : 24;
609 } n;
610 uint64_t u;
611} SVMINTCTRL;
612/** Pointer to an SVMINTCTRL structure. */
613typedef SVMINTCTRL *PSVMINTCTRL;
614/** Pointer to a const SVMINTCTRL structure. */
615typedef const SVMINTCTRL *PCSVMINTCTRL;
616
617/**
618 * SVM TLB control structure.
619 */
620typedef union
621{
622 struct
623 {
624 uint32_t u32ASID : 32;
625 uint32_t u8TLBFlush : 8;
626 uint32_t u24Reserved : 24;
627 } n;
628 uint64_t u;
629} SVMTLBCTRL;
630
631/**
632 * SVM IOIO exit info. structure (EXITINFO1 for IOIO intercepts).
633 */
634typedef union
635{
636 struct
637 {
638 uint32_t u1Type : 1; /**< Bit 0: 0 = out, 1 = in */
639 uint32_t u1Reserved : 1; /**< Bit 1: Reserved */
640 uint32_t u1Str : 1; /**< Bit 2: String I/O (1) or not (0). */
641 uint32_t u1Rep : 1; /**< Bit 3: Repeat prefixed string I/O. */
642 uint32_t u1Op8 : 1; /**< Bit 4: 8-bit operand. */
643 uint32_t u1Op16 : 1; /**< Bit 5: 16-bit operand. */
644 uint32_t u1Op32 : 1; /**< Bit 6: 32-bit operand. */
645 uint32_t u1Addr16 : 1; /**< Bit 7: 16-bit address size. */
646 uint32_t u1Addr32 : 1; /**< Bit 8: 32-bit address size. */
647 uint32_t u1Addr64 : 1; /**< Bit 9: 64-bit address size. */
648 uint32_t u3Seg : 3; /**< Bits 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
649 uint32_t u3Reserved : 3;
650 uint32_t u16Port : 16; /**< Bits 31:16: Port number. */
651 } n;
652 uint32_t u;
653} SVMIOIOEXITINFO;
654/** Pointer to an SVM IOIO exit info. structure. */
655typedef SVMIOIOEXITINFO *PSVMIOIOEXITINFO;
656/** Pointer to a const SVM IOIO exit info. structure. */
657typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
658
659/** 8-bit IO transfer. */
660#define SVM_IOIO_8_BIT_OP RT_BIT_32(4)
661/** 16-bit IO transfer. */
662#define SVM_IOIO_16_BIT_OP RT_BIT_32(5)
663/** 32-bit IO transfer. */
664#define SVM_IOIO_32_BIT_OP RT_BIT_32(6)
665/** Number of bits to shift right to get the operand sizes. */
666#define SVM_IOIO_OP_SIZE_SHIFT 4
667/** Mask of all possible IO transfer sizes. */
668#define SVM_IOIO_OP_SIZE_MASK (SVM_IOIO_8_BIT_OP | SVM_IOIO_16_BIT_OP | SVM_IOIO_32_BIT_OP)
669/** 16-bit address for the IO buffer. */
670#define SVM_IOIO_16_BIT_ADDR RT_BIT_32(7)
671/** 32-bit address for the IO buffer. */
672#define SVM_IOIO_32_BIT_ADDR RT_BIT_32(8)
673/** 64-bit address for the IO buffer. */
674#define SVM_IOIO_64_BIT_ADDR RT_BIT_32(9)
675/** Number of bits to shift right to get the address sizes. */
676#define SVM_IOIO_ADDR_SIZE_SHIFT 7
677/** Mask of all the IO address sizes. */
678#define SVM_IOIO_ADDR_SIZE_MASK (SVM_IOIO_16_BIT_ADDR | SVM_IOIO_32_BIT_ADDR | SVM_IOIO_64_BIT_ADDR)
679/** Number of bits to shift right to get the IO port number. */
680#define SVM_IOIO_PORT_SHIFT 16
681/** IO write. */
682#define SVM_IOIO_WRITE 0
683/** IO read. */
684#define SVM_IOIO_READ 1
685/**
686 * SVM IOIO transfer type.
687 */
688typedef enum
689{
690 SVMIOIOTYPE_OUT = SVM_IOIO_WRITE,
691 SVMIOIOTYPE_IN = SVM_IOIO_READ
692} SVMIOIOTYPE;
693
694/**
695 * SVM AVIC.
696 */
697typedef union
698{
699 struct
700 {
701 RT_GCC_EXTENSION uint64_t u12Reserved0 : 12;
702 RT_GCC_EXTENSION uint64_t u40Addr : 40;
703 RT_GCC_EXTENSION uint64_t u12Reserved1 : 12;
704 } n;
705 uint64_t u;
706} SVMAVIC;
707AssertCompileSize(SVMAVIC, 8);
708
709/**
710 * SVM AVIC PHYSICAL_TABLE pointer.
711 */
712typedef union
713{
714 struct
715 {
716 RT_GCC_EXTENSION uint64_t u8LastGuestCoreId : 8;
717 RT_GCC_EXTENSION uint64_t u4Reserved : 4;
718 RT_GCC_EXTENSION uint64_t u40Addr : 40;
719 RT_GCC_EXTENSION uint64_t u12Reserved : 12;
720 } n;
721 uint64_t u;
722} SVMAVICPHYS;
723AssertCompileSize(SVMAVICPHYS, 8);
724
725/**
726 * SVM Nested Paging struct.
727 */
728typedef union
729{
730 struct
731 {
732 uint32_t u1NestedPaging : 1;
733 uint32_t u1Sev : 1;
734 uint32_t u1SevEs : 1;
735 uint32_t u29Reserved : 29;
736 } n;
737 uint64_t u;
738} SVMNP;
739AssertCompileSize(SVMNP, 8);
740
741/**
742 * SVM Interrupt shadow struct.
743 */
744typedef union
745{
746 struct
747 {
748 uint32_t u1IntShadow : 1;
749 uint32_t u1GuestIntMask : 1;
750 uint32_t u30Reserved : 30;
751 } n;
752 uint64_t u;
753} SVMINTSHADOW;
754AssertCompileSize(SVMINTSHADOW, 8);
755
756/**
757 * SVM LBR virtualization struct.
758 */
759typedef union
760{
761 struct
762 {
763 uint32_t u1LbrVirt : 1;
764 uint32_t u1VirtVmsaveVmload : 1;
765 uint32_t u30Reserved : 30;
766 } n;
767 uint64_t u;
768} SVMLBRVIRT;
769AssertCompileSize(SVMLBRVIRT, 8);
770
771/** Maximum number of bytes in the Guest-instruction bytes field. */
772#define SVM_CTRL_GUEST_INSTR_BYTES_MAX 15
773
774/**
775 * SVM VMCB control area.
776 */
777#pragma pack(1)
778typedef struct
779{
780 /** Offset 0x00 - Intercept reads of CR0-CR15. */
781 uint16_t u16InterceptRdCRx;
782 /** Offset 0x02 - Intercept writes to CR0-CR15. */
783 uint16_t u16InterceptWrCRx;
784 /** Offset 0x04 - Intercept reads of DR0-DR15. */
785 uint16_t u16InterceptRdDRx;
786 /** Offset 0x06 - Intercept writes to DR0-DR15. */
787 uint16_t u16InterceptWrDRx;
788 /** Offset 0x08 - Intercept exception vectors 0-31. */
789 uint32_t u32InterceptXcpt;
790 /** Offset 0x0c - Intercept control. */
791 uint64_t u64InterceptCtrl;
792 /** Offset 0x14-0x3f - Reserved. */
793 uint8_t u8Reserved0[0x3c - 0x14];
794 /** Offset 0x3c - PAUSE filter threshold. */
795 uint16_t u16PauseFilterThreshold;
796 /** Offset 0x3e - PAUSE intercept filter count. */
797 uint16_t u16PauseFilterCount;
798 /** Offset 0x40 - Physical address of IOPM. */
799 uint64_t u64IOPMPhysAddr;
800 /** Offset 0x48 - Physical address of MSRPM. */
801 uint64_t u64MSRPMPhysAddr;
802 /** Offset 0x50 - TSC Offset. */
803 uint64_t u64TSCOffset;
804 /** Offset 0x58 - TLB control field. */
805 SVMTLBCTRL TLBCtrl;
806 /** Offset 0x60 - Interrupt control field. */
807 SVMINTCTRL IntCtrl;
808 /** Offset 0x68 - Interrupt shadow. */
809 SVMINTSHADOW IntShadow;
810 /** Offset 0x70 - Exit code. */
811 uint64_t u64ExitCode;
812 /** Offset 0x78 - Exit info 1. */
813 uint64_t u64ExitInfo1;
814 /** Offset 0x80 - Exit info 2. */
815 uint64_t u64ExitInfo2;
816 /** Offset 0x88 - Exit Interrupt info. */
817 SVMEVENT ExitIntInfo;
818 /** Offset 0x90 - Nested Paging control. */
819 SVMNP NestedPagingCtrl;
820 /** Offset 0x98 - AVIC APIC BAR. */
821 SVMAVIC AvicBar;
822 /** Offset 0xa0-0xa7 - Reserved. */
823 uint8_t u8Reserved1[0xa8 - 0xa0];
824 /** Offset 0xa8 - Event injection. */
825 SVMEVENT EventInject;
826 /** Offset 0xb0 - Host CR3 for nested paging. */
827 uint64_t u64NestedPagingCR3;
828 /** Offset 0xb8 - LBR Virtualization. */
829 SVMLBRVIRT LbrVirt;
830 /** Offset 0xc0 - VMCB Clean Bits. */
831 uint32_t u32VmcbCleanBits;
832 uint32_t u32Reserved0;
833 /** Offset 0xc8 - Next sequential instruction pointer. */
834 uint64_t u64NextRIP;
835 /** Offset 0xd0 - Number of bytes fetched. */
836 uint8_t cbInstrFetched;
837 /** Offset 0xd1 - Guest instruction bytes. */
838 uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
839 /** Offset 0xe0 - AVIC APIC_BACKING_PAGE pointer. */
840 SVMAVIC AvicBackingPagePtr;
841 /** Offset 0xe8-0xef - Reserved. */
842 uint8_t u8Reserved2[0xf0 - 0xe8];
843 /** Offset 0xf0 - AVIC LOGICAL_TABLE pointer. */
844 SVMAVIC AvicLogicalTablePtr;
845 /** Offset 0xf8 - AVIC PHYSICAL_TABLE pointer. */
846 SVMAVICPHYS AvicPhysicalTablePtr;
847} SVMVMCBCTRL;
848#pragma pack()
849/** Pointer to the SVMVMCBSTATESAVE structure. */
850typedef SVMVMCBCTRL *PSVMVMCBCTRL;
851/** Pointer to a const SVMVMCBSTATESAVE structure. */
852typedef const SVMVMCBCTRL *PCSVMVMCBCTRL;
853AssertCompileSize(SVMVMCBCTRL, 0x100);
854AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdCRx, 0x00);
855AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrCRx, 0x02);
856AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdDRx, 0x04);
857AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrDRx, 0x06);
858AssertCompileMemberOffset(SVMVMCBCTRL, u32InterceptXcpt, 0x08);
859AssertCompileMemberOffset(SVMVMCBCTRL, u64InterceptCtrl, 0x0c);
860AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved0, 0x14);
861AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterThreshold, 0x3c);
862AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterCount, 0x3e);
863AssertCompileMemberOffset(SVMVMCBCTRL, u64IOPMPhysAddr, 0x40);
864AssertCompileMemberOffset(SVMVMCBCTRL, u64MSRPMPhysAddr, 0x48);
865AssertCompileMemberOffset(SVMVMCBCTRL, u64TSCOffset, 0x50);
866AssertCompileMemberOffset(SVMVMCBCTRL, TLBCtrl, 0x58);
867AssertCompileMemberOffset(SVMVMCBCTRL, IntCtrl, 0x60);
868AssertCompileMemberOffset(SVMVMCBCTRL, IntShadow, 0x68);
869AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitCode, 0x70);
870AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo1, 0x78);
871AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo2, 0x80);
872AssertCompileMemberOffset(SVMVMCBCTRL, ExitIntInfo, 0x88);
873AssertCompileMemberOffset(SVMVMCBCTRL, NestedPagingCtrl, 0x90);
874AssertCompileMemberOffset(SVMVMCBCTRL, AvicBar, 0x98);
875AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved1, 0xa0);
876AssertCompileMemberOffset(SVMVMCBCTRL, EventInject, 0xa8);
877AssertCompileMemberOffset(SVMVMCBCTRL, u64NestedPagingCR3, 0xb0);
878AssertCompileMemberOffset(SVMVMCBCTRL, LbrVirt, 0xb8);
879AssertCompileMemberOffset(SVMVMCBCTRL, u32VmcbCleanBits, 0xc0);
880AssertCompileMemberOffset(SVMVMCBCTRL, u64NextRIP, 0xc8);
881AssertCompileMemberOffset(SVMVMCBCTRL, cbInstrFetched, 0xd0);
882AssertCompileMemberOffset(SVMVMCBCTRL, abInstr, 0xd1);
883AssertCompileMemberOffset(SVMVMCBCTRL, AvicBackingPagePtr, 0xe0);
884AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2, 0xe8);
885AssertCompileMemberOffset(SVMVMCBCTRL, AvicLogicalTablePtr, 0xf0);
886AssertCompileMemberOffset(SVMVMCBCTRL, AvicPhysicalTablePtr, 0xf8);
887AssertCompileMemberSize(SVMVMCBCTRL, abInstr, 0x0f);
888
889/**
890 * SVM VMCB state save area.
891 */
892#pragma pack(1)
893typedef struct
894{
895 /** Offset 0x400 - Guest ES register + hidden parts. */
896 SVMSELREG ES;
897 /** Offset 0x410 - Guest CS register + hidden parts. */
898 SVMSELREG CS;
899 /** Offset 0x420 - Guest SS register + hidden parts. */
900 SVMSELREG SS;
901 /** Offset 0x430 - Guest DS register + hidden parts. */
902 SVMSELREG DS;
903 /** Offset 0x440 - Guest FS register + hidden parts. */
904 SVMSELREG FS;
905 /** Offset 0x450 - Guest GS register + hidden parts. */
906 SVMSELREG GS;
907 /** Offset 0x460 - Guest GDTR register. */
908 SVMGDTR GDTR;
909 /** Offset 0x470 - Guest LDTR register + hidden parts. */
910 SVMSELREG LDTR;
911 /** Offset 0x480 - Guest IDTR register. */
912 SVMIDTR IDTR;
913 /** Offset 0x490 - Guest TR register + hidden parts. */
914 SVMSELREG TR;
915 /** Offset 0x4A0-0x4CA - Reserved. */
916 uint8_t u8Reserved0[0x4cb - 0x4a0];
917 /** Offset 0x4CB - CPL. */
918 uint8_t u8CPL;
919 /** Offset 0x4CC-0x4CF - Reserved. */
920 uint8_t u8Reserved1[0x4d0 - 0x4cc];
921 /** Offset 0x4D0 - EFER. */
922 uint64_t u64EFER;
923 /** Offset 0x4D8-0x547 - Reserved. */
924 uint8_t u8Reserved2[0x548 - 0x4d8];
925 /** Offset 0x548 - CR4. */
926 uint64_t u64CR4;
927 /** Offset 0x550 - CR3. */
928 uint64_t u64CR3;
929 /** Offset 0x558 - CR0. */
930 uint64_t u64CR0;
931 /** Offset 0x560 - DR7. */
932 uint64_t u64DR7;
933 /** Offset 0x568 - DR6. */
934 uint64_t u64DR6;
935 /** Offset 0x570 - RFLAGS. */
936 uint64_t u64RFlags;
937 /** Offset 0x578 - RIP. */
938 uint64_t u64RIP;
939 /** Offset 0x580-0x5D7 - Reserved. */
940 uint8_t u8Reserved3[0x5d8 - 0x580];
941 /** Offset 0x5D8 - RSP. */
942 uint64_t u64RSP;
943 /** Offset 0x5E0-0x5F7 - Reserved. */
944 uint8_t u8Reserved4[0x5f8 - 0x5e0];
945 /** Offset 0x5F8 - RAX. */
946 uint64_t u64RAX;
947 /** Offset 0x600 - STAR. */
948 uint64_t u64STAR;
949 /** Offset 0x608 - LSTAR. */
950 uint64_t u64LSTAR;
951 /** Offset 0x610 - CSTAR. */
952 uint64_t u64CSTAR;
953 /** Offset 0x618 - SFMASK. */
954 uint64_t u64SFMASK;
955 /** Offset 0x620 - KernelGSBase. */
956 uint64_t u64KernelGSBase;
957 /** Offset 0x628 - SYSENTER_CS. */
958 uint64_t u64SysEnterCS;
959 /** Offset 0x630 - SYSENTER_ESP. */
960 uint64_t u64SysEnterESP;
961 /** Offset 0x638 - SYSENTER_EIP. */
962 uint64_t u64SysEnterEIP;
963 /** Offset 0x640 - CR2. */
964 uint64_t u64CR2;
965 /** Offset 0x648-0x667 - Reserved. */
966 uint8_t u8Reserved5[0x668 - 0x648];
967 /** Offset 0x668 - PAT (Page Attribute Table) MSR. */
968 uint64_t u64PAT;
969 /** Offset 0x670 - DBGCTL. */
970 uint64_t u64DBGCTL;
971 /** Offset 0x678 - BR_FROM. */
972 uint64_t u64BR_FROM;
973 /** Offset 0x680 - BR_TO. */
974 uint64_t u64BR_TO;
975 /** Offset 0x688 - LASTEXCPFROM. */
976 uint64_t u64LASTEXCPFROM;
977 /** Offset 0x690 - LASTEXCPTO. */
978 uint64_t u64LASTEXCPTO;
979} SVMVMCBSTATESAVE;
980#pragma pack()
981/** Pointer to the SVMVMCBSTATESAVE structure. */
982typedef SVMVMCBSTATESAVE *PSVMVMCBSTATESAVE;
983/** Pointer to a const SVMVMCBSTATESAVE structure. */
984typedef const SVMVMCBSTATESAVE *PCSVMVMCBSTATESAVE;
985AssertCompileSize(SVMVMCBSTATESAVE, 0x298);
986AssertCompileMemberOffset(SVMVMCBSTATESAVE, ES, 0x400 - 0x400);
987AssertCompileMemberOffset(SVMVMCBSTATESAVE, CS, 0x410 - 0x400);
988AssertCompileMemberOffset(SVMVMCBSTATESAVE, SS, 0x420 - 0x400);
989AssertCompileMemberOffset(SVMVMCBSTATESAVE, DS, 0x430 - 0x400);
990AssertCompileMemberOffset(SVMVMCBSTATESAVE, FS, 0x440 - 0x400);
991AssertCompileMemberOffset(SVMVMCBSTATESAVE, GS, 0x450 - 0x400);
992AssertCompileMemberOffset(SVMVMCBSTATESAVE, GDTR, 0x460 - 0x400);
993AssertCompileMemberOffset(SVMVMCBSTATESAVE, LDTR, 0x470 - 0x400);
994AssertCompileMemberOffset(SVMVMCBSTATESAVE, IDTR, 0x480 - 0x400);
995AssertCompileMemberOffset(SVMVMCBSTATESAVE, TR, 0x490 - 0x400);
996AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved0, 0x4a0 - 0x400);
997AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8CPL, 0x4cb - 0x400);
998AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved1, 0x4cc - 0x400);
999AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64EFER, 0x4d0 - 0x400);
1000AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved2, 0x4d8 - 0x400);
1001AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR4, 0x548 - 0x400);
1002AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR3, 0x550 - 0x400);
1003AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR0, 0x558 - 0x400);
1004AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR7, 0x560 - 0x400);
1005AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR6, 0x568 - 0x400);
1006AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RFlags, 0x570 - 0x400);
1007AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RIP, 0x578 - 0x400);
1008AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved3, 0x580 - 0x400);
1009AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RSP, 0x5d8 - 0x400);
1010AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4, 0x5e0 - 0x400);
1011AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RAX, 0x5f8 - 0x400);
1012AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64STAR, 0x600 - 0x400);
1013AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LSTAR, 0x608 - 0x400);
1014AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CSTAR, 0x610 - 0x400);
1015AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SFMASK, 0x618 - 0x400);
1016AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64KernelGSBase, 0x620 - 0x400);
1017AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterCS, 0x628 - 0x400);
1018AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterESP, 0x630 - 0x400);
1019AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterEIP, 0x638 - 0x400);
1020AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR2, 0x640 - 0x400);
1021AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5, 0x648 - 0x400);
1022AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64PAT, 0x668 - 0x400);
1023AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DBGCTL, 0x670 - 0x400);
1024AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_FROM, 0x678 - 0x400);
1025AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_TO, 0x680 - 0x400);
1026AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPFROM, 0x688 - 0x400);
1027AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPTO, 0x690 - 0x400);
1028
1029/**
1030 * SVM VM Control Block. (VMCB)
1031 */
1032#pragma pack(1)
1033typedef struct SVMVMCB
1034{
1035 /** Offset 0x00 - Control area. */
1036 SVMVMCBCTRL ctrl;
1037 /** Offset 0x100-0x3FF - Reserved. */
1038 uint8_t u8Reserved0[0x400 - 0x100];
1039 /** Offset 0x400 - State save area. */
1040 SVMVMCBSTATESAVE guest;
1041 /** Offset 0x698-0xFFF- Reserved. */
1042 uint8_t u8Reserved1[0x1000 - 0x698];
1043} SVMVMCB;
1044#pragma pack()
1045/** Pointer to the SVMVMCB structure. */
1046typedef SVMVMCB *PSVMVMCB;
1047/** Pointer to a const SVMVMCB structure. */
1048typedef const SVMVMCB *PCSVMVMCB;
1049AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
1050AssertCompileMemberOffset(SVMVMCB, u8Reserved0, 0x100);
1051AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
1052AssertCompileMemberOffset(SVMVMCB, u8Reserved1, 0x698);
1053AssertCompileSize(SVMVMCB, 0x1000);
1054
1055/**
1056 * SVM MSRs.
1057 */
1058typedef struct SVMMSRS
1059{
1060 /** HWCR MSR. */
1061 uint64_t u64MsrHwcr;
1062 /** Reserved for future. */
1063 uint64_t u64Padding[27];
1064} SVMMSRS;
1065AssertCompileSizeAlignment(SVMMSRS, 8);
1066AssertCompileSize(SVMMSRS, 224);
1067/** Pointer to a SVMMSRS struct. */
1068typedef SVMMSRS *PSVMMSRS;
1069/** Pointer to a const SVMMSRS struct. */
1070typedef const SVMMSRS *PCSVMMSRS;
1071
1072/**
1073 * SVM VM-exit auxiliary information.
1074 *
1075 * This includes information that isn't necessarily stored in the guest-CPU
1076 * context but provided as part of \#VMEXITs.
1077 */
1078typedef struct
1079{
1080 uint64_t u64ExitCode;
1081 uint64_t u64ExitInfo1;
1082 uint64_t u64ExitInfo2;
1083 SVMEVENT ExitIntInfo;
1084} SVMEXITAUX;
1085/** Pointer to a SVMEXITAUX struct. */
1086typedef SVMEXITAUX *PSVMEXITAUX;
1087/** Pointer to a const SVMEXITAUX struct. */
1088typedef const SVMEXITAUX *PCSVMEXITAUX;
1089
1090/**
1091 * Segment attribute conversion between CPU and AMD-V VMCB format.
1092 *
1093 * The CPU format of the segment attribute is described in X86DESCATTRBITS
1094 * which is 16-bits (i.e. includes 4 bits of the segment limit).
1095 *
1096 * The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
1097 * only the attribute bits and nothing else). Upper 4-bits are unused.
1098 */
1099#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0xf000) >> 4) )
1100#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0x0f00) << 4) )
1101
1102/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1103 * Copies the specified segment register to a VMCB from a virtual CPU context.
1104 *
1105 * @param a_pCtx The virtual-CPU context.
1106 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1107 * @param a_REG The segment register in the VMCB state-save
1108 * struct (ES/CS/SS/DS).
1109 * @param a_reg The segment register in the virtual CPU struct
1110 * (es/cs/ss/ds).
1111 */
1112#define HMSVM_SEG_REG_COPY_TO_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1113 do \
1114 { \
1115 Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID); \
1116 Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel); \
1117 (a_pVmcbStateSave)->a_REG.u16Sel = (a_pCtx)->a_reg.Sel; \
1118 (a_pVmcbStateSave)->a_REG.u32Limit = (a_pCtx)->a_reg.u32Limit; \
1119 (a_pVmcbStateSave)->a_REG.u64Base = (a_pCtx)->a_reg.u64Base; \
1120 (a_pVmcbStateSave)->a_REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
1121 } while (0)
1122
1123/** @def HMSVM_SEG_REG_COPY_FROM_VMCB
1124 * Copies the specified segment register from the VMCB to a virtual CPU
1125 * context.
1126 *
1127 * @param a_pCtx The virtual-CPU context.
1128 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1129 * @param a_REG The segment register in the VMCB state-save
1130 * struct (ES/CS/SS/DS).
1131 * @param a_reg The segment register in the virtual CPU struct
1132 * (es/ds/ss/ds).
1133 */
1134#define HMSVM_SEG_REG_COPY_FROM_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1135 do \
1136 { \
1137 (a_pCtx)->a_reg.Sel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1138 (a_pCtx)->a_reg.ValidSel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1139 (a_pCtx)->a_reg.fFlags = CPUMSELREG_FLAGS_VALID; \
1140 (a_pCtx)->a_reg.u32Limit = (a_pVmcbStateSave)->a_REG.u32Limit; \
1141 (a_pCtx)->a_reg.u64Base = (a_pVmcbStateSave)->a_REG.u64Base; \
1142 (a_pCtx)->a_reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
1143 } while (0)
1144
1145
1146/** @defgroup grp_hm_svm_hwexec SVM Hardware-assisted execution Helpers
1147 *
1148 * These functions are only here because the inline functions in cpum.h calls them.
1149 * Don't add any more functions here unless there is no other option.
1150 * @{
1151 */
1152VMM_INT_DECL(bool) HMGetGuestSvmCtrlIntercepts(PCVMCPU pVCpu, uint64_t *pu64Intercepts);
1153VMM_INT_DECL(bool) HMGetGuestSvmReadCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1154VMM_INT_DECL(bool) HMGetGuestSvmWriteCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1155VMM_INT_DECL(bool) HMGetGuestSvmReadDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1156VMM_INT_DECL(bool) HMGetGuestSvmWriteDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1157VMM_INT_DECL(bool) HMGetGuestSvmXcptIntercepts(PCVMCPU pVCpu, uint32_t *pu32Intercepts);
1158VMM_INT_DECL(bool) HMGetGuestSvmVirtIntrMasking(PCVMCPU pVCpu, bool *pfVIntrMasking);
1159VMM_INT_DECL(bool) HMGetGuestSvmNestedPaging(PCVMCPU pVCpu, bool *pfNestedPagingCtrl);
1160VMM_INT_DECL(bool) HMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, uint16_t *pu16PauseFilterCount);
1161VMM_INT_DECL(bool) HMGetGuestSvmTscOffset(PCVMCPU pVCpu, uint64_t *pu64TscOffset);
1162/** @} */
1163
1164
1165/** @} */
1166
1167#endif /* !VBOX_INCLUDED_vmm_hm_svm_h */
1168
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette