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source: vbox/trunk/include/VBox/vmm/hm.h@ 69759

Last change on this file since 69759 was 69107, checked in by vboxsync, 7 years ago

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1/** @file
2 * HM - Intel/AMD VM Hardware Assisted Virtualization Manager (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2017 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_hm_h
27#define ___VBox_vmm_hm_h
28
29#include <VBox/vmm/pgm.h>
30#include <VBox/vmm/cpum.h>
31#include <VBox/vmm/vmm.h>
32#include <VBox/vmm/hm_svm.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/mp.h>
35
36
37/** @defgroup grp_hm The Hardware Assisted Virtualization Manager API
38 * @ingroup grp_vmm
39 * @{
40 */
41
42RT_C_DECLS_BEGIN
43
44/**
45 * Checks whether HM (VT-x/AMD-V) is being used by this VM.
46 *
47 * @retval true if used.
48 * @retval false if software virtualization (raw-mode) is used.
49 *
50 * @param a_pVM The cross context VM structure.
51 * @sa HMIsEnabledNotMacro, HMR3IsEnabled
52 * @internal
53 */
54#if defined(VBOX_STRICT) && defined(IN_RING3)
55# define HMIsEnabled(a_pVM) HMIsEnabledNotMacro(a_pVM)
56#else
57# define HMIsEnabled(a_pVM) ((a_pVM)->fHMEnabled)
58#endif
59
60/**
61 * Checks whether raw-mode context is required for any purpose.
62 *
63 * @retval true if required either by raw-mode itself or by HM for doing
64 * switching the cpu to 64-bit mode.
65 * @retval false if not required.
66 *
67 * @param a_pVM The cross context VM structure.
68 * @internal
69 */
70#if HC_ARCH_BITS == 64
71# define HMIsRawModeCtxNeeded(a_pVM) (!HMIsEnabled(a_pVM))
72#else
73# define HMIsRawModeCtxNeeded(a_pVM) (!HMIsEnabled(a_pVM) || (a_pVM)->fHMNeedRawModeCtx)
74#endif
75
76 /**
77 * Check if the current CPU state is valid for emulating IO blocks in the recompiler
78 *
79 * @returns boolean
80 * @param a_pVCpu Pointer to the shared virtual CPU structure.
81 * @internal
82 */
83#define HMCanEmulateIoBlock(a_pVCpu) (!CPUMIsGuestInPagedProtectedMode(a_pVCpu))
84
85 /**
86 * Check if the current CPU state is valid for emulating IO blocks in the recompiler
87 *
88 * @returns boolean
89 * @param a_pCtx Pointer to the CPU context (within PVM).
90 * @internal
91 */
92#define HMCanEmulateIoBlockEx(a_pCtx) (!CPUMIsGuestInPagedProtectedModeEx(a_pCtx))
93
94/**
95 * Checks whether we're in the special hardware virtualization context.
96 * @returns true / false.
97 * @param a_pVCpu The caller's cross context virtual CPU structure.
98 * @thread EMT
99 */
100#ifdef IN_RING0
101# define HMIsInHwVirtCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_HM)
102#else
103# define HMIsInHwVirtCtx(a_pVCpu) (false)
104#endif
105
106/**
107 * Checks whether we're in the special hardware virtualization context and we
108 * cannot perform long jump without guru meditating and possibly messing up the
109 * host and/or guest state.
110 *
111 * This is after we've turned interrupts off and such.
112 *
113 * @returns true / false.
114 * @param a_pVCpu The caller's cross context virtual CPU structure.
115 * @thread EMT
116 */
117#ifdef IN_RING0
118# define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_EXEC)
119#else
120# define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (false)
121#endif
122
123/**
124 * 64-bit raw-mode (intermediate memory context) operations.
125 *
126 * These are special hypervisor eip values used when running 64-bit guests on
127 * 32-bit hosts. Each operation corresponds to a routine.
128 *
129 * @note Duplicated in the assembly code!
130 */
131typedef enum HM64ON32OP
132{
133 HM64ON32OP_INVALID = 0,
134 HM64ON32OP_VMXRCStartVM64,
135 HM64ON32OP_SVMRCVMRun64,
136 HM64ON32OP_HMRCSaveGuestFPU64,
137 HM64ON32OP_HMRCSaveGuestDebug64,
138 HM64ON32OP_HMRCTestSwitcher64,
139 HM64ON32OP_END,
140 HM64ON32OP_32BIT_HACK = 0x7fffffff
141} HM64ON32OP;
142
143/** @name All-context HM API.
144 * @{ */
145VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM);
146VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
147VMM_INT_DECL(bool) HMHasPendingIrq(PVM pVM);
148VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu);
149VMM_INT_DECL(int) HMAmdIsSubjectToErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping);
150VMM_INT_DECL(bool) HMSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable);
151VMM_INT_DECL(void) HMHypercallsEnable(PVMCPU pVCpu);
152VMM_INT_DECL(void) HMHypercallsDisable(PVMCPU pVCpu);
153/** @} */
154
155/** @name All-context SVM helpers.
156 * @{ */
157VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pSvmEvent);
158VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint32_t *puMsrpmBit);
159VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
160 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
161 PSVMIOIOEXITINFO pIoExitInfo);
162VMM_INT_DECL(VBOXSTRICTRC) HMSvmVmmcall(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfRipUpdated);
163/** @} */
164
165/** @name Nested hardware virtualization.
166 * @{
167 */
168#ifdef VBOX_WITH_NESTED_HWVIRT
169VMM_INT_DECL(void) HMSvmNstGstVmExitNotify(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst);
170#endif
171/** @} */
172
173#ifndef IN_RC
174VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu);
175VMM_INT_DECL(int) HMFlushTLBOnAllVCpus(PVM pVM);
176VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
177VMM_INT_DECL(int) HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
178VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM);
179VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVM pVM);
180VMM_INT_DECL(bool) HMIsLongModeAllowed(PVM pVM);
181VMM_INT_DECL(bool) HMAreMsrBitmapsAvailable(PVM pVM);
182VMM_INT_DECL(PGMMODE) HMGetShwPagingMode(PVM pVM);
183#else /* Nops in RC: */
184# define HMFlushTLB(pVCpu) do { } while (0)
185# define HMIsNestedPagingActive(pVM) false
186# define HMAreNestedPagingAndFullGuestExecEnabled(pVM) false
187# define HMIsLongModeAllowed(pVM) false
188# define HMAreMsrBitmapsAvailable(pVM) false
189# define HMFlushTLBOnAllVCpus(pVM) do { } while (0)
190#endif
191
192#ifdef IN_RING0
193/** @defgroup grp_hm_r0 The HM ring-0 Context API
194 * @{
195 */
196VMMR0_INT_DECL(int) HMR0Init(void);
197VMMR0_INT_DECL(int) HMR0Term(void);
198VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM);
199VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM);
200VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM);
201# ifdef VBOX_WITH_RAW_MODE
202VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
203VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
204# endif
205
206VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
207 unsigned uPort, unsigned uAndVal, unsigned cbSize);
208VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM);
209VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
210VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu);
211VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu);
212VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu);
213VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser);
214VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU VCpu);
215VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU VCpu);
216VMMR0_INT_DECL(bool) HMR0SuspendPending(void);
217
218# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
219VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
220VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
221VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM);
222# endif
223
224VMMR0_INT_DECL(int) HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx);
225
226/** @} */
227#endif /* IN_RING0 */
228
229
230#ifdef IN_RING3
231/** @defgroup grp_hm_r3 The HM ring-3 Context API
232 * @{
233 */
234VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM);
235VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM);
236VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM);
237VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM);
238VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM);
239VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM);
240VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM);
241VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM);
242
243VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu);
244VMMR3_INT_DECL(int) HMR3Init(PVM pVM);
245VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
246VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM);
247VMMR3_INT_DECL(int) HMR3Term(PVM pVM);
248VMMR3_INT_DECL(void) HMR3Reset(PVM pVM);
249VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu);
250VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode);
251VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx);
252VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu);
253VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu);
254VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM);
255VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu);
256VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu);
257VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
258VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx);
259VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
260VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
261VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
262VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
263VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx);
264VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM);
265VMMR3_INT_DECL(void) HMR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix);
266/** @} */
267#endif /* IN_RING3 */
268
269/** @} */
270RT_C_DECLS_END
271
272
273#endif
274
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