VirtualBox

source: vbox/trunk/include/VBox/vmm/hm.h@ 56291

Last change on this file since 56291 was 55863, checked in by vboxsync, 10 years ago

IPRT,SUPDrv,VMM: Revised the context switching hook interface. Do less work when enabling the hook (formerly 'registration'). Drop the reference counting (kept internally for solaris) as it complicates restrictions wrt destroying enabled hooks. Bumped support driver version.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 9.7 KB
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1/** @file
2 * HM - Intel/AMD VM Hardware Assisted Virtualization Manager (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2015 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_hm_h
27#define ___VBox_vmm_hm_h
28
29#include <VBox/vmm/pgm.h>
30#include <VBox/vmm/cpum.h>
31#include <VBox/vmm/vmm.h>
32#include <iprt/mp.h>
33
34
35/** @defgroup grp_hm The VM Hardware Manager API
36 * @{
37 */
38
39RT_C_DECLS_BEGIN
40
41/**
42 * Checks whether HM (VT-x/AMD-V) is being used by this VM.
43 *
44 * @retval @c true if used.
45 * @retval @c false if software virtualization (raw-mode) is used.
46 *
47 * @param a_pVM The cross context VM structure.
48 * @sa HMIsEnabledNotMacro, HMR3IsEnabled
49 * @internal
50 */
51#if defined(VBOX_STRICT) && defined(IN_RING3)
52# define HMIsEnabled(a_pVM) HMIsEnabledNotMacro(a_pVM)
53#else
54# define HMIsEnabled(a_pVM) ((a_pVM)->fHMEnabled)
55#endif
56
57/**
58 * Checks whether raw-mode context is required for any purpose.
59 *
60 * @retval @c true if required either by raw-mode itself or by HM for doing
61 * switching the cpu to 64-bit mode.
62 * @retval @c false if not required.
63 *
64 * @param a_pVM The cross context VM structure.
65 * @internal
66 */
67#if HC_ARCH_BITS == 64
68# define HMIsRawModeCtxNeeded(a_pVM) (!HMIsEnabled(a_pVM))
69#else
70# define HMIsRawModeCtxNeeded(a_pVM) (!HMIsEnabled(a_pVM) || (a_pVM)->fHMNeedRawModeCtx)
71#endif
72
73 /**
74 * Check if the current CPU state is valid for emulating IO blocks in the recompiler
75 *
76 * @returns boolean
77 * @param a_pVCpu Pointer to the shared virtual CPU structure.
78 * @internal
79 */
80#define HMCanEmulateIoBlock(a_pVCpu) (!CPUMIsGuestInPagedProtectedMode(a_pVCpu))
81
82 /**
83 * Check if the current CPU state is valid for emulating IO blocks in the recompiler
84 *
85 * @returns boolean
86 * @param a_pCtx Pointer to the CPU context (within PVM).
87 * @internal
88 */
89#define HMCanEmulateIoBlockEx(a_pCtx) (!CPUMIsGuestInPagedProtectedModeEx(a_pCtx))
90
91/**
92 * Checks whether we're in the special hardware virtualization context.
93 * @returns true / false.
94 * @param a_pVCpu The caller's cross context virtual CPU structure.
95 * @thread EMT
96 */
97#ifdef IN_RING0
98# define HMIsInHwVirtCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_HM)
99#else
100# define HMIsInHwVirtCtx(a_pVCpu) (false)
101#endif
102
103/**
104 * Checks whether we're in the special hardware virtualization context and we
105 * cannot perform long jump without guru meditating and possibly messing up the
106 * host and/or guest state.
107 *
108 * This is after we've turned interrupts off and such.
109 *
110 * @returns true / false.
111 * @param a_pVCpu The caller's cross context virtual CPU structure.
112 * @thread EMT
113 */
114#ifdef IN_RING0
115# define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_EXEC)
116#else
117# define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (false)
118#endif
119
120/**
121 * 64-bit raw-mode (intermediate memory context) operations.
122 *
123 * These are special hypervisor eip values used when running 64-bit guests on
124 * 32-bit hosts. Each operation corresponds to a routine.
125 *
126 * @note Duplicated in the assembly code!
127 */
128typedef enum HM64ON32OP
129{
130 HM64ON32OP_INVALID = 0,
131 HM64ON32OP_VMXRCStartVM64,
132 HM64ON32OP_SVMRCVMRun64,
133 HM64ON32OP_HMRCSaveGuestFPU64,
134 HM64ON32OP_HMRCSaveGuestDebug64,
135 HM64ON32OP_HMRCTestSwitcher64,
136 HM64ON32OP_END,
137 HM64ON32OP_32BIT_HACK = 0x7fffffff
138} HM64ON32OP;
139
140VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM);
141VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
142VMM_INT_DECL(bool) HMHasPendingIrq(PVM pVM);
143VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu);
144VMM_INT_DECL(int) HMAmdIsSubjectToErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping);
145VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCPU pVCpu, bool fEnable);
146VMM_INT_DECL(void) HMHypercallsEnable(PVMCPU pVCpu);
147VMM_INT_DECL(void) HMHypercallsDisable(PVMCPU pVCpu);
148
149#ifndef IN_RC
150VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu);
151VMM_INT_DECL(int) HMFlushTLBOnAllVCpus(PVM pVM);
152VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
153VMM_INT_DECL(int) HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
154VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM);
155VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVM pVM);
156VMM_INT_DECL(bool) HMIsLongModeAllowed(PVM pVM);
157VMM_INT_DECL(bool) HMAreMsrBitmapsAvailable(PVM pVM);
158VMM_INT_DECL(PGMMODE) HMGetShwPagingMode(PVM pVM);
159#else /* Nops in RC: */
160# define HMFlushTLB(pVCpu) do { } while (0)
161# define HMIsNestedPagingActive(pVM) false
162# define HMAreNestedPagingAndFullGuestExecEnabled(pVM) false
163# define HMIsLongModeAllowed(pVM) false
164# define HMAreMsrBitmapsAvailable(pVM) false
165# define HMFlushTLBOnAllVCpus(pVM) do { } while (0)
166#endif
167
168#ifdef IN_RING0
169/** @defgroup grp_hm_r0 The VM Hardware Manager API
170 * @{
171 */
172VMMR0_INT_DECL(int) HMR0Init(void);
173VMMR0_INT_DECL(int) HMR0Term(void);
174VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM);
175VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM);
176VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM);
177VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
178VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
179
180VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
181 unsigned uPort, unsigned uAndVal, unsigned cbSize);
182VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
183 unsigned uPort, unsigned uAndVal, unsigned cbSize);
184VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM);
185VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
186VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu);
187VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu);
188VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu);
189VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser);
190VMMR0_INT_DECL(bool) HMR0SuspendPending(void);
191
192# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
193VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
194VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
195VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM);
196# endif
197
198VMMR0_INT_DECL(int) HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx);
199
200/** @} */
201#endif /* IN_RING0 */
202
203
204#ifdef IN_RING3
205/** @defgroup grp_hm_r3 The VM Hardware Manager API
206 * @{
207 */
208VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM);
209VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM);
210VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM);
211VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM);
212VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM);
213VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM);
214
215VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu);
216VMMR3_INT_DECL(int) HMR3Init(PVM pVM);
217VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
218VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM);
219VMMR3_INT_DECL(int) HMR3Term(PVM pVM);
220VMMR3_INT_DECL(void) HMR3Reset(PVM pVM);
221VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu);
222VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode);
223VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx);
224VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu);
225VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu);
226VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu);
227VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
228VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx);
229VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
230VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
231VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
232VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
233VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx);
234VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM);
235
236/** @} */
237#endif /* IN_RING3 */
238
239/** @} */
240RT_C_DECLS_END
241
242
243#endif
244
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