| 1 | /** @file
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| 2 | * EM - Execution Monitor.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2006-2013 Oracle Corporation
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| 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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| 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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| 24 | */
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| 25 |
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| 26 | #ifndef ___VBox_vmm_em_h
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| 27 | #define ___VBox_vmm_em_h
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| 28 |
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| 29 | #include <VBox/types.h>
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| 30 | #include <VBox/vmm/trpm.h>
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| 31 |
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| 32 |
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| 33 | RT_C_DECLS_BEGIN
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| 34 |
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| 35 | /** @defgroup grp_em The Execution Monitor / Manager API
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| 36 | * @{
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| 37 | */
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| 38 |
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| 39 | /** Enable to allow V86 code to run in raw mode. */
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| 40 | #define VBOX_RAW_V86
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| 41 |
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| 42 | /**
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| 43 | * The Execution Manager State.
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| 44 | *
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| 45 | * @remarks This is used in the saved state!
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| 46 | */
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| 47 | typedef enum EMSTATE
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| 48 | {
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| 49 | /** Not yet started. */
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| 50 | EMSTATE_NONE = 1,
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| 51 | /** Raw-mode execution. */
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| 52 | EMSTATE_RAW,
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| 53 | /** Hardware accelerated raw-mode execution. */
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| 54 | EMSTATE_HM,
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| 55 | /** Executing in IEM. */
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| 56 | EMSTATE_IEM,
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| 57 | /** Recompiled mode execution. */
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| 58 | EMSTATE_REM,
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| 59 | /** Execution is halted. (waiting for interrupt) */
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| 60 | EMSTATE_HALTED,
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| 61 | /** Application processor execution is halted. (waiting for startup IPI (SIPI)) */
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| 62 | EMSTATE_WAIT_SIPI,
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| 63 | /** Execution is suspended. */
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| 64 | EMSTATE_SUSPENDED,
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| 65 | /** The VM is terminating. */
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| 66 | EMSTATE_TERMINATING,
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| 67 | /** Guest debug event from raw-mode is being processed. */
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| 68 | EMSTATE_DEBUG_GUEST_RAW,
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| 69 | /** Guest debug event from hardware accelerated mode is being processed. */
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| 70 | EMSTATE_DEBUG_GUEST_HM,
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| 71 | /** Guest debug event from interpreted execution mode is being processed. */
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| 72 | EMSTATE_DEBUG_GUEST_IEM,
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| 73 | /** Guest debug event from recompiled-mode is being processed. */
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| 74 | EMSTATE_DEBUG_GUEST_REM,
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| 75 | /** Hypervisor debug event being processed. */
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| 76 | EMSTATE_DEBUG_HYPER,
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| 77 | /** The VM has encountered a fatal error. (And everyone is panicing....) */
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| 78 | EMSTATE_GURU_MEDITATION,
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| 79 | /** Executing in IEM, falling back on REM if we cannot switch back to HM or
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| 80 | * RAW after a short while. */
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| 81 | EMSTATE_IEM_THEN_REM,
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| 82 | /** Just a hack to ensure that we get a 32-bit integer. */
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| 83 | EMSTATE_MAKE_32BIT_HACK = 0x7fffffff
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| 84 | } EMSTATE;
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| 85 |
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| 86 |
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| 87 | /**
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| 88 | * EMInterpretInstructionCPU execution modes.
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| 89 | */
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| 90 | typedef enum
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| 91 | {
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| 92 | /** Only supervisor code (CPL=0). */
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| 93 | EMCODETYPE_SUPERVISOR,
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| 94 | /** User-level code only. */
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| 95 | EMCODETYPE_USER,
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| 96 | /** Supervisor and user-level code (use with great care!). */
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| 97 | EMCODETYPE_ALL,
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| 98 | /** Just a hack to ensure that we get a 32-bit integer. */
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| 99 | EMCODETYPE_32BIT_HACK = 0x7fffffff
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| 100 | } EMCODETYPE;
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| 101 |
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| 102 | VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu);
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| 103 | VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
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| 104 |
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| 105 | /** @name Callback handlers for instruction emulation functions.
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| 106 | * These are placed here because IOM wants to use them as well.
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| 107 | * @{
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| 108 | */
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| 109 | typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2UINT32(void *pvParam1, uint64_t val2);
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| 110 | typedef FNEMULATEPARAM2UINT32 *PFNEMULATEPARAM2UINT32;
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| 111 | typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2(void *pvParam1, size_t val2);
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| 112 | typedef FNEMULATEPARAM2 *PFNEMULATEPARAM2;
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| 113 | typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM3(void *pvParam1, uint64_t val2, size_t val3);
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| 114 | typedef FNEMULATEPARAM3 *PFNEMULATEPARAM3;
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| 115 | typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
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| 116 | typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
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| 117 | typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
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| 118 | typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
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| 119 | /** @} */
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| 120 |
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| 121 |
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| 122 | /**
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| 123 | * Checks if raw ring-3 execute mode is enabled.
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| 124 | *
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| 125 | * @returns true if enabled.
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| 126 | * @returns false if disabled.
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| 127 | * @param pVM The VM to operate on.
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| 128 | */
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| 129 | #define EMIsRawRing3Enabled(pVM) (!(pVM)->fRecompileUser)
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| 130 |
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| 131 | /**
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| 132 | * Checks if raw ring-0 execute mode is enabled.
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| 133 | *
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| 134 | * @returns true if enabled.
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| 135 | * @returns false if disabled.
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| 136 | * @param pVM The VM to operate on.
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| 137 | */
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| 138 | #define EMIsRawRing0Enabled(pVM) (!(pVM)->fRecompileSupervisor)
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| 139 |
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| 140 | #ifdef VBOX_WITH_RAW_RING1
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| 141 | /**
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| 142 | * Checks if raw ring-1 execute mode is enabled.
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| 143 | *
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| 144 | * @returns true if enabled.
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| 145 | * @returns false if disabled.
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| 146 | * @param pVM The VM to operate on.
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| 147 | */
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| 148 | # define EMIsRawRing1Enabled(pVM) ((pVM)->fRawRing1Enabled)
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| 149 | #else
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| 150 | # define EMIsRawRing1Enabled(pVM) false
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| 151 | #endif
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| 152 |
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| 153 | /**
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| 154 | * Checks if execution with hardware assisted virtualization is enabled.
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| 155 | *
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| 156 | * @returns true if enabled.
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| 157 | * @returns false if disabled.
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| 158 | * @param pVM The VM to operate on.
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| 159 | */
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| 160 | #define EMIsHwVirtExecutionEnabled(pVM) (!(pVM)->fRecompileSupervisor && !(pVM)->fRecompileUser)
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| 161 |
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| 162 | /**
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| 163 | * Checks if execution of supervisor code should be done in the
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| 164 | * recompiler or not.
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| 165 | *
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| 166 | * @returns true if enabled.
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| 167 | * @returns false if disabled.
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| 168 | * @param pVM The VM to operate on.
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| 169 | */
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| 170 | #define EMIsSupervisorCodeRecompiled(pVM) ((pVM)->fRecompileSupervisor)
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| 171 |
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| 172 | VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
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| 173 | VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
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| 174 | VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pCpu, unsigned *pcbInstr);
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| 175 | VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
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| 176 | PDISCPUSTATE pDISState, unsigned *pcbInstr);
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| 177 | VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault);
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| 178 | VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten);
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| 179 | VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx,
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| 180 | RTGCPTR pvFault, EMCODETYPE enmCodeType);
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| 181 |
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| 182 | #ifdef IN_RC
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| 183 | VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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| 184 | #endif
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| 185 |
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| 186 | VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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| 187 | VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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| 188 | VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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| 189 | VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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| 190 | VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
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| 191 | VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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| 192 | VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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| 193 | VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
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| 194 | VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
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| 195 | VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
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| 196 | VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
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| 197 | VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
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| 198 | VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
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| 199 | VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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| 200 | VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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| 201 | VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
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| 202 | VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx);
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| 203 | VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys);
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| 204 | VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx);
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| 205 |
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| 206 | /** @name Assembly routines
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| 207 | * @{ */
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| 208 | VMMDECL(uint32_t) EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
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| 209 | VMMDECL(uint32_t) EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
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| 210 | VMMDECL(uint32_t) EMEmulateInc(void *pvParam1, size_t cb);
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| 211 | VMMDECL(uint32_t) EMEmulateDec(void *pvParam1, size_t cb);
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| 212 | VMMDECL(uint32_t) EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
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| 213 | VMMDECL(int) EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
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| 214 | VMMDECL(uint32_t) EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
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| 215 | VMMDECL(int) EMEmulateLockXor(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
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| 216 | VMMDECL(uint32_t) EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
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| 217 | VMMDECL(int) EMEmulateLockAnd(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
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| 218 | VMMDECL(uint32_t) EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
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| 219 | VMMDECL(uint32_t) EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
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| 220 | VMMDECL(uint32_t) EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
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| 221 | VMMDECL(int) EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
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| 222 | VMMDECL(uint32_t) EMEmulateBts(void *pvParam1, uint64_t u64Param2);
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| 223 | VMMDECL(uint32_t) EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
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| 224 | VMMDECL(uint32_t) EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
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| 225 | VMMDECL(uint32_t) EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
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| 226 | VMMDECL(uint32_t) EMEmulateCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
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| 227 | VMMDECL(uint32_t) EMEmulateLockCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
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| 228 | VMMDECL(uint32_t) EMEmulateXAdd(void *pvParam1, void *pvParam2, size_t cbOp);
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| 229 | VMMDECL(uint32_t) EMEmulateLockXAdd(void *pvParam1, void *pvParam2, size_t cbOp);
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| 230 | /** @} */
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| 231 |
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| 232 | /** @name REM locking routines
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| 233 | * @{ */
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| 234 | VMMDECL(void) EMRemUnlock(PVM pVM);
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| 235 | VMMDECL(void) EMRemLock(PVM pVM);
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| 236 | VMMDECL(bool) EMRemIsLockOwner(PVM pVM);
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| 237 | VMM_INT_DECL(int) EMRemTryLock(PVM pVM);
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| 238 | /** @} */
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| 239 |
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| 240 |
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| 241 | /** @name EM_ONE_INS_FLAGS_XXX - flags for EMR3HmSingleInstruction (et al).
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| 242 | * @{ */
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| 243 | /** Return when CS:RIP changes or some other important event happens.
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| 244 | * This means running whole REP and LOOP $ sequences for instance. */
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| 245 | #define EM_ONE_INS_FLAGS_RIP_CHANGE RT_BIT_32(0)
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| 246 | /** Mask of valid flags. */
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| 247 | #define EM_ONE_INS_FLAGS_MASK UINT32_C(0x00000001)
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| 248 | /** @} */
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| 249 |
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| 250 |
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| 251 | #ifdef IN_RING3
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| 252 | /** @defgroup grp_em_r3 The EM Host Context Ring-3 API
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| 253 | * @ingroup grp_em
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| 254 | * @{
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| 255 | */
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| 256 |
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| 257 | /**
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| 258 | * Command argument for EMR3RawSetMode().
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| 259 | *
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| 260 | * It's possible to extend this interface to change several
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| 261 | * execution modes at once should the need arise.
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| 262 | */
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| 263 | typedef enum EMEXECPOLICY
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| 264 | {
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| 265 | /** The customary invalid zero entry. */
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| 266 | EMEXECPOLICY_INVALID = 0,
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| 267 | /** Whether to recompile ring-0 code or execute it in raw/hm. */
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| 268 | EMEXECPOLICY_RECOMPILE_RING0,
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| 269 | /** Whether to recompile ring-3 code or execute it in raw/hm. */
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| 270 | EMEXECPOLICY_RECOMPILE_RING3,
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| 271 | /** Whether to only use IEM for execution. */
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| 272 | EMEXECPOLICY_IEM_ALL,
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| 273 | /** End of valid value (not included). */
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| 274 | EMEXECPOLICY_END,
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| 275 | /** The customary 32-bit type blowup. */
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| 276 | EMEXECPOLICY_32BIT_HACK = 0x7fffffff
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| 277 | } EMEXECPOLICY;
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| 278 | VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce);
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| 279 | VMMR3DECL(int) EMR3QueryExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool *pfEnforced);
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| 280 |
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| 281 | VMMR3_INT_DECL(int) EMR3Init(PVM pVM);
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| 282 | VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM);
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| 283 | VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu);
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| 284 | VMMR3_INT_DECL(void) EMR3Reset(PVM pVM);
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| 285 | VMMR3_INT_DECL(int) EMR3Term(PVM pVM);
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| 286 | VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
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| 287 | VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
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| 288 | VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
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| 289 | VMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM);
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| 290 | VMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM);
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| 291 | VMMR3_INT_DECL(VBOXSTRICTRC) EMR3HmSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags);
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| 292 |
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| 293 | /** @} */
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| 294 | #endif /* IN_RING3 */
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| 295 |
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| 296 | /** @} */
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| 297 |
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| 298 | RT_C_DECLS_END
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| 299 |
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| 300 | #endif
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| 301 |
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