cpumctx.h@ 96407

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1	/** @file
2	* CPUM - CPU Monitor(/ Manager), Context Structures.
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpumctx_h
37	#define VBOX_INCLUDED_vmm_cpumctx_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/x86.h>
44	# include <VBox/types.h>
45	# include <VBox/vmm/hm_svm.h>
46	# include <VBox/vmm/hm_vmx.h>
47	#else
48	# pragma D depends_on library x86.d
49	#endif
50
51
52	RT_C_DECLS_BEGIN
53
54	/** @defgroup grp_cpum_ctx The CPUM Context Structures
55	* @ingroup grp_cpum
56	* @{
57	*/
58
59	/**
60	* Selector hidden registers.
61	*/
62	typedef struct CPUMSELREG
63	{
64	/** The selector register. */
65	RTSEL Sel;
66	/** Padding, don't use. */
67	RTSEL PaddingSel;
68	/** The selector which info resides in u64Base, u32Limit and Attr, provided
69	* that CPUMSELREG_FLAGS_VALID is set. */
70	RTSEL ValidSel;
71	/** Flags, see CPUMSELREG_FLAGS_XXX. */
72	uint16_t fFlags;
73
74	/** Base register.
75	*
76	* Long mode remarks:
77	* - Unused in long mode for CS, DS, ES, SS
78	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
79	* - 64 bits for TR & LDTR
80	*/
81	uint64_t u64Base;
82	/** Limit (expanded). */
83	uint32_t u32Limit;
84	/** Flags.
85	* This is the high 32-bit word of the descriptor entry.
86	* Only the flags, dpl and type are used. */
87	X86DESCATTR Attr;
88	} CPUMSELREG;
89	#ifndef VBOX_FOR_DTRACE_LIB
90	AssertCompileSize(CPUMSELREG, 24);
91	#endif
92
93	/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
94	* @{ */
95	#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
96	#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
97	#define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
98	/** @} */
99
100	/** Checks if the hidden parts of the selector register are valid. */
101	#define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
102	( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
103	&& (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
104
105	/** Old type used for the hidden register part.
106	* @deprecated */
107	typedef CPUMSELREG CPUMSELREGHID;
108
109	/**
110	* The sysenter register set.
111	*/
112	typedef struct CPUMSYSENTER
113	{
114	/** Ring 0 cs.
115	* This value + 8 is the Ring 0 ss.
116	* This value + 16 is the Ring 3 cs.
117	* This value + 24 is the Ring 3 ss.
118	*/
119	uint64_t cs;
120	/** Ring 0 eip. */
121	uint64_t eip;
122	/** Ring 0 esp. */
123	uint64_t esp;
124	} CPUMSYSENTER;
125
126	/** @def CPUM_UNION_NM
127	* For compilers (like DTrace) that does not grok nameless unions, we have a
128	* little hack to make them palatable.
129	*/
130	/** @def CPUM_STRUCT_NM
131	* For compilers (like DTrace) that does not grok nameless structs (it is
132	* non-standard C++), we have a little hack to make them palatable.
133	*/
134	#ifdef VBOX_FOR_DTRACE_LIB
135	# define CPUM_UNION_NM(a_Nm) a_Nm
136	# define CPUM_STRUCT_NM(a_Nm) a_Nm
137	#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
138	# define CPUM_UNION_NM(a_Nm) a_Nm
139	# define CPUM_STRUCT_NM(a_Nm) a_Nm
140	#else
141	# define CPUM_UNION_NM(a_Nm)
142	# define CPUM_STRUCT_NM(a_Nm)
143	#endif
144	/** @def CPUM_UNION_STRUCT_NM
145	* Combines CPUM_UNION_NM and CPUM_STRUCT_NM to avoid hitting the right side of
146	* the screen in the compile time assertions.
147	*/
148	#define CPUM_UNION_STRUCT_NM(a_UnionNm, a_StructNm) CPUM_UNION_NM(a_UnionNm .) CPUM_STRUCT_NM(a_StructNm)
149
150	/** A general register (union). */
151	typedef union CPUMCTXGREG
152	{
153	/** Natural unsigned integer view. */
154	uint64_t u;
155	/** 64-bit view. */
156	uint64_t u64;
157	/** 32-bit view. */
158	uint32_t u32;
159	/** 16-bit view. */
160	uint16_t u16;
161	/** 8-bit view. */
162	uint8_t u8;
163	/** 8-bit low/high view. */
164	RT_GCC_EXTENSION struct
165	{
166	/** Low byte (al, cl, dl, bl, ++). */
167	uint8_t bLo;
168	/** High byte in the first word - ah, ch, dh, bh. */
169	uint8_t bHi;
170	} CPUM_STRUCT_NM(s);
171	} CPUMCTXGREG;
172	#ifndef VBOX_FOR_DTRACE_LIB
173	AssertCompileSize(CPUMCTXGREG, 8);
174	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
175	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
176	#endif
177
178
179
180	/**
181	* CPU context core.
182	*
183	* @todo Eliminate this structure!
184	* @deprecated We don't push any context cores any more in TRPM.
185	*/
186	#pragma pack(1)
187	typedef struct CPUMCTXCORE
188	{
189	/** @name General Register.
190	* @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
191	* an array starting a rax.
192	* @{ */
193	union
194	{
195	uint8_t al;
196	uint16_t ax;
197	uint32_t eax;
198	uint64_t rax;
199	} CPUM_UNION_NM(rax);
200	union
201	{
202	uint8_t cl;
203	uint16_t cx;
204	uint32_t ecx;
205	uint64_t rcx;
206	} CPUM_UNION_NM(rcx);
207	union
208	{
209	uint8_t dl;
210	uint16_t dx;
211	uint32_t edx;
212	uint64_t rdx;
213	} CPUM_UNION_NM(rdx);
214	union
215	{
216	uint8_t bl;
217	uint16_t bx;
218	uint32_t ebx;
219	uint64_t rbx;
220	} CPUM_UNION_NM(rbx);
221	union
222	{
223	uint16_t sp;
224	uint32_t esp;
225	uint64_t rsp;
226	} CPUM_UNION_NM(rsp);
227	union
228	{
229	uint16_t bp;
230	uint32_t ebp;
231	uint64_t rbp;
232	} CPUM_UNION_NM(rbp);
233	union
234	{
235	uint8_t sil;
236	uint16_t si;
237	uint32_t esi;
238	uint64_t rsi;
239	} CPUM_UNION_NM(rsi);
240	union
241	{
242	uint8_t dil;
243	uint16_t di;
244	uint32_t edi;
245	uint64_t rdi;
246	} CPUM_UNION_NM(rdi);
247	uint64_t r8;
248	uint64_t r9;
249	uint64_t r10;
250	uint64_t r11;
251	uint64_t r12;
252	uint64_t r13;
253	uint64_t r14;
254	uint64_t r15;
255	/** @} */
256
257	/** @name Segment registers.
258	* @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
259	* an array starting a es.
260	* @{ */
261	CPUMSELREG es;
262	CPUMSELREG cs;
263	CPUMSELREG ss;
264	CPUMSELREG ds;
265	CPUMSELREG fs;
266	CPUMSELREG gs;
267	/** @} */
268
269	/** The program counter. */
270	union
271	{
272	uint16_t ip;
273	uint32_t eip;
274	uint64_t rip;
275	} CPUM_UNION_NM(rip);
276
277	/** The flags register. */
278	union
279	{
280	X86EFLAGS eflags;
281	X86RFLAGS rflags;
282	} CPUM_UNION_NM(rflags);
283
284	} CPUMCTXCORE;
285	#pragma pack()
286
287
288	/**
289	* SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
290	*
291	* @warning Exercise caution while modifying the layout of this struct. It's
292	* part of VM saved states.
293	*/
294	#pragma pack(1)
295	typedef struct SVMHOSTSTATE
296	{
297	uint64_t uEferMsr;
298	uint64_t uCr0;
299	uint64_t uCr4;
300	uint64_t uCr3;
301	uint64_t uRip;
302	uint64_t uRsp;
303	uint64_t uRax;
304	X86RFLAGS rflags;
305	CPUMSELREG es;
306	CPUMSELREG cs;
307	CPUMSELREG ss;
308	CPUMSELREG ds;
309	VBOXGDTR gdtr;
310	VBOXIDTR idtr;
311	uint8_t abPadding[4];
312	} SVMHOSTSTATE;
313	#pragma pack()
314	/** Pointer to the SVMHOSTSTATE structure. */
315	typedef SVMHOSTSTATE *PSVMHOSTSTATE;
316	/** Pointer to a const SVMHOSTSTATE structure. */
317	typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
318	#ifndef VBOX_FOR_DTRACE_LIB
319	AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
320	AssertCompileSize(SVMHOSTSTATE, 184);
321	#endif
322
323
324	/**
325	* CPU hardware virtualization types.
326	*/
327	typedef enum
328	{
329	CPUMHWVIRT_NONE = 0,
330	CPUMHWVIRT_VMX,
331	CPUMHWVIRT_SVM,
332	CPUMHWVIRT_32BIT_HACK = 0x7fffffff
333	} CPUMHWVIRT;
334	#ifndef VBOX_FOR_DTRACE_LIB
335	AssertCompileSize(CPUMHWVIRT, 4);
336	#endif
337
338
339	/**
340	* CPU context.
341	*/
342	#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
343	typedef struct CPUMCTX
344	{
345	/** CPUMCTXCORE Part.
346	* @{ */
347
348	/** General purpose registers. */
349	union /* no tag! */
350	{
351	/** The general purpose register array view, indexed by X86_GREG_XXX. */
352	CPUMCTXGREG aGRegs[16];
353
354	/** 64-bit general purpose register view. */
355	RT_GCC_EXTENSION struct /* no tag! */
356	{
357	uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
358	} CPUM_STRUCT_NM(qw);
359	/** 64-bit general purpose register view. */
360	RT_GCC_EXTENSION struct /* no tag! */
361	{
362	uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
363	} CPUM_STRUCT_NM(qw2);
364	/** 32-bit general purpose register view. */
365	RT_GCC_EXTENSION struct /* no tag! */
366	{
367	uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
368	esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
369	r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
370	r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
371	} CPUM_STRUCT_NM(dw);
372	/** 16-bit general purpose register view. */
373	RT_GCC_EXTENSION struct /* no tag! */
374	{
375	uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
376	sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
377	r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
378	r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
379	} CPUM_STRUCT_NM(w);
380	RT_GCC_EXTENSION struct /* no tag! */
381	{
382	uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
383	spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
384	r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
385	r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
386	} CPUM_STRUCT_NM(b);
387	} CPUM_UNION_NM(g);
388
389	/** Segment registers. */
390	union /* no tag! */
391	{
392	/** The segment register array view, indexed by X86_SREG_XXX. */
393	CPUMSELREG aSRegs[6];
394	/** The named segment register view. */
395	RT_GCC_EXTENSION struct /* no tag! */
396	{
397	CPUMSELREG es, cs, ss, ds, fs, gs;
398	} CPUM_STRUCT_NM(n);
399	} CPUM_UNION_NM(s);
400
401	/** The program counter. */
402	union
403	{
404	uint16_t ip;
405	uint32_t eip;
406	uint64_t rip;
407	} CPUM_UNION_NM(rip);
408
409	/** The flags register. */
410	union
411	{
412	X86EFLAGS eflags;
413	X86RFLAGS rflags;
414	} CPUM_UNION_NM(rflags);
415
416	/** @} / /(CPUMCTXCORE)*/
417
418
419	/** @name Control registers.
420	* @{ */
421	uint64_t cr0;
422	uint64_t cr2;
423	uint64_t cr3;
424	/** @todo the 4 PAE PDPE registers. See PGMCPU::aGstPaePdpeRegs. */
425	uint64_t cr4;
426	/** @} */
427
428	/** Debug registers.
429	* @remarks DR4 and DR5 should not be used since they are aliases for
430	* DR6 and DR7 respectively on both AMD and Intel CPUs.
431	* @remarks DR8-15 are currently not supported by AMD or Intel, so
432	* neither do we.
433	*/
434	uint64_t dr[8];
435
436	/** Padding before the structure so the 64-bit member is correctly aligned.
437	* @todo fix this structure! */
438	uint16_t gdtrPadding[3];
439	/** Global Descriptor Table register. */
440	VBOXGDTR gdtr;
441
442	/** Padding before the structure so the 64-bit member is correctly aligned.
443	* @todo fix this structure! */
444	uint16_t idtrPadding[3];
445	/** Interrupt Descriptor Table register. */
446	VBOXIDTR idtr;
447
448	/** The task register.
449	* Only the guest context uses all the members. */
450	CPUMSELREG ldtr;
451	/** The task register.
452	* Only the guest context uses all the members. */
453	CPUMSELREG tr;
454
455	/** The sysenter msr registers.
456	* This member is not used by the hypervisor context. */
457	CPUMSYSENTER SysEnter;
458
459	/** @name System MSRs.
460	* @{ */
461	uint64_t msrEFER;
462	uint64_t msrSTAR; /*< Legacy syscall eip, cs & ss. /
463	uint64_t msrPAT; /*< Page attribute table. /
464	uint64_t msrLSTAR; /*< 64 bits mode syscall rip. /
465	uint64_t msrCSTAR; /*< Compatibility mode syscall rip. /
466	uint64_t msrSFMASK; /*< syscall flag mask. /
467	uint64_t msrKERNELGSBASE; /*< swapgs exchange value. /
468	uint64_t uMsrPadding0; /*< no longer used (used to hold a copy of APIC base MSR). /
469	/** @} */
470
471	/** 0x228 - Externalized state tracker, CPUMCTX_EXTRN_XXX.
472	* Currently only used internally in NEM/win. */
473	uint64_t fExtrn;
474
475	uint64_t au64Unused[2];
476
477	/** 0x240 - PAE PDPTEs. */
478	X86PDPE aPaePdpes[4];
479
480	/** 0x260 - The XCR0..XCR1 registers. */
481	uint64_t aXcr[2];
482	/** 0x270 - The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
483	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
484	uint64_t fXStateMask;
485	/** 0x278 - Mirror of CPUMCPU::fUseFlags[CPUM_USED_FPU_GUEST]. */
486	bool fUsedFpuGuest;
487	uint8_t afUnused[7];
488
489	/* ---- Start of members not zeroed at reset. ---- */
490
491	/** 0x280 - State component offsets into pXState, UINT16_MAX if not present.
492	* @note Everything before this member will be memset to zero during reset. */
493	uint16_t aoffXState[64];
494	/** 0x300 - The extended state (FPU/SSE/AVX/AVX-2/XXXX).
495	* Aligned on 256 byte boundrary (min req is currently 64 bytes). */
496	union /* no tag */
497	{
498	X86XSAVEAREA XState;
499	/** Byte view for simple indexing and space allocation. */
500	uint8_t abXState[0x4000 - 0x300];
501	} CPUM_UNION_NM(u);
502
503	/** 0x4000 - Hardware virtualization state.
504	* @note This is page aligned, so an full page member comes first in the
505	* substructures. */
506	struct
507	{
508	union /* no tag! */
509	{
510	struct
511	{
512	/** 0x4000 - Cache of the nested-guest VMCB. */
513	SVMVMCB Vmcb;
514	/** 0x5000 - The MSRPM (MSR Permission bitmap).
515	*
516	* This need not be physically contiguous pages because we use the one from
517	* HMPHYSCPU while executing the nested-guest using hardware-assisted SVM.
518	* This one is just used for caching the bitmap from guest physical memory.
519	*
520	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
521	* really need to even be page aligned.
522	*
523	* Also, couldn't we just access the guest page directly when we need to,
524	* or do we have to use a cached copy of it? */
525	uint8_t abMsrBitmap[SVM_MSRPM_PAGES * X86_PAGE_SIZE];
526	/** 0x7000 - The IOPM (IO Permission bitmap).
527	*
528	* This need not be physically contiguous pages because we re-use the ring-0
529	* allocated IOPM while executing the nested-guest using hardware-assisted SVM
530	* because it's identical (we trap all IO accesses).
531	*
532	* This one is just used for caching the IOPM from guest physical memory in
533	* case the guest hypervisor allows direct access to some IO ports.
534	*
535	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
536	* really need to even be page aligned.
537	*
538	* Also, couldn't we just access the guest page directly when we need to,
539	* or do we have to use a cached copy of it? */
540	uint8_t abIoBitmap[SVM_IOPM_PAGES * X86_PAGE_SIZE];
541
542	/** 0xa000 - MSR holding physical address of the Guest's Host-state. */
543	uint64_t uMsrHSavePa;
544	/** 0xa008 - Guest physical address of the nested-guest VMCB. */
545	RTGCPHYS GCPhysVmcb;
546	/** 0xa010 - Guest's host-state save area. */
547	SVMHOSTSTATE HostState;
548	/** 0xa0c8 - Guest TSC time-stamp of when the previous PAUSE instr. was
549	* executed. */
550	uint64_t uPrevPauseTick;
551	/** 0xa0d0 - Pause filter count. */
552	uint16_t cPauseFilter;
553	/** 0xa0d2 - Pause filter threshold. */
554	uint16_t cPauseFilterThreshold;
555	/** 0xa0d4 - Whether the injected event is subject to event intercepts. */
556	bool fInterceptEvents;
557	/** 0xa0d5 - Padding. */
558	bool afPadding[3];
559	} svm;
560
561	struct
562	{
563	/** 0x4000 - The current VMCS. */
564	VMXVVMCS Vmcs;
565	/** 0X5000 - The shadow VMCS. */
566	VMXVVMCS ShadowVmcs;
567	/** 0x6000 - The VMREAD bitmap.
568	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
569	* access the guest memory directly as needed? */
570	uint8_t abVmreadBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
571	/** 0x7000 - The VMWRITE bitmap.
572	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
573	* access the guest memory directly as needed? */
574	uint8_t abVmwriteBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
575	/** 0x8000 - The VM-entry MSR-load area. */
576	VMXAUTOMSR aEntryMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
577	/** 0xa000 - The VM-exit MSR-store area. */
578	VMXAUTOMSR aExitMsrStoreArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
579	/** 0xc000 - The VM-exit MSR-load area. */
580	VMXAUTOMSR aExitMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
581	/** 0xe000 - The MSR permission bitmap.
582	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
583	* access the guest memory directly as needed? */
584	uint8_t abMsrBitmap[VMX_V_MSR_BITMAP_SIZE];
585	/** 0xf000 - The I/O permission bitmap.
586	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
587	* access the guest memory directly as needed? */
588	uint8_t abIoBitmap[VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE];
589	/** 0x11000 - The virtual-APIC page.
590	* @note This is used by VT-x hardware... */
591	uint8_t abVirtApicPage[VMX_V_VIRT_APIC_SIZE];
592
593	/** 0x12000 - Guest physical address of the VMXON region. */
594	RTGCPHYS GCPhysVmxon;
595	/** 0x12008 - Guest physical address of the current VMCS pointer. */
596	RTGCPHYS GCPhysVmcs;
597	/** 0x12010 - Guest physical address of the shadow VMCS pointer. */
598	RTGCPHYS GCPhysShadowVmcs;
599	/** 0x12018 - Last emulated VMX instruction/VM-exit diagnostic. */
600	VMXVDIAG enmDiag;
601	/** 0x1201c - VMX abort reason. */
602	VMXABORT enmAbort;
603	/** 0x12020 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info.
604	* (mainly used for info. that's not part of the VMCS). */
605	uint64_t uDiagAux;
606	/** 0x12028 - VMX abort auxiliary info. */
607	uint32_t uAbortAux;
608	/** 0x1202c - Whether the guest is in VMX root mode. */
609	bool fInVmxRootMode;
610	/** 0x1202d - Whether the guest is in VMX non-root mode. */
611	bool fInVmxNonRootMode;
612	/** 0x1202e - Whether the injected events are subjected to event intercepts. */
613	bool fInterceptEvents;
614	/** 0x1202f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX
615	* non-root mode before execution of IRET. */
616	bool fNmiUnblockingIret;
617	/** 0x12030 - Guest TSC timestamp of the first PAUSE instruction that is
618	* considered to be the first in a loop. */
619	uint64_t uFirstPauseLoopTick;
620	/** 0x12038 - Guest TSC timestamp of the previous PAUSE instruction. */
621	uint64_t uPrevPauseTick;
622	/** 0x12040 - Guest TSC timestamp of VM-entry (used for VMX-preemption
623	* timer). */
624	uint64_t uEntryTick;
625	/** 0x12048 - Virtual-APIC write offset (until trap-like VM-exit). */
626	uint16_t offVirtApicWrite;
627	/** 0x1204a - Whether virtual-NMI blocking is in effect. */
628	bool fVirtNmiBlocking;
629	/** 0x1204b - Padding. */
630	uint8_t abPadding0[5];
631	/** 0x12050 - Guest VMX MSRs. */
632	VMXMSRS Msrs;
633	} vmx;
634	} CPUM_UNION_NM(s);
635
636	/** 0x12130 - Hardware virtualization type currently in use. */
637	CPUMHWVIRT enmHwvirt;
638	/** 0x12134 - Global interrupt flag - AMD only (always true on Intel). */
639	bool fGif;
640	bool afPadding1[3];
641	/** 0x12138 - A subset of guest force flags that are saved while running the
642	* nested-guest. */
643	#ifdef VMCPU_WITH_64_BIT_FFS
644	uint64_t fLocalForcedActions;
645	#else
646	uint32_t fLocalForcedActions;
647	uint32_t fPadding;
648	#endif
649	#if 0
650	/** 0x12140 - Pad to 64 byte boundary. */
651	uint8_t abPadding0[8+16+32];
652	#endif
653	} hwvirt;
654	} CPUMCTX;
655	#pragma pack()
656
657	#ifndef VBOX_FOR_DTRACE_LIB
658	AssertCompileSizeAlignment(CPUMCTX, 64);
659	AssertCompileSizeAlignment(CPUMCTX, 32);
660	AssertCompileSizeAlignment(CPUMCTX, 16);
661	AssertCompileSizeAlignment(CPUMCTX, 8);
662	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0);
663	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 8);
664	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 16);
665	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 24);
666	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 32);
667	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 40);
668	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 48);
669	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 56);
670	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 64);
671	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 72);
672	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 80);
673	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 88);
674	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 96);
675	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 104);
676	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 112);
677	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 120);
678	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 128);
679	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 152);
680	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 176);
681	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 200);
682	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 224);
683	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 248);
684	AssertCompileMemberOffset(CPUMCTX, rip, 272);
685	AssertCompileMemberOffset(CPUMCTX, rflags, 280);
686	AssertCompileMemberOffset(CPUMCTX, cr0, 288);
687	AssertCompileMemberOffset(CPUMCTX, cr2, 296);
688	AssertCompileMemberOffset(CPUMCTX, cr3, 304);
689	AssertCompileMemberOffset(CPUMCTX, cr4, 312);
690	AssertCompileMemberOffset(CPUMCTX, dr, 320);
691	AssertCompileMemberOffset(CPUMCTX, gdtr, 384+6);
692	AssertCompileMemberOffset(CPUMCTX, idtr, 400+6);
693	AssertCompileMemberOffset(CPUMCTX, ldtr, 416);
694	AssertCompileMemberOffset(CPUMCTX, tr, 440);
695	AssertCompileMemberOffset(CPUMCTX, SysEnter, 464);
696	AssertCompileMemberOffset(CPUMCTX, msrEFER, 488);
697	AssertCompileMemberOffset(CPUMCTX, msrSTAR, 496);
698	AssertCompileMemberOffset(CPUMCTX, msrPAT, 504);
699	AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 512);
700	AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 520);
701	AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 528);
702	AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 536);
703	AssertCompileMemberOffset(CPUMCTX, aPaePdpes, 0x240);
704	AssertCompileMemberOffset(CPUMCTX, aXcr, 0x260);
705	AssertCompileMemberOffset(CPUMCTX, fXStateMask, 0x270);
706	AssertCompileMemberOffset(CPUMCTX, fUsedFpuGuest, 0x278);
707	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x300);
708	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) abXState, 0x300);
709	AssertCompileMemberAlignment(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x100);
710	/* Only do spot checks for hwvirt */
711	AssertCompileMemberAlignment(CPUMCTX, hwvirt, 0x1000);
712	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.Vmcb, X86_PAGE_SIZE);
713	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abMsrBitmap, X86_PAGE_SIZE);
714	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, X86_PAGE_SIZE);
715	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Vmcs, X86_PAGE_SIZE);
716	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.ShadowVmcs, X86_PAGE_SIZE);
717	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmreadBitmap, X86_PAGE_SIZE);
718	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmwriteBitmap, X86_PAGE_SIZE);
719	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aEntryMsrLoadArea, X86_PAGE_SIZE);
720	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrStoreArea, X86_PAGE_SIZE);
721	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrLoadArea, X86_PAGE_SIZE);
722	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abMsrBitmap, X86_PAGE_SIZE);
723	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, X86_PAGE_SIZE);
724	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVirtApicPage, X86_PAGE_SIZE);
725	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs, 8);
726	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, 0x7000);
727	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fInterceptEvents, 0xa0d4);
728	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, 0xf000);
729	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking, 0x1204a);
730	AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt, 0x12130);
731	AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif, 0x12134);
732	AssertCompileMemberOffset(CPUMCTX, hwvirt.fLocalForcedActions, 0x12138);
733	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
734	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
735	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
736	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
737	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
738	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
739	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
740	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
741	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
742	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
743	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
744	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
745	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
746	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
747	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
748	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
749	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
750	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
751	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
752	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
753	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
754	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
755	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
756	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
757	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
758	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
759	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
760	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
761	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
762	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
763	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
764	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
765	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
766	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
767	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
768	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
769	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
770	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
771	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
772	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
773	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
774	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
775	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
776	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
777	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
778	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
779	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
780	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
781	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
782	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
783	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
784	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
785	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
786	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
787	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
788	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
789	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
790	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
791	# ifndef _MSC_VER
792	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
793	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
794	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
795	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
796	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
797	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
798	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
799	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
800	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
801	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
802	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
803	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
804	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
805	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
806	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
807	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
808	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
809	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
810	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
811	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
812	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
813	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
814	# endif
815
816
817	/**
818	* Calculates the pointer to the given extended state component.
819	*
820	* @returns Pointer of type @a a_PtrType
821	* @param a_pCtx Pointer to the context.
822	* @param a_iCompBit The extended state component bit number. This bit
823	* must be set in CPUMCTX::fXStateMask.
824	* @param a_PtrType The pointer type of the extended state component.
825	*
826	*/
827	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
828	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
829	([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
830	{ \
831	AssertCompile((a_iCompBit) < 64U); \
832	AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
833	AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
834	return (a_PtrType)(&a_pLambdaCtx->abXState[a_pLambdaCtx->aoffXState[(a_iCompBit)]]); \
835	}(a_pCtx))
836	#elif defined(VBOX_STRICT) && defined(__GNUC__)
837	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
838	__extension__ (\
839	{ \
840	AssertCompile((a_iCompBit) < 64U); \
841	AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
842	AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
843	(a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]); \
844	})
845	#else
846	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
847	((a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]))
848	#endif
849
850	/**
851	* Gets the CPUMCTXCORE part of a CPUMCTX.
852	*/
853	# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->rax)
854
855	/**
856	* Gets the CPUMCTX part from a CPUMCTXCORE.
857	*/
858	# define CPUMCTX_FROM_CORE(a_pCtxCore) RT_FROM_MEMBER(a_pCtxCore, CPUMCTX, rax)
859
860	/**
861	* Gets the first selector register of a CPUMCTX.
862	*
863	* Use this with X86_SREG_COUNT to loop thru the selector registers.
864	*/
865	# define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
866
867	#endif /* !VBOX_FOR_DTRACE_LIB */
868
869
870	/** @name CPUMCTX_EXTRN_XXX
871	* Used for parts of the CPUM state that is externalized and needs fetching
872	* before use.
873	*
874	* @{ */
875	/** External state keeper: Invalid. */
876	#define CPUMCTX_EXTRN_KEEPER_INVALID UINT64_C(0x0000000000000000)
877	/** External state keeper: HM. */
878	#define CPUMCTX_EXTRN_KEEPER_HM UINT64_C(0x0000000000000001)
879	/** External state keeper: NEM. */
880	#define CPUMCTX_EXTRN_KEEPER_NEM UINT64_C(0x0000000000000002)
881	/** External state keeper: REM. */
882	#define CPUMCTX_EXTRN_KEEPER_REM UINT64_C(0x0000000000000003)
883	/** External state keeper mask. */
884	#define CPUMCTX_EXTRN_KEEPER_MASK UINT64_C(0x0000000000000003)
885
886	/** The RIP register value is kept externally. */
887	#define CPUMCTX_EXTRN_RIP UINT64_C(0x0000000000000004)
888	/** The RFLAGS register values are kept externally. */
889	#define CPUMCTX_EXTRN_RFLAGS UINT64_C(0x0000000000000008)
890
891	/** The RAX register value is kept externally. */
892	#define CPUMCTX_EXTRN_RAX UINT64_C(0x0000000000000010)
893	/** The RCX register value is kept externally. */
894	#define CPUMCTX_EXTRN_RCX UINT64_C(0x0000000000000020)
895	/** The RDX register value is kept externally. */
896	#define CPUMCTX_EXTRN_RDX UINT64_C(0x0000000000000040)
897	/** The RBX register value is kept externally. */
898	#define CPUMCTX_EXTRN_RBX UINT64_C(0x0000000000000080)
899	/** The RSP register value is kept externally. */
900	#define CPUMCTX_EXTRN_RSP UINT64_C(0x0000000000000100)
901	/** The RBP register value is kept externally. */
902	#define CPUMCTX_EXTRN_RBP UINT64_C(0x0000000000000200)
903	/** The RSI register value is kept externally. */
904	#define CPUMCTX_EXTRN_RSI UINT64_C(0x0000000000000400)
905	/** The RDI register value is kept externally. */
906	#define CPUMCTX_EXTRN_RDI UINT64_C(0x0000000000000800)
907	/** The R8 thru R15 register values are kept externally. */
908	#define CPUMCTX_EXTRN_R8_R15 UINT64_C(0x0000000000001000)
909	/** General purpose registers mask. */
910	#define CPUMCTX_EXTRN_GPRS_MASK UINT64_C(0x0000000000001ff0)
911
912	/** The ES register values are kept externally. */
913	#define CPUMCTX_EXTRN_ES UINT64_C(0x0000000000002000)
914	/** The CS register values are kept externally. */
915	#define CPUMCTX_EXTRN_CS UINT64_C(0x0000000000004000)
916	/** The SS register values are kept externally. */
917	#define CPUMCTX_EXTRN_SS UINT64_C(0x0000000000008000)
918	/** The DS register values are kept externally. */
919	#define CPUMCTX_EXTRN_DS UINT64_C(0x0000000000010000)
920	/** The FS register values are kept externally. */
921	#define CPUMCTX_EXTRN_FS UINT64_C(0x0000000000020000)
922	/** The GS register values are kept externally. */
923	#define CPUMCTX_EXTRN_GS UINT64_C(0x0000000000040000)
924	/** Segment registers (includes CS). */
925	#define CPUMCTX_EXTRN_SREG_MASK UINT64_C(0x000000000007e000)
926	/** Converts a X86_XREG_XXX index to a CPUMCTX_EXTRN_xS mask. */
927	#define CPUMCTX_EXTRN_SREG_FROM_IDX(a_SRegIdx) RT_BIT_64((a_SRegIdx) + 13)
928	#ifndef VBOX_FOR_DTRACE_LIB
929	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_ES) == CPUMCTX_EXTRN_ES);
930	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_CS) == CPUMCTX_EXTRN_CS);
931	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_DS) == CPUMCTX_EXTRN_DS);
932	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_FS) == CPUMCTX_EXTRN_FS);
933	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_GS) == CPUMCTX_EXTRN_GS);
934	#endif
935
936	/** The GDTR register values are kept externally. */
937	#define CPUMCTX_EXTRN_GDTR UINT64_C(0x0000000000080000)
938	/** The IDTR register values are kept externally. */
939	#define CPUMCTX_EXTRN_IDTR UINT64_C(0x0000000000100000)
940	/** The LDTR register values are kept externally. */
941	#define CPUMCTX_EXTRN_LDTR UINT64_C(0x0000000000200000)
942	/** The TR register values are kept externally. */
943	#define CPUMCTX_EXTRN_TR UINT64_C(0x0000000000400000)
944	/** Table register mask. */
945	#define CPUMCTX_EXTRN_TABLE_MASK UINT64_C(0x0000000000780000)
946
947	/** The CR0 register value is kept externally. */
948	#define CPUMCTX_EXTRN_CR0 UINT64_C(0x0000000000800000)
949	/** The CR2 register value is kept externally. */
950	#define CPUMCTX_EXTRN_CR2 UINT64_C(0x0000000001000000)
951	/** The CR3 register value is kept externally. */
952	#define CPUMCTX_EXTRN_CR3 UINT64_C(0x0000000002000000)
953	/** The CR4 register value is kept externally. */
954	#define CPUMCTX_EXTRN_CR4 UINT64_C(0x0000000004000000)
955	/** Control register mask. */
956	#define CPUMCTX_EXTRN_CR_MASK UINT64_C(0x0000000007800000)
957	/** The TPR/CR8 register value is kept externally. */
958	#define CPUMCTX_EXTRN_APIC_TPR UINT64_C(0x0000000008000000)
959	/** The EFER register value is kept externally. */
960	#define CPUMCTX_EXTRN_EFER UINT64_C(0x0000000010000000)
961
962	/** The DR0, DR1, DR2 and DR3 register values are kept externally. */
963	#define CPUMCTX_EXTRN_DR0_DR3 UINT64_C(0x0000000020000000)
964	/** The DR6 register value is kept externally. */
965	#define CPUMCTX_EXTRN_DR6 UINT64_C(0x0000000040000000)
966	/** The DR7 register value is kept externally. */
967	#define CPUMCTX_EXTRN_DR7 UINT64_C(0x0000000080000000)
968	/** Debug register mask. */
969	#define CPUMCTX_EXTRN_DR_MASK UINT64_C(0x00000000e0000000)
970
971	/** The XSAVE_C_X87 state is kept externally. */
972	#define CPUMCTX_EXTRN_X87 UINT64_C(0x0000000100000000)
973	/** The XSAVE_C_SSE, XSAVE_C_YMM, XSAVE_C_ZMM_HI256, XSAVE_C_ZMM_16HI and
974	* XSAVE_C_OPMASK state is kept externally. */
975	#define CPUMCTX_EXTRN_SSE_AVX UINT64_C(0x0000000200000000)
976	/** The state of XSAVE components not covered by CPUMCTX_EXTRN_X87 and
977	* CPUMCTX_EXTRN_SEE_AVX is kept externally. */
978	#define CPUMCTX_EXTRN_OTHER_XSAVE UINT64_C(0x0000000400000000)
979	/** The state of XCR0 and XCR1 register values are kept externally. */
980	#define CPUMCTX_EXTRN_XCRx UINT64_C(0x0000000800000000)
981
982
983	/** The KERNEL GS BASE MSR value is kept externally. */
984	#define CPUMCTX_EXTRN_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
985	/** The STAR, LSTAR, CSTAR and SFMASK MSR values are kept externally. */
986	#define CPUMCTX_EXTRN_SYSCALL_MSRS UINT64_C(0x0000002000000000)
987	/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
988	#define CPUMCTX_EXTRN_SYSENTER_MSRS UINT64_C(0x0000004000000000)
989	/** The TSC_AUX MSR is kept externally. */
990	#define CPUMCTX_EXTRN_TSC_AUX UINT64_C(0x0000008000000000)
991	/** All other stateful MSRs not covered by CPUMCTX_EXTRN_EFER,
992	* CPUMCTX_EXTRN_KERNEL_GS_BASE, CPUMCTX_EXTRN_SYSCALL_MSRS,
993	* CPUMCTX_EXTRN_SYSENTER_MSRS, and CPUMCTX_EXTRN_TSC_AUX. */
994	#define CPUMCTX_EXTRN_OTHER_MSRS UINT64_C(0x0000010000000000)
995
996	/** Mask of all the MSRs. */
997	#define CPUMCTX_EXTRN_ALL_MSRS ( CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \
998	\| CPUMCTX_EXTRN_SYSENTER_MSRS \| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS)
999
1000	/** Hardware-virtualization (SVM or VMX) state is kept externally. */
1001	#define CPUMCTX_EXTRN_HWVIRT UINT64_C(0x0000020000000000)
1002
1003	/** Inhibit maskable interrupts (VMCPU_FF_INHIBIT_INTERRUPTS) */
1004	#define CPUMCTX_EXTRN_INHIBIT_INT UINT64_C(0x0000040000000000)
1005	/** Inhibit non-maskable interrupts (VMCPU_FF_BLOCK_NMIS). */
1006	#define CPUMCTX_EXTRN_INHIBIT_NMI UINT64_C(0x0000080000000000)
1007
1008	/** Mask of bits the keepers can use for state tracking. */
1009	#define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
1010
1011	/** NEM/Win: Event injection (known was interruption) pending state. */
1012	#define CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT UINT64_C(0x0001000000000000)
1013	/** NEM/Win: Mask. */
1014	#define CPUMCTX_EXTRN_NEM_WIN_MASK UINT64_C(0x0001000000000000)
1015
1016	/** HM/SVM: Nested-guest interrupt pending (VMCPU_FF_INTERRUPT_NESTED_GUEST). */
1017	#define CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ UINT64_C(0x0001000000000000)
1018	/** HM/SVM: Mask. */
1019	#define CPUMCTX_EXTRN_HM_SVM_MASK UINT64_C(0x0001000000000000)
1020
1021	/** All CPUM state bits, not including keeper specific ones. */
1022	#define CPUMCTX_EXTRN_ALL UINT64_C(0x00000ffffffffffc)
1023	/** All CPUM state bits, including keeper specific ones. */
1024	#define CPUMCTX_EXTRN_ABSOLUTELY_ALL UINT64_C(0xfffffffffffffffc)
1025	/** @} */
1026
1027
1028	/**
1029	* Additional guest MSRs (i.e. not part of the CPU context structure).
1030	*
1031	* @remarks Never change the order here because of the saved stated! The size
1032	* can in theory be changed, but keep older VBox versions in mind.
1033	*/
1034	typedef union CPUMCTXMSRS
1035	{
1036	struct
1037	{
1038	uint64_t TscAux; /*< MSR_K8_TSC_AUX /
1039	uint64_t MiscEnable; /*< MSR_IA32_MISC_ENABLE /
1040	uint64_t MtrrDefType; /*< IA32_MTRR_DEF_TYPE /
1041	uint64_t MtrrFix64K_00000; /*< IA32_MTRR_FIX16K_80000 /
1042	uint64_t MtrrFix16K_80000; /*< IA32_MTRR_FIX16K_80000 /
1043	uint64_t MtrrFix16K_A0000; /*< IA32_MTRR_FIX16K_A0000 /
1044	uint64_t MtrrFix4K_C0000; /*< IA32_MTRR_FIX4K_C0000 /
1045	uint64_t MtrrFix4K_C8000; /*< IA32_MTRR_FIX4K_C8000 /
1046	uint64_t MtrrFix4K_D0000; /*< IA32_MTRR_FIX4K_D0000 /
1047	uint64_t MtrrFix4K_D8000; /*< IA32_MTRR_FIX4K_D8000 /
1048	uint64_t MtrrFix4K_E0000; /*< IA32_MTRR_FIX4K_E0000 /
1049	uint64_t MtrrFix4K_E8000; /*< IA32_MTRR_FIX4K_E8000 /
1050	uint64_t MtrrFix4K_F0000; /*< IA32_MTRR_FIX4K_F0000 /
1051	uint64_t MtrrFix4K_F8000; /*< IA32_MTRR_FIX4K_F8000 /
1052	uint64_t PkgCStateCfgCtrl; /*< MSR_PKG_CST_CONFIG_CONTROL /
1053	uint64_t SpecCtrl; /*< IA32_SPEC_CTRL /
1054	uint64_t ArchCaps; /*< IA32_ARCH_CAPABILITIES /
1055	} msr;
1056	uint64_t au64[64];
1057	} CPUMCTXMSRS;
1058	/** Pointer to the guest MSR state. */
1059	typedef CPUMCTXMSRS *PCPUMCTXMSRS;
1060	/** Pointer to the const guest MSR state. */
1061	typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
1062
1063	/** @} */
1064
1065	RT_C_DECLS_END
1066
1067	#endif /* !VBOX_INCLUDED_vmm_cpumctx_h */
1068

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source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 96407

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