VirtualBox

source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 41899

Last change on this file since 41899 was 41899, checked in by vboxsync, 13 years ago

CPUM: Working over the saved state code to put/get structures using field descriptors instead of memory blobs. Found a bustage restoring the 1.6 state wrt hyper state not being subjected to the same restore procedure as the guest one... Probably very relevant since nobody complained.
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File size: 11.5 KB
Line 
1/** @file
2 * CPUM - CPU Monitor(/ Manager), Context Structures.
3 */
4
5/*
6 * Copyright (C) 2006-2012 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_cpumctx_h
27#define ___VBox_vmm_cpumctx_h
28
29#ifndef VBOX_FOR_DTRACE_LIB
30# include <iprt/x86.h>
31#else
32# pragma D depends_on library x86.d
33#endif
34
35
36RT_C_DECLS_BEGIN
37
38/** @addgroup grp_cpum_ctx The CPUM Context Structures
39 * @ingroup grp_cpum
40 * @{
41 */
42
43/**
44 * Selector hidden registers.
45 */
46typedef struct CPUMSELREGHID
47{
48 /** Base register.
49 *
50 * Long mode remarks:
51 * - Unused in long mode for CS, DS, ES, SS
52 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
53 * - 64 bits for TR & LDTR
54 */
55 uint64_t u64Base;
56 /** Limit (expanded). */
57 uint32_t u32Limit;
58 /** Flags.
59 * This is the high 32-bit word of the descriptor entry.
60 * Only the flags, dpl and type are used. */
61 X86DESCATTR Attr;
62} CPUMSELREGHID;
63
64
65/**
66 * The sysenter register set.
67 */
68typedef struct CPUMSYSENTER
69{
70 /** Ring 0 cs.
71 * This value + 8 is the Ring 0 ss.
72 * This value + 16 is the Ring 3 cs.
73 * This value + 24 is the Ring 3 ss.
74 */
75 uint64_t cs;
76 /** Ring 0 eip. */
77 uint64_t eip;
78 /** Ring 0 esp. */
79 uint64_t esp;
80} CPUMSYSENTER;
81
82/**
83 * For compilers (like DTrace) that does not grok nameless unions, we have a
84 * little hack to make them palatable.
85 */
86#ifdef VBOX_FOR_DTRACE_LIB
87# define CPUM_UNION_NAME(a_Nm) a_Nm
88#elif defined(VBOX_WITHOUT_UNNAMED_UNIONS)
89# define CPUM_UNION_NAME(a_Nm) a_Nm
90#else
91# define CPUM_UNION_NAME(a_Nm)
92#endif
93
94
95/**
96 * CPU context core.
97 */
98#pragma pack(1)
99typedef struct CPUMCTXCORE
100{
101 union
102 {
103 uint16_t di;
104 uint32_t edi;
105 uint64_t rdi;
106 } CPUM_UNION_NAME(rdi);
107 union
108 {
109 uint16_t si;
110 uint32_t esi;
111 uint64_t rsi;
112 } CPUM_UNION_NAME(rsi);
113 union
114 {
115 uint16_t bp;
116 uint32_t ebp;
117 uint64_t rbp;
118 } CPUM_UNION_NAME(rbp);
119 union
120 {
121 uint16_t ax;
122 uint32_t eax;
123 uint64_t rax;
124 } CPUM_UNION_NAME(rax);
125 union
126 {
127 uint16_t bx;
128 uint32_t ebx;
129 uint64_t rbx;
130 } CPUM_UNION_NAME(rbx);
131 union
132 {
133 uint16_t dx;
134 uint32_t edx;
135 uint64_t rdx;
136 } CPUM_UNION_NAME(rdx);
137 union
138 {
139 uint16_t cx;
140 uint32_t ecx;
141 uint64_t rcx;
142 } CPUM_UNION_NAME(rcx);
143 union
144 {
145 uint16_t sp;
146 uint32_t esp;
147 uint64_t rsp;
148 } CPUM_UNION_NAME(rsp);
149 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
150 uint32_t lss_esp;
151 RTSEL ss;
152 RTSEL ssPadding;
153
154 RTSEL gs;
155 RTSEL gsPadding;
156 RTSEL fs;
157 RTSEL fsPadding;
158 RTSEL es;
159 RTSEL esPadding;
160 RTSEL ds;
161 RTSEL dsPadding;
162 RTSEL cs;
163 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
164
165 union
166 {
167 X86EFLAGS eflags;
168 X86RFLAGS rflags;
169 } CPUM_UNION_NAME(rflags);
170 union
171 {
172 uint16_t ip;
173 uint32_t eip;
174 uint64_t rip;
175 } CPUM_UNION_NAME(rip);
176
177 uint64_t r8;
178 uint64_t r9;
179 uint64_t r10;
180 uint64_t r11;
181 uint64_t r12;
182 uint64_t r13;
183 uint64_t r14;
184 uint64_t r15;
185
186 /** Hidden selector registers.
187 * @{ */
188 CPUMSELREGHID esHid;
189 CPUMSELREGHID csHid;
190 CPUMSELREGHID ssHid;
191 CPUMSELREGHID dsHid;
192 CPUMSELREGHID fsHid;
193 CPUMSELREGHID gsHid;
194 /** @} */
195
196} CPUMCTXCORE;
197#pragma pack()
198
199
200/**
201 * CPU context.
202 */
203#pragma pack(1)
204typedef struct CPUMCTX
205{
206 /** FPU state. (16-byte alignment)
207 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
208 * actual format or convert it (waste of time). */
209 X86FXSTATE fpu;
210
211 /** CPUMCTXCORE Part.
212 * @{ */
213 union
214 {
215 uint8_t dil;
216 uint16_t di;
217 uint32_t edi;
218 uint64_t rdi;
219 } CPUM_UNION_NAME(rdi);
220 union
221 {
222 uint8_t sil;
223 uint16_t si;
224 uint32_t esi;
225 uint64_t rsi;
226 } CPUM_UNION_NAME(rsi);
227 union
228 {
229 uint16_t bp;
230 uint32_t ebp;
231 uint64_t rbp;
232 } CPUM_UNION_NAME(rbp);
233 union
234 {
235 uint8_t al;
236 uint16_t ax;
237 uint32_t eax;
238 uint64_t rax;
239 } CPUM_UNION_NAME(rax);
240 union
241 {
242 uint8_t bl;
243 uint16_t bx;
244 uint32_t ebx;
245 uint64_t rbx;
246 } CPUM_UNION_NAME(rbx);
247 union
248 {
249 uint8_t dl;
250 uint16_t dx;
251 uint32_t edx;
252 uint64_t rdx;
253 } CPUM_UNION_NAME(rdx);
254 union
255 {
256 uint8_t cl;
257 uint16_t cx;
258 uint32_t ecx;
259 uint64_t rcx;
260 } CPUM_UNION_NAME(rcx);
261 union
262 {
263 uint16_t sp;
264 uint32_t esp;
265 uint64_t rsp;
266 } CPUM_UNION_NAME(rsp);
267 /** @note lss esp, [] in the switcher needs some space, so we reserve it here
268 * instead of relying on the exact esp & ss layout as before (prevented
269 * us from using a union with rsp). */
270 uint32_t lss_esp;
271 RTSEL ss;
272 RTSEL ssPadding;
273
274 RTSEL gs;
275 RTSEL gsPadding;
276 RTSEL fs;
277 RTSEL fsPadding;
278 RTSEL es;
279 RTSEL esPadding;
280 RTSEL ds;
281 RTSEL dsPadding;
282 RTSEL cs;
283 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
284
285 union
286 {
287 X86EFLAGS eflags;
288 X86RFLAGS rflags;
289 } CPUM_UNION_NAME(rflags);
290 union
291 {
292 uint16_t ip;
293 uint32_t eip;
294 uint64_t rip;
295 } CPUM_UNION_NAME(rip);
296
297 uint64_t r8;
298 uint64_t r9;
299 uint64_t r10;
300 uint64_t r11;
301 uint64_t r12;
302 uint64_t r13;
303 uint64_t r14;
304 uint64_t r15;
305
306 /** Hidden selector registers.
307 * @{ */
308 CPUMSELREGHID esHid;
309 CPUMSELREGHID csHid;
310 CPUMSELREGHID ssHid;
311 CPUMSELREGHID dsHid;
312 CPUMSELREGHID fsHid;
313 CPUMSELREGHID gsHid;
314 /** @} */
315
316 /** @} */
317
318 /** Control registers.
319 * @{ */
320 uint64_t cr0;
321 uint64_t cr2;
322 uint64_t cr3;
323 uint64_t cr4;
324 /** @} */
325
326 /** Debug registers.
327 * @remarks DR4 and DR5 should not be used since they are aliases for
328 * DR6 and DR7 respectively on both AMD and Intel CPUs.
329 * @remarks DR8-15 are currently not supported by AMD or Intel, so
330 * neither do we.
331 * @{ */
332 uint64_t dr[8];
333 /** @} */
334
335 /** Global Descriptor Table register. */
336 VBOXGDTR gdtr;
337 uint16_t gdtrPadding;
338 /** Interrupt Descriptor Table register. */
339 VBOXIDTR idtr;
340 uint16_t idtrPadding;
341 /** The task register.
342 * Only the guest context uses all the members. */
343 RTSEL ldtr;
344 RTSEL ldtrPadding;
345 /** The task register.
346 * Only the guest context uses all the members. */
347 RTSEL tr;
348 RTSEL trPadding;
349
350 /** The sysenter msr registers.
351 * This member is not used by the hypervisor context. */
352 CPUMSYSENTER SysEnter;
353
354 /** System MSRs.
355 * @{ */
356 uint64_t msrEFER;
357 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */
358 uint64_t msrPAT;
359 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */
360 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */
361 uint64_t msrSFMASK; /**< syscall flag mask. */
362 uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */
363 /** @} */
364
365 /** Hidden selector registers.
366 * @{ */
367 CPUMSELREGHID ldtrHid;
368 CPUMSELREGHID trHid;
369 /** @} */
370
371#if 0
372 /** Padding to align the size on a 64 byte boundary. */
373 uint32_t padding[6];
374#endif
375} CPUMCTX;
376#pragma pack()
377
378#ifndef VBOX_FOR_DTRACE_LIB
379
380/**
381 * Gets the CPUMCTXCORE part of a CPUMCTX.
382 */
383# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
384
385#endif /* VBOX_FOR_DTRACE_LIB */
386
387/**
388 * Additional guest MSRs (i.e. not part of the CPU context structure).
389 *
390 * @remarks Never change the order here because of the saved stated! The size
391 * can in theory be changed, but keep older VBox versions in mind.
392 */
393typedef union CPUMCTXMSRS
394{
395 struct
396 {
397 uint64_t TscAux; /**< MSR_K8_TSC_AUX */
398 uint64_t MiscEnable; /**< MSR_IA32_MISC_ENABLE */
399 uint64_t MtrrDefType; /**< IA32_MTRR_DEF_TYPE */
400 uint64_t MtrrFix64K_00000; /**< IA32_MTRR_FIX16K_80000 */
401 uint64_t MtrrFix16K_80000; /**< IA32_MTRR_FIX16K_80000 */
402 uint64_t MtrrFix16K_A0000; /**< IA32_MTRR_FIX16K_A0000 */
403 uint64_t MtrrFix4K_C0000; /**< IA32_MTRR_FIX4K_C0000 */
404 uint64_t MtrrFix4K_C8000; /**< IA32_MTRR_FIX4K_C8000 */
405 uint64_t MtrrFix4K_D0000; /**< IA32_MTRR_FIX4K_D0000 */
406 uint64_t MtrrFix4K_D8000; /**< IA32_MTRR_FIX4K_D8000 */
407 uint64_t MtrrFix4K_E0000; /**< IA32_MTRR_FIX4K_E0000 */
408 uint64_t MtrrFix4K_E8000; /**< IA32_MTRR_FIX4K_E8000 */
409 uint64_t MtrrFix4K_F0000; /**< IA32_MTRR_FIX4K_F0000 */
410 uint64_t MtrrFix4K_F8000; /**< IA32_MTRR_FIX4K_F8000 */
411 } msr;
412 uint64_t au64[64];
413} CPUMCTXMSRS;
414/** Pointer to the guest MSR state. */
415typedef CPUMCTXMSRS *PCPUMCTXMSRS;
416/** Pointer to the const guest MSR state. */
417typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
418
419/**
420 * The register set returned by a CPUID operation.
421 */
422typedef struct CPUMCPUID
423{
424 uint32_t eax;
425 uint32_t ebx;
426 uint32_t ecx;
427 uint32_t edx;
428} CPUMCPUID;
429/** Pointer to a CPUID leaf. */
430typedef CPUMCPUID *PCPUMCPUID;
431/** Pointer to a const CPUID leaf. */
432typedef const CPUMCPUID *PCCPUMCPUID;
433
434/** @} */
435
436RT_C_DECLS_END
437
438#endif
439
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