cpumctx.h@ 41247

Last change on this file since 41247 was 41247, checked in by vboxsync, 13 years ago
More dtrace library stuff. On 64-bit solaris dtrace can now grok the library files (point it to them using the -L parameter).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 16.2 KB

Line
1	/** @file
2	* CPUM - CPU Monitor(/ Manager), Context Structures.
3	*/
4
5	/*
6	* Copyright (C) 2006-2012 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_cpumctx_h
27	#define ___VBox_vmm_cpumctx_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/x86.h>
31	#else
32	# pragma D depends_on library x86.d
33	#endif
34
35
36	RT_C_DECLS_BEGIN
37
38	/** @addgroup grp_cpum_ctx The CPUM Context Structures
39	* @ingroup grp_cpum
40	* @{
41	*/
42
43	/**
44	* Selector hidden registers.
45	*/
46	typedef struct CPUMSELREGHID
47	{
48	/** Base register.
49	*
50	* Long mode remarks:
51	* - Unused in long mode for CS, DS, ES, SS
52	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
53	* - 64 bits for TR & LDTR
54	*/
55	uint64_t u64Base;
56	/** Limit (expanded). */
57	uint32_t u32Limit;
58	/** Flags.
59	* This is the high 32-bit word of the descriptor entry.
60	* Only the flags, dpl and type are used. */
61	X86DESCATTR Attr;
62	} CPUMSELREGHID;
63
64
65	/**
66	* The sysenter register set.
67	*/
68	typedef struct CPUMSYSENTER
69	{
70	/** Ring 0 cs.
71	* This value + 8 is the Ring 0 ss.
72	* This value + 16 is the Ring 3 cs.
73	* This value + 24 is the Ring 3 ss.
74	*/
75	uint64_t cs;
76	/** Ring 0 eip. */
77	uint64_t eip;
78	/** Ring 0 esp. */
79	uint64_t esp;
80	} CPUMSYSENTER;
81
82	/**
83	* For compilers (like DTrace) that does not grok nameless unions, we have a
84	* little hack to make them palatable.
85	*/
86	#ifdef VBOX_FOR_DTRACE_LIB
87	# define CPUM_UNION_NAME(a_Nm) a_Nm
88	#elif defined(VBOX_WITHOUT_UNNAMED_UNIONS)
89	# define CPUM_UNION_NAME(a_Nm) a_Nm
90	#else
91	# define CPUM_UNION_NAME(a_Nm)
92	#endif
93
94
95	/**
96	* CPU context core.
97	*/
98	#ifndef VBOX_FOR_DTRACE_LIB
99	# pragma pack(1)
100	#endif
101	typedef struct CPUMCTXCORE
102	{
103	union
104	{
105	uint16_t di;
106	uint32_t edi;
107	uint64_t rdi;
108	} CPUM_UNION_NAME(rdi);
109	union
110	{
111	uint16_t si;
112	uint32_t esi;
113	uint64_t rsi;
114	} CPUM_UNION_NAME(rsi);
115	union
116	{
117	uint16_t bp;
118	uint32_t ebp;
119	uint64_t rbp;
120	} CPUM_UNION_NAME(rbp);
121	union
122	{
123	uint16_t ax;
124	uint32_t eax;
125	uint64_t rax;
126	} CPUM_UNION_NAME(rax);
127	union
128	{
129	uint16_t bx;
130	uint32_t ebx;
131	uint64_t rbx;
132	} CPUM_UNION_NAME(rbx);
133	union
134	{
135	uint16_t dx;
136	uint32_t edx;
137	uint64_t rdx;
138	} CPUM_UNION_NAME(rdx);
139	union
140	{
141	uint16_t cx;
142	uint32_t ecx;
143	uint64_t rcx;
144	} CPUM_UNION_NAME(rcx);
145	union
146	{
147	uint16_t sp;
148	uint32_t esp;
149	uint64_t rsp;
150	} CPUM_UNION_NAME(rsp);
151	/* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
152	uint32_t lss_esp;
153	RTSEL ss;
154	RTSEL ssPadding;
155
156	RTSEL gs;
157	RTSEL gsPadding;
158	RTSEL fs;
159	RTSEL fsPadding;
160	RTSEL es;
161	RTSEL esPadding;
162	RTSEL ds;
163	RTSEL dsPadding;
164	RTSEL cs;
165	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
166
167	union
168	{
169	X86EFLAGS eflags;
170	X86RFLAGS rflags;
171	} CPUM_UNION_NAME(rflags);
172	union
173	{
174	uint16_t ip;
175	uint32_t eip;
176	uint64_t rip;
177	} CPUM_UNION_NAME(rip);
178
179	uint64_t r8;
180	uint64_t r9;
181	uint64_t r10;
182	uint64_t r11;
183	uint64_t r12;
184	uint64_t r13;
185	uint64_t r14;
186	uint64_t r15;
187
188	/** Hidden selector registers.
189	* @{ */
190	CPUMSELREGHID esHid;
191	CPUMSELREGHID csHid;
192	CPUMSELREGHID ssHid;
193	CPUMSELREGHID dsHid;
194	CPUMSELREGHID fsHid;
195	CPUMSELREGHID gsHid;
196	/** @} */
197
198	} CPUMCTXCORE;
199
200	# ifndef VBOX_FOR_DTRACE_LIB
201	# pragma pack()
202	# endif
203
204
205	/**
206	* CPU context.
207	*/
208	#ifndef VBOX_FOR_DTRACE_LIB
209	# pragma pack(1)
210	#endif
211	typedef struct CPUMCTX
212	{
213	/** FPU state. (16-byte alignment)
214	* @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
215	* actual format or convert it (waste of time). */
216	X86FXSTATE fpu;
217
218	/** CPUMCTXCORE Part.
219	* @{ */
220	union
221	{
222	uint8_t dil;
223	uint16_t di;
224	uint32_t edi;
225	uint64_t rdi;
226	} CPUM_UNION_NAME(rdi);
227	union
228	{
229	uint8_t sil;
230	uint16_t si;
231	uint32_t esi;
232	uint64_t rsi;
233	} CPUM_UNION_NAME(rsi);
234	union
235	{
236	uint16_t bp;
237	uint32_t ebp;
238	uint64_t rbp;
239	} CPUM_UNION_NAME(rbp);
240	union
241	{
242	uint8_t al;
243	uint16_t ax;
244	uint32_t eax;
245	uint64_t rax;
246	} CPUM_UNION_NAME(rax);
247	union
248	{
249	uint8_t bl;
250	uint16_t bx;
251	uint32_t ebx;
252	uint64_t rbx;
253	} CPUM_UNION_NAME(rbx);
254	union
255	{
256	uint8_t dl;
257	uint16_t dx;
258	uint32_t edx;
259	uint64_t rdx;
260	} CPUM_UNION_NAME(rdx);
261	union
262	{
263	uint8_t cl;
264	uint16_t cx;
265	uint32_t ecx;
266	uint64_t rcx;
267	} CPUM_UNION_NAME(rcx);
268	union
269	{
270	uint16_t sp;
271	uint32_t esp;
272	uint64_t rsp;
273	} CPUM_UNION_NAME(rsp);
274	/** @note lss esp, [] in the switcher needs some space, so we reserve it here
275	* instead of relying on the exact esp & ss layout as before (prevented
276	* us from using a union with rsp). */
277	uint32_t lss_esp;
278	RTSEL ss;
279	RTSEL ssPadding;
280
281	RTSEL gs;
282	RTSEL gsPadding;
283	RTSEL fs;
284	RTSEL fsPadding;
285	RTSEL es;
286	RTSEL esPadding;
287	RTSEL ds;
288	RTSEL dsPadding;
289	RTSEL cs;
290	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
291
292	union
293	{
294	X86EFLAGS eflags;
295	X86RFLAGS rflags;
296	} CPUM_UNION_NAME(rflags);
297	union
298	{
299	uint16_t ip;
300	uint32_t eip;
301	uint64_t rip;
302	} CPUM_UNION_NAME(rip);
303
304	uint64_t r8;
305	uint64_t r9;
306	uint64_t r10;
307	uint64_t r11;
308	uint64_t r12;
309	uint64_t r13;
310	uint64_t r14;
311	uint64_t r15;
312
313	/** Hidden selector registers.
314	* @{ */
315	CPUMSELREGHID esHid;
316	CPUMSELREGHID csHid;
317	CPUMSELREGHID ssHid;
318	CPUMSELREGHID dsHid;
319	CPUMSELREGHID fsHid;
320	CPUMSELREGHID gsHid;
321	/** @} */
322
323	/** @} */
324
325	/** Control registers.
326	* @{ */
327	uint64_t cr0;
328	uint64_t cr2;
329	uint64_t cr3;
330	uint64_t cr4;
331	/** @} */
332
333	/** Debug registers.
334	* @remarks DR4 and DR5 should not be used since they are aliases for
335	* DR6 and DR7 respectively on both AMD and Intel CPUs.
336	* @remarks DR8-15 are currently not supported by AMD or Intel, so
337	* neither do we.
338	* @{ */
339	uint64_t dr[8];
340	/** @} */
341
342	/** Global Descriptor Table register. */
343	VBOXGDTR gdtr;
344	uint16_t gdtrPadding;
345	/** Interrupt Descriptor Table register. */
346	VBOXIDTR idtr;
347	uint16_t idtrPadding;
348	/** The task register.
349	* Only the guest context uses all the members. */
350	RTSEL ldtr;
351	RTSEL ldtrPadding;
352	/** The task register.
353	* Only the guest context uses all the members. */
354	RTSEL tr;
355	RTSEL trPadding;
356
357	/** The sysenter msr registers.
358	* This member is not used by the hypervisor context. */
359	CPUMSYSENTER SysEnter;
360
361	/** System MSRs.
362	* @{ */
363	uint64_t msrEFER;
364	uint64_t msrSTAR; /*< Legacy syscall eip, cs & ss. /
365	uint64_t msrPAT;
366	uint64_t msrLSTAR; /*< 64 bits mode syscall rip. /
367	uint64_t msrCSTAR; /*< Compatibility mode syscall rip. /
368	uint64_t msrSFMASK; /*< syscall flag mask. /
369	uint64_t msrKERNELGSBASE; /*< swapgs exchange value. /
370	/** @} */
371
372	/** Hidden selector registers.
373	* @{ */
374	CPUMSELREGHID ldtrHid;
375	CPUMSELREGHID trHid;
376	/** @} */
377
378	# if 0
379	/** Padding to align the size on a 64 byte boundary. */
380	uint32_t padding[6];
381	# endif
382	} CPUMCTX;
383	# ifndef VBOX_FOR_DTRACE_LIB
384	# pragma pack()
385	# endif
386
387	#ifndef VBOX_FOR_DTRACE_LIB
388
389	/**
390	* Gets the CPUMCTXCORE part of a CPUMCTX.
391	*/
392	# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
393
394
395	/**
396	* Selector hidden registers, for version 1.6 saved state.
397	*/
398	typedef struct CPUMSELREGHID_VER1_6
399	{
400	/** Base register. */
401	uint32_t u32Base;
402	/** Limit (expanded). */
403	uint32_t u32Limit;
404	/** Flags.
405	* This is the high 32-bit word of the descriptor entry.
406	* Only the flags, dpl and type are used. */
407	X86DESCATTR Attr;
408	} CPUMSELREGHID_VER1_6;
409
410	/**
411	* CPU context, for version 1.6 saved state.
412	* @remarks PATM uses this, which is why it has to be here.
413	*/
414	# pragma pack(1)
415	typedef struct CPUMCTX_VER1_6
416	{
417	/** FPU state. (16-byte alignment)
418	* @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
419	* actual format or convert it (waste of time). */
420	X86FXSTATE fpu;
421
422	/** CPUMCTXCORE Part.
423	* @{ */
424	union
425	{
426	uint32_t edi;
427	uint64_t rdi;
428	} CPUM_UNION_NAME(rdi);
429	union
430	{
431	uint32_t esi;
432	uint64_t rsi;
433	} CPUM_UNION_NAME(rsi);
434	union
435	{
436	uint32_t ebp;
437	uint64_t rbp;
438	} CPUM_UNION_NAME(rbp);
439	union
440	{
441	uint32_t eax;
442	uint64_t rax;
443	} CPUM_UNION_NAME(rax);
444	union
445	{
446	uint32_t ebx;
447	uint64_t rbx;
448	} CPUM_UNION_NAME(rbx);
449	union
450	{
451	uint32_t edx;
452	uint64_t rdx;
453	} CPUM_UNION_NAME(rdx);
454	union
455	{
456	uint32_t ecx;
457	uint64_t rcx;
458	} CPUM_UNION_NAME(rcx);
459	/** @note We rely on the exact layout, because we use lss esp, [] in the
460	* switcher. */
461	uint32_t esp;
462	RTSEL ss;
463	RTSEL ssPadding;
464	/* Note: no overlap with esp here. */
465	uint64_t rsp_notused;
466
467	RTSEL gs;
468	RTSEL gsPadding;
469	RTSEL fs;
470	RTSEL fsPadding;
471	RTSEL es;
472	RTSEL esPadding;
473	RTSEL ds;
474	RTSEL dsPadding;
475	RTSEL cs;
476	RTSEL csPadding[3]; /*< 3 words to force 8 byte alignment for the remainder. /
477
478	union
479	{
480	X86EFLAGS eflags;
481	X86RFLAGS rflags;
482	} CPUM_UNION_NAME(rflags);
483	union
484	{
485	uint32_t eip;
486	uint64_t rip;
487	} CPUM_UNION_NAME(rip);
488
489	uint64_t r8;
490	uint64_t r9;
491	uint64_t r10;
492	uint64_t r11;
493	uint64_t r12;
494	uint64_t r13;
495	uint64_t r14;
496	uint64_t r15;
497
498	/** Hidden selector registers.
499	* @{ */
500	CPUMSELREGHID_VER1_6 esHid;
501	CPUMSELREGHID_VER1_6 csHid;
502	CPUMSELREGHID_VER1_6 ssHid;
503	CPUMSELREGHID_VER1_6 dsHid;
504	CPUMSELREGHID_VER1_6 fsHid;
505	CPUMSELREGHID_VER1_6 gsHid;
506	/** @} */
507
508	/** @} */
509
510	/** Control registers.
511	* @{ */
512	uint64_t cr0;
513	uint64_t cr2;
514	uint64_t cr3;
515	uint64_t cr4;
516	uint64_t cr8;
517	/** @} */
518
519	/** Debug registers.
520	* @{ */
521	uint64_t dr0;
522	uint64_t dr1;
523	uint64_t dr2;
524	uint64_t dr3;
525	uint64_t dr4; /*< @todo remove dr4 and dr5. /
526	uint64_t dr5;
527	uint64_t dr6;
528	uint64_t dr7;
529	/* DR8-15 are currently not supported */
530	/** @} */
531
532	/** Global Descriptor Table register. */
533	VBOXGDTR_VER1_6 gdtr;
534	uint16_t gdtrPadding;
535	uint32_t gdtrPadding64;/** @todo fix this hack */
536	/** Interrupt Descriptor Table register. */
537	VBOXIDTR_VER1_6 idtr;
538	uint16_t idtrPadding;
539	uint32_t idtrPadding64;/** @todo fix this hack */
540	/** The task register.
541	* Only the guest context uses all the members. */
542	RTSEL ldtr;
543	RTSEL ldtrPadding;
544	/** The task register.
545	* Only the guest context uses all the members. */
546	RTSEL tr;
547	RTSEL trPadding;
548
549	/** The sysenter msr registers.
550	* This member is not used by the hypervisor context. */
551	CPUMSYSENTER SysEnter;
552
553	/** System MSRs.
554	* @{ */
555	uint64_t msrEFER;
556	uint64_t msrSTAR;
557	uint64_t msrPAT;
558	uint64_t msrLSTAR;
559	uint64_t msrCSTAR;
560	uint64_t msrSFMASK;
561	uint64_t msrFSBASE;
562	uint64_t msrGSBASE;
563	uint64_t msrKERNELGSBASE;
564	/** @} */
565
566	/** Hidden selector registers.
567	* @{ */
568	CPUMSELREGHID_VER1_6 ldtrHid;
569	CPUMSELREGHID_VER1_6 trHid;
570	/** @} */
571
572	/** padding to get 32byte aligned size. */
573	uint32_t padding[2];
574	} CPUMCTX_VER1_6;
575	# pragma pack()
576
577	#endif /* VBOX_FOR_DTRACE_LIB */
578
579	/**
580	* Additional guest MSRs (i.e. not part of the CPU context structure).
581	*
582	* @remarks Never change the order here because of the saved stated! The size
583	* can in theory be changed, but keep older VBox versions in mind.
584	*/
585	typedef union CPUMCTXMSRS
586	{
587	struct
588	{
589	uint64_t TscAux; /*< MSR_K8_TSC_AUX /
590	uint64_t MiscEnable; /*< MSR_IA32_MISC_ENABLE /
591	uint64_t MtrrDefType; /*< IA32_MTRR_DEF_TYPE /
592	uint64_t MtrrFix64K_00000; /*< IA32_MTRR_FIX16K_80000 /
593	uint64_t MtrrFix16K_80000; /*< IA32_MTRR_FIX16K_80000 /
594	uint64_t MtrrFix16K_A0000; /*< IA32_MTRR_FIX16K_A0000 /
595	uint64_t MtrrFix4K_C0000; /*< IA32_MTRR_FIX4K_C0000 /
596	uint64_t MtrrFix4K_C8000; /*< IA32_MTRR_FIX4K_C8000 /
597	uint64_t MtrrFix4K_D0000; /*< IA32_MTRR_FIX4K_D0000 /
598	uint64_t MtrrFix4K_D8000; /*< IA32_MTRR_FIX4K_D8000 /
599	uint64_t MtrrFix4K_E0000; /*< IA32_MTRR_FIX4K_E0000 /
600	uint64_t MtrrFix4K_E8000; /*< IA32_MTRR_FIX4K_E8000 /
601	uint64_t MtrrFix4K_F0000; /*< IA32_MTRR_FIX4K_F0000 /
602	uint64_t MtrrFix4K_F8000; /*< IA32_MTRR_FIX4K_F8000 /
603	} msr;
604	uint64_t au64[64];
605	} CPUMCTXMSRS;
606	/** Pointer to the guest MSR state. */
607	typedef CPUMCTXMSRS *PCPUMCTXMSRS;
608	/** Pointer to the const guest MSR state. */
609	typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
610
611	/**
612	* The register set returned by a CPUID operation.
613	*/
614	typedef struct CPUMCPUID
615	{
616	uint32_t eax;
617	uint32_t ebx;
618	uint32_t ecx;
619	uint32_t edx;
620	} CPUMCPUID;
621	/** Pointer to a CPUID leaf. */
622	typedef CPUMCPUID *PCPUMCPUID;
623	/** Pointer to a const CPUID leaf. */
624	typedef const CPUMCPUID *PCCPUMCPUID;
625
626	/** @} */
627
628	RT_C_DECLS_END
629
630	#endif
631

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 41247

Download in other formats: