cpumctx-x86-amd64.h

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1	/** @file
2	* CPUM - CPU Monitor(/ Manager), Context Structures for the x86/amd64 emulation/virtualization.
3	*/
4
5	/*
6	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpumctx_x86_amd64_h
37	#define VBOX_INCLUDED_vmm_cpumctx_x86_amd64_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/x86.h>
44	# include <VBox/types.h>
45	# include <VBox/vmm/hm_svm.h>
46	# include <VBox/vmm/hm_vmx.h>
47	#else
48	# pragma D depends_on library x86.d
49	#endif
50
51
52	RT_C_DECLS_BEGIN
53
54	/** @defgroup grp_cpum_ctx The CPUM Context Structures
55	* @ingroup grp_cpum
56	* @{
57	*/
58
59	/**
60	* Selector hidden registers.
61	*/
62	typedef struct CPUMSELREG
63	{
64	/** The selector register. */
65	RTSEL Sel;
66	/** Padding, don't use. */
67	RTSEL PaddingSel;
68	/** The selector which info resides in u64Base, u32Limit and Attr, provided
69	* that CPUMSELREG_FLAGS_VALID is set. */
70	RTSEL ValidSel;
71	/** Flags, see CPUMSELREG_FLAGS_XXX. */
72	uint16_t fFlags;
73
74	/** Base register.
75	*
76	* Long mode remarks:
77	* - Unused in long mode for CS, DS, ES, SS
78	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
79	* - 64 bits for TR & LDTR
80	*/
81	uint64_t u64Base;
82	/** Limit (expanded). */
83	uint32_t u32Limit;
84	/** Flags.
85	* This is the high 32-bit word of the descriptor entry.
86	* Only the flags, dpl and type are used. */
87	X86DESCATTR Attr;
88	} CPUMSELREG;
89	#ifndef VBOX_FOR_DTRACE_LIB
90	AssertCompileSize(CPUMSELREG, 24);
91	#endif
92
93	/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
94	* @{ */
95	#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
96	#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
97	#define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
98	/** @} */
99
100	/** Checks if the hidden parts of the selector register are valid. */
101	#define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
102	( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
103	&& (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
104
105	/** Old type used for the hidden register part.
106	* @deprecated */
107	typedef CPUMSELREG CPUMSELREGHID;
108
109	/**
110	* The sysenter register set.
111	*/
112	typedef struct CPUMSYSENTER
113	{
114	/** Ring 0 cs.
115	* This value + 8 is the Ring 0 ss.
116	* This value + 16 is the Ring 3 cs.
117	* This value + 24 is the Ring 3 ss.
118	*/
119	uint64_t cs;
120	/** Ring 0 eip. */
121	uint64_t eip;
122	/** Ring 0 esp. */
123	uint64_t esp;
124	} CPUMSYSENTER;
125
126	/** A general register (union). */
127	typedef union CPUMCTXGREG
128	{
129	/** Natural unsigned integer view. */
130	uint64_t u;
131	/** 64-bit view. */
132	uint64_t u64;
133	/** 32-bit view. */
134	uint32_t u32;
135	/** 16-bit view. */
136	uint16_t u16;
137	/** 8-bit view. */
138	uint8_t u8;
139	/** 8-bit low/high view. */
140	RT_GCC_EXTENSION struct
141	{
142	/** Low byte (al, cl, dl, bl, ++). */
143	uint8_t bLo;
144	/** High byte in the first word - ah, ch, dh, bh. */
145	uint8_t bHi;
146	} CPUM_STRUCT_NM(s);
147	} CPUMCTXGREG;
148	#ifndef VBOX_FOR_DTRACE_LIB
149	AssertCompileSize(CPUMCTXGREG, 8);
150	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
151	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
152	#endif
153
154
155
156	/**
157	* SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
158	*
159	* @warning Exercise caution while modifying the layout of this struct. It's
160	* part of VM saved states.
161	*/
162	#pragma pack(1)
163	typedef struct SVMHOSTSTATE
164	{
165	uint64_t uEferMsr;
166	uint64_t uCr0;
167	uint64_t uCr4;
168	uint64_t uCr3;
169	uint64_t uRip;
170	uint64_t uRsp;
171	uint64_t uRax;
172	X86RFLAGS rflags;
173	CPUMSELREG es;
174	CPUMSELREG cs;
175	CPUMSELREG ss;
176	CPUMSELREG ds;
177	VBOXGDTR gdtr;
178	VBOXIDTR idtr;
179	uint8_t abPadding[4];
180	} SVMHOSTSTATE;
181	#pragma pack()
182	/** Pointer to the SVMHOSTSTATE structure. */
183	typedef SVMHOSTSTATE *PSVMHOSTSTATE;
184	/** Pointer to a const SVMHOSTSTATE structure. */
185	typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
186	#ifndef VBOX_FOR_DTRACE_LIB
187	AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
188	AssertCompileSize(SVMHOSTSTATE, 184);
189	#endif
190
191
192	/**
193	* CPU hardware virtualization types.
194	*/
195	typedef enum
196	{
197	CPUMHWVIRT_NONE = 0,
198	CPUMHWVIRT_VMX,
199	CPUMHWVIRT_SVM,
200	CPUMHWVIRT_32BIT_HACK = 0x7fffffff
201	} CPUMHWVIRT;
202	#ifndef VBOX_FOR_DTRACE_LIB
203	AssertCompileSize(CPUMHWVIRT, 4);
204	#endif
205
206	/** Number of EFLAGS bits we put aside for the hardware EFLAGS, with the bits
207	* above this we use for storing internal state not visible to the guest.
208	*
209	* Using a value less than 32 here means some code bloat when loading and
210	* fetching the hardware EFLAGS value. Comparing VMMR0.r0 text size when
211	* compiling release build using gcc 11.3.1 on linux:
212	* - 32 bits: 2475709 bytes
213	* - 24 bits: 2482069 bytes; +6360 bytes.
214	* - 22 bits: 2482261 bytes; +6552 bytes.
215	* Same for windows (virtual size of .text):
216	* - 32 bits: 1498502 bytes
217	* - 24 bits: 1502278 bytes; +3776 bytes.
218	* - 22 bits: 1502198 bytes; +3696 bytes.
219	*
220	* In addition we pass pointer the 32-bit EFLAGS to a number of IEM assembly
221	* functions, so it would be safer to not store anything in the lower 32 bits.
222	* OTOH, we'd sooner discover buggy assembly code by doing so, as we've had one
223	* example of accidental EFLAGS trashing by these functions already.
224	*
225	* It would be more efficient for IEM to store the interrupt shadow bit (and
226	* anything else that needs to be cleared at the same time) in the 30:22 bit
227	* range, because that would allow using a simple AND imm32 instruction on x86
228	* and a MOVN imm16,16 instruction to load the constant on ARM64 (assuming the
229	* other flag needing clearing is RF (bit 16)). Putting it in the 63:32 range
230	* means we that on x86 we'll either use a memory variant of AND or require a
231	* separate load instruction for the immediate, whereas on ARM we'll need more
232	* instructions to construct the immediate value.
233	*
234	* Comparing the instruction exit thruput via the bs2-test-1 testcase, there
235	* seems to be little difference between 32 and 24 here (best results out of 9
236	* runs on Linux/VT-x). So, unless the results are really wrong and there is
237	* clear drop in thruput, it would on the whole make the most sense to use 24
238	* here.
239	*
240	* Update: We need more than 8 bits because of DBGF, so using 22 now.
241	*/
242	#define CPUMX86EFLAGS_HW_BITS 22
243	/** Mask for the hardware EFLAGS bits, 64-bit version. */
244	#define CPUMX86EFLAGS_HW_MASK_64 (RT_BIT_64(CPUMX86EFLAGS_HW_BITS) - UINT64_C(1))
245	/** Mask for the hardware EFLAGS bits, 32-bit version. */
246	#if CPUMX86EFLAGS_HW_BITS == 32
247	# define CPUMX86EFLAGS_HW_MASK_32 UINT32_MAX
248	#elif CPUMX86EFLAGS_HW_BITS < 32 && CPUMX86EFLAGS_HW_BITS >= 22
249	# define CPUMX86EFLAGS_HW_MASK_32 (RT_BIT_32(CPUMX86EFLAGS_HW_BITS) - UINT32_C(1))
250	#else
251	# error "Misconfigured CPUMX86EFLAGS_HW_BITS value!"
252	#endif
253
254	/** Mask of internal flags kept with EFLAGS, 64-bit version.
255	* Bits 22-24 are taken by CPUMCTX_INHIBIT_SHADOW_SS, CPUMCTX_INHIBIT_SHADOW_STI
256	* and CPUMCTX_INHIBIT_NMI, bits 25-28 are for CPUMCTX_DBG_HIT_DRX_MASK, and
257	* bits 29-30 are for DBGF events and breakpoints.
258	*
259	* @todo The two DBGF bits could be merged. The NMI inhibiting could move to
260	* bit 32 or higher as it isn't automatically cleared on instruction
261	* completion (except for iret).
262	*/
263	#define CPUMX86EFLAGS_INT_MASK_64 UINT64_C(0x00000000ffc00000)
264	/** Mask of internal flags kept with EFLAGS, 32-bit version. */
265	#define CPUMX86EFLAGS_INT_MASK_32 UINT32_C(0xffc00000)
266
267
268	/**
269	* CPUM EFLAGS.
270	*
271	* This differs from X86EFLAGS in that we could use bits 31:22 for internal
272	* purposes, see CPUMX86EFLAGS_HW_BITS.
273	*/
274	typedef union CPUMX86EFLAGS
275	{
276	/** The full unsigned view, both hardware and VBox bits. */
277	uint32_t uBoth;
278	/** The plain unsigned view of the hardware bits. */
279	#if CPUMX86EFLAGS_HW_BITS == 32
280	uint32_t u;
281	#else
282	uint32_t u : CPUMX86EFLAGS_HW_BITS;
283	#endif
284	#ifndef VBOX_FOR_DTRACE_LIB
285	/** The bitfield view. */
286	X86EFLAGSBITS Bits;
287	#endif
288	} CPUMX86EFLAGS;
289	/** Pointer to CPUM EFLAGS. */
290	typedef CPUMX86EFLAGS *PCPUMX86EFLAGS;
291	/** Pointer to const CPUM EFLAGS. */
292	typedef const CPUMX86EFLAGS *PCCPUMX86EFLAGS;
293
294	/**
295	* CPUM RFLAGS.
296	*
297	* This differs from X86EFLAGS in that we use could be using bits 63:22 for
298	* internal purposes, see CPUMX86EFLAGS_HW_BITS.
299	*/
300	typedef union CPUMX86RFLAGS
301	{
302	/** The full unsigned view, both hardware and VBox bits. */
303	uint64_t uBoth;
304	/** The plain unsigned view of the hardware bits. */
305	#if CPUMX86EFLAGS_HW_BITS == 32
306	uint32_t u;
307	#else
308	uint32_t u : CPUMX86EFLAGS_HW_BITS;
309	#endif
310	#ifndef VBOX_FOR_DTRACE_LIB
311	/** The bitfield view. */
312	X86EFLAGSBITS Bits;
313	#endif
314	} CPUMX86RFLAGS;
315	/** Pointer to CPUM RFLAGS. */
316	typedef CPUMX86RFLAGS *PCPUMX86RFLAGS;
317	/** Pointer to const CPUM RFLAGS. */
318	typedef const CPUMX86RFLAGS *PCCPUMX86RFLAGS;
319
320
321	/**
322	* CPU context.
323	*/
324	#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
325	typedef struct CPUMCTX
326	{
327	/** 0x0000 - General purpose registers. */
328	union /* no tag! */
329	{
330	/** The general purpose register array view, indexed by X86_GREG_XXX. */
331	CPUMCTXGREG aGRegs[16];
332
333	/** 64-bit general purpose register view. */
334	RT_GCC_EXTENSION struct /* no tag! */
335	{
336	uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
337	} CPUM_STRUCT_NM(qw);
338	/** 64-bit general purpose register view. */
339	RT_GCC_EXTENSION struct /* no tag! */
340	{
341	uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
342	} CPUM_STRUCT_NM(qw2);
343	/** 32-bit general purpose register view. */
344	RT_GCC_EXTENSION struct /* no tag! */
345	{
346	uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
347	esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
348	r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
349	r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
350	} CPUM_STRUCT_NM(dw);
351	/** 16-bit general purpose register view. */
352	RT_GCC_EXTENSION struct /* no tag! */
353	{
354	uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
355	sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
356	r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
357	r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
358	} CPUM_STRUCT_NM(w);
359	RT_GCC_EXTENSION struct /* no tag! */
360	{
361	uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
362	spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
363	r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
364	r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
365	} CPUM_STRUCT_NM(b);
366	} CPUM_UNION_NM(g);
367
368	/** 0x0080 - Segment registers. */
369	union /* no tag! */
370	{
371	/** The segment register array view, indexed by X86_SREG_XXX. */
372	CPUMSELREG aSRegs[6];
373	/** The named segment register view. */
374	RT_GCC_EXTENSION struct /* no tag! */
375	{
376	CPUMSELREG es, cs, ss, ds, fs, gs;
377	} CPUM_STRUCT_NM(n);
378	} CPUM_UNION_NM(s);
379
380	/** 0x0110 - The task register.
381	* Only the guest context uses all the members. */
382	CPUMSELREG ldtr;
383	/** 0x0128 - The task register.
384	* Only the guest context uses all the members. */
385	CPUMSELREG tr;
386
387	/** 0x0140 - The program counter. */
388	union
389	{
390	uint16_t ip;
391	uint32_t eip;
392	uint64_t rip;
393	} CPUM_UNION_NM(rip);
394
395	/** 0x0148 - The flags register. */
396	union
397	{
398	CPUMX86EFLAGS eflags;
399	CPUMX86RFLAGS rflags;
400	} CPUM_UNION_NM(rflags);
401
402	/** 0x0150 - Externalized state tracker, CPUMCTX_EXTRN_XXX. */
403	uint64_t fExtrn;
404
405	/** 0x0158 The RIP value an interrupt shadow is/was valid for. */
406	uint64_t uRipInhibitInt;
407
408	/** @name Control registers.
409	* @{ */
410	uint64_t cr0; /*< 0x0160 /
411	uint64_t cr2; /*< 0x0168 /
412	uint64_t cr3; /*< 0x0170 /
413	uint64_t cr4; /*< 0x0178 /
414	/** @} */
415
416	/** 0x0180 - Debug registers.
417	* @remarks DR4 and DR5 should not be used since they are aliases for
418	* DR6 and DR7 respectively on both AMD and Intel CPUs.
419	* @remarks DR8-15 are currently not supported by AMD or Intel, so
420	* neither do we.
421	*/
422	uint64_t dr[8];
423
424	/** 0x01c0 - Padding before the structure so the 64-bit member is correctly aligned.
425	* @todo fix this structure! */
426	uint16_t gdtrPadding[3];
427	/** Global Descriptor Table register. */
428	VBOXGDTR gdtr;
429
430	/** 0x01d0 - Padding before the structure so the 64-bit member is correctly aligned.
431	* @todo fix this structure! */
432	uint16_t idtrPadding[3];
433	/** Interrupt Descriptor Table register. */
434	VBOXIDTR idtr;
435
436	/** 0x01e0 - The sysenter msr registers.
437	* This member is not used by the hypervisor context. */
438	CPUMSYSENTER SysEnter;
439
440	/** @name System MSRs.
441	* @{ */
442	uint64_t msrEFER; /*< 0x01f8 - @todo move EFER up to the crX registers for better cacheline mojo /
443	uint64_t msrSTAR; /*< 0x0200 - Legacy syscall eip, cs & ss. /
444	uint64_t msrPAT; /*< 0x0208 - Page attribute table. /
445	uint64_t msrLSTAR; /*< 0x0210 - 64 bits mode syscall rip. /
446	uint64_t msrCSTAR; /*< 0x0218 - Compatibility mode syscall rip. /
447	uint64_t msrSFMASK; /*< 0x0220 - syscall flag mask. /
448	uint64_t msrKERNELGSBASE; /*< 0x0228 - swapgs exchange value. /
449	/** @} */
450
451	uint64_t au64Unused[2]; /*< 0x0230 /
452
453	/** 0x240 - PAE PDPTEs. */
454	X86PDPE aPaePdpes[4];
455
456	/** 0x260 - The XCR0..XCR1 registers. */
457	uint64_t aXcr[2];
458	/** 0x270 - The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
459	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
460	uint64_t fXStateMask;
461	/** 0x278 - Mirror of CPUMCPU::fUseFlags[CPUM_USED_FPU_GUEST]. */
462	bool fUsedFpuGuest;
463	uint8_t afUnused[7];
464
465	/* ---- Start of members not zeroed at reset. ---- */
466
467	/** 0x280 - State component offsets into pXState, UINT16_MAX if not present.
468	* @note Everything before this member will be memset to zero during reset. */
469	uint16_t aoffXState[64];
470	/** 0x300 - The extended state (FPU/SSE/AVX/AVX-2/XXXX).
471	* Aligned on 256 byte boundrary (min req is currently 64 bytes). */
472	union /* no tag */
473	{
474	X86XSAVEAREA XState;
475	/** Byte view for simple indexing and space allocation. */
476	uint8_t abXState[0x4000 - 0x300];
477	} CPUM_UNION_NM(u);
478
479	/** 0x4000 - Hardware virtualization state.
480	* @note This is page aligned, so an full page member comes first in the
481	* substructures. */
482	struct
483	{
484	union /* no tag! */
485	{
486	struct
487	{
488	/** 0x4000 - Cache of the nested-guest VMCB. */
489	SVMVMCB Vmcb;
490	/** 0x5000 - The MSRPM (MSR Permission bitmap).
491	*
492	* This need not be physically contiguous pages because we use the one from
493	* HMPHYSCPU while executing the nested-guest using hardware-assisted SVM.
494	* This one is just used for caching the bitmap from guest physical memory.
495	*
496	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
497	* really need to even be page aligned.
498	*
499	* Also, couldn't we just access the guest page directly when we need to,
500	* or do we have to use a cached copy of it? */
501	uint8_t abMsrBitmap[SVM_MSRPM_PAGES * X86_PAGE_SIZE];
502	/** 0x7000 - The IOPM (IO Permission bitmap).
503	*
504	* This need not be physically contiguous pages because we re-use the ring-0
505	* allocated IOPM while executing the nested-guest using hardware-assisted SVM
506	* because it's identical (we trap all IO accesses).
507	*
508	* This one is just used for caching the IOPM from guest physical memory in
509	* case the guest hypervisor allows direct access to some IO ports.
510	*
511	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
512	* really need to even be page aligned.
513	*
514	* Also, couldn't we just access the guest page directly when we need to,
515	* or do we have to use a cached copy of it? */
516	uint8_t abIoBitmap[SVM_IOPM_PAGES * X86_PAGE_SIZE];
517
518	/** 0xa000 - MSR holding physical address of the Guest's Host-state. */
519	uint64_t uMsrHSavePa;
520	/** 0xa008 - Guest physical address of the nested-guest VMCB. */
521	RTGCPHYS GCPhysVmcb;
522	/** 0xa010 - Guest's host-state save area. */
523	SVMHOSTSTATE HostState;
524	/** 0xa0c8 - Guest TSC time-stamp of when the previous PAUSE instr. was
525	* executed. */
526	uint64_t uPrevPauseTick;
527	/** 0xa0d0 - Pause filter count. */
528	uint16_t cPauseFilter;
529	/** 0xa0d2 - Pause filter threshold. */
530	uint16_t cPauseFilterThreshold;
531	/** 0xa0d4 - Whether the injected event is subject to event intercepts. */
532	bool fInterceptEvents;
533	/** 0xa0d5 - Padding. */
534	bool afPadding[3];
535	} svm;
536
537	struct
538	{
539	/** 0x4000 - The current VMCS. */
540	VMXVVMCS Vmcs;
541	/** 0X5000 - The shadow VMCS. */
542	VMXVVMCS ShadowVmcs;
543	/** 0x6000 - The VMREAD bitmap.
544	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
545	* access the guest memory directly as needed? */
546	uint8_t abVmreadBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
547	/** 0x7000 - The VMWRITE bitmap.
548	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
549	* access the guest memory directly as needed? */
550	uint8_t abVmwriteBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
551	/** 0x8000 - The VM-entry MSR-load area. */
552	VMXAUTOMSR aEntryMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
553	/** 0xa000 - The VM-exit MSR-store area. */
554	VMXAUTOMSR aExitMsrStoreArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
555	/** 0xc000 - The VM-exit MSR-load area. */
556	VMXAUTOMSR aExitMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
557	/** 0xe000 - The MSR permission bitmap.
558	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
559	* access the guest memory directly as needed? */
560	uint8_t abMsrBitmap[VMX_V_MSR_BITMAP_SIZE];
561	/** 0xf000 - The I/O permission bitmap.
562	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
563	* access the guest memory directly as needed? */
564	uint8_t abIoBitmap[VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE];
565
566	/** 0x11000 - Guest physical address of the VMXON region. */
567	RTGCPHYS GCPhysVmxon;
568	/** 0x11008 - Guest physical address of the current VMCS pointer. */
569	RTGCPHYS GCPhysVmcs;
570	/** 0x11010 - Guest physical address of the shadow VMCS pointer. */
571	RTGCPHYS GCPhysShadowVmcs;
572	/** 0x11018 - Last emulated VMX instruction/VM-exit diagnostic. */
573	VMXVDIAG enmDiag;
574	/** 0x1101c - VMX abort reason. */
575	VMXABORT enmAbort;
576	/** 0x11020 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info.
577	* (mainly used for info. that's not part of the VMCS). */
578	uint64_t uDiagAux;
579	/** 0x11028 - VMX abort auxiliary info. */
580	uint32_t uAbortAux;
581	/** 0x1102c - Whether the guest is in VMX root mode. */
582	bool fInVmxRootMode;
583	/** 0x1102d - Whether the guest is in VMX non-root mode. */
584	bool fInVmxNonRootMode;
585	/** 0x1102e - Whether the injected events are subjected to event intercepts. */
586	bool fInterceptEvents;
587	/** 0x1102f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX
588	* non-root mode before execution of IRET. */
589	bool fNmiUnblockingIret;
590	/** 0x11030 - Guest TSC timestamp of the first PAUSE instruction that is
591	* considered to be the first in a loop. */
592	uint64_t uFirstPauseLoopTick;
593	/** 0x11038 - Guest TSC timestamp of the previous PAUSE instruction. */
594	uint64_t uPrevPauseTick;
595	/** 0x11040 - Guest TSC timestamp of VM-entry (used for VMX-preemption
596	* timer). */
597	uint64_t uEntryTick;
598	/** 0x11048 - Virtual-APIC write offset (until trap-like VM-exit). */
599	uint16_t offVirtApicWrite;
600	/** 0x1104a - Whether virtual-NMI blocking is in effect. */
601	bool fVirtNmiBlocking;
602	/** 0x1104b - Padding. */
603	uint8_t abPadding0[5];
604	/** 0x11050 - Guest VMX MSRs. */
605	VMXMSRS Msrs;
606	} vmx;
607	} CPUM_UNION_NM(s);
608
609	/** 0x11130 - Hardware virtualization type currently in use. */
610	CPUMHWVIRT enmHwvirt;
611	/** 0x11134 - Global interrupt flag - AMD only (always true on Intel). */
612	bool fGif;
613	/** 0x11135 - Padding. */
614	bool afPadding0[3];
615	/** 0x11138 - A subset of guest inhibit flags (CPUMCTX_INHIBIT_XXX) that are
616	* saved while running the nested-guest. */
617	uint32_t fSavedInhibit;
618	/** 0x1113c - Pad to 64 byte boundary. */
619	uint8_t abPadding1[4];
620	} hwvirt;
621	} CPUMCTX;
622	#pragma pack()
623
624	#ifndef VBOX_FOR_DTRACE_LIB
625	AssertCompileSizeAlignment(CPUMCTX, 64);
626	AssertCompileSizeAlignment(CPUMCTX, 32);
627	AssertCompileSizeAlignment(CPUMCTX, 16);
628	AssertCompileSizeAlignment(CPUMCTX, 8);
629	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0x0000);
630	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 0x0008);
631	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 0x0010);
632	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 0x0018);
633	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 0x0020);
634	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 0x0028);
635	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 0x0030);
636	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 0x0038);
637	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 0x0040);
638	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 0x0048);
639	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 0x0050);
640	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 0x0058);
641	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 0x0060);
642	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 0x0068);
643	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 0x0070);
644	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 0x0078);
645	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 0x0080);
646	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 0x0098);
647	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 0x00b0);
648	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 0x00c8);
649	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 0x00e0);
650	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 0x00f8);
651	AssertCompileMemberOffset(CPUMCTX, ldtr, 0x0110);
652	AssertCompileMemberOffset(CPUMCTX, tr, 0x0128);
653	AssertCompileMemberOffset(CPUMCTX, rip, 0x0140);
654	AssertCompileMemberOffset(CPUMCTX, rflags, 0x0148);
655	AssertCompileMemberOffset(CPUMCTX, fExtrn, 0x0150);
656	AssertCompileMemberOffset(CPUMCTX, uRipInhibitInt, 0x0158);
657	AssertCompileMemberOffset(CPUMCTX, cr0, 0x0160);
658	AssertCompileMemberOffset(CPUMCTX, cr2, 0x0168);
659	AssertCompileMemberOffset(CPUMCTX, cr3, 0x0170);
660	AssertCompileMemberOffset(CPUMCTX, cr4, 0x0178);
661	AssertCompileMemberOffset(CPUMCTX, dr, 0x0180);
662	AssertCompileMemberOffset(CPUMCTX, gdtr, 0x01c0+6);
663	AssertCompileMemberOffset(CPUMCTX, idtr, 0x01d0+6);
664	AssertCompileMemberOffset(CPUMCTX, SysEnter, 0x01e0);
665	AssertCompileMemberOffset(CPUMCTX, msrEFER, 0x01f8);
666	AssertCompileMemberOffset(CPUMCTX, msrSTAR, 0x0200);
667	AssertCompileMemberOffset(CPUMCTX, msrPAT, 0x0208);
668	AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 0x0210);
669	AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 0x0218);
670	AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 0x0220);
671	AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 0x0228);
672	AssertCompileMemberOffset(CPUMCTX, aPaePdpes, 0x0240);
673	AssertCompileMemberOffset(CPUMCTX, aXcr, 0x0260);
674	AssertCompileMemberOffset(CPUMCTX, fXStateMask, 0x0270);
675	AssertCompileMemberOffset(CPUMCTX, fUsedFpuGuest, 0x0278);
676	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0300);
677	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) abXState, 0x0300);
678	AssertCompileMemberAlignment(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0100);
679	/* Only do spot checks for hwvirt */
680	AssertCompileMemberAlignment(CPUMCTX, hwvirt, 0x1000);
681	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.Vmcb, X86_PAGE_SIZE);
682	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abMsrBitmap, X86_PAGE_SIZE);
683	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, X86_PAGE_SIZE);
684	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Vmcs, X86_PAGE_SIZE);
685	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.ShadowVmcs, X86_PAGE_SIZE);
686	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmreadBitmap, X86_PAGE_SIZE);
687	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmwriteBitmap, X86_PAGE_SIZE);
688	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aEntryMsrLoadArea, X86_PAGE_SIZE);
689	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrStoreArea, X86_PAGE_SIZE);
690	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrLoadArea, X86_PAGE_SIZE);
691	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abMsrBitmap, X86_PAGE_SIZE);
692	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, X86_PAGE_SIZE);
693	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs, 8);
694	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, 0x7000);
695	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fInterceptEvents, 0xa0d4);
696	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, 0xf000);
697	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking, 0x1104a);
698	AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt, 0x11130);
699	AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif, 0x11134);
700	AssertCompileMemberOffset(CPUMCTX, hwvirt.fSavedInhibit, 0x11138);
701	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
702	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
703	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
704	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
705	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
706	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
707	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
708	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
709	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
710	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
711	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
712	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
713	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
714	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
715	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
716	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
717	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
718	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
719	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
720	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
721	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
722	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
723	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
724	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
725	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
726	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
727	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
728	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
729	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
730	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
731	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
732	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
733	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
734	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
735	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
736	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
737	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
738	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
739	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
740	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
741	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
742	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
743	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
744	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
745	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
746	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
747	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
748	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
749	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
750	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
751	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
752	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
753	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
754	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
755	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
756	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
757	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
758	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
759	# ifndef _MSC_VER
760	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
761	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
762	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
763	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
764	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
765	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
766	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
767	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
768	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
769	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
770	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
771	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
772	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
773	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
774	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
775	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
776	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
777	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
778	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
779	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
780	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
781	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
782	# endif
783
784
785	/**
786	* Calculates the pointer to the given extended state component.
787	*
788	* @returns Pointer of type @a a_PtrType
789	* @param a_pCtx Pointer to the context.
790	* @param a_iCompBit The extended state component bit number. This bit
791	* must be set in CPUMCTX::fXStateMask.
792	* @param a_PtrType The pointer type of the extended state component.
793	*
794	*/
795	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
796	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
797	([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
798	{ \
799	AssertCompile((a_iCompBit) < 64U); \
800	AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
801	AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
802	return (a_PtrType)(&a_pLambdaCtx->abXState[a_pLambdaCtx->aoffXState[(a_iCompBit)]]); \
803	}(a_pCtx))
804	#elif defined(VBOX_STRICT) && defined(__GNUC__)
805	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
806	__extension__ (\
807	{ \
808	AssertCompile((a_iCompBit) < 64U); \
809	AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
810	AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
811	(a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]); \
812	})
813	#else
814	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
815	((a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]))
816	#endif
817
818	/**
819	* Gets the first selector register of a CPUMCTX.
820	*
821	* Use this with X86_SREG_COUNT to loop thru the selector registers.
822	*/
823	# define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
824
825	#endif /* !VBOX_FOR_DTRACE_LIB */
826
827
828	/** @name CPUMCTX_EXTRN_XXX
829	* Used for parts of the CPUM state that is externalized and needs fetching
830	* before use.
831	*
832	* @{ */
833	/** External state keeper: Invalid. */
834	#define CPUMCTX_EXTRN_KEEPER_INVALID UINT64_C(0x0000000000000000)
835	/** External state keeper: HM. */
836	#define CPUMCTX_EXTRN_KEEPER_HM UINT64_C(0x0000000000000001)
837	/** External state keeper: NEM. */
838	#define CPUMCTX_EXTRN_KEEPER_NEM UINT64_C(0x0000000000000002)
839	/** External state keeper: REM. */
840	#define CPUMCTX_EXTRN_KEEPER_REM UINT64_C(0x0000000000000003)
841	/** External state keeper mask. */
842	#define CPUMCTX_EXTRN_KEEPER_MASK UINT64_C(0x0000000000000003)
843
844	/** The RIP register value is kept externally. */
845	#define CPUMCTX_EXTRN_RIP UINT64_C(0x0000000000000004)
846	/** The RFLAGS register values are kept externally. */
847	#define CPUMCTX_EXTRN_RFLAGS UINT64_C(0x0000000000000008)
848
849	/** The RAX register value is kept externally. */
850	#define CPUMCTX_EXTRN_RAX UINT64_C(0x0000000000000010)
851	/** The RCX register value is kept externally. */
852	#define CPUMCTX_EXTRN_RCX UINT64_C(0x0000000000000020)
853	/** The RDX register value is kept externally. */
854	#define CPUMCTX_EXTRN_RDX UINT64_C(0x0000000000000040)
855	/** The RBX register value is kept externally. */
856	#define CPUMCTX_EXTRN_RBX UINT64_C(0x0000000000000080)
857	/** The RSP register value is kept externally. */
858	#define CPUMCTX_EXTRN_RSP UINT64_C(0x0000000000000100)
859	/** The RBP register value is kept externally. */
860	#define CPUMCTX_EXTRN_RBP UINT64_C(0x0000000000000200)
861	/** The RSI register value is kept externally. */
862	#define CPUMCTX_EXTRN_RSI UINT64_C(0x0000000000000400)
863	/** The RDI register value is kept externally. */
864	#define CPUMCTX_EXTRN_RDI UINT64_C(0x0000000000000800)
865	/** The R8 thru R15 register values are kept externally. */
866	#define CPUMCTX_EXTRN_R8_R15 UINT64_C(0x0000000000001000)
867	/** General purpose registers mask. */
868	#define CPUMCTX_EXTRN_GPRS_MASK UINT64_C(0x0000000000001ff0)
869
870	/** The ES register values are kept externally. */
871	#define CPUMCTX_EXTRN_ES UINT64_C(0x0000000000002000)
872	/** The CS register values are kept externally. */
873	#define CPUMCTX_EXTRN_CS UINT64_C(0x0000000000004000)
874	/** The SS register values are kept externally. */
875	#define CPUMCTX_EXTRN_SS UINT64_C(0x0000000000008000)
876	/** The DS register values are kept externally. */
877	#define CPUMCTX_EXTRN_DS UINT64_C(0x0000000000010000)
878	/** The FS register values are kept externally. */
879	#define CPUMCTX_EXTRN_FS UINT64_C(0x0000000000020000)
880	/** The GS register values are kept externally. */
881	#define CPUMCTX_EXTRN_GS UINT64_C(0x0000000000040000)
882	/** Segment registers (includes CS). */
883	#define CPUMCTX_EXTRN_SREG_MASK UINT64_C(0x000000000007e000)
884	/** Converts a X86_XREG_XXX index to a CPUMCTX_EXTRN_xS mask. */
885	#define CPUMCTX_EXTRN_SREG_FROM_IDX(a_SRegIdx) RT_BIT_64((a_SRegIdx) + 13)
886	#ifndef VBOX_FOR_DTRACE_LIB
887	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_ES) == CPUMCTX_EXTRN_ES);
888	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_CS) == CPUMCTX_EXTRN_CS);
889	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_DS) == CPUMCTX_EXTRN_DS);
890	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_FS) == CPUMCTX_EXTRN_FS);
891	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_GS) == CPUMCTX_EXTRN_GS);
892	#endif
893
894	/** The GDTR register values are kept externally. */
895	#define CPUMCTX_EXTRN_GDTR UINT64_C(0x0000000000080000)
896	/** The IDTR register values are kept externally. */
897	#define CPUMCTX_EXTRN_IDTR UINT64_C(0x0000000000100000)
898	/** The LDTR register values are kept externally. */
899	#define CPUMCTX_EXTRN_LDTR UINT64_C(0x0000000000200000)
900	/** The TR register values are kept externally. */
901	#define CPUMCTX_EXTRN_TR UINT64_C(0x0000000000400000)
902	/** Table register mask. */
903	#define CPUMCTX_EXTRN_TABLE_MASK UINT64_C(0x0000000000780000)
904
905	/** The CR0 register value is kept externally. */
906	#define CPUMCTX_EXTRN_CR0 UINT64_C(0x0000000000800000)
907	/** The CR2 register value is kept externally. */
908	#define CPUMCTX_EXTRN_CR2 UINT64_C(0x0000000001000000)
909	/** The CR3 register value is kept externally. */
910	#define CPUMCTX_EXTRN_CR3 UINT64_C(0x0000000002000000)
911	/** The CR4 register value is kept externally. */
912	#define CPUMCTX_EXTRN_CR4 UINT64_C(0x0000000004000000)
913	/** Control register mask. */
914	#define CPUMCTX_EXTRN_CR_MASK UINT64_C(0x0000000007800000)
915	/** The TPR/CR8 register value is kept externally. */
916	#define CPUMCTX_EXTRN_APIC_TPR UINT64_C(0x0000000008000000)
917	/** The EFER register value is kept externally. */
918	#define CPUMCTX_EXTRN_EFER UINT64_C(0x0000000010000000)
919
920	/** The DR0, DR1, DR2 and DR3 register values are kept externally. */
921	#define CPUMCTX_EXTRN_DR0_DR3 UINT64_C(0x0000000020000000)
922	/** The DR6 register value is kept externally. */
923	#define CPUMCTX_EXTRN_DR6 UINT64_C(0x0000000040000000)
924	/** The DR7 register value is kept externally. */
925	#define CPUMCTX_EXTRN_DR7 UINT64_C(0x0000000080000000)
926	/** Debug register mask. */
927	#define CPUMCTX_EXTRN_DR_MASK UINT64_C(0x00000000e0000000)
928
929	/** The XSAVE_C_X87 state is kept externally. */
930	#define CPUMCTX_EXTRN_X87 UINT64_C(0x0000000100000000)
931	/** The XSAVE_C_SSE, XSAVE_C_YMM, XSAVE_C_ZMM_HI256, XSAVE_C_ZMM_16HI and
932	* XSAVE_C_OPMASK state is kept externally. */
933	#define CPUMCTX_EXTRN_SSE_AVX UINT64_C(0x0000000200000000)
934	/** The state of XSAVE components not covered by CPUMCTX_EXTRN_X87 and
935	* CPUMCTX_EXTRN_SEE_AVX is kept externally. */
936	#define CPUMCTX_EXTRN_OTHER_XSAVE UINT64_C(0x0000000400000000)
937	/** The state of XCR0 and XCR1 register values are kept externally. */
938	#define CPUMCTX_EXTRN_XCRx UINT64_C(0x0000000800000000)
939
940
941	/** The KERNEL GS BASE MSR value is kept externally. */
942	#define CPUMCTX_EXTRN_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
943	/** The STAR, LSTAR, CSTAR and SFMASK MSR values are kept externally. */
944	#define CPUMCTX_EXTRN_SYSCALL_MSRS UINT64_C(0x0000002000000000)
945	/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
946	#define CPUMCTX_EXTRN_SYSENTER_MSRS UINT64_C(0x0000004000000000)
947	/** The TSC_AUX MSR is kept externally. */
948	#define CPUMCTX_EXTRN_TSC_AUX UINT64_C(0x0000008000000000)
949	/** All other stateful MSRs not covered by CPUMCTX_EXTRN_EFER,
950	* CPUMCTX_EXTRN_KERNEL_GS_BASE, CPUMCTX_EXTRN_SYSCALL_MSRS,
951	* CPUMCTX_EXTRN_SYSENTER_MSRS, and CPUMCTX_EXTRN_TSC_AUX. */
952	#define CPUMCTX_EXTRN_OTHER_MSRS UINT64_C(0x0000010000000000)
953
954	/** Mask of all the MSRs. */
955	#define CPUMCTX_EXTRN_ALL_MSRS ( CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \
956	\| CPUMCTX_EXTRN_SYSENTER_MSRS \| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS)
957
958	/** Hardware-virtualization (SVM or VMX) state is kept externally. */
959	#define CPUMCTX_EXTRN_HWVIRT UINT64_C(0x0000020000000000)
960
961	/** Inhibit maskable interrupts (VMCPU_FF_INHIBIT_INTERRUPTS) */
962	#define CPUMCTX_EXTRN_INHIBIT_INT UINT64_C(0x0000040000000000)
963	/** Inhibit non-maskable interrupts (VMCPU_FF_BLOCK_NMIS). */
964	#define CPUMCTX_EXTRN_INHIBIT_NMI UINT64_C(0x0000080000000000)
965
966	/** Mask of bits the keepers can use for state tracking. */
967	#define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
968
969	/** NEM/Win: Event injection (known was interruption) pending state. */
970	#define CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT UINT64_C(0x0001000000000000)
971	/** NEM/Win: Mask. */
972	#define CPUMCTX_EXTRN_NEM_WIN_MASK UINT64_C(0x0001000000000000)
973
974	/** HM/SVM: Nested-guest interrupt pending (VMCPU_FF_INTERRUPT_NESTED_GUEST). */
975	#define CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ UINT64_C(0x0001000000000000)
976	/** HM/SVM: Mask. */
977	#define CPUMCTX_EXTRN_HM_SVM_MASK UINT64_C(0x0001000000000000)
978
979	/** All CPUM state bits, not including keeper specific ones. */
980	#define CPUMCTX_EXTRN_ALL UINT64_C(0x00000ffffffffffc)
981	/** All CPUM state bits, including keeper specific ones. */
982	#define CPUMCTX_EXTRN_ABSOLUTELY_ALL UINT64_C(0xfffffffffffffffc)
983	/** @} */
984
985
986	/** @name CPUMCTX_INHIBIT_XXX - Interrupt inhibiting flags.
987	* @{ */
988	/** Interrupt shadow following MOV SS or POP SS.
989	*
990	* When this in effect, both maskable and non-maskable interrupts are blocked
991	* from delivery for one instruction. Same for certain debug exceptions too,
992	* unlike the STI variant.
993	*
994	* It is implementation specific whether a sequence of two or more of these
995	* instructions will have any effect on the instruction following the last one
996	* of them. */
997	#define CPUMCTX_INHIBIT_SHADOW_SS RT_BIT_32(0 + CPUMX86EFLAGS_HW_BITS)
998	/** Interrupt shadow following STI.
999	* Same as CPUMCTX_INHIBIT_SHADOW_SS but without blocking any debug exceptions. */
1000	#define CPUMCTX_INHIBIT_SHADOW_STI RT_BIT_32(1 + CPUMX86EFLAGS_HW_BITS)
1001	/** Mask combining STI and SS shadowing. */
1002	#define CPUMCTX_INHIBIT_SHADOW (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI)
1003
1004	/** Interrupts blocked by NMI delivery. This condition is cleared by IRET.
1005	*
1006	* Section "6.7 NONMASKABLE INTERRUPT (NMI)" in Intel SDM Vol 3A states that
1007	* "The processor also invokes certain hardware conditions to ensure that no
1008	* other interrupts, including NMI interrupts, are received until the NMI
1009	* handler has completed executing." This flag indicates that these
1010	* conditions are currently active.
1011	*
1012	* @todo this does not really need to be in the lower 32-bits of EFLAGS.
1013	*/
1014	#define CPUMCTX_INHIBIT_NMI RT_BIT_32(2 + CPUMX86EFLAGS_HW_BITS)
1015
1016	/** Mask containing all the interrupt inhibit bits. */
1017	#define CPUMCTX_INHIBIT_ALL_MASK (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI \| CPUMCTX_INHIBIT_NMI)
1018	AssertCompile(CPUMCTX_INHIBIT_ALL_MASK < UINT32_MAX);
1019	/** @} */
1020
1021	/** @name CPUMCTX_DBG_XXX - Pending debug events.
1022	* @{ */
1023	/** Hit guest DR0 breakpoint. */
1024	#define CPUMCTX_DBG_HIT_DR0 RT_BIT_32(CPUMCTX_DBG_HIT_DR0_BIT)
1025	#define CPUMCTX_DBG_HIT_DR0_BIT (3 + CPUMX86EFLAGS_HW_BITS)
1026	/** Hit guest DR1 breakpoint. */
1027	#define CPUMCTX_DBG_HIT_DR1 RT_BIT_32(CPUMCTX_DBG_HIT_DR1_BIT)
1028	#define CPUMCTX_DBG_HIT_DR1_BIT (4 + CPUMX86EFLAGS_HW_BITS)
1029	/** Hit guest DR2 breakpoint. */
1030	#define CPUMCTX_DBG_HIT_DR2 RT_BIT_32(CPUMCTX_DBG_HIT_DR2_BIT)
1031	#define CPUMCTX_DBG_HIT_DR2_BIT (5 + CPUMX86EFLAGS_HW_BITS)
1032	/** Hit guest DR3 breakpoint. */
1033	#define CPUMCTX_DBG_HIT_DR3 RT_BIT_32(CPUMCTX_DBG_HIT_DR3_BIT)
1034	#define CPUMCTX_DBG_HIT_DR3_BIT (6 + CPUMX86EFLAGS_HW_BITS)
1035	/** Silent guest DRx breakpoint (presistent Intel errata fun). */
1036	#define CPUMCTX_DBG_HIT_DRX_SILENT RT_BIT_32(CPUMCTX_DBG_HIT_DRX_SILENT_BIT)
1037	#define CPUMCTX_DBG_HIT_DRX_SILENT_BIT (7 + CPUMX86EFLAGS_HW_BITS)
1038	/** Shift for the CPUMCTX_DBG_HIT_DRx bits. */
1039	#define CPUMCTX_DBG_HIT_DRX_SHIFT CPUMCTX_DBG_HIT_DR0_BIT
1040	/** Mask of all guest pending DR0-DR3 indicators (excluding the silent). */
1041	#define CPUMCTX_DBG_HIT_DRX_MASK_NONSILENT (CPUMCTX_DBG_HIT_DR0 \| CPUMCTX_DBG_HIT_DR1 \| CPUMCTX_DBG_HIT_DR2 \| CPUMCTX_DBG_HIT_DR3)
1042	/** Mask of all guest pending DR0-DR3 + silent breakpoint indicators. */
1043	#define CPUMCTX_DBG_HIT_DRX_MASK (CPUMCTX_DBG_HIT_DRX_MASK_NONSILENT \| CPUMCTX_DBG_HIT_DRX_SILENT)
1044	/** DBGF event/breakpoint pending. */
1045	#define CPUMCTX_DBG_DBGF_EVENT RT_BIT_32(CPUMCTX_DBG_DBGF_EVENT_BIT)
1046	#define CPUMCTX_DBG_DBGF_EVENT_BIT (8 + CPUMX86EFLAGS_HW_BITS)
1047	/** DBGF event/breakpoint pending. */
1048	#define CPUMCTX_DBG_DBGF_BP RT_BIT_32(CPUMCTX_DBG_DBGF_BP_BIT)
1049	#define CPUMCTX_DBG_DBGF_BP_BIT (9 + CPUMX86EFLAGS_HW_BITS)
1050	/** Mask of all DBGF indicators. */
1051	#define CPUMCTX_DBG_DBGF_MASK (CPUMCTX_DBG_DBGF_EVENT \| CPUMCTX_DBG_DBGF_BP)
1052	AssertCompile((CPUMCTX_DBG_HIT_DRX_MASK \| CPUMCTX_DBG_DBGF_MASK) < UINT32_MAX);
1053	/** @} */
1054
1055	/** Maximum number of variable-range MTRR pairs supported.
1056	*
1057	* Intel documents upto 10, see IA32_MTRR_PHYS[BASE\|MASK](0..9).
1058	* AMD documents upto 8, see MTRR_phys[Base\|Mask](0..7)
1059	* Hyper-V documents upto 16, see WHvX64RegisterMsrMtrrPhys[Base\|Mask](0..F).
1060	*
1061	* CPUs can in theory accomodate upto 39 pairs ([0x200,0x201]..[0x24e,0x24f])
1062	* unless AMD/Intel decides to put something else in this range.
1063	*/
1064	#define CPUMCTX_MAX_MTRRVAR_COUNT 16
1065
1066
1067	/**
1068	* Additional guest MSRs (i.e. not part of the CPU context structure).
1069	*
1070	* @remarks Never change the order here because of the saved stated! The size
1071	* can in theory be changed, but keep older VBox versions in mind.
1072	*/
1073	typedef union CPUMCTXMSRS
1074	{
1075	struct
1076	{
1077	uint64_t TscAux; /*< MSR_K8_TSC_AUX /
1078	uint64_t MiscEnable; /*< MSR_IA32_MISC_ENABLE /
1079	uint64_t MtrrDefType; /*< IA32_MTRR_DEF_TYPE /
1080	uint64_t MtrrFix64K_00000; /*< IA32_MTRR_FIX16K_80000 /
1081	uint64_t MtrrFix16K_80000; /*< IA32_MTRR_FIX16K_80000 /
1082	uint64_t MtrrFix16K_A0000; /*< IA32_MTRR_FIX16K_A0000 /
1083	uint64_t MtrrFix4K_C0000; /*< IA32_MTRR_FIX4K_C0000 /
1084	uint64_t MtrrFix4K_C8000; /*< IA32_MTRR_FIX4K_C8000 /
1085	uint64_t MtrrFix4K_D0000; /*< IA32_MTRR_FIX4K_D0000 /
1086	uint64_t MtrrFix4K_D8000; /*< IA32_MTRR_FIX4K_D8000 /
1087	uint64_t MtrrFix4K_E0000; /*< IA32_MTRR_FIX4K_E0000 /
1088	uint64_t MtrrFix4K_E8000; /*< IA32_MTRR_FIX4K_E8000 /
1089	uint64_t MtrrFix4K_F0000; /*< IA32_MTRR_FIX4K_F0000 /
1090	uint64_t MtrrFix4K_F8000; /*< IA32_MTRR_FIX4K_F8000 /
1091	uint64_t PkgCStateCfgCtrl; /*< MSR_PKG_CST_CONFIG_CONTROL /
1092	uint64_t SpecCtrl; /*< IA32_SPEC_CTRL /
1093	uint64_t ArchCaps; /*< IA32_ARCH_CAPABILITIES /
1094	uint64_t MtrrCap; /*< IA32_MTRR_CAP /
1095	X86MTRRVAR aMtrrVarMsrs[CPUMCTX_MAX_MTRRVAR_COUNT]; /*< IA32_MTRR_PHYSBASE, IA32_MTRR_PHYSMASK /
1096	} msr;
1097	uint64_t au64[64];
1098	} CPUMCTXMSRS;
1099	/** Pointer to the guest MSR state. */
1100	typedef CPUMCTXMSRS *PCPUMCTXMSRS;
1101	/** Pointer to the const guest MSR state. */
1102	typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
1103
1104	/** @} */
1105
1106	RT_C_DECLS_END
1107
1108	#endif /* !VBOX_INCLUDED_vmm_cpumctx_x86_amd64_h */
1109

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source: vbox/trunk/include/VBox/vmm/cpumctx-x86-amd64.h

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