| 1 | ;; @file
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| 2 | ; CPUM - CPU Monitor, Assembly header file.
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| 3 | ;
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| 4 |
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| 5 | ;
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| 6 | ; Copyright (C) 2006-2023 Oracle and/or its affiliates.
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| 7 | ;
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| 8 | ; This file is part of VirtualBox base platform packages, as
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| 9 | ; available from https://www.virtualbox.org.
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| 10 | ;
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| 11 | ; This program is free software; you can redistribute it and/or
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| 12 | ; modify it under the terms of the GNU General Public License
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| 13 | ; as published by the Free Software Foundation, in version 3 of the
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| 14 | ; License.
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| 15 | ;
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| 16 | ; This program is distributed in the hope that it will be useful, but
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| 17 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
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| 18 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 19 | ; General Public License for more details.
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| 20 | ;
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| 21 | ; You should have received a copy of the GNU General Public License
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| 22 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
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| 23 | ;
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| 24 | ; The contents of this file may alternatively be used under the terms
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| 25 | ; of the Common Development and Distribution License Version 1.0
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| 26 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 27 | ; in the VirtualBox distribution, in which case the provisions of the
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| 28 | ; CDDL are applicable instead of those of the GPL.
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| 29 | ;
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| 30 | ; You may elect to license modified versions of this file under the
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| 31 | ; terms and conditions of either the GPL or the CDDL or both.
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| 32 | ;
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| 33 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 34 | ;
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| 35 |
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| 36 | %ifndef ___VBox_vmm_cpum_mac__
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| 37 | %define ___VBox_vmm_cpum_mac__
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| 38 |
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| 39 | %include "iprt/asmdefs.mac"
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| 40 |
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| 41 |
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| 42 | ;;
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| 43 | ; The volatile XSAVE components when VBOX_WITH_KERNEL_USING_XMM is active.
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| 44 | ; @note ASSUMED to be at the most 32-bit in width at the moment.
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| 45 | %ifdef VBOX_WITH_KERNEL_USING_XMM
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| 46 | %define CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)
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| 47 | %endif
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| 48 |
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| 49 | ;;
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| 50 | ; CPUID leaf.
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| 51 | ; @remarks This structure is used by the patch manager and can only be extended
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| 52 | ; by adding to the end of it.
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| 53 | struc CPUMCPUIDLEAF
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| 54 | .uLeaf resd 1
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| 55 | .uSubLeaf resd 1
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| 56 | .fSubLeafMask resd 1
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| 57 | .uEax resd 1
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| 58 | .uEbx resd 1
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| 59 | .uEcx resd 1
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| 60 | .uEdx resd 1
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| 61 | .fFlags resd 1
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| 62 | endstruc
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| 63 | %define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
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| 64 | %define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
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| 65 | %define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
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| 66 | %define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
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| 67 |
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| 68 |
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| 69 | ;;
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| 70 | ; For the default CPUID leaf value.
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| 71 | ; @remarks This is used by the patch manager and cannot be modified in any way.
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| 72 | struc CPUMCPUID
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| 73 | .uEax resd 1
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| 74 | .uEbx resd 1
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| 75 | .uEcx resd 1
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| 76 | .uEdx resd 1
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| 77 | endstruc
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| 78 |
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| 79 |
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| 80 | ;; @name Method used to deal with unknown CPUID leaves.
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| 81 | ;; @{
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| 82 | %define CPUMUNKNOWNCPUID_DEFAULTS 1
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| 83 | %define CPUMUNKNOWNCPUID_LAST_STD_LEAF 2
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| 84 | %define CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX 3
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| 85 | %define CPUMUNKNOWNCPUID_PASSTHRU 4
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| 86 | ;; @}
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| 87 |
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| 88 |
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| 89 | %define XSTATE_SIZE 8192
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| 90 |
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| 91 | ;; Note! Updates here must be reflected in CPUMInternal.mac too!
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| 92 | struc CPUMCTX
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| 93 | .eax resq 1
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| 94 | .ecx resq 1
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| 95 | .edx resq 1
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| 96 | .ebx resq 1
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| 97 | .esp resq 1
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| 98 | .ebp resq 1
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| 99 | .esi resq 1
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| 100 | .edi resq 1
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| 101 | .r8 resq 1
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| 102 | .r9 resq 1
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| 103 | .r10 resq 1
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| 104 | .r11 resq 1
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| 105 | .r12 resq 1
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| 106 | .r13 resq 1
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| 107 | .r14 resq 1
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| 108 | .r15 resq 1
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| 109 | .es.Sel resw 1
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| 110 | .es.PaddingSel resw 1
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| 111 | .es.ValidSel resw 1
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| 112 | .es.fFlags resw 1
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| 113 | .es.u64Base resq 1
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| 114 | .es.u32Limit resd 1
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| 115 | .es.Attr resd 1
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| 116 | .cs.Sel resw 1
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| 117 | .cs.PaddingSel resw 1
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| 118 | .cs.ValidSel resw 1
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| 119 | .cs.fFlags resw 1
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| 120 | .cs.u64Base resq 1
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| 121 | .cs.u32Limit resd 1
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| 122 | .cs.Attr resd 1
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| 123 | .ss.Sel resw 1
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| 124 | .ss.PaddingSel resw 1
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| 125 | .ss.ValidSel resw 1
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| 126 | .ss.fFlags resw 1
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| 127 | .ss.u64Base resq 1
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| 128 | .ss.u32Limit resd 1
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| 129 | .ss.Attr resd 1
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| 130 | .ds.Sel resw 1
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| 131 | .ds.PaddingSel resw 1
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| 132 | .ds.ValidSel resw 1
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| 133 | .ds.fFlags resw 1
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| 134 | .ds.u64Base resq 1
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| 135 | .ds.u32Limit resd 1
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| 136 | .ds.Attr resd 1
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| 137 | .fs.Sel resw 1
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| 138 | .fs.PaddingSel resw 1
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| 139 | .fs.ValidSel resw 1
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| 140 | .fs.fFlags resw 1
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| 141 | .fs.u64Base resq 1
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| 142 | .fs.u32Limit resd 1
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| 143 | .fs.Attr resd 1
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| 144 | .gs.Sel resw 1
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| 145 | .gs.PaddingSel resw 1
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| 146 | .gs.ValidSel resw 1
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| 147 | .gs.fFlags resw 1
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| 148 | .gs.u64Base resq 1
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| 149 | .gs.u32Limit resd 1
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| 150 | .gs.Attr resd 1
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| 151 | .ldtr.Sel resw 1
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| 152 | .ldtr.PaddingSel resw 1
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| 153 | .ldtr.ValidSel resw 1
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| 154 | .ldtr.fFlags resw 1
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| 155 | .ldtr.u64Base resq 1
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| 156 | .ldtr.u32Limit resd 1
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| 157 | .ldtr.Attr resd 1
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| 158 | .tr.Sel resw 1
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| 159 | .tr.PaddingSel resw 1
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| 160 | .tr.ValidSel resw 1
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| 161 | .tr.fFlags resw 1
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| 162 | .tr.u64Base resq 1
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| 163 | .tr.u32Limit resd 1
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| 164 | .tr.Attr resd 1
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| 165 | alignb 8
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| 166 | .eip resq 1
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| 167 | .eflags resq 1
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| 168 | .fExtrn resq 1
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| 169 | .uRipInhibitInt resq 1
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| 170 | .cr0 resq 1
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| 171 | .cr2 resq 1
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| 172 | .cr3 resq 1
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| 173 | .cr4 resq 1
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| 174 | .dr resq 8
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| 175 | .gdtrPadding resw 3
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| 176 | .gdtr resw 0
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| 177 | .gdtr.cbGdt resw 1
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| 178 | .gdtr.pGdt resq 1
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| 179 | .idtrPadding resw 3
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| 180 | .idtr resw 0
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| 181 | .idtr.cbIdt resw 1
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| 182 | .idtr.pIdt resq 1
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| 183 | .SysEnter.cs resb 8
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| 184 | .SysEnter.eip resb 8
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| 185 | .SysEnter.esp resb 8
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| 186 | .msrEFER resb 8
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| 187 | .msrSTAR resb 8
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| 188 | .msrPAT resb 8
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| 189 | .msrLSTAR resb 8
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| 190 | .msrCSTAR resb 8
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| 191 | .msrSFMASK resb 8
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| 192 | .msrKERNELGSBASE resb 8
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| 193 |
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| 194 | alignb 32
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| 195 | .aPaePdpes resq 4
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| 196 |
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| 197 | alignb 8
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| 198 | .aXcr resq 2
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| 199 | .fXStateMask resq 1
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| 200 | .fUsedFpuGuest resb 1
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| 201 | alignb 8
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| 202 | .aoffXState resw 64
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| 203 | alignb 256
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| 204 | .abXState resb 0x4000-0x300
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| 205 | .XState EQU .abXState
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| 206 |
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| 207 | alignb 4096
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| 208 | .hwvirt resb 0
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| 209 | .hwvirt.svm resb 0
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| 210 | .hwvirt.vmx resb 0
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| 211 |
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| 212 | .hwvirt.svm.Vmcb EQU .hwvirt.svm
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| 213 | .hwvirt.svm.abMsrBitmap EQU (.hwvirt.svm.Vmcb + 0x1000)
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| 214 | .hwvirt.svm.abIoBitmap EQU (.hwvirt.svm.abMsrBitmap + 0x2000)
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| 215 | .hwvirt.svm.uMsrHSavePa EQU (.hwvirt.svm.abIoBitmap + 0x3000) ; resq 1
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| 216 | .hwvirt.svm.GCPhysVmcb EQU (.hwvirt.svm.uMsrHSavePa + 8) ; resq 1
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| 217 | alignb 8
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| 218 | .hwvirt.svm.HostState EQU (.hwvirt.svm.GCPhysVmcb + 8) ; resb 184
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| 219 | .hwvirt.svm.uPrevPauseTick EQU (.hwvirt.svm.HostState + 184) ; resq 1
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| 220 | .hwvirt.svm.cPauseFilter EQU (.hwvirt.svm.uPrevPauseTick + 8) ; resw 1
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| 221 | .hwvirt.svm.cPauseFilterThreshold EQU (.hwvirt.svm.cPauseFilter + 2) ; resw 1
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| 222 | .hwvirt.svm.fInterceptEvents EQU (.hwvirt.svm.cPauseFilterThreshold + 2) ; resb 1
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| 223 |
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| 224 | .hwvirt.vmx.Vmcs resb 0x1000
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| 225 | .hwvirt.vmx.ShadowVmcs resb 0x1000
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| 226 | .hwvirt.vmx.abVmreadBitmap resb 0x1000
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| 227 | .hwvirt.vmx.abVmwriteBitmap resb 0x1000
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| 228 | .hwvirt.vmx.aEntryMsrLoadArea resb 0x2000
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| 229 | .hwvirt.vmx.aExitMsrStoreArea resb 0x2000
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| 230 | .hwvirt.vmx.aExitMsrLoadArea resb 0x2000
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| 231 | .hwvirt.vmx.abMsrBitmap resb 0x1000
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| 232 | .hwvirt.vmx.abIoBitmap resb 0x1000+0x1000
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| 233 | alignb 8
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| 234 | .hwvirt.vmx.GCPhysVmxon resq 1
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| 235 | .hwvirt.vmx.GCPhysVmcs resq 1
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| 236 | .hwvirt.vmx.GCPhysShadowVmcs resq 1
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| 237 | .hwvirt.vmx.enmDiag resd 1
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| 238 | .hwvirt.vmx.enmAbort resd 1
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| 239 | .hwvirt.vmx.uDiagAux resq 1
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| 240 | .hwvirt.vmx.uAbortAux resd 1
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| 241 | .hwvirt.vmx.fInVmxRootMode resb 1
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| 242 | .hwvirt.vmx.fInVmxNonRootMode resb 1
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| 243 | .hwvirt.vmx.fInterceptEvents resb 1
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| 244 | .hwvirt.vmx.fNmiUnblockingIret resb 1
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| 245 | .hwvirt.vmx.uFirstPauseLoopTick resq 1
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| 246 | .hwvirt.vmx.uPrevPauseTick resq 1
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| 247 | .hwvirt.vmx.uEntryTick resq 1
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| 248 | .hwvirt.vmx.offVirtApicWrite resw 1
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| 249 | .hwvirt.vmx.fVirtNmiBlocking resb 1
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| 250 | alignb 8
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| 251 | .hwvirt.vmx.Msrs resb 224
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| 252 |
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| 253 | alignb 8
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| 254 | .hwvirt.enmHwvirt resd 1
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| 255 | .hwvirt.fGif resb 1
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| 256 | alignb 4
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| 257 | .hwvirt.fSavedInhibit resd 1
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| 258 | alignb 64
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| 259 | endstruc
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| 260 |
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| 261 |
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| 262 | %define CPUMSELREG_FLAGS_VALID 0x0001
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| 263 | %define CPUMSELREG_FLAGS_STALE 0x0002
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| 264 | %define CPUMSELREG_FLAGS_VALID_MASK 0x0003
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| 265 |
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| 266 |
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| 267 | ;;
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| 268 | ; Guest MSR state.
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| 269 | struc CPUMCTXMSRS
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| 270 | .au64 resq 64
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| 271 | endstruc
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| 272 |
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| 273 |
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| 274 | %endif
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| 275 |
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