VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum.h@ 87450

Last change on this file since 87450 was 87351, checked in by vboxsync, 4 years ago

VMM/CPUM: Slapped a @todo on CPUM_CHANGED_XXX / CPUMCPU::fChanged.
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File size: 105.6 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_cpum_h
27#define VBOX_INCLUDED_vmm_cpum_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/x86.h>
33#include <VBox/types.h>
34#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_ARM64)
35# include <VBox/vmm/cpumctx.h>
36#endif
37#include <VBox/vmm/stam.h>
38#include <VBox/vmm/vmapi.h>
39#include <VBox/vmm/hm_svm.h>
40#include <VBox/vmm/hm_vmx.h>
41
42RT_C_DECLS_BEGIN
43
44/** @defgroup grp_cpum The CPU Monitor / Manager API
45 * @ingroup grp_vmm
46 * @{
47 */
48
49/**
50 * CPUID feature to set or clear.
51 */
52typedef enum CPUMCPUIDFEATURE
53{
54 CPUMCPUIDFEATURE_INVALID = 0,
55 /** The APIC feature bit. (Std+Ext)
56 * Note! There is a per-cpu flag for masking this CPUID feature bit when the
57 * APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
58 * at VM construction time like all the others. This didn't used to be
59 * that way, this is new with 5.1. */
60 CPUMCPUIDFEATURE_APIC,
61 /** The sysenter/sysexit feature bit. (Std) */
62 CPUMCPUIDFEATURE_SEP,
63 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
64 CPUMCPUIDFEATURE_SYSCALL,
65 /** The PAE feature bit. (Std+Ext) */
66 CPUMCPUIDFEATURE_PAE,
67 /** The NX feature bit. (Ext) */
68 CPUMCPUIDFEATURE_NX,
69 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
70 CPUMCPUIDFEATURE_LAHF,
71 /** The LONG MODE feature bit. (Ext) */
72 CPUMCPUIDFEATURE_LONG_MODE,
73 /** The PAT feature bit. (Std+Ext) */
74 CPUMCPUIDFEATURE_PAT,
75 /** The x2APIC feature bit. (Std) */
76 CPUMCPUIDFEATURE_X2APIC,
77 /** The RDTSCP feature bit. (Ext) */
78 CPUMCPUIDFEATURE_RDTSCP,
79 /** The Hypervisor Present bit. (Std) */
80 CPUMCPUIDFEATURE_HVP,
81 /** The MWait Extensions bits (Std) */
82 CPUMCPUIDFEATURE_MWAIT_EXTS,
83 /** The speculation control feature bits. (StExt) */
84 CPUMCPUIDFEATURE_SPEC_CTRL,
85 /** 32bit hackishness. */
86 CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
87} CPUMCPUIDFEATURE;
88
89/**
90 * CPU Vendor.
91 */
92typedef enum CPUMCPUVENDOR
93{
94 CPUMCPUVENDOR_INVALID = 0,
95 CPUMCPUVENDOR_INTEL,
96 CPUMCPUVENDOR_AMD,
97 CPUMCPUVENDOR_VIA,
98 CPUMCPUVENDOR_CYRIX,
99 CPUMCPUVENDOR_SHANGHAI,
100 CPUMCPUVENDOR_HYGON,
101 CPUMCPUVENDOR_UNKNOWN,
102 /** 32bit hackishness. */
103 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
104} CPUMCPUVENDOR;
105
106
107/**
108 * X86 and AMD64 CPU microarchitectures and in processor generations.
109 *
110 * @remarks The separation here is sometimes a little bit too finely grained,
111 * and the differences is more like processor generation than micro
112 * arch. This can be useful, so we'll provide functions for getting at
113 * more coarse grained info.
114 */
115typedef enum CPUMMICROARCH
116{
117 kCpumMicroarch_Invalid = 0,
118
119 kCpumMicroarch_Intel_First,
120
121 kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
122 kCpumMicroarch_Intel_80186,
123 kCpumMicroarch_Intel_80286,
124 kCpumMicroarch_Intel_80386,
125 kCpumMicroarch_Intel_80486,
126 kCpumMicroarch_Intel_P5,
127
128 kCpumMicroarch_Intel_P6_Core_Atom_First,
129 kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
130 kCpumMicroarch_Intel_P6_II,
131 kCpumMicroarch_Intel_P6_III,
132
133 kCpumMicroarch_Intel_P6_M_Banias,
134 kCpumMicroarch_Intel_P6_M_Dothan,
135 kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
136
137 kCpumMicroarch_Intel_Core2_First,
138 kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /**< 65nm, Merom/Conroe/Kentsfield/Tigerton */
139 kCpumMicroarch_Intel_Core2_Penryn, /**< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown */
140 kCpumMicroarch_Intel_Core2_End,
141
142 kCpumMicroarch_Intel_Core7_First,
143 kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
144 kCpumMicroarch_Intel_Core7_Westmere,
145 kCpumMicroarch_Intel_Core7_SandyBridge,
146 kCpumMicroarch_Intel_Core7_IvyBridge,
147 kCpumMicroarch_Intel_Core7_Haswell,
148 kCpumMicroarch_Intel_Core7_Broadwell,
149 kCpumMicroarch_Intel_Core7_Skylake,
150 kCpumMicroarch_Intel_Core7_KabyLake,
151 kCpumMicroarch_Intel_Core7_CoffeeLake,
152 kCpumMicroarch_Intel_Core7_WhiskeyLake,
153 kCpumMicroarch_Intel_Core7_CascadeLake,
154 kCpumMicroarch_Intel_Core7_CannonLake,
155 kCpumMicroarch_Intel_Core7_IceLake,
156 kCpumMicroarch_Intel_Core7_TigerLake,
157 kCpumMicroarch_Intel_Core7_End,
158
159 kCpumMicroarch_Intel_Atom_First,
160 kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
161 kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
162 kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
163 kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */
164 kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */
165 kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */
166 kCpumMicroarch_Intel_Atom_GoldmontPlus, /**< 14nm */
167 kCpumMicroarch_Intel_Atom_Unknown,
168 kCpumMicroarch_Intel_Atom_End,
169
170
171 kCpumMicroarch_Intel_Phi_First,
172 kCpumMicroarch_Intel_Phi_KnightsFerry = kCpumMicroarch_Intel_Phi_First,
173 kCpumMicroarch_Intel_Phi_KnightsCorner,
174 kCpumMicroarch_Intel_Phi_KnightsLanding,
175 kCpumMicroarch_Intel_Phi_KnightsHill,
176 kCpumMicroarch_Intel_Phi_KnightsMill,
177 kCpumMicroarch_Intel_Phi_End,
178
179 kCpumMicroarch_Intel_P6_Core_Atom_End,
180
181 kCpumMicroarch_Intel_NB_First,
182 kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
183 kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */
184 kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */
185 kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */
186 kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */
187 kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
188 kCpumMicroarch_Intel_NB_Unknown,
189 kCpumMicroarch_Intel_NB_End,
190
191 kCpumMicroarch_Intel_Unknown,
192 kCpumMicroarch_Intel_End,
193
194 kCpumMicroarch_AMD_First,
195 kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
196 kCpumMicroarch_AMD_Am386,
197 kCpumMicroarch_AMD_Am486,
198 kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
199 kCpumMicroarch_AMD_K5,
200 kCpumMicroarch_AMD_K6,
201
202 kCpumMicroarch_AMD_K7_First,
203 kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
204 kCpumMicroarch_AMD_K7_Spitfire,
205 kCpumMicroarch_AMD_K7_Thunderbird,
206 kCpumMicroarch_AMD_K7_Morgan,
207 kCpumMicroarch_AMD_K7_Thoroughbred,
208 kCpumMicroarch_AMD_K7_Barton,
209 kCpumMicroarch_AMD_K7_Unknown,
210 kCpumMicroarch_AMD_K7_End,
211
212 kCpumMicroarch_AMD_K8_First,
213 kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
214 kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */
215 kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
216 kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
217 kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */
218 kCpumMicroarch_AMD_K8_End,
219
220 kCpumMicroarch_AMD_K10,
221 kCpumMicroarch_AMD_K10_Lion,
222 kCpumMicroarch_AMD_K10_Llano,
223 kCpumMicroarch_AMD_Bobcat,
224 kCpumMicroarch_AMD_Jaguar,
225
226 kCpumMicroarch_AMD_15h_First,
227 kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
228 kCpumMicroarch_AMD_15h_Piledriver,
229 kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
230 kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
231 kCpumMicroarch_AMD_15h_Unknown,
232 kCpumMicroarch_AMD_15h_End,
233
234 kCpumMicroarch_AMD_16h_First,
235 kCpumMicroarch_AMD_16h_End,
236
237 kCpumMicroarch_AMD_Zen_First,
238 kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
239 kCpumMicroarch_AMD_Zen_End,
240
241 kCpumMicroarch_AMD_Unknown,
242 kCpumMicroarch_AMD_End,
243
244 kCpumMicroarch_Hygon_First,
245 kCpumMicroarch_Hygon_Dhyana = kCpumMicroarch_Hygon_First,
246 kCpumMicroarch_Hygon_Unknown,
247 kCpumMicroarch_Hygon_End,
248
249 kCpumMicroarch_VIA_First,
250 kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
251 kCpumMicroarch_Centaur_C2,
252 kCpumMicroarch_Centaur_C3,
253 kCpumMicroarch_VIA_C3_M2,
254 kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
255 kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
256 kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
257 kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
258 kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
259 kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
260 kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
261 kCpumMicroarch_VIA_Isaiah,
262 kCpumMicroarch_VIA_Unknown,
263 kCpumMicroarch_VIA_End,
264
265 kCpumMicroarch_Shanghai_First,
266 kCpumMicroarch_Shanghai_Wudaokou = kCpumMicroarch_Shanghai_First,
267 kCpumMicroarch_Shanghai_Unknown,
268 kCpumMicroarch_Shanghai_End,
269
270 kCpumMicroarch_Cyrix_First,
271 kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
272 kCpumMicroarch_Cyrix_M1,
273 kCpumMicroarch_Cyrix_MediaGX,
274 kCpumMicroarch_Cyrix_MediaGXm,
275 kCpumMicroarch_Cyrix_M2,
276 kCpumMicroarch_Cyrix_Unknown,
277 kCpumMicroarch_Cyrix_End,
278
279 kCpumMicroarch_NEC_First,
280 kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
281 kCpumMicroarch_NEC_V30,
282 kCpumMicroarch_NEC_End,
283
284 kCpumMicroarch_Unknown,
285
286 kCpumMicroarch_32BitHack = 0x7fffffff
287} CPUMMICROARCH;
288
289
290/** Predicate macro for catching netburst CPUs. */
291#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
292 ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
293
294/** Predicate macro for catching Core7 CPUs. */
295#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
296 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
297
298/** Predicate macro for catching Core 2 CPUs. */
299#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
300 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
301
302/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
303#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
304 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
305
306/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
307#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
308 ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
309
310/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
311#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
312
313/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
314#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
315
316/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
317#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
318
319/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
320#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
321
322/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
323 * decendants). */
324#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
325 ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
326
327/** Predicate macro for catching AMD Family 16H CPUs. */
328#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
329 ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
330
331/** Predicate macro for catching AMD Zen Family CPUs. */
332#define CPUMMICROARCH_IS_AMD_FAM_ZEN(a_enmMicroarch) \
333 ((a_enmMicroarch) >= kCpumMicroarch_AMD_Zen_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_Zen_End)
334
335
336/**
337 * CPUID leaf.
338 *
339 * @remarks This structure is used by the patch manager and is therefore
340 * more or less set in stone.
341 */
342typedef struct CPUMCPUIDLEAF
343{
344 /** The leaf number. */
345 uint32_t uLeaf;
346 /** The sub-leaf number. */
347 uint32_t uSubLeaf;
348 /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
349 uint32_t fSubLeafMask;
350
351 /** The EAX value. */
352 uint32_t uEax;
353 /** The EBX value. */
354 uint32_t uEbx;
355 /** The ECX value. */
356 uint32_t uEcx;
357 /** The EDX value. */
358 uint32_t uEdx;
359
360 /** Flags. */
361 uint32_t fFlags;
362} CPUMCPUIDLEAF;
363#ifndef VBOX_FOR_DTRACE_LIB
364AssertCompileSize(CPUMCPUIDLEAF, 32);
365#endif
366/** Pointer to a CPUID leaf. */
367typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
368/** Pointer to a const CPUID leaf. */
369typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
370
371/** @name CPUMCPUIDLEAF::fFlags
372 * @{ */
373/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
374 * and EDX containing the extended APIC ID. */
375#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
376/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
377#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
378/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
379#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
380/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
381#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
382/** Mask of the valid flags. */
383#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
384/** @} */
385
386/**
387 * Method used to deal with unknown CPUID leaves.
388 * @remarks Used in patch code.
389 */
390typedef enum CPUMUNKNOWNCPUID
391{
392 /** Invalid zero value. */
393 CPUMUNKNOWNCPUID_INVALID = 0,
394 /** Use given default values (DefCpuId). */
395 CPUMUNKNOWNCPUID_DEFAULTS,
396 /** Return the last standard leaf.
397 * Intel Sandy Bridge has been observed doing this. */
398 CPUMUNKNOWNCPUID_LAST_STD_LEAF,
399 /** Return the last standard leaf, with ecx observed.
400 * Intel Sandy Bridge has been observed doing this. */
401 CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
402 /** The register values are passed thru unmodified. */
403 CPUMUNKNOWNCPUID_PASSTHRU,
404 /** End of valid value. */
405 CPUMUNKNOWNCPUID_END,
406 /** Ensure 32-bit type. */
407 CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
408} CPUMUNKNOWNCPUID;
409/** Pointer to unknown CPUID leaf method. */
410typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
411
412
413/**
414 * The register set returned by a CPUID operation.
415 */
416typedef struct CPUMCPUID
417{
418 uint32_t uEax;
419 uint32_t uEbx;
420 uint32_t uEcx;
421 uint32_t uEdx;
422} CPUMCPUID;
423/** Pointer to a CPUID leaf. */
424typedef CPUMCPUID *PCPUMCPUID;
425/** Pointer to a const CPUID leaf. */
426typedef const CPUMCPUID *PCCPUMCPUID;
427
428
429/**
430 * MSR read functions.
431 */
432typedef enum CPUMMSRRDFN
433{
434 /** Invalid zero value. */
435 kCpumMsrRdFn_Invalid = 0,
436 /** Return the CPUMMSRRANGE::uValue. */
437 kCpumMsrRdFn_FixedValue,
438 /** Alias to the MSR range starting at the MSR given by
439 * CPUMMSRRANGE::uValue. Must be used in pair with
440 * kCpumMsrWrFn_MsrAlias. */
441 kCpumMsrRdFn_MsrAlias,
442 /** Write only register, GP all read attempts. */
443 kCpumMsrRdFn_WriteOnly,
444
445 kCpumMsrRdFn_Ia32P5McAddr,
446 kCpumMsrRdFn_Ia32P5McType,
447 kCpumMsrRdFn_Ia32TimestampCounter,
448 kCpumMsrRdFn_Ia32PlatformId, /**< Takes real CPU value for reference. */
449 kCpumMsrRdFn_Ia32ApicBase,
450 kCpumMsrRdFn_Ia32FeatureControl,
451 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
452 kCpumMsrRdFn_Ia32SmmMonitorCtl,
453 kCpumMsrRdFn_Ia32PmcN,
454 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
455 kCpumMsrRdFn_Ia32MPerf,
456 kCpumMsrRdFn_Ia32APerf,
457 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
458 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
459 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
460 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
461 kCpumMsrRdFn_Ia32MtrrDefType,
462 kCpumMsrRdFn_Ia32Pat,
463 kCpumMsrRdFn_Ia32SysEnterCs,
464 kCpumMsrRdFn_Ia32SysEnterEsp,
465 kCpumMsrRdFn_Ia32SysEnterEip,
466 kCpumMsrRdFn_Ia32McgCap,
467 kCpumMsrRdFn_Ia32McgStatus,
468 kCpumMsrRdFn_Ia32McgCtl,
469 kCpumMsrRdFn_Ia32DebugCtl,
470 kCpumMsrRdFn_Ia32SmrrPhysBase,
471 kCpumMsrRdFn_Ia32SmrrPhysMask,
472 kCpumMsrRdFn_Ia32PlatformDcaCap,
473 kCpumMsrRdFn_Ia32CpuDcaCap,
474 kCpumMsrRdFn_Ia32Dca0Cap,
475 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
476 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
477 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
478 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
479 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
480 kCpumMsrRdFn_Ia32FixedCtrCtrl,
481 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
482 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
483 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
484 kCpumMsrRdFn_Ia32PebsEnable,
485 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
486 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
487 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
488 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
489 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
490 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
491 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
492 kCpumMsrRdFn_Ia32DsArea,
493 kCpumMsrRdFn_Ia32TscDeadline,
494 kCpumMsrRdFn_Ia32X2ApicN,
495 kCpumMsrRdFn_Ia32DebugInterface,
496 kCpumMsrRdFn_Ia32VmxBasic, /**< Takes real value as reference. */
497 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
498 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
499 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
500 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
501 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
502 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
503 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
504 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
505 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
506 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
507 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
508 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
509 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
510 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
511 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
512 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
513 kCpumMsrRdFn_Ia32VmxVmFunc, /**< Takes real value as reference. */
514 kCpumMsrRdFn_Ia32SpecCtrl,
515 kCpumMsrRdFn_Ia32ArchCapabilities,
516
517 kCpumMsrRdFn_Amd64Efer,
518 kCpumMsrRdFn_Amd64SyscallTarget,
519 kCpumMsrRdFn_Amd64LongSyscallTarget,
520 kCpumMsrRdFn_Amd64CompSyscallTarget,
521 kCpumMsrRdFn_Amd64SyscallFlagMask,
522 kCpumMsrRdFn_Amd64FsBase,
523 kCpumMsrRdFn_Amd64GsBase,
524 kCpumMsrRdFn_Amd64KernelGsBase,
525 kCpumMsrRdFn_Amd64TscAux,
526
527 kCpumMsrRdFn_IntelEblCrPowerOn,
528 kCpumMsrRdFn_IntelI7CoreThreadCount,
529 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
530 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
531 kCpumMsrRdFn_IntelP4EbcFrequencyId,
532 kCpumMsrRdFn_IntelP6FsbFrequency, /**< Takes real value as reference. */
533 kCpumMsrRdFn_IntelPlatformInfo,
534 kCpumMsrRdFn_IntelFlexRatio, /**< Takes real value as reference. */
535 kCpumMsrRdFn_IntelPkgCStConfigControl,
536 kCpumMsrRdFn_IntelPmgIoCaptureBase,
537 kCpumMsrRdFn_IntelLastBranchFromToN,
538 kCpumMsrRdFn_IntelLastBranchFromN,
539 kCpumMsrRdFn_IntelLastBranchToN,
540 kCpumMsrRdFn_IntelLastBranchTos,
541 kCpumMsrRdFn_IntelBblCrCtl,
542 kCpumMsrRdFn_IntelBblCrCtl3,
543 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
544 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
545 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
546 kCpumMsrRdFn_IntelP6CrN,
547 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
548 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
549 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
550 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
551 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
552 kCpumMsrRdFn_IntelI7LbrSelect,
553 kCpumMsrRdFn_IntelI7SandyErrorControl,
554 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
555 kCpumMsrRdFn_IntelI7PowerCtl,
556 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
557 kCpumMsrRdFn_IntelI7PebsLdLat,
558 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
559 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
560 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
561 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
562 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
563 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
564 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
565 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
566 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
567 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
568 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
569 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
570 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
571 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
572 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
573 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
574 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
575 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
576 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
577 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
578 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
579 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
580 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
581 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
582 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
583 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
584 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
585 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
586 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
587 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
588 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
589 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
590 kCpumMsrRdFn_IntelI7UncCBoxConfig,
591 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
592 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
593 kCpumMsrRdFn_IntelI7SmiCount,
594 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
595 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
596 kCpumMsrRdFn_IntelCore1ExtConfig,
597 kCpumMsrRdFn_IntelCore1DtsCalControl,
598 kCpumMsrRdFn_IntelCore2PeciControl,
599 kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
600
601 kCpumMsrRdFn_P6LastBranchFromIp,
602 kCpumMsrRdFn_P6LastBranchToIp,
603 kCpumMsrRdFn_P6LastIntFromIp,
604 kCpumMsrRdFn_P6LastIntToIp,
605
606 kCpumMsrRdFn_AmdFam15hTscRate,
607 kCpumMsrRdFn_AmdFam15hLwpCfg,
608 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
609 kCpumMsrRdFn_AmdFam10hMc4MiscN,
610 kCpumMsrRdFn_AmdK8PerfCtlN,
611 kCpumMsrRdFn_AmdK8PerfCtrN,
612 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
613 kCpumMsrRdFn_AmdK8HwCr,
614 kCpumMsrRdFn_AmdK8IorrBaseN,
615 kCpumMsrRdFn_AmdK8IorrMaskN,
616 kCpumMsrRdFn_AmdK8TopOfMemN,
617 kCpumMsrRdFn_AmdK8NbCfg1,
618 kCpumMsrRdFn_AmdK8McXcptRedir,
619 kCpumMsrRdFn_AmdK8CpuNameN,
620 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
621 kCpumMsrRdFn_AmdK8SwThermalCtrl,
622 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
623 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
624 kCpumMsrRdFn_AmdK8McCtlMaskN,
625 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
626 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
627 kCpumMsrRdFn_AmdK8IntPendingMessage,
628 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
629 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
630 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
631 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
632 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
633 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
634 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
635 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
636 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
637 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
638 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
639 kCpumMsrRdFn_AmdK8SmmBase,
640 kCpumMsrRdFn_AmdK8SmmAddr,
641 kCpumMsrRdFn_AmdK8SmmMask,
642 kCpumMsrRdFn_AmdK8VmCr,
643 kCpumMsrRdFn_AmdK8IgnNe,
644 kCpumMsrRdFn_AmdK8SmmCtl,
645 kCpumMsrRdFn_AmdK8VmHSavePa,
646 kCpumMsrRdFn_AmdFam10hVmLockKey,
647 kCpumMsrRdFn_AmdFam10hSmmLockKey,
648 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
649 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
650 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
651 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
652 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
653 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
654 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
655 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
656 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
657 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
658 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
659 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
660 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
661 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
662 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
663 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
664 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
665 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
666 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
667 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
668 kCpumMsrRdFn_AmdK7NodeId,
669 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
670 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
671 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
672 kCpumMsrRdFn_AmdK7LoadStoreCfg,
673 kCpumMsrRdFn_AmdK7InstrCacheCfg,
674 kCpumMsrRdFn_AmdK7DataCacheCfg,
675 kCpumMsrRdFn_AmdK7BusUnitCfg,
676 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
677 kCpumMsrRdFn_AmdFam15hFpuCfg,
678 kCpumMsrRdFn_AmdFam15hDecoderCfg,
679 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
680 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
681 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
682 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
683 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
684 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
685 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
686 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
687 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
688 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
689 kCpumMsrRdFn_AmdFam10hIbsOpRip,
690 kCpumMsrRdFn_AmdFam10hIbsOpData,
691 kCpumMsrRdFn_AmdFam10hIbsOpData2,
692 kCpumMsrRdFn_AmdFam10hIbsOpData3,
693 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
694 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
695 kCpumMsrRdFn_AmdFam10hIbsCtl,
696 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
697
698 kCpumMsrRdFn_Gim,
699
700 /** End of valid MSR read function indexes. */
701 kCpumMsrRdFn_End
702} CPUMMSRRDFN;
703
704/**
705 * MSR write functions.
706 */
707typedef enum CPUMMSRWRFN
708{
709 /** Invalid zero value. */
710 kCpumMsrWrFn_Invalid = 0,
711 /** Writes are ignored, the fWrGpMask is observed though. */
712 kCpumMsrWrFn_IgnoreWrite,
713 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
714 kCpumMsrWrFn_ReadOnly,
715 /** Alias to the MSR range starting at the MSR given by
716 * CPUMMSRRANGE::uValue. Must be used in pair with
717 * kCpumMsrRdFn_MsrAlias. */
718 kCpumMsrWrFn_MsrAlias,
719
720 kCpumMsrWrFn_Ia32P5McAddr,
721 kCpumMsrWrFn_Ia32P5McType,
722 kCpumMsrWrFn_Ia32TimestampCounter,
723 kCpumMsrWrFn_Ia32ApicBase,
724 kCpumMsrWrFn_Ia32FeatureControl,
725 kCpumMsrWrFn_Ia32BiosSignId,
726 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
727 kCpumMsrWrFn_Ia32SmmMonitorCtl,
728 kCpumMsrWrFn_Ia32PmcN,
729 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
730 kCpumMsrWrFn_Ia32MPerf,
731 kCpumMsrWrFn_Ia32APerf,
732 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
733 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
734 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
735 kCpumMsrWrFn_Ia32MtrrDefType,
736 kCpumMsrWrFn_Ia32Pat,
737 kCpumMsrWrFn_Ia32SysEnterCs,
738 kCpumMsrWrFn_Ia32SysEnterEsp,
739 kCpumMsrWrFn_Ia32SysEnterEip,
740 kCpumMsrWrFn_Ia32McgStatus,
741 kCpumMsrWrFn_Ia32McgCtl,
742 kCpumMsrWrFn_Ia32DebugCtl,
743 kCpumMsrWrFn_Ia32SmrrPhysBase,
744 kCpumMsrWrFn_Ia32SmrrPhysMask,
745 kCpumMsrWrFn_Ia32PlatformDcaCap,
746 kCpumMsrWrFn_Ia32Dca0Cap,
747 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
748 kCpumMsrWrFn_Ia32PerfStatus,
749 kCpumMsrWrFn_Ia32PerfCtl,
750 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
751 kCpumMsrWrFn_Ia32PerfCapabilities,
752 kCpumMsrWrFn_Ia32FixedCtrCtrl,
753 kCpumMsrWrFn_Ia32PerfGlobalStatus,
754 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
755 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
756 kCpumMsrWrFn_Ia32PebsEnable,
757 kCpumMsrWrFn_Ia32ClockModulation,
758 kCpumMsrWrFn_Ia32ThermInterrupt,
759 kCpumMsrWrFn_Ia32ThermStatus,
760 kCpumMsrWrFn_Ia32Therm2Ctl,
761 kCpumMsrWrFn_Ia32MiscEnable,
762 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
763 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
764 kCpumMsrWrFn_Ia32DsArea,
765 kCpumMsrWrFn_Ia32TscDeadline,
766 kCpumMsrWrFn_Ia32X2ApicN,
767 kCpumMsrWrFn_Ia32DebugInterface,
768 kCpumMsrWrFn_Ia32SpecCtrl,
769 kCpumMsrWrFn_Ia32PredCmd,
770 kCpumMsrWrFn_Ia32FlushCmd,
771
772 kCpumMsrWrFn_Amd64Efer,
773 kCpumMsrWrFn_Amd64SyscallTarget,
774 kCpumMsrWrFn_Amd64LongSyscallTarget,
775 kCpumMsrWrFn_Amd64CompSyscallTarget,
776 kCpumMsrWrFn_Amd64SyscallFlagMask,
777 kCpumMsrWrFn_Amd64FsBase,
778 kCpumMsrWrFn_Amd64GsBase,
779 kCpumMsrWrFn_Amd64KernelGsBase,
780 kCpumMsrWrFn_Amd64TscAux,
781 kCpumMsrWrFn_IntelEblCrPowerOn,
782 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
783 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
784 kCpumMsrWrFn_IntelP4EbcFrequencyId,
785 kCpumMsrWrFn_IntelFlexRatio,
786 kCpumMsrWrFn_IntelPkgCStConfigControl,
787 kCpumMsrWrFn_IntelPmgIoCaptureBase,
788 kCpumMsrWrFn_IntelLastBranchFromToN,
789 kCpumMsrWrFn_IntelLastBranchFromN,
790 kCpumMsrWrFn_IntelLastBranchToN,
791 kCpumMsrWrFn_IntelLastBranchTos,
792 kCpumMsrWrFn_IntelBblCrCtl,
793 kCpumMsrWrFn_IntelBblCrCtl3,
794 kCpumMsrWrFn_IntelI7TemperatureTarget,
795 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
796 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
797 kCpumMsrWrFn_IntelP6CrN,
798 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
799 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
800 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
801 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
802 kCpumMsrWrFn_IntelI7TurboRatioLimit,
803 kCpumMsrWrFn_IntelI7LbrSelect,
804 kCpumMsrWrFn_IntelI7SandyErrorControl,
805 kCpumMsrWrFn_IntelI7PowerCtl,
806 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
807 kCpumMsrWrFn_IntelI7PebsLdLat,
808 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
809 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
810 kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /**< R/O but found writable bits on a Silvermont CPU here. */
811 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
812 kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /**< R/O but found writable bits on a Silvermont CPU here. */
813 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
814 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
815 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
816 kCpumMsrWrFn_IntelI7RaplPp0Policy,
817 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
818 kCpumMsrWrFn_IntelI7RaplPp1Policy,
819 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
820 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
821 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
822 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
823 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
824 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
825 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
826 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
827 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
828 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
829 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
830 kCpumMsrWrFn_IntelCore1ExtConfig,
831 kCpumMsrWrFn_IntelCore1DtsCalControl,
832 kCpumMsrWrFn_IntelCore2PeciControl,
833
834 kCpumMsrWrFn_P6LastIntFromIp,
835 kCpumMsrWrFn_P6LastIntToIp,
836
837 kCpumMsrWrFn_AmdFam15hTscRate,
838 kCpumMsrWrFn_AmdFam15hLwpCfg,
839 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
840 kCpumMsrWrFn_AmdFam10hMc4MiscN,
841 kCpumMsrWrFn_AmdK8PerfCtlN,
842 kCpumMsrWrFn_AmdK8PerfCtrN,
843 kCpumMsrWrFn_AmdK8SysCfg,
844 kCpumMsrWrFn_AmdK8HwCr,
845 kCpumMsrWrFn_AmdK8IorrBaseN,
846 kCpumMsrWrFn_AmdK8IorrMaskN,
847 kCpumMsrWrFn_AmdK8TopOfMemN,
848 kCpumMsrWrFn_AmdK8NbCfg1,
849 kCpumMsrWrFn_AmdK8McXcptRedir,
850 kCpumMsrWrFn_AmdK8CpuNameN,
851 kCpumMsrWrFn_AmdK8HwThermalCtrl,
852 kCpumMsrWrFn_AmdK8SwThermalCtrl,
853 kCpumMsrWrFn_AmdK8FidVidControl,
854 kCpumMsrWrFn_AmdK8McCtlMaskN,
855 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
856 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
857 kCpumMsrWrFn_AmdK8IntPendingMessage,
858 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
859 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
860 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
861 kCpumMsrWrFn_AmdFam10hPStateControl,
862 kCpumMsrWrFn_AmdFam10hPStateStatus,
863 kCpumMsrWrFn_AmdFam10hPStateN,
864 kCpumMsrWrFn_AmdFam10hCofVidControl,
865 kCpumMsrWrFn_AmdFam10hCofVidStatus,
866 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
867 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
868 kCpumMsrWrFn_AmdK8SmmBase,
869 kCpumMsrWrFn_AmdK8SmmAddr,
870 kCpumMsrWrFn_AmdK8SmmMask,
871 kCpumMsrWrFn_AmdK8VmCr,
872 kCpumMsrWrFn_AmdK8IgnNe,
873 kCpumMsrWrFn_AmdK8SmmCtl,
874 kCpumMsrWrFn_AmdK8VmHSavePa,
875 kCpumMsrWrFn_AmdFam10hVmLockKey,
876 kCpumMsrWrFn_AmdFam10hSmmLockKey,
877 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
878 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
879 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
880 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
881 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
882 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
883 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
884 kCpumMsrWrFn_AmdK7MicrocodeCtl,
885 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
886 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
887 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
888 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
889 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
890 kCpumMsrWrFn_AmdK8PatchLoader,
891 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
892 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
893 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
894 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
895 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
896 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
897 kCpumMsrWrFn_AmdK7NodeId,
898 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
899 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
900 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
901 kCpumMsrWrFn_AmdK7LoadStoreCfg,
902 kCpumMsrWrFn_AmdK7InstrCacheCfg,
903 kCpumMsrWrFn_AmdK7DataCacheCfg,
904 kCpumMsrWrFn_AmdK7BusUnitCfg,
905 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
906 kCpumMsrWrFn_AmdFam15hFpuCfg,
907 kCpumMsrWrFn_AmdFam15hDecoderCfg,
908 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
909 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
910 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
911 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
912 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
913 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
914 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
915 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
916 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
917 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
918 kCpumMsrWrFn_AmdFam10hIbsOpRip,
919 kCpumMsrWrFn_AmdFam10hIbsOpData,
920 kCpumMsrWrFn_AmdFam10hIbsOpData2,
921 kCpumMsrWrFn_AmdFam10hIbsOpData3,
922 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
923 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
924 kCpumMsrWrFn_AmdFam10hIbsCtl,
925 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
926
927 kCpumMsrWrFn_Gim,
928
929 /** End of valid MSR write function indexes. */
930 kCpumMsrWrFn_End
931} CPUMMSRWRFN;
932
933/**
934 * MSR range.
935 */
936typedef struct CPUMMSRRANGE
937{
938 /** The first MSR. [0] */
939 uint32_t uFirst;
940 /** The last MSR. [4] */
941 uint32_t uLast;
942 /** The read function (CPUMMSRRDFN). [8] */
943 uint16_t enmRdFn;
944 /** The write function (CPUMMSRWRFN). [10] */
945 uint16_t enmWrFn;
946 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
947 * UINT16_MAX if not used by the read and write functions. [12] */
948 uint16_t offCpumCpu;
949 /** Reserved for future hacks. [14] */
950 uint16_t fReserved;
951 /** The init/read value. [16]
952 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
953 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
954 * offset into CPUM. */
955 uint64_t uValue;
956 /** The bits to ignore when writing. [24] */
957 uint64_t fWrIgnMask;
958 /** The bits that will cause a GP(0) when writing. [32]
959 * This is always checked prior to calling the write function. Using
960 * UINT64_MAX effectively marks the MSR as read-only. */
961 uint64_t fWrGpMask;
962 /** The register name, if applicable. [40] */
963 char szName[56];
964
965#ifdef VBOX_WITH_STATISTICS
966 /** The number of reads. */
967 STAMCOUNTER cReads;
968 /** The number of writes. */
969 STAMCOUNTER cWrites;
970 /** The number of times ignored bits were written. */
971 STAMCOUNTER cIgnoredBits;
972 /** The number of GPs generated. */
973 STAMCOUNTER cGps;
974#endif
975} CPUMMSRRANGE;
976#ifndef VBOX_FOR_DTRACE_LIB
977# ifdef VBOX_WITH_STATISTICS
978AssertCompileSize(CPUMMSRRANGE, 128);
979# else
980AssertCompileSize(CPUMMSRRANGE, 96);
981# endif
982#endif
983/** Pointer to an MSR range. */
984typedef CPUMMSRRANGE *PCPUMMSRRANGE;
985/** Pointer to a const MSR range. */
986typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
987
988
989/**
990 * MSRs.
991 * MSRs which are required while exploding features.
992 */
993typedef struct CPUMMSRS
994{
995 union
996 {
997 VMXMSRS vmx;
998 SVMMSRS svm;
999 } hwvirt;
1000} CPUMMSRS;
1001/** Pointer to an CPUMMSRS struct. */
1002typedef CPUMMSRS *PCPUMMSRS;
1003/** Pointer to a const CPUMMSRS struct. */
1004typedef CPUMMSRS const *PCCPUMMSRS;
1005
1006
1007/**
1008 * CPU features and quirks.
1009 * This is mostly exploded CPUID info.
1010 */
1011typedef struct CPUMFEATURES
1012{
1013 /** The CPU vendor (CPUMCPUVENDOR). */
1014 uint8_t enmCpuVendor;
1015 /** The CPU family. */
1016 uint8_t uFamily;
1017 /** The CPU model. */
1018 uint8_t uModel;
1019 /** The CPU stepping. */
1020 uint8_t uStepping;
1021 /** The microarchitecture. */
1022#ifndef VBOX_FOR_DTRACE_LIB
1023 CPUMMICROARCH enmMicroarch;
1024#else
1025 uint32_t enmMicroarch;
1026#endif
1027 /** The maximum physical address width of the CPU. */
1028 uint8_t cMaxPhysAddrWidth;
1029 /** The maximum linear address width of the CPU. */
1030 uint8_t cMaxLinearAddrWidth;
1031 /** Max size of the extended state (or FPU state if no XSAVE). */
1032 uint16_t cbMaxExtendedState;
1033
1034 /** Supports MSRs. */
1035 uint32_t fMsr : 1;
1036 /** Supports the page size extension (4/2 MB pages). */
1037 uint32_t fPse : 1;
1038 /** Supports 36-bit page size extension (4 MB pages can map memory above
1039 * 4GB). */
1040 uint32_t fPse36 : 1;
1041 /** Supports physical address extension (PAE). */
1042 uint32_t fPae : 1;
1043 /** Page attribute table (PAT) support (page level cache control). */
1044 uint32_t fPat : 1;
1045 /** Supports the FXSAVE and FXRSTOR instructions. */
1046 uint32_t fFxSaveRstor : 1;
1047 /** Supports the XSAVE and XRSTOR instructions. */
1048 uint32_t fXSaveRstor : 1;
1049 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
1050 uint32_t fOpSysXSaveRstor : 1;
1051 /** Supports MMX. */
1052 uint32_t fMmx : 1;
1053 /** Supports AMD extensions to MMX instructions. */
1054 uint32_t fAmdMmxExts : 1;
1055 /** Supports SSE. */
1056 uint32_t fSse : 1;
1057 /** Supports SSE2. */
1058 uint32_t fSse2 : 1;
1059 /** Supports SSE3. */
1060 uint32_t fSse3 : 1;
1061 /** Supports SSSE3. */
1062 uint32_t fSsse3 : 1;
1063 /** Supports SSE4.1. */
1064 uint32_t fSse41 : 1;
1065 /** Supports SSE4.2. */
1066 uint32_t fSse42 : 1;
1067 /** Supports AVX. */
1068 uint32_t fAvx : 1;
1069 /** Supports AVX2. */
1070 uint32_t fAvx2 : 1;
1071 /** Supports AVX512 foundation. */
1072 uint32_t fAvx512Foundation : 1;
1073 /** Supports RDTSC. */
1074 uint32_t fTsc : 1;
1075 /** Intel SYSENTER/SYSEXIT support */
1076 uint32_t fSysEnter : 1;
1077 /** First generation APIC. */
1078 uint32_t fApic : 1;
1079 /** Second generation APIC. */
1080 uint32_t fX2Apic : 1;
1081 /** Hypervisor present. */
1082 uint32_t fHypervisorPresent : 1;
1083 /** MWAIT & MONITOR instructions supported. */
1084 uint32_t fMonitorMWait : 1;
1085 /** MWAIT Extensions present. */
1086 uint32_t fMWaitExtensions : 1;
1087 /** Supports CMPXCHG16B in 64-bit mode. */
1088 uint32_t fMovCmpXchg16b : 1;
1089 /** Supports CLFLUSH. */
1090 uint32_t fClFlush : 1;
1091 /** Supports CLFLUSHOPT. */
1092 uint32_t fClFlushOpt : 1;
1093 /** Supports IA32_PRED_CMD.IBPB. */
1094 uint32_t fIbpb : 1;
1095 /** Supports IA32_SPEC_CTRL.IBRS. */
1096 uint32_t fIbrs : 1;
1097 /** Supports IA32_SPEC_CTRL.STIBP. */
1098 uint32_t fStibp : 1;
1099 /** Supports IA32_FLUSH_CMD. */
1100 uint32_t fFlushCmd : 1;
1101 /** Supports IA32_ARCH_CAP. */
1102 uint32_t fArchCap : 1;
1103 /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
1104 uint32_t fMdsClear : 1;
1105 /** Supports PCID. */
1106 uint32_t fPcid : 1;
1107 /** Supports INVPCID. */
1108 uint32_t fInvpcid : 1;
1109 /** Supports read/write FSGSBASE instructions. */
1110 uint32_t fFsGsBase : 1;
1111
1112 /** Supports AMD 3DNow instructions. */
1113 uint32_t f3DNow : 1;
1114 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
1115 uint32_t f3DNowPrefetch : 1;
1116
1117 /** AMD64: Supports long mode. */
1118 uint32_t fLongMode : 1;
1119 /** AMD64: SYSCALL/SYSRET support. */
1120 uint32_t fSysCall : 1;
1121 /** AMD64: No-execute page table bit. */
1122 uint32_t fNoExecute : 1;
1123 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
1124 uint32_t fLahfSahf : 1;
1125 /** AMD64: Supports RDTSCP. */
1126 uint32_t fRdTscP : 1;
1127 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
1128 uint32_t fMovCr8In32Bit : 1;
1129 /** AMD64: Supports XOP (similar to VEX3/AVX). */
1130 uint32_t fXop : 1;
1131
1132 /** Indicates that FPU instruction and data pointers may leak.
1133 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
1134 * is only saved and restored if an exception is pending. */
1135 uint32_t fLeakyFxSR : 1;
1136
1137 /** AMD64: Supports AMD SVM. */
1138 uint32_t fSvm : 1;
1139
1140 /** Support for Intel VMX. */
1141 uint32_t fVmx : 1;
1142
1143 /** Indicates that speculative execution control CPUID bits and MSRs are exposed.
1144 * The details are different for Intel and AMD but both have similar
1145 * functionality. */
1146 uint32_t fSpeculationControl : 1;
1147
1148 /** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
1149 * @remarks Only safe use after CPUM ring-0 init! */
1150 uint32_t fArchRdclNo : 1;
1151 /** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
1152 * @remarks Only safe use after CPUM ring-0 init! */
1153 uint32_t fArchIbrsAll : 1;
1154 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
1155 * @remarks Only safe use after CPUM ring-0 init! */
1156 uint32_t fArchRsbOverride : 1;
1157 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
1158 * @remarks Only safe use after CPUM ring-0 init! */
1159 uint32_t fArchVmmNeedNotFlushL1d : 1;
1160 /** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4).
1161 * @remarks Only safe use after CPUM ring-0 init! */
1162 uint32_t fArchMdsNo : 1;
1163
1164 /** Alignment padding / reserved for future use. */
1165 uint32_t fPadding : 8;
1166
1167 /** SVM: Supports Nested-paging. */
1168 uint32_t fSvmNestedPaging : 1;
1169 /** SVM: Support LBR (Last Branch Record) virtualization. */
1170 uint32_t fSvmLbrVirt : 1;
1171 /** SVM: Supports SVM lock. */
1172 uint32_t fSvmSvmLock : 1;
1173 /** SVM: Supports Next RIP save. */
1174 uint32_t fSvmNextRipSave : 1;
1175 /** SVM: Supports TSC rate MSR. */
1176 uint32_t fSvmTscRateMsr : 1;
1177 /** SVM: Supports VMCB clean bits. */
1178 uint32_t fSvmVmcbClean : 1;
1179 /** SVM: Supports Flush-by-ASID. */
1180 uint32_t fSvmFlusbByAsid : 1;
1181 /** SVM: Supports decode assist. */
1182 uint32_t fSvmDecodeAssists : 1;
1183 /** SVM: Supports Pause filter. */
1184 uint32_t fSvmPauseFilter : 1;
1185 /** SVM: Supports Pause filter threshold. */
1186 uint32_t fSvmPauseFilterThreshold : 1;
1187 /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
1188 uint32_t fSvmAvic : 1;
1189 /** SVM: Supports Virtualized VMSAVE/VMLOAD. */
1190 uint32_t fSvmVirtVmsaveVmload : 1;
1191 /** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
1192 uint32_t fSvmVGif : 1;
1193 /** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
1194 uint32_t fSvmGmet : 1;
1195 /** SVM: Padding / reserved for future features. */
1196 uint32_t fSvmPadding0 : 18;
1197 /** SVM: Maximum supported ASID. */
1198 uint32_t uSvmMaxAsid;
1199
1200 /** VMX: Maximum physical address width. */
1201 uint8_t cVmxMaxPhysAddrWidth;
1202 /** VMX: Padding / reserved for future. */
1203 uint8_t abVmxPadding[3];
1204 /** VMX: Padding / reserved for future. */
1205 uint32_t fVmxPadding0;
1206
1207 /** @name VMX basic controls.
1208 * @{ */
1209 /** VMX: Supports INS/OUTS VM-exit instruction info. */
1210 uint32_t fVmxInsOutInfo : 1;
1211 /** @} */
1212
1213 /** @name VMX Pin-based controls.
1214 * @{ */
1215 /** VMX: Supports external interrupt VM-exit. */
1216 uint32_t fVmxExtIntExit : 1;
1217 /** VMX: Supports NMI VM-exit. */
1218 uint32_t fVmxNmiExit : 1;
1219 /** VMX: Supports Virtual NMIs. */
1220 uint32_t fVmxVirtNmi : 1;
1221 /** VMX: Supports preemption timer. */
1222 uint32_t fVmxPreemptTimer : 1;
1223 /** VMX: Supports posted interrupts. */
1224 uint32_t fVmxPostedInt : 1;
1225 /** @} */
1226
1227 /** @name VMX Processor-based controls.
1228 * @{ */
1229 /** VMX: Supports Interrupt-window exiting. */
1230 uint32_t fVmxIntWindowExit : 1;
1231 /** VMX: Supports TSC offsetting. */
1232 uint32_t fVmxTscOffsetting : 1;
1233 /** VMX: Supports HLT exiting. */
1234 uint32_t fVmxHltExit : 1;
1235 /** VMX: Supports INVLPG exiting. */
1236 uint32_t fVmxInvlpgExit : 1;
1237 /** VMX: Supports MWAIT exiting. */
1238 uint32_t fVmxMwaitExit : 1;
1239 /** VMX: Supports RDPMC exiting. */
1240 uint32_t fVmxRdpmcExit : 1;
1241 /** VMX: Supports RDTSC exiting. */
1242 uint32_t fVmxRdtscExit : 1;
1243 /** VMX: Supports CR3-load exiting. */
1244 uint32_t fVmxCr3LoadExit : 1;
1245 /** VMX: Supports CR3-store exiting. */
1246 uint32_t fVmxCr3StoreExit : 1;
1247 /** VMX: Supports CR8-load exiting. */
1248 uint32_t fVmxCr8LoadExit : 1;
1249 /** VMX: Supports CR8-store exiting. */
1250 uint32_t fVmxCr8StoreExit : 1;
1251 /** VMX: Supports TPR shadow. */
1252 uint32_t fVmxUseTprShadow : 1;
1253 /** VMX: Supports NMI-window exiting. */
1254 uint32_t fVmxNmiWindowExit : 1;
1255 /** VMX: Supports Mov-DRx exiting. */
1256 uint32_t fVmxMovDRxExit : 1;
1257 /** VMX: Supports Unconditional I/O exiting. */
1258 uint32_t fVmxUncondIoExit : 1;
1259 /** VMX: Supportgs I/O bitmaps. */
1260 uint32_t fVmxUseIoBitmaps : 1;
1261 /** VMX: Supports Monitor Trap Flag. */
1262 uint32_t fVmxMonitorTrapFlag : 1;
1263 /** VMX: Supports MSR bitmap. */
1264 uint32_t fVmxUseMsrBitmaps : 1;
1265 /** VMX: Supports MONITOR exiting. */
1266 uint32_t fVmxMonitorExit : 1;
1267 /** VMX: Supports PAUSE exiting. */
1268 uint32_t fVmxPauseExit : 1;
1269 /** VMX: Supports secondary processor-based VM-execution controls. */
1270 uint32_t fVmxSecondaryExecCtls : 1;
1271 /** @} */
1272
1273 /** @name VMX Secondary processor-based controls.
1274 * @{ */
1275 /** VMX: Supports virtualize-APIC access. */
1276 uint32_t fVmxVirtApicAccess : 1;
1277 /** VMX: Supports EPT (Extended Page Tables). */
1278 uint32_t fVmxEpt : 1;
1279 /** VMX: Supports descriptor-table exiting. */
1280 uint32_t fVmxDescTableExit : 1;
1281 /** VMX: Supports RDTSCP. */
1282 uint32_t fVmxRdtscp : 1;
1283 /** VMX: Supports virtualize-x2APIC mode. */
1284 uint32_t fVmxVirtX2ApicMode : 1;
1285 /** VMX: Supports VPID. */
1286 uint32_t fVmxVpid : 1;
1287 /** VMX: Supports WBIND exiting. */
1288 uint32_t fVmxWbinvdExit : 1;
1289 /** VMX: Supports Unrestricted guest. */
1290 uint32_t fVmxUnrestrictedGuest : 1;
1291 /** VMX: Supports APIC-register virtualization. */
1292 uint32_t fVmxApicRegVirt : 1;
1293 /** VMX: Supports virtual-interrupt delivery. */
1294 uint32_t fVmxVirtIntDelivery : 1;
1295 /** VMX: Supports Pause-loop exiting. */
1296 uint32_t fVmxPauseLoopExit : 1;
1297 /** VMX: Supports RDRAND exiting. */
1298 uint32_t fVmxRdrandExit : 1;
1299 /** VMX: Supports INVPCID. */
1300 uint32_t fVmxInvpcid : 1;
1301 /** VMX: Supports VM functions. */
1302 uint32_t fVmxVmFunc : 1;
1303 /** VMX: Supports VMCS shadowing. */
1304 uint32_t fVmxVmcsShadowing : 1;
1305 /** VMX: Supports RDSEED exiting. */
1306 uint32_t fVmxRdseedExit : 1;
1307 /** VMX: Supports PML. */
1308 uint32_t fVmxPml : 1;
1309 /** VMX: Supports EPT-violations \#VE. */
1310 uint32_t fVmxEptXcptVe : 1;
1311 /** VMX: Supports XSAVES/XRSTORS. */
1312 uint32_t fVmxXsavesXrstors : 1;
1313 /** VMX: Supports TSC scaling. */
1314 uint32_t fVmxUseTscScaling : 1;
1315 /** @} */
1316
1317 /** @name VMX VM-entry controls.
1318 * @{ */
1319 /** VMX: Supports load-debug controls on VM-entry. */
1320 uint32_t fVmxEntryLoadDebugCtls : 1;
1321 /** VMX: Supports IA32e mode guest. */
1322 uint32_t fVmxIa32eModeGuest : 1;
1323 /** VMX: Supports load guest EFER MSR on VM-entry. */
1324 uint32_t fVmxEntryLoadEferMsr : 1;
1325 /** VMX: Supports load guest PAT MSR on VM-entry. */
1326 uint32_t fVmxEntryLoadPatMsr : 1;
1327 /** @} */
1328
1329 /** @name VMX VM-exit controls.
1330 * @{ */
1331 /** VMX: Supports save debug controls on VM-exit. */
1332 uint32_t fVmxExitSaveDebugCtls : 1;
1333 /** VMX: Supports host-address space size. */
1334 uint32_t fVmxHostAddrSpaceSize : 1;
1335 /** VMX: Supports acknowledge external interrupt on VM-exit. */
1336 uint32_t fVmxExitAckExtInt : 1;
1337 /** VMX: Supports save guest PAT MSR on VM-exit. */
1338 uint32_t fVmxExitSavePatMsr : 1;
1339 /** VMX: Supports load hsot PAT MSR on VM-exit. */
1340 uint32_t fVmxExitLoadPatMsr : 1;
1341 /** VMX: Supports save guest EFER MSR on VM-exit. */
1342 uint32_t fVmxExitSaveEferMsr : 1;
1343 /** VMX: Supports load host EFER MSR on VM-exit. */
1344 uint32_t fVmxExitLoadEferMsr : 1;
1345 /** VMX: Supports save VMX preemption timer on VM-exit. */
1346 uint32_t fVmxSavePreemptTimer : 1;
1347 /** @} */
1348
1349 /** @name VMX Miscellaneous data.
1350 * @{ */
1351 /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
1352 uint32_t fVmxExitSaveEferLma : 1;
1353 /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
1354 uint32_t fVmxIntelPt : 1;
1355 /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1356 * VMWRITE cannot modify read-only VM-exit information fields. */
1357 uint32_t fVmxVmwriteAll : 1;
1358 /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
1359 * length instructions. */
1360 uint32_t fVmxEntryInjectSoftInt : 1;
1361 /** @} */
1362
1363 /** VMX: Padding / reserved for future features. */
1364 uint32_t fVmxPadding1 : 1;
1365 uint32_t fVmxPadding2;
1366} CPUMFEATURES;
1367#ifndef VBOX_FOR_DTRACE_LIB
1368AssertCompileSize(CPUMFEATURES, 48);
1369#endif
1370/** Pointer to a CPU feature structure. */
1371typedef CPUMFEATURES *PCPUMFEATURES;
1372/** Pointer to a const CPU feature structure. */
1373typedef CPUMFEATURES const *PCCPUMFEATURES;
1374
1375
1376/**
1377 * CPU database entry.
1378 */
1379typedef struct CPUMDBENTRY
1380{
1381 /** The CPU name. */
1382 const char *pszName;
1383 /** The full CPU name. */
1384 const char *pszFullName;
1385 /** The CPU vendor (CPUMCPUVENDOR). */
1386 uint8_t enmVendor;
1387 /** The CPU family. */
1388 uint8_t uFamily;
1389 /** The CPU model. */
1390 uint8_t uModel;
1391 /** The CPU stepping. */
1392 uint8_t uStepping;
1393 /** The microarchitecture. */
1394 CPUMMICROARCH enmMicroarch;
1395 /** Scalable bus frequency used for reporting other frequencies. */
1396 uint64_t uScalableBusFreq;
1397 /** Flags - CPUMDB_F_XXX. */
1398 uint32_t fFlags;
1399 /** The maximum physical address with of the CPU. This should correspond to
1400 * the value in CPUID leaf 0x80000008 when present. */
1401 uint8_t cMaxPhysAddrWidth;
1402 /** The MXCSR mask. */
1403 uint32_t fMxCsrMask;
1404 /** Pointer to an array of CPUID leaves. */
1405 PCCPUMCPUIDLEAF paCpuIdLeaves;
1406 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
1407 uint32_t cCpuIdLeaves;
1408 /** The method used to deal with unknown CPUID leaves. */
1409 CPUMUNKNOWNCPUID enmUnknownCpuId;
1410 /** The default unknown CPUID value. */
1411 CPUMCPUID DefUnknownCpuId;
1412
1413 /** MSR mask. Several microarchitectures ignore the higher bits of ECX in
1414 * the RDMSR and WRMSR instructions. */
1415 uint32_t fMsrMask;
1416
1417 /** The number of ranges in the table pointed to b paMsrRanges. */
1418 uint32_t cMsrRanges;
1419 /** MSR ranges for this CPU. */
1420 PCCPUMMSRRANGE paMsrRanges;
1421} CPUMDBENTRY;
1422/** Pointer to a const CPU database entry. */
1423typedef CPUMDBENTRY const *PCCPUMDBENTRY;
1424
1425/** @name CPUMDB_F_XXX - CPUDBENTRY::fFlags
1426 * @{ */
1427/** Should execute all in IEM.
1428 * @todo Implement this - currently done in Main... */
1429#define CPUMDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
1430/** @} */
1431
1432
1433
1434#ifndef VBOX_FOR_DTRACE_LIB
1435
1436/** @name Guest Register Getters.
1437 * @{ */
1438VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR);
1439VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit);
1440VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden);
1441VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu);
1442VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
1443VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu);
1444VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu);
1445VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu);
1446VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu);
1447VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu);
1448VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue);
1449VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu);
1450VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu);
1451VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu);
1452VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu);
1453VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu);
1454VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu);
1455VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu);
1456VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu);
1457VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu);
1458VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu);
1459VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu);
1460VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu);
1461VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu);
1462VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu);
1463VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu);
1464VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu);
1465VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu);
1466VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
1467VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
1468VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu);
1469VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu);
1470VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu);
1471VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu);
1472VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu);
1473VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu);
1474VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1475VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t iLeaf, uint32_t iSubLeaf,
1476 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
1477VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu);
1478VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu);
1479VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPU pVCpu);
1480VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue);
1481VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue);
1482VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1483VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM);
1484VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1485VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM);
1486/** @} */
1487
1488/** @name Guest Register Setters.
1489 * @{ */
1490VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1491VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1492VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1493VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1494VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0);
1495VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1496VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1497VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1498VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0);
1499VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1);
1500VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2);
1501VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3);
1502VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1503VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7);
1504VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value);
1505VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue);
1506VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1507VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1508VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1509VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1510VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1511VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1512VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1513VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1514VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1515VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1516VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1517VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1518VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1519VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1520VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1521VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1522VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1523VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1524VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1525VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1526VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
1527VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1528VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue);
1529VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu);
1530VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue);
1531VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu);
1532VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM);
1533/** @} */
1534
1535
1536/** @name Misc Guest Predicate Functions.
1537 * @{ */
1538VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1539VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu);
1540VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu);
1541VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu);
1542VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu);
1543VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu);
1544VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu);
1545VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu);
1546VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu);
1547VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu);
1548VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu);
1549/** @} */
1550
1551/** @name Nested Hardware-Virtualization Helpers.
1552 * @{ */
1553VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu);
1554VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu);
1555VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1556VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1557
1558/* SVM helpers. */
1559VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1560VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1561VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx);
1562VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx);
1563VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
1564VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1565 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
1566 PSVMIOIOEXITINFO pIoExitInfo);
1567VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit);
1568
1569/* VMX helpers. */
1570VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField);
1571VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess);
1572VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3);
1573VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc);
1574VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick);
1575VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu);
1576VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr);
1577/** @} */
1578
1579/** @name Externalized State Helpers.
1580 * @{ */
1581/** @def CPUM_ASSERT_NOT_EXTRN
1582 * Macro for asserting that @a a_fNotExtrn are present.
1583 *
1584 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1585 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
1586 *
1587 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1588 */
1589#define CPUM_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
1590 AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fNotExtrn)), \
1591 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fNotExtrn)))
1592
1593/** @def CPUM_IMPORT_EXTRN_RET
1594 * Macro for making sure the state specified by @a fExtrnImport is present,
1595 * calling CPUMImportGuestStateOnDemand() to get it if necessary.
1596 *
1597 * Will return if CPUMImportGuestStateOnDemand() fails.
1598 *
1599 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1600 * @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1601 * @thread EMT(a_pVCpu)
1602 *
1603 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1604 */
1605#define CPUM_IMPORT_EXTRN_RET(a_pVCpu, a_fExtrnImport) \
1606 do { \
1607 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1608 { /* already present, consider this likely */ } \
1609 else \
1610 { \
1611 int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1612 AssertRCReturn(rcCpumImport, rcCpumImport); \
1613 } \
1614 } while (0)
1615
1616/** @def CPUM_IMPORT_EXTRN_RCSTRICT
1617 * Macro for making sure the state specified by @a fExtrnImport is present,
1618 * calling CPUMImportGuestStateOnDemand() to get it if necessary.
1619 *
1620 * Will update a_rcStrict if CPUMImportGuestStateOnDemand() fails.
1621 *
1622 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1623 * @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1624 * @param a_rcStrict Strict status code variable to update on failure.
1625 * @thread EMT(a_pVCpu)
1626 *
1627 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1628 */
1629#define CPUM_IMPORT_EXTRN_RCSTRICT(a_pVCpu, a_fExtrnImport, a_rcStrict) \
1630 do { \
1631 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1632 { /* already present, consider this likely */ } \
1633 else \
1634 { \
1635 int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1636 AssertStmt(RT_SUCCESS(rcCpumImport) || RT_FAILURE_NP(a_rcStrict), a_rcStrict = rcCpumImport); \
1637 } \
1638 } while (0)
1639
1640VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport);
1641/** @} */
1642
1643#if (!defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS) && defined(RT_ARCH_AMD64)) || defined(DOXYGEN_RUNNING)
1644/** @name Inlined Guest Getters and predicates Functions.
1645 * @{ */
1646
1647/**
1648 * Gets valid CR0 bits for the guest.
1649 *
1650 * @returns Valid CR0 bits.
1651 */
1652DECLINLINE(uint64_t) CPUMGetGuestCR0ValidMask(void)
1653{
1654 return ( X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
1655 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
1656 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG);
1657}
1658
1659/**
1660 * Tests if the guest is running in real mode or not.
1661 *
1662 * @returns true if in real mode, otherwise false.
1663 * @param pCtx Current CPU context.
1664 */
1665DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCCPUMCTX pCtx)
1666{
1667 return !(pCtx->cr0 & X86_CR0_PE);
1668}
1669
1670/**
1671 * Tests if the guest is running in real or virtual 8086 mode.
1672 *
1673 * @returns @c true if it is, @c false if not.
1674 * @param pCtx Current CPU context.
1675 */
1676DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCCPUMCTX pCtx)
1677{
1678 return !(pCtx->cr0 & X86_CR0_PE)
1679 || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1680}
1681
1682/**
1683 * Tests if the guest is running in virtual 8086 mode.
1684 *
1685 * @returns @c true if it is, @c false if not.
1686 * @param pCtx Current CPU context.
1687 */
1688DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCCPUMCTX pCtx)
1689{
1690 return (pCtx->eflags.Bits.u1VM == 1);
1691}
1692
1693/**
1694 * Tests if the guest is running in paged protected or not.
1695 *
1696 * @returns true if in paged protected mode, otherwise false.
1697 * @param pCtx Current CPU context.
1698 */
1699DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1700{
1701 return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1702}
1703
1704/**
1705 * Tests if the guest is running in long mode or not.
1706 *
1707 * @returns true if in long mode, otherwise false.
1708 * @param pCtx Current CPU context.
1709 */
1710DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCCPUMCTX pCtx)
1711{
1712 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1713}
1714
1715VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1716
1717/**
1718 * Tests if the guest is running in 64 bits mode or not.
1719 *
1720 * @returns true if in 64 bits protected mode, otherwise false.
1721 * @param pCtx Current CPU context.
1722 */
1723DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1724{
1725 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1726 return false;
1727 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1728 return CPUMIsGuestIn64BitCodeSlow(pCtx);
1729 return pCtx->cs.Attr.n.u1Long;
1730}
1731
1732/**
1733 * Tests if the guest has paging enabled or not.
1734 *
1735 * @returns true if paging is enabled, otherwise false.
1736 * @param pCtx Current CPU context.
1737 */
1738DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCCPUMCTX pCtx)
1739{
1740 return !!(pCtx->cr0 & X86_CR0_PG);
1741}
1742
1743/**
1744 * Tests if the guest is running in PAE mode or not.
1745 *
1746 * @returns true if in PAE mode, otherwise false.
1747 * @param pCtx Current CPU context.
1748 */
1749DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCCPUMCTX pCtx)
1750{
1751 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1752 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1753 return ( (pCtx->cr4 & X86_CR4_PAE)
1754 && CPUMIsGuestPagingEnabledEx(pCtx)
1755 && !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1756}
1757
1758/**
1759 * Tests if the guest has AMD SVM enabled or not.
1760 *
1761 * @returns true if SMV is enabled, otherwise false.
1762 * @param pCtx Current CPU context.
1763 */
1764DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1765{
1766 return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1767}
1768
1769/**
1770 * Tests if the guest has Intel VT-x enabled or not.
1771 *
1772 * @returns true if VMX is enabled, otherwise false.
1773 * @param pCtx Current CPU context.
1774 */
1775DECLINLINE(bool) CPUMIsGuestVmxEnabled(PCCPUMCTX pCtx)
1776{
1777 return RT_BOOL(pCtx->cr4 & X86_CR4_VMXE);
1778}
1779
1780/**
1781 * Returns the guest's global-interrupt (GIF) flag.
1782 *
1783 * @returns true when global-interrupts are enabled, otherwise false.
1784 * @param pCtx Current CPU context.
1785 */
1786DECLINLINE(bool) CPUMGetGuestGif(PCCPUMCTX pCtx)
1787{
1788 return pCtx->hwvirt.fGif;
1789}
1790
1791/**
1792 * Sets the guest's global-interrupt flag (GIF).
1793 *
1794 * @param pCtx Current CPU context.
1795 * @param fGif The value to set.
1796 */
1797DECLINLINE(void) CPUMSetGuestGif(PCPUMCTX pCtx, bool fGif)
1798{
1799 pCtx->hwvirt.fGif = fGif;
1800}
1801
1802/**
1803 * Checks if we are executing inside an SVM nested hardware-virtualized guest.
1804 *
1805 * @returns @c true if in SVM nested-guest mode, @c false otherwise.
1806 * @param pCtx Current CPU context.
1807 */
1808DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
1809{
1810 /*
1811 * With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
1812 * See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
1813 */
1814#ifndef IN_RC
1815 if ( pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM
1816 || !(pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN))
1817 return false;
1818 return true;
1819#else
1820 NOREF(pCtx);
1821 return false;
1822#endif
1823}
1824
1825/**
1826 * Checks if the guest is in VMX non-root operation.
1827 *
1828 * @returns @c true if in VMX non-root operation, @c false otherwise.
1829 * @param pCtx Current CPU context.
1830 */
1831DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx)
1832{
1833#ifndef IN_RC
1834 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
1835 return false;
1836 Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
1837 return pCtx->hwvirt.vmx.fInVmxNonRootMode;
1838#else
1839 NOREF(pCtx);
1840 return false;
1841#endif
1842}
1843
1844/**
1845 * Checks if we are executing inside an SVM or VMX nested hardware-virtualized
1846 * guest.
1847 *
1848 * @returns @c true if in nested-guest mode, @c false otherwise.
1849 * @param pCtx Current CPU context.
1850 */
1851DECLINLINE(bool) CPUMIsGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
1852{
1853 return CPUMIsGuestInVmxNonRootMode(pCtx) || CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
1854}
1855
1856/**
1857 * Checks if the guest is in VMX root operation.
1858 *
1859 * @returns @c true if in VMX root operation, @c false otherwise.
1860 * @param pCtx Current CPU context.
1861 */
1862DECLINLINE(bool) CPUMIsGuestInVmxRootMode(PCCPUMCTX pCtx)
1863{
1864#ifndef IN_RC
1865 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
1866 return false;
1867 return pCtx->hwvirt.vmx.fInVmxRootMode;
1868#else
1869 NOREF(pCtx);
1870 return false;
1871#endif
1872}
1873
1874# ifndef IN_RC
1875
1876/**
1877 * Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
1878 * active.
1879 *
1880 * @returns @c true if in intercept is set, @c false otherwise.
1881 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1882 * @param pCtx Pointer to the context.
1883 * @param fIntercept The SVM control/instruction intercept, see
1884 * SVM_CTRL_INTERCEPT_*.
1885 */
1886DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint64_t fIntercept)
1887{
1888 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1889 return false;
1890 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1891 Assert(pVmcb);
1892 uint64_t u64Intercepts;
1893 if (!HMGetGuestSvmCtrlIntercepts(pVCpu, &u64Intercepts))
1894 u64Intercepts = pVmcb->ctrl.u64InterceptCtrl;
1895 return RT_BOOL(u64Intercepts & fIntercept);
1896}
1897
1898/**
1899 * Checks if the nested-guest VMCB has the specified CR read intercept active.
1900 *
1901 * @returns @c true if in intercept is set, @c false otherwise.
1902 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1903 * @param pCtx Pointer to the context.
1904 * @param uCr The CR register number (0 to 15).
1905 */
1906DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1907{
1908 Assert(uCr < 16);
1909 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1910 return false;
1911 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1912 Assert(pVmcb);
1913 uint16_t u16Intercepts;
1914 if (!HMGetGuestSvmReadCRxIntercepts(pVCpu, &u16Intercepts))
1915 u16Intercepts = pVmcb->ctrl.u16InterceptRdCRx;
1916 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
1917}
1918
1919/**
1920 * Checks if the nested-guest VMCB has the specified CR write intercept active.
1921 *
1922 * @returns @c true if in intercept is set, @c false otherwise.
1923 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1924 * @param pCtx Pointer to the context.
1925 * @param uCr The CR register number (0 to 15).
1926 */
1927DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1928{
1929 Assert(uCr < 16);
1930 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1931 return false;
1932 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1933 Assert(pVmcb);
1934 uint16_t u16Intercepts;
1935 if (!HMGetGuestSvmWriteCRxIntercepts(pVCpu, &u16Intercepts))
1936 u16Intercepts = pVmcb->ctrl.u16InterceptWrCRx;
1937 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
1938}
1939
1940/**
1941 * Checks if the nested-guest VMCB has the specified DR read intercept active.
1942 *
1943 * @returns @c true if in intercept is set, @c false otherwise.
1944 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1945 * @param pCtx Pointer to the context.
1946 * @param uDr The DR register number (0 to 15).
1947 */
1948DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1949{
1950 Assert(uDr < 16);
1951 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1952 return false;
1953 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1954 Assert(pVmcb);
1955 uint16_t u16Intercepts;
1956 if (!HMGetGuestSvmReadDRxIntercepts(pVCpu, &u16Intercepts))
1957 u16Intercepts = pVmcb->ctrl.u16InterceptRdDRx;
1958 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
1959}
1960
1961/**
1962 * Checks if the nested-guest VMCB has the specified DR write intercept active.
1963 *
1964 * @returns @c true if in intercept is set, @c false otherwise.
1965 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1966 * @param pCtx Pointer to the context.
1967 * @param uDr The DR register number (0 to 15).
1968 */
1969DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1970{
1971 Assert(uDr < 16);
1972 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1973 return false;
1974 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1975 Assert(pVmcb);
1976 uint16_t u16Intercepts;
1977 if (!HMGetGuestSvmWriteDRxIntercepts(pVCpu, &u16Intercepts))
1978 u16Intercepts = pVmcb->ctrl.u16InterceptWrDRx;
1979 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
1980}
1981
1982/**
1983 * Checks if the nested-guest VMCB has the specified exception intercept active.
1984 *
1985 * @returns @c true if in intercept is active, @c false otherwise.
1986 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1987 * @param pCtx Pointer to the context.
1988 * @param uVector The exception / interrupt vector.
1989 */
1990DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
1991{
1992 Assert(uVector <= X86_XCPT_LAST);
1993 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1994 return false;
1995 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1996 Assert(pVmcb);
1997 uint32_t u32Intercepts;
1998 if (!HMGetGuestSvmXcptIntercepts(pVCpu, &u32Intercepts))
1999 u32Intercepts = pVmcb->ctrl.u32InterceptXcpt;
2000 return RT_BOOL(u32Intercepts & RT_BIT(uVector));
2001}
2002
2003/**
2004 * Checks if the nested-guest VMCB has virtual-interrupt masking enabled.
2005 *
2006 * @returns @c true if virtual-interrupts are masked, @c false otherwise.
2007 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2008 * @param pCtx Pointer to the context.
2009 *
2010 * @remarks Should only be called when SVM feature is exposed to the guest.
2011 */
2012DECLINLINE(bool) CPUMIsGuestSvmVirtIntrMasking(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2013{
2014 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2015 return false;
2016 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2017 Assert(pVmcb);
2018 bool fVIntrMasking;
2019 if (!HMGetGuestSvmVirtIntrMasking(pVCpu, &fVIntrMasking))
2020 fVIntrMasking = pVmcb->ctrl.IntCtrl.n.u1VIntrMasking;
2021 return fVIntrMasking;
2022}
2023
2024/**
2025 * Checks if the nested-guest VMCB has nested-paging enabled.
2026 *
2027 * @returns @c true if nested-paging is enabled, @c false otherwise.
2028 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2029 * @param pCtx Pointer to the context.
2030 *
2031 * @remarks Should only be called when SVM feature is exposed to the guest.
2032 */
2033DECLINLINE(bool) CPUMIsGuestSvmNestedPagingEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2034{
2035 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2036 return false;
2037 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2038 Assert(pVmcb);
2039 bool fNestedPaging;
2040 if (!HMGetGuestSvmNestedPaging(pVCpu, &fNestedPaging))
2041 fNestedPaging = pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging;
2042 return fNestedPaging;
2043}
2044
2045/**
2046 * Gets the nested-guest VMCB pause-filter count.
2047 *
2048 * @returns The pause-filter count.
2049 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2050 * @param pCtx Pointer to the context.
2051 *
2052 * @remarks Should only be called when SVM feature is exposed to the guest.
2053 */
2054DECLINLINE(uint16_t) CPUMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2055{
2056 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2057 return false;
2058 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2059 Assert(pVmcb);
2060 uint16_t u16PauseFilterCount;
2061 if (!HMGetGuestSvmPauseFilterCount(pVCpu, &u16PauseFilterCount))
2062 u16PauseFilterCount = pVmcb->ctrl.u16PauseFilterCount;
2063 return u16PauseFilterCount;
2064}
2065
2066/**
2067 * Updates the NextRIP (NRIP) field in the nested-guest VMCB.
2068 *
2069 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2070 * @param pCtx Pointer to the context.
2071 * @param cbInstr The length of the current instruction in bytes.
2072 *
2073 * @remarks Should only be called when SVM feature is exposed to the guest.
2074 */
2075DECLINLINE(void) CPUMGuestSvmUpdateNRip(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t cbInstr)
2076{
2077 RT_NOREF(pVCpu);
2078 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2079 PSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2080 Assert(pVmcb);
2081 pVmcb->ctrl.u64NextRIP = pCtx->rip + cbInstr;
2082}
2083
2084/**
2085 * Checks whether one of the given Pin-based VM-execution controls are set when
2086 * executing a nested-guest.
2087 *
2088 * @returns @c true if set, @c false otherwise.
2089 * @param pCtx Pointer to the context.
2090 * @param uPinCtls The Pin-based VM-execution controls to check.
2091 *
2092 * @remarks This does not check if all given controls are set if more than one
2093 * control is passed in @a uPinCtl.
2094 */
2095DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls)
2096{
2097 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2098 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2099 Assert(pVmcs);
2100 return RT_BOOL(pVmcs->u32PinCtls & uPinCtls);
2101}
2102
2103/**
2104 * Checks whether one of the given Processor-based VM-execution controls are set
2105 * when executing a nested-guest.
2106 *
2107 * @returns @c true if set, @c false otherwise.
2108 * @param pCtx Pointer to the context.
2109 * @param uProcCtls The Processor-based VM-execution controls to check.
2110 *
2111 * @remarks This does not check if all given controls are set if more than one
2112 * control is passed in @a uProcCtls.
2113 */
2114DECLINLINE(bool) CPUMIsGuestVmxProcCtlsSet(PCCPUMCTX pCtx, uint32_t uProcCtls)
2115{
2116 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2117 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2118 Assert(pVmcs);
2119 return RT_BOOL(pVmcs->u32ProcCtls & uProcCtls);
2120}
2121
2122/**
2123 * Checks whether one of the given Secondary Processor-based VM-execution controls
2124 * are set when executing a nested-guest.
2125 *
2126 * @returns @c true if set, @c false otherwise.
2127 * @param pCtx Pointer to the context.
2128 * @param uProcCtls2 The Secondary Processor-based VM-execution controls to
2129 * check.
2130 *
2131 * @remarks This does not check if all given controls are set if more than one
2132 * control is passed in @a uProcCtls2.
2133 */
2134DECLINLINE(bool) CPUMIsGuestVmxProcCtls2Set(PCCPUMCTX pCtx, uint32_t uProcCtls2)
2135{
2136 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2137 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2138 Assert(pVmcs);
2139 return RT_BOOL(pVmcs->u32ProcCtls2 & uProcCtls2);
2140}
2141
2142/**
2143 * Checks whether one of the given VM-exit controls are set when executing a
2144 * nested-guest.
2145 *
2146 * @returns @c true if set, @c false otherwise.
2147 * @param pCtx Pointer to the context.
2148 * @param uExitCtls The VM-exit controls to check.
2149 *
2150 * @remarks This does not check if all given controls are set if more than one
2151 * control is passed in @a uExitCtls.
2152 */
2153DECLINLINE(bool) CPUMIsGuestVmxExitCtlsSet(PCCPUMCTX pCtx, uint32_t uExitCtls)
2154{
2155 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2156 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2157 Assert(pVmcs);
2158 return RT_BOOL(pVmcs->u32ExitCtls & uExitCtls);
2159}
2160
2161/**
2162 * Checks whether one of the given VM-entry controls are set when executing a
2163 * nested-guest.
2164 *
2165 * @returns @c true if set, @c false otherwise.
2166 * @param pCtx Pointer to the context.
2167 * @param uEntryCtls The VM-entry controls to check.
2168 *
2169 * @remarks This does not check if all given controls are set if more than one
2170 * control is passed in @a uEntryCtls.
2171 */
2172DECLINLINE(bool) CPUMIsGuestVmxEntryCtlsSet(PCCPUMCTX pCtx, uint32_t uEntryCtls)
2173{
2174 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2175 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2176 Assert(pVmcs);
2177 return RT_BOOL(pVmcs->u32EntryCtls & uEntryCtls);
2178}
2179
2180/**
2181 * Checks whether events injected in the nested-guest are subject to VM-exit checks.
2182 *
2183 * @returns @c true if set, @c false otherwise.
2184 * @param pCtx Pointer to the context.
2185 */
2186DECLINLINE(bool) CPUMIsGuestVmxInterceptEvents(PCCPUMCTX pCtx)
2187{
2188 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2189 return pCtx->hwvirt.vmx.fInterceptEvents;
2190}
2191
2192/**
2193 * Sets whether events injected in the nested-guest are subject to VM-exit checks.
2194 *
2195 * @param pCtx Pointer to the context.
2196 * @param fIntercept Whether to subject injected events to VM-exits or not.
2197 */
2198DECLINLINE(void) CPUMSetGuestVmxInterceptEvents(PCPUMCTX pCtx, bool fInterceptEvents)
2199{
2200 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2201 pCtx->hwvirt.vmx.fInterceptEvents = fInterceptEvents;
2202}
2203
2204/**
2205 * Checks whether the given exception causes a VM-exit.
2206 *
2207 * The exception type include hardware exceptions, software exceptions (#BP, #OF)
2208 * and privileged software exceptions (#DB generated by INT1/ICEBP).
2209 *
2210 * Software interrupts do -not- cause VM-exits and hence must not be used with this
2211 * function.
2212 *
2213 * @returns @c true if the exception causes a VM-exit, @c false otherwise.
2214 * @param pCtx Pointer to the context.
2215 * @param uVector The exception vector.
2216 * @param uErrCode The error code associated with the exception. Pass 0 if not
2217 * applicable.
2218 */
2219DECLINLINE(bool) CPUMIsGuestVmxXcptInterceptSet(PCCPUMCTX pCtx, uint8_t uVector, uint32_t uErrCode)
2220{
2221 Assert(uVector <= X86_XCPT_LAST);
2222
2223 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2224 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2225 Assert(pVmcs);
2226
2227 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
2228 if (uVector == X86_XCPT_NMI)
2229 return RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
2230
2231 /* Page-faults are subject to masking using its error code. */
2232 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
2233 if (uVector == X86_XCPT_PF)
2234 {
2235 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
2236 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
2237 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
2238 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
2239 }
2240
2241 /* Consult the exception bitmap for all other exceptions. */
2242 if (fXcptBitmap & RT_BIT(uVector))
2243 return true;
2244 return false;
2245}
2246
2247/**
2248 * Implements VMSucceed for VMX instruction success.
2249 *
2250 * @param pVCpu The cross context virtual CPU structure.
2251 */
2252DECLINLINE(void) CPUMSetGuestVmxVmSucceed(PCPUMCTX pCtx)
2253{
2254 pCtx->eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2255}
2256
2257/**
2258 * Implements VMFailInvalid for VMX instruction failure.
2259 *
2260 * @param pVCpu The cross context virtual CPU structure.
2261 */
2262DECLINLINE(void) CPUMSetGuestVmxVmFailInvalid(PCPUMCTX pCtx)
2263{
2264 pCtx->eflags.u32 &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2265 pCtx->eflags.u32 |= X86_EFL_CF;
2266}
2267
2268/**
2269 * Implements VMFailValid for VMX instruction failure.
2270 *
2271 * @param pVCpu The cross context virtual CPU structure.
2272 * @param enmInsErr The VM instruction error.
2273 */
2274DECLINLINE(void) CPUMSetGuestVmxVmFailValid(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2275{
2276 pCtx->eflags.u32 &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2277 pCtx->eflags.u32 |= X86_EFL_ZF;
2278 pCtx->hwvirt.vmx.CTX_SUFF(pVmcs)->u32RoVmInstrError = enmInsErr;
2279}
2280
2281/**
2282 * Implements VMFail for VMX instruction failure.
2283 *
2284 * @param pVCpu The cross context virtual CPU structure.
2285 * @param enmInsErr The VM instruction error.
2286 */
2287DECLINLINE(void) CPUMSetGuestVmxVmFail(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2288{
2289 if (pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS)
2290 CPUMSetGuestVmxVmFailValid(pCtx, enmInsErr);
2291 else
2292 CPUMSetGuestVmxVmFailInvalid(pCtx);
2293}
2294
2295/**
2296 * Returns the guest-physical address of the APIC-access page when executing a
2297 * nested-guest.
2298 *
2299 * @returns The APIC-access page guest-physical address.
2300 * @param pCtx Pointer to the context.
2301 */
2302DECLINLINE(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCCPUMCTX pCtx)
2303{
2304 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2305 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2306 Assert(pVmcs);
2307 return pVmcs->u64AddrApicAccess.u;
2308}
2309
2310/**
2311 * Gets the nested-guest CR0 subject to the guest/host mask and the read-shadow.
2312 *
2313 * @returns The nested-guest CR0.
2314 * @param pCtx Pointer to the context.
2315 * @param fGstHostMask The CR0 guest/host mask to use.
2316 */
2317DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr0(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2318{
2319 /*
2320 * For each CR0 bit owned by the host, the corresponding bit from the
2321 * CR0 read shadow is loaded. For each CR0 bit that is not owned by the host,
2322 * the corresponding bit from the guest CR0 is loaded.
2323 *
2324 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2325 */
2326 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2327 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2328 Assert(pVmcs);
2329 uint64_t const uGstCr0 = pCtx->cr0;
2330 uint64_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2331 return (fReadShadow & fGstHostMask) | (uGstCr0 & ~fGstHostMask);
2332}
2333
2334/**
2335 * Gets the nested-guest CR4 subject to the guest/host mask and the read-shadow.
2336 *
2337 * @returns The nested-guest CR4.
2338 * @param pCtx Pointer to the context.
2339 * @param fGstHostMask The CR4 guest/host mask to use.
2340 */
2341DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr4(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2342{
2343 /*
2344 * For each CR4 bit owned by the host, the corresponding bit from the
2345 * CR4 read shadow is loaded. For each CR4 bit that is not owned by the host,
2346 * the corresponding bit from the guest CR4 is loaded.
2347 *
2348 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2349 */
2350 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2351 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2352 Assert(pVmcs);
2353 uint64_t const uGstCr4 = pCtx->cr4;
2354 uint64_t const fReadShadow = pVmcs->u64Cr4ReadShadow.u;
2355 return (fReadShadow & fGstHostMask) | (uGstCr4 & ~fGstHostMask);
2356}
2357
2358/**
2359 * Checks whether the LMSW access causes a VM-exit or not.
2360 *
2361 * @returns @c true if the LMSW access causes a VM-exit, @c false otherwise.
2362 * @param pCtx Pointer to the context.
2363 * @param uNewMsw The LMSW source operand (the Machine Status Word).
2364 */
2365DECLINLINE(bool) CPUMIsGuestVmxLmswInterceptSet(PCCPUMCTX pCtx, uint16_t uNewMsw)
2366{
2367 /*
2368 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
2369 *
2370 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
2371 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2372 */
2373 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2374 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2375 Assert(pVmcs);
2376
2377 uint32_t const fGstHostMask = (uint32_t)pVmcs->u64Cr0Mask.u;
2378 uint32_t const fReadShadow = (uint32_t)pVmcs->u64Cr0ReadShadow.u;
2379
2380 /*
2381 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
2382 * CR0.PE case first, before the rest of the bits in the MSW.
2383 *
2384 * If CR0.PE is owned by the host and CR0.PE differs between the
2385 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
2386 */
2387 if ( (fGstHostMask & X86_CR0_PE)
2388 && (uNewMsw & X86_CR0_PE)
2389 && !(fReadShadow & X86_CR0_PE))
2390 return true;
2391
2392 /*
2393 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
2394 * bits differ between the MSW (source operand) and the read-shadow, we must
2395 * cause a VM-exit.
2396 */
2397 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2398 if ((fReadShadow & fGstHostLmswMask) != (uNewMsw & fGstHostLmswMask))
2399 return true;
2400
2401 return false;
2402}
2403
2404/**
2405 * Checks whether the Mov-to-CR0/CR4 access causes a VM-exit or not.
2406 *
2407 * @returns @c true if the Mov CRX access causes a VM-exit, @c false otherwise.
2408 * @param pCtx Pointer to the context.
2409 * @param iCrReg The control register number (must be 0 or 4).
2410 * @param uNewCrX The CR0/CR4 value being written.
2411 */
2412DECLINLINE(bool) CPUMIsGuestVmxMovToCr0Cr4InterceptSet(PCCPUMCTX pCtx, uint8_t iCrReg, uint64_t uNewCrX)
2413{
2414 /*
2415 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
2416 * corresponding bits differ between the source operand and the read-shadow,
2417 * we must cause a VM-exit.
2418 *
2419 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2420 */
2421 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2422 PCVMXVVMCS pVmcs = pCtx->hwvirt.vmx.CTX_SUFF(pVmcs);
2423 Assert(pVmcs);
2424 Assert(iCrReg == 0 || iCrReg == 4);
2425
2426 uint64_t fGstHostMask;
2427 uint64_t fReadShadow;
2428 if (iCrReg == 0)
2429 {
2430 fGstHostMask = pVmcs->u64Cr0Mask.u;
2431 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
2432 }
2433 else
2434 {
2435 fGstHostMask = pVmcs->u64Cr4Mask.u;
2436 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
2437 }
2438
2439 if ((fReadShadow & fGstHostMask) != (uNewCrX & fGstHostMask))
2440 {
2441 Assert(fGstHostMask != 0);
2442 return true;
2443 }
2444
2445 return false;
2446}
2447
2448/**
2449 * Returns whether the guest has an active, current VMCS.
2450 *
2451 * @returns @c true if the guest has an active, current VMCS, @c false otherwise.
2452 * @param pCtx Pointer to the context.
2453 */
2454DECLINLINE(bool) CPUMIsGuestVmxCurrentVmcsValid(PCCPUMCTX pCtx)
2455{
2456 RTGCPHYS const GCPhysVmcs = pCtx->hwvirt.vmx.GCPhysVmcs;
2457 return RT_BOOL(GCPhysVmcs != NIL_RTGCPHYS);
2458}
2459
2460/**
2461 * Gets the nested-guest virtual-APIC page.
2462 *
2463 * @returns The virtual-APIC page.
2464 * @param pCtx Pointer to the context.
2465 * @param pHCPhys Where to store the host-physical address of the virtual-APIC
2466 * page.
2467 */
2468DECLINLINE(void *) CPUMGetGuestVmxVirtApicPage(PCCPUMCTX pCtx, PRTHCPHYS pHCPhysVirtApicPage)
2469{
2470 Assert(pHCPhysVirtApicPage);
2471 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
2472 *pHCPhysVirtApicPage = pCtx->hwvirt.vmx.HCPhysVirtApicPage;
2473 return pCtx->hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
2474}
2475
2476# endif /* !IN_RC */
2477
2478/**
2479 * Checks whether the VMX nested-guest is in a state to receive physical (APIC)
2480 * interrupts.
2481 *
2482 * @returns @c true if it's ready, @c false otherwise.
2483 * @param pCtx The guest-CPU context.
2484 */
2485DECLINLINE(bool) CPUMIsGuestVmxPhysIntrEnabled(PCCPUMCTX pCtx)
2486{
2487#ifdef IN_RC
2488 AssertReleaseFailedReturn(false);
2489#else
2490 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2491 if (CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_EXT_INT_EXIT))
2492 return true;
2493 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2494#endif
2495}
2496
2497/**
2498 * Checks whether the VMX nested-guest is blocking virtual-NMIs.
2499 *
2500 * @returns @c true if it's blocked, @c false otherwise.
2501 * @param pCtx The guest-CPU context.
2502 */
2503DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx)
2504{
2505#ifdef IN_RC
2506 RT_NOREF(pCtx);
2507 AssertReleaseFailedReturn(false);
2508#else
2509 /*
2510 * Return the state of virtual-NMI blocking, if we are executing a
2511 * VMX nested-guest with virtual-NMIs enabled.
2512 */
2513 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2514 Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2515 return pCtx->hwvirt.vmx.fVirtNmiBlocking;
2516#endif
2517}
2518
2519/**
2520 * Sets or clears VMX nested-guest virtual-NMI blocking.
2521 *
2522 * @param pCtx The guest-CPU context.
2523 * @param fBlocking Whether virtual-NMI blocking is in effect or not.
2524 */
2525DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking)
2526{
2527#ifdef IN_RC
2528 RT_NOREF2(pCtx, fBlocking);
2529 AssertReleaseFailedReturnVoid();
2530#else
2531 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2532 Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2533 pCtx->hwvirt.vmx.fVirtNmiBlocking = fBlocking;
2534#endif
2535}
2536
2537/**
2538 * Checks whether the VMX nested-guest is in a state to receive virtual interrupts
2539 * (those injected with the "virtual-interrupt delivery" feature).
2540 *
2541 * @returns @c true if it's ready, @c false otherwise.
2542 * @param pCtx The guest-CPU context.
2543 */
2544DECLINLINE(bool) CPUMIsGuestVmxVirtIntrEnabled(PCCPUMCTX pCtx)
2545{
2546#ifdef IN_RC
2547 RT_NOREF2(pCtx);
2548 AssertReleaseFailedReturn(false);
2549#else
2550 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2551 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2552#endif
2553}
2554
2555/** @} */
2556#endif /* !IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS && RT_ARCH_AMD64 */
2557
2558
2559
2560/** @name Hypervisor Register Getters.
2561 * @{ */
2562VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
2563VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
2564VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
2565VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
2566VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
2567VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
2568VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
2569/** @} */
2570
2571/** @name Hypervisor Register Setters.
2572 * @{ */
2573VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
2574VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
2575VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
2576VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
2577VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
2578VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
2579VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
2580VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg);
2581/** @} */
2582
2583VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
2584#ifdef VBOX_INCLUDED_vmm_cpumctx_h
2585VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
2586#endif
2587VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
2588
2589/** @name Changed flags.
2590 * These flags are used to keep track of which important register that
2591 * have been changed since last they were reset. The only one allowed
2592 * to clear them is REM!
2593 *
2594 * @todo This is obsolete, but remains as it will be refactored for coordinating
2595 * IEM and NEM/HM later. Probably.
2596 * @{
2597 */
2598#define CPUM_CHANGED_FPU_REM RT_BIT(0)
2599#define CPUM_CHANGED_CR0 RT_BIT(1)
2600#define CPUM_CHANGED_CR4 RT_BIT(2)
2601#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
2602#define CPUM_CHANGED_CR3 RT_BIT(4)
2603#define CPUM_CHANGED_GDTR RT_BIT(5)
2604#define CPUM_CHANGED_IDTR RT_BIT(6)
2605#define CPUM_CHANGED_LDTR RT_BIT(7)
2606#define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */
2607#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
2608#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */
2609#define CPUM_CHANGED_CPUID RT_BIT(11)
2610#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
2611 | CPUM_CHANGED_CR0 \
2612 | CPUM_CHANGED_CR4 \
2613 | CPUM_CHANGED_GLOBAL_TLB_FLUSH \
2614 | CPUM_CHANGED_CR3 \
2615 | CPUM_CHANGED_GDTR \
2616 | CPUM_CHANGED_IDTR \
2617 | CPUM_CHANGED_LDTR \
2618 | CPUM_CHANGED_TR \
2619 | CPUM_CHANGED_SYSENTER_MSR \
2620 | CPUM_CHANGED_HIDDEN_SEL_REGS \
2621 | CPUM_CHANGED_CPUID )
2622/** @} */
2623
2624VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
2625VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
2626VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
2627VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
2628VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
2629VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
2630VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
2631VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
2632VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
2633VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
2634VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
2635VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
2636VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
2637VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
2638VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
2639VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
2640VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM);
2641VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
2642 uint64_t *puValidEfer);
2643VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
2644VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue);
2645
2646
2647/** Guest CPU interruptibility level, see CPUMGetGuestInterruptibility(). */
2648typedef enum CPUMINTERRUPTIBILITY
2649{
2650 CPUMINTERRUPTIBILITY_INVALID = 0,
2651 CPUMINTERRUPTIBILITY_UNRESTRAINED,
2652 CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED,
2653 CPUMINTERRUPTIBILITY_INT_DISABLED,
2654 CPUMINTERRUPTIBILITY_INT_INHIBITED,
2655 CPUMINTERRUPTIBILITY_NMI_INHIBIT,
2656 CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT,
2657 CPUMINTERRUPTIBILITY_END,
2658 CPUMINTERRUPTIBILITY_32BIT_HACK = 0x7fffffff
2659} CPUMINTERRUPTIBILITY;
2660
2661VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu);
2662VMM_INT_DECL(bool) CPUMIsGuestNmiBlocking(PCVMCPU pVCpu);
2663VMM_INT_DECL(void) CPUMSetGuestNmiBlocking(PVMCPU pVCpu, bool fBlock);
2664
2665/** @name Typical scalable bus frequency values.
2666 * @{ */
2667/** Special internal value indicating that we don't know the frequency.
2668 * @internal */
2669#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
2670#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
2671#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
2672#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
2673#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
2674#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
2675#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
2676#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
2677/** @} */
2678
2679
2680#ifdef IN_RING3
2681/** @defgroup grp_cpum_r3 The CPUM ring-3 API
2682 * @{
2683 */
2684
2685VMMR3DECL(int) CPUMR3Init(PVM pVM);
2686VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
2687VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM);
2688VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
2689VMMR3DECL(int) CPUMR3Term(PVM pVM);
2690VMMR3DECL(void) CPUMR3Reset(PVM pVM);
2691VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
2692VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
2693VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
2694
2695VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
2696VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
2697VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
2698 uint8_t bModel, uint8_t bStepping);
2699VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
2700VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
2701VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
2702VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
2703VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
2704VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
2705VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
2706
2707VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
2708
2709VMMR3DECL(uint32_t) CPUMR3DbGetEntries(void);
2710/** Pointer to CPUMR3DbGetEntries. */
2711typedef DECLCALLBACKPTR(uint32_t, PFNCPUMDBGETENTRIES, (void));
2712VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByIndex(uint32_t idxCpuDb);
2713/** Pointer to CPUMR3DbGetEntryByIndex. */
2714typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYINDEX, (uint32_t idxCpuDb));
2715VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByName(const char *pszName);
2716/** Pointer to CPUMR3DbGetEntryByName. */
2717typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYNAME, (const char *pszName));
2718/** @} */
2719#endif /* IN_RING3 */
2720
2721#ifdef IN_RING0
2722/** @defgroup grp_cpum_r0 The CPUM ring-0 API
2723 * @{
2724 */
2725VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
2726VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
2727VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM);
2728DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPUCC pVCpu);
2729DECLASM(void) CPUMR0TouchHostFpu(void);
2730VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu);
2731VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu);
2732VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu);
2733VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVMCC pVM, PVMCPUCC pVCpu);
2734VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6);
2735VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6);
2736
2737VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6);
2738VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6);
2739#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
2740VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPUCC pVCpu, uint32_t iHostCpuSet);
2741#endif
2742
2743/** @} */
2744#endif /* IN_RING0 */
2745
2746/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
2747 * @{
2748 */
2749VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPUCC pVCpu);
2750VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPUCC pVCpu);
2751VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPUCC pVCpu);
2752VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPUCC pVCpu);
2753VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPUCC pVCpu);
2754/** @} */
2755
2756
2757#endif /* !VBOX_FOR_DTRACE_LIB */
2758/** @} */
2759RT_C_DECLS_END
2760
2761
2762#endif /* !VBOX_INCLUDED_vmm_cpum_h */
2763
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