cpum.h@ 52664

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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2014 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_cpum_h
27	#define ___VBox_vmm_cpum_h
28
29	#include <iprt/x86.h>
30	#include <VBox/types.h>
31	#include <VBox/vmm/cpumctx.h>
32	#include <VBox/vmm/stam.h>
33
34	RT_C_DECLS_BEGIN
35
36	/** @defgroup grp_cpum The CPU Monitor / Manager API
37	* @{
38	*/
39
40	/**
41	* CPUID feature to set or clear.
42	*/
43	typedef enum CPUMCPUIDFEATURE
44	{
45	CPUMCPUIDFEATURE_INVALID = 0,
46	/** The APIC feature bit. (Std+Ext) */
47	CPUMCPUIDFEATURE_APIC,
48	/** The sysenter/sysexit feature bit. (Std) */
49	CPUMCPUIDFEATURE_SEP,
50	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
51	CPUMCPUIDFEATURE_SYSCALL,
52	/** The PAE feature bit. (Std+Ext) */
53	CPUMCPUIDFEATURE_PAE,
54	/** The NX feature bit. (Ext) */
55	CPUMCPUIDFEATURE_NX,
56	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
57	CPUMCPUIDFEATURE_LAHF,
58	/** The LONG MODE feature bit. (Ext) */
59	CPUMCPUIDFEATURE_LONG_MODE,
60	/** The PAT feature bit. (Std+Ext) */
61	CPUMCPUIDFEATURE_PAT,
62	/** The x2APIC feature bit. (Std) */
63	CPUMCPUIDFEATURE_X2APIC,
64	/** The RDTSCP feature bit. (Ext) */
65	CPUMCPUIDFEATURE_RDTSCP,
66	/** The Hypervisor Present bit. (Std) */
67	CPUMCPUIDFEATURE_HVP,
68	/** The MWait Extensions bits (Std) */
69	CPUMCPUIDFEATURE_MWAIT_EXTS,
70	/** 32bit hackishness. */
71	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
72	} CPUMCPUIDFEATURE;
73
74	/**
75	* CPU Vendor.
76	*/
77	typedef enum CPUMCPUVENDOR
78	{
79	CPUMCPUVENDOR_INVALID = 0,
80	CPUMCPUVENDOR_INTEL,
81	CPUMCPUVENDOR_AMD,
82	CPUMCPUVENDOR_VIA,
83	CPUMCPUVENDOR_CYRIX,
84	CPUMCPUVENDOR_UNKNOWN,
85	/** 32bit hackishness. */
86	CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
87	} CPUMCPUVENDOR;
88
89
90	/**
91	* X86 and AMD64 CPU microarchitectures and in processor generations.
92	*
93	* @remarks The separation here is sometimes a little bit too finely grained,
94	* and the differences is more like processor generation than micro
95	* arch. This can be useful, so we'll provide functions for getting at
96	* more coarse grained info.
97	*/
98	typedef enum CPUMMICROARCH
99	{
100	kCpumMicroarch_Invalid = 0,
101
102	kCpumMicroarch_Intel_First,
103
104	kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
105	kCpumMicroarch_Intel_80186,
106	kCpumMicroarch_Intel_80286,
107	kCpumMicroarch_Intel_80386,
108	kCpumMicroarch_Intel_80486,
109	kCpumMicroarch_Intel_P5,
110
111	kCpumMicroarch_Intel_P6_Core_Atom_First,
112	kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
113	kCpumMicroarch_Intel_P6_II,
114	kCpumMicroarch_Intel_P6_III,
115
116	kCpumMicroarch_Intel_P6_M_Banias,
117	kCpumMicroarch_Intel_P6_M_Dothan,
118	kCpumMicroarch_Intel_Core_Yonah, /*< Core, also known as Enhanced Pentium M. /
119
120	kCpumMicroarch_Intel_Core2_First,
121	kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First,
122	kCpumMicroarch_Intel_Core2_Penryn,
123
124	kCpumMicroarch_Intel_Core7_First,
125	kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
126	kCpumMicroarch_Intel_Core7_Westmere,
127	kCpumMicroarch_Intel_Core7_SandyBridge,
128	kCpumMicroarch_Intel_Core7_IvyBridge,
129	kCpumMicroarch_Intel_Core7_Haswell,
130	kCpumMicroarch_Intel_Core7_Broadwell,
131	kCpumMicroarch_Intel_Core7_Skylake,
132	kCpumMicroarch_Intel_Core7_Cannonlake,
133	kCpumMicroarch_Intel_Core7_End,
134
135	kCpumMicroarch_Intel_Atom_First,
136	kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
137	kCpumMicroarch_Intel_Atom_Lincroft, /*< Second generation bonnell (44nm). /
138	kCpumMicroarch_Intel_Atom_Saltwell, /*< 32nm shrink of Bonnell. /
139	kCpumMicroarch_Intel_Atom_Silvermont, /*< 22nm /
140	kCpumMicroarch_Intel_Atom_Airmount, /*< 14nm /
141	kCpumMicroarch_Intel_Atom_Goldmont, /*< 14nm /
142	kCpumMicroarch_Intel_Atom_Unknown,
143	kCpumMicroarch_Intel_Atom_End,
144
145	kCpumMicroarch_Intel_P6_Core_Atom_End,
146
147	kCpumMicroarch_Intel_NB_First,
148	kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /*< 180nm /
149	kCpumMicroarch_Intel_NB_Northwood, /*< 130nm /
150	kCpumMicroarch_Intel_NB_Prescott, /*< 90nm /
151	kCpumMicroarch_Intel_NB_Prescott2M, /*< 90nm /
152	kCpumMicroarch_Intel_NB_CedarMill, /*< 65nm /
153	kCpumMicroarch_Intel_NB_Gallatin, /*< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). /
154	kCpumMicroarch_Intel_NB_Unknown,
155	kCpumMicroarch_Intel_NB_End,
156
157	kCpumMicroarch_Intel_Unknown,
158	kCpumMicroarch_Intel_End,
159
160	kCpumMicroarch_AMD_First,
161	kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
162	kCpumMicroarch_AMD_Am386,
163	kCpumMicroarch_AMD_Am486,
164	kCpumMicroarch_AMD_Am486Enh, /*< Covers Am5x86 as well. /
165	kCpumMicroarch_AMD_K5,
166	kCpumMicroarch_AMD_K6,
167
168	kCpumMicroarch_AMD_K7_First,
169	kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
170	kCpumMicroarch_AMD_K7_Spitfire,
171	kCpumMicroarch_AMD_K7_Thunderbird,
172	kCpumMicroarch_AMD_K7_Morgan,
173	kCpumMicroarch_AMD_K7_Thoroughbred,
174	kCpumMicroarch_AMD_K7_Barton,
175	kCpumMicroarch_AMD_K7_Unknown,
176	kCpumMicroarch_AMD_K7_End,
177
178	kCpumMicroarch_AMD_K8_First,
179	kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /*< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin /
180	kCpumMicroarch_AMD_K8_90nm, /*< 90nm shrink /
181	kCpumMicroarch_AMD_K8_90nm_DualCore, /*< 90nm with two cores. /
182	kCpumMicroarch_AMD_K8_90nm_AMDV, /*< 90nm with AMD-V (usually) and two cores (usually). /
183	kCpumMicroarch_AMD_K8_65nm, /*< 65nm shrink. /
184	kCpumMicroarch_AMD_K8_End,
185
186	kCpumMicroarch_AMD_K10,
187	kCpumMicroarch_AMD_K10_Lion,
188	kCpumMicroarch_AMD_K10_Llano,
189	kCpumMicroarch_AMD_Bobcat,
190	kCpumMicroarch_AMD_Jaguar,
191
192	kCpumMicroarch_AMD_15h_First,
193	kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
194	kCpumMicroarch_AMD_15h_Piledriver,
195	kCpumMicroarch_AMD_15h_Steamroller, /*< Yet to be released, might have different family. /
196	kCpumMicroarch_AMD_15h_Excavator, /*< Yet to be released, might have different family. /
197	kCpumMicroarch_AMD_15h_Unknown,
198	kCpumMicroarch_AMD_15h_End,
199
200	kCpumMicroarch_AMD_16h_First,
201	kCpumMicroarch_AMD_16h_End,
202
203	kCpumMicroarch_AMD_Unknown,
204	kCpumMicroarch_AMD_End,
205
206	kCpumMicroarch_VIA_First,
207	kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
208	kCpumMicroarch_Centaur_C2,
209	kCpumMicroarch_Centaur_C3,
210	kCpumMicroarch_VIA_C3_M2,
211	kCpumMicroarch_VIA_C3_C5A, /*< 180nm Samuel - Cyrix III, C3, 1GigaPro. /
212	kCpumMicroarch_VIA_C3_C5B, /*< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. /
213	kCpumMicroarch_VIA_C3_C5C, /*< 130nm Ezra - C3, Eden ESP. /
214	kCpumMicroarch_VIA_C3_C5N, /*< 130nm Ezra-T - C3. /
215	kCpumMicroarch_VIA_C3_C5XL, /*< 130nm Nehemiah - C3, Eden ESP, Eden-N. /
216	kCpumMicroarch_VIA_C3_C5P, /*< 130nm Nehemiah+ - C3. /
217	kCpumMicroarch_VIA_C7_C5J, /*< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. /
218	kCpumMicroarch_VIA_Isaiah,
219	kCpumMicroarch_VIA_Unknown,
220	kCpumMicroarch_VIA_End,
221
222	kCpumMicroarch_Cyrix_First,
223	kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
224	kCpumMicroarch_Cyrix_M1,
225	kCpumMicroarch_Cyrix_MediaGX,
226	kCpumMicroarch_Cyrix_MediaGXm,
227	kCpumMicroarch_Cyrix_M2,
228	kCpumMicroarch_Cyrix_Unknown,
229	kCpumMicroarch_Cyrix_End,
230
231	kCpumMicroarch_Unknown,
232
233	kCpumMicroarch_32BitHack = 0x7fffffff
234	} CPUMMICROARCH;
235
236
237	/** Predicate macro for catching netburst CPUs. */
238	#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
239	((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
240
241	/** Predicate macro for catching Core7 CPUs. */
242	#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
243	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
244
245	/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
246	#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
247	((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
248
249	/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
250	#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
251
252	/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
253	#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
254
255	/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
256	#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
257
258	/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
259	#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
260
261	/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
262	* decendants). */
263	#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
264	((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
265
266	/** Predicate macro for catching AMD Family 16H CPUs. */
267	#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
268	((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
269
270
271
272	/**
273	* CPUID leaf.
274	*/
275	typedef struct CPUMCPUIDLEAF
276	{
277	/** The leaf number. */
278	uint32_t uLeaf;
279	/** The sub-leaf number. */
280	uint32_t uSubLeaf;
281	/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
282	uint32_t fSubLeafMask;
283
284	/** The EAX value. */
285	uint32_t uEax;
286	/** The EBX value. */
287	uint32_t uEbx;
288	/** The ECX value. */
289	uint32_t uEcx;
290	/** The EDX value. */
291	uint32_t uEdx;
292
293	/** Flags. */
294	uint32_t fFlags;
295	} CPUMCPUIDLEAF;
296	/** Pointer to a CPUID leaf. */
297	typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
298	/** Pointer to a const CPUID leaf. */
299	typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
300
301	/** @name CPUMCPUIDLEAF::fFlags
302	* @{ */
303	/** Indicates that ECX (the sub-leaf indicator) doesn't change when
304	* requesting the final leaf and all undefined leaves that follows it.
305	* Observed for 0x0000000b on Intel. */
306	#define CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED RT_BIT_32(0)
307	/** @} */
308
309	/**
310	* Method used to deal with unknown CPUID leafs.
311	*/
312	typedef enum CPUMUKNOWNCPUID
313	{
314	/** Invalid zero value. */
315	CPUMUKNOWNCPUID_INVALID = 0,
316	/** Use given default values (DefCpuId). */
317	CPUMUKNOWNCPUID_DEFAULTS,
318	/** Return the last standard leaf.
319	* Intel Sandy Bridge has been observed doing this. */
320	CPUMUKNOWNCPUID_LAST_STD_LEAF,
321	/** Return the last standard leaf, with ecx observed.
322	* Intel Sandy Bridge has been observed doing this. */
323	CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
324	/** The register values are passed thru unmodified. */
325	CPUMUKNOWNCPUID_PASSTHRU,
326	/** End of valid value. */
327	CPUMUKNOWNCPUID_END,
328	/** Ensure 32-bit type. */
329	CPUMUKNOWNCPUID_32BIT_HACK = 0x7fffffff
330	} CPUMUKNOWNCPUID;
331	/** Pointer to unknown CPUID leaf method. */
332	typedef CPUMUKNOWNCPUID *PCPUMUKNOWNCPUID;
333
334
335	/**
336	* MSR read functions.
337	*/
338	typedef enum CPUMMSRRDFN
339	{
340	/** Invalid zero value. */
341	kCpumMsrRdFn_Invalid = 0,
342	/** Return the CPUMMSRRANGE::uValue. */
343	kCpumMsrRdFn_FixedValue,
344	/** Alias to the MSR range starting at the MSR given by
345	* CPUMMSRRANGE::uValue. Must be used in pair with
346	* kCpumMsrWrFn_MsrAlias. */
347	kCpumMsrRdFn_MsrAlias,
348	/** Write only register, GP all read attempts. */
349	kCpumMsrRdFn_WriteOnly,
350
351	kCpumMsrRdFn_Ia32P5McAddr,
352	kCpumMsrRdFn_Ia32P5McType,
353	kCpumMsrRdFn_Ia32TimestampCounter,
354	kCpumMsrRdFn_Ia32PlatformId, /*< Takes real CPU value for reference. /
355	kCpumMsrRdFn_Ia32ApicBase,
356	kCpumMsrRdFn_Ia32FeatureControl,
357	kCpumMsrRdFn_Ia32BiosSignId, /*< Range value returned. /
358	kCpumMsrRdFn_Ia32SmmMonitorCtl,
359	kCpumMsrRdFn_Ia32PmcN,
360	kCpumMsrRdFn_Ia32MonitorFilterLineSize,
361	kCpumMsrRdFn_Ia32MPerf,
362	kCpumMsrRdFn_Ia32APerf,
363	kCpumMsrRdFn_Ia32MtrrCap, /*< Takes real CPU value for reference. /
364	kCpumMsrRdFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
365	kCpumMsrRdFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
366	kCpumMsrRdFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
367	kCpumMsrRdFn_Ia32MtrrDefType,
368	kCpumMsrRdFn_Ia32Pat,
369	kCpumMsrRdFn_Ia32SysEnterCs,
370	kCpumMsrRdFn_Ia32SysEnterEsp,
371	kCpumMsrRdFn_Ia32SysEnterEip,
372	kCpumMsrRdFn_Ia32McgCap,
373	kCpumMsrRdFn_Ia32McgStatus,
374	kCpumMsrRdFn_Ia32McgCtl,
375	kCpumMsrRdFn_Ia32DebugCtl,
376	kCpumMsrRdFn_Ia32SmrrPhysBase,
377	kCpumMsrRdFn_Ia32SmrrPhysMask,
378	kCpumMsrRdFn_Ia32PlatformDcaCap,
379	kCpumMsrRdFn_Ia32CpuDcaCap,
380	kCpumMsrRdFn_Ia32Dca0Cap,
381	kCpumMsrRdFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
382	kCpumMsrRdFn_Ia32PerfStatus, /*< Range value returned. /
383	kCpumMsrRdFn_Ia32PerfCtl, /*< Range value returned. /
384	kCpumMsrRdFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
385	kCpumMsrRdFn_Ia32PerfCapabilities, /*< Takes reference value. /
386	kCpumMsrRdFn_Ia32FixedCtrCtrl,
387	kCpumMsrRdFn_Ia32PerfGlobalStatus, /*< Takes reference value. /
388	kCpumMsrRdFn_Ia32PerfGlobalCtrl,
389	kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
390	kCpumMsrRdFn_Ia32PebsEnable,
391	kCpumMsrRdFn_Ia32ClockModulation, /*< Range value returned. /
392	kCpumMsrRdFn_Ia32ThermInterrupt, /*< Range value returned. /
393	kCpumMsrRdFn_Ia32ThermStatus, /*< Range value returned. /
394	kCpumMsrRdFn_Ia32Therm2Ctl, /*< Range value returned. /
395	kCpumMsrRdFn_Ia32MiscEnable, /*< Range value returned. /
396	kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
397	kCpumMsrRdFn_Ia32McNCtl2, /*< Takes register number of start of range. /
398	kCpumMsrRdFn_Ia32DsArea,
399	kCpumMsrRdFn_Ia32TscDeadline,
400	kCpumMsrRdFn_Ia32X2ApicN,
401	kCpumMsrRdFn_Ia32DebugInterface,
402	kCpumMsrRdFn_Ia32VmxBase, /*< Takes real value as reference. /
403	kCpumMsrRdFn_Ia32VmxPinbasedCtls, /*< Takes real value as reference. /
404	kCpumMsrRdFn_Ia32VmxProcbasedCtls, /*< Takes real value as reference. /
405	kCpumMsrRdFn_Ia32VmxExitCtls, /*< Takes real value as reference. /
406	kCpumMsrRdFn_Ia32VmxEntryCtls, /*< Takes real value as reference. /
407	kCpumMsrRdFn_Ia32VmxMisc, /*< Takes real value as reference. /
408	kCpumMsrRdFn_Ia32VmxCr0Fixed0, /*< Takes real value as reference. /
409	kCpumMsrRdFn_Ia32VmxCr0Fixed1, /*< Takes real value as reference. /
410	kCpumMsrRdFn_Ia32VmxCr4Fixed0, /*< Takes real value as reference. /
411	kCpumMsrRdFn_Ia32VmxCr4Fixed1, /*< Takes real value as reference. /
412	kCpumMsrRdFn_Ia32VmxVmcsEnum, /*< Takes real value as reference. /
413	kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /*< Takes real value as reference. /
414	kCpumMsrRdFn_Ia32VmxEptVpidCap, /*< Takes real value as reference. /
415	kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /*< Takes real value as reference. /
416	kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /*< Takes real value as reference. /
417	kCpumMsrRdFn_Ia32VmxTrueExitCtls, /*< Takes real value as reference. /
418	kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /*< Takes real value as reference. /
419
420	kCpumMsrRdFn_Amd64Efer,
421	kCpumMsrRdFn_Amd64SyscallTarget,
422	kCpumMsrRdFn_Amd64LongSyscallTarget,
423	kCpumMsrRdFn_Amd64CompSyscallTarget,
424	kCpumMsrRdFn_Amd64SyscallFlagMask,
425	kCpumMsrRdFn_Amd64FsBase,
426	kCpumMsrRdFn_Amd64GsBase,
427	kCpumMsrRdFn_Amd64KernelGsBase,
428	kCpumMsrRdFn_Amd64TscAux,
429
430	kCpumMsrRdFn_IntelEblCrPowerOn,
431	kCpumMsrRdFn_IntelI7CoreThreadCount,
432	kCpumMsrRdFn_IntelP4EbcHardPowerOn,
433	kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
434	kCpumMsrRdFn_IntelP4EbcFrequencyId,
435	kCpumMsrRdFn_IntelP6FsbFrequency, /*< Takes real value as reference. /
436	kCpumMsrRdFn_IntelPlatformInfo,
437	kCpumMsrRdFn_IntelFlexRatio, /*< Takes real value as reference. /
438	kCpumMsrRdFn_IntelPkgCStConfigControl,
439	kCpumMsrRdFn_IntelPmgIoCaptureBase,
440	kCpumMsrRdFn_IntelLastBranchFromToN,
441	kCpumMsrRdFn_IntelLastBranchFromN,
442	kCpumMsrRdFn_IntelLastBranchToN,
443	kCpumMsrRdFn_IntelLastBranchTos,
444	kCpumMsrRdFn_IntelBblCrCtl,
445	kCpumMsrRdFn_IntelBblCrCtl3,
446	kCpumMsrRdFn_IntelI7TemperatureTarget, /*< Range value returned. /
447	kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/*< Takes register number. /
448	kCpumMsrRdFn_IntelI7MiscPwrMgmt,
449	kCpumMsrRdFn_IntelP6CrN,
450	kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
451	kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
452	kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
453	kCpumMsrRdFn_IntelI7SandyAesNiCtl,
454	kCpumMsrRdFn_IntelI7TurboRatioLimit, /*< Returns range value. /
455	kCpumMsrRdFn_IntelI7LbrSelect,
456	kCpumMsrRdFn_IntelI7SandyErrorControl,
457	kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/*< Returns range value. /
458	kCpumMsrRdFn_IntelI7PowerCtl,
459	kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
460	kCpumMsrRdFn_IntelI7PebsLdLat,
461	kCpumMsrRdFn_IntelI7PkgCnResidencyN, /*< Takes C-state number. /
462	kCpumMsrRdFn_IntelI7CoreCnResidencyN, /*< Takes C-state number. /
463	kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/*< Takes real value as reference. /
464	kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /*< Takes real value as reference. /
465	kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /*< Takes real value as reference. /
466	kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /*< Takes real value as reference. /
467	kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /*< Takes real value as reference. /
468	kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /*< Takes real value as reference. /
469	kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /*< Takes real value as reference. /
470	kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /*< Takes real value as reference. /
471	kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /*< Takes real value as reference. /
472	kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /*< Takes real value as reference. /
473	kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/*< Takes real value as reference. /
474	kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /*< Takes real value as reference. /
475	kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /*< Takes real value as reference. /
476	kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /*< Takes real value as reference. /
477	kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /*< Takes real value as reference. /
478	kCpumMsrRdFn_IntelI7RaplPp0Policy, /*< Takes real value as reference. /
479	kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /*< Takes real value as reference. /
480	kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /*< Takes real value as reference. /
481	kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /*< Takes real value as reference. /
482	kCpumMsrRdFn_IntelI7RaplPp1Policy, /*< Takes real value as reference. /
483	kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /*< Takes real value as reference. /
484	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /*< Takes real value as reference. /
485	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /*< Takes real value as reference. /
486	kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
487	kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
488	kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
489	kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
490	kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
491	kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
492	kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
493	kCpumMsrRdFn_IntelI7UncCBoxConfig,
494	kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
495	kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
496	kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /*< Range value returned. /
497	kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
498	kCpumMsrRdFn_IntelCore1ExtConfig,
499	kCpumMsrRdFn_IntelCore1DtsCalControl,
500	kCpumMsrRdFn_IntelCore2PeciControl,
501
502	kCpumMsrRdFn_P6LastBranchFromIp,
503	kCpumMsrRdFn_P6LastBranchToIp,
504	kCpumMsrRdFn_P6LastIntFromIp,
505	kCpumMsrRdFn_P6LastIntToIp,
506
507	kCpumMsrRdFn_AmdFam15hTscRate,
508	kCpumMsrRdFn_AmdFam15hLwpCfg,
509	kCpumMsrRdFn_AmdFam15hLwpCbAddr,
510	kCpumMsrRdFn_AmdFam10hMc4MiscN,
511	kCpumMsrRdFn_AmdK8PerfCtlN,
512	kCpumMsrRdFn_AmdK8PerfCtrN,
513	kCpumMsrRdFn_AmdK8SysCfg, /*< Range value returned. /
514	kCpumMsrRdFn_AmdK8HwCr,
515	kCpumMsrRdFn_AmdK8IorrBaseN,
516	kCpumMsrRdFn_AmdK8IorrMaskN,
517	kCpumMsrRdFn_AmdK8TopOfMemN,
518	kCpumMsrRdFn_AmdK8NbCfg1,
519	kCpumMsrRdFn_AmdK8McXcptRedir,
520	kCpumMsrRdFn_AmdK8CpuNameN,
521	kCpumMsrRdFn_AmdK8HwThermalCtrl, /*< Range value returned. /
522	kCpumMsrRdFn_AmdK8SwThermalCtrl,
523	kCpumMsrRdFn_AmdK8FidVidControl, /*< Range value returned. /
524	kCpumMsrRdFn_AmdK8FidVidStatus, /*< Range value returned. /
525	kCpumMsrRdFn_AmdK8McCtlMaskN,
526	kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
527	kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
528	kCpumMsrRdFn_AmdK8IntPendingMessage,
529	kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
530	kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
531	kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
532	kCpumMsrRdFn_AmdFam10hPStateCurLimit, /*< Returns range value. /
533	kCpumMsrRdFn_AmdFam10hPStateControl, /*< Returns range value. /
534	kCpumMsrRdFn_AmdFam10hPStateStatus, /*< Returns range value. /
535	kCpumMsrRdFn_AmdFam10hPStateN, /*< Returns range value. This isn't an register index! /
536	kCpumMsrRdFn_AmdFam10hCofVidControl, /*< Returns range value. /
537	kCpumMsrRdFn_AmdFam10hCofVidStatus, /*< Returns range value. /
538	kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
539	kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
540	kCpumMsrRdFn_AmdK8SmmBase,
541	kCpumMsrRdFn_AmdK8SmmAddr,
542	kCpumMsrRdFn_AmdK8SmmMask,
543	kCpumMsrRdFn_AmdK8VmCr,
544	kCpumMsrRdFn_AmdK8IgnNe,
545	kCpumMsrRdFn_AmdK8SmmCtl,
546	kCpumMsrRdFn_AmdK8VmHSavePa,
547	kCpumMsrRdFn_AmdFam10hVmLockKey,
548	kCpumMsrRdFn_AmdFam10hSmmLockKey,
549	kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
550	kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
551	kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
552	kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
553	kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
554	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
555	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
556	kCpumMsrRdFn_AmdK7MicrocodeCtl, /*< Returns range value. /
557	kCpumMsrRdFn_AmdK7ClusterIdMaybe, /*< Returns range value. /
558	kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
559	kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
560	kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
561	kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
562	kCpumMsrRdFn_AmdK8PatchLevel, /*< Returns range value. /
563	kCpumMsrRdFn_AmdK7DebugStatusMaybe,
564	kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
565	kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
566	kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
567	kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
568	kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
569	kCpumMsrRdFn_AmdK7NodeId,
570	kCpumMsrRdFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
571	kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
572	kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
573	kCpumMsrRdFn_AmdK7LoadStoreCfg,
574	kCpumMsrRdFn_AmdK7InstrCacheCfg,
575	kCpumMsrRdFn_AmdK7DataCacheCfg,
576	kCpumMsrRdFn_AmdK7BusUnitCfg,
577	kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
578	kCpumMsrRdFn_AmdFam15hFpuCfg,
579	kCpumMsrRdFn_AmdFam15hDecoderCfg,
580	kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
581	kCpumMsrRdFn_AmdFam15hCombUnitCfg,
582	kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
583	kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
584	kCpumMsrRdFn_AmdFam15hExecUnitCfg,
585	kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
586	kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
587	kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
588	kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
589	kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
590	kCpumMsrRdFn_AmdFam10hIbsOpRip,
591	kCpumMsrRdFn_AmdFam10hIbsOpData,
592	kCpumMsrRdFn_AmdFam10hIbsOpData2,
593	kCpumMsrRdFn_AmdFam10hIbsOpData3,
594	kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
595	kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
596	kCpumMsrRdFn_AmdFam10hIbsCtl,
597	kCpumMsrRdFn_AmdFam14hIbsBrTarget,
598
599	kCpumMsrRdFn_Gim,
600
601	/** End of valid MSR read function indexes. */
602	kCpumMsrRdFn_End
603	} CPUMMSRRDFN;
604
605	/**
606	* MSR write functions.
607	*/
608	typedef enum CPUMMSRWRFN
609	{
610	/** Invalid zero value. */
611	kCpumMsrWrFn_Invalid = 0,
612	/** Writes are ignored, the fWrGpMask is observed though. */
613	kCpumMsrWrFn_IgnoreWrite,
614	/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
615	kCpumMsrWrFn_ReadOnly,
616	/** Alias to the MSR range starting at the MSR given by
617	* CPUMMSRRANGE::uValue. Must be used in pair with
618	* kCpumMsrRdFn_MsrAlias. */
619	kCpumMsrWrFn_MsrAlias,
620
621	kCpumMsrWrFn_Ia32P5McAddr,
622	kCpumMsrWrFn_Ia32P5McType,
623	kCpumMsrWrFn_Ia32TimestampCounter,
624	kCpumMsrWrFn_Ia32ApicBase,
625	kCpumMsrWrFn_Ia32FeatureControl,
626	kCpumMsrWrFn_Ia32BiosSignId,
627	kCpumMsrWrFn_Ia32BiosUpdateTrigger,
628	kCpumMsrWrFn_Ia32SmmMonitorCtl,
629	kCpumMsrWrFn_Ia32PmcN,
630	kCpumMsrWrFn_Ia32MonitorFilterLineSize,
631	kCpumMsrWrFn_Ia32MPerf,
632	kCpumMsrWrFn_Ia32APerf,
633	kCpumMsrWrFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
634	kCpumMsrWrFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
635	kCpumMsrWrFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
636	kCpumMsrWrFn_Ia32MtrrDefType,
637	kCpumMsrWrFn_Ia32Pat,
638	kCpumMsrWrFn_Ia32SysEnterCs,
639	kCpumMsrWrFn_Ia32SysEnterEsp,
640	kCpumMsrWrFn_Ia32SysEnterEip,
641	kCpumMsrWrFn_Ia32McgStatus,
642	kCpumMsrWrFn_Ia32McgCtl,
643	kCpumMsrWrFn_Ia32DebugCtl,
644	kCpumMsrWrFn_Ia32SmrrPhysBase,
645	kCpumMsrWrFn_Ia32SmrrPhysMask,
646	kCpumMsrWrFn_Ia32PlatformDcaCap,
647	kCpumMsrWrFn_Ia32Dca0Cap,
648	kCpumMsrWrFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
649	kCpumMsrWrFn_Ia32PerfStatus,
650	kCpumMsrWrFn_Ia32PerfCtl,
651	kCpumMsrWrFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
652	kCpumMsrWrFn_Ia32PerfCapabilities,
653	kCpumMsrWrFn_Ia32FixedCtrCtrl,
654	kCpumMsrWrFn_Ia32PerfGlobalStatus,
655	kCpumMsrWrFn_Ia32PerfGlobalCtrl,
656	kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
657	kCpumMsrWrFn_Ia32PebsEnable,
658	kCpumMsrWrFn_Ia32ClockModulation,
659	kCpumMsrWrFn_Ia32ThermInterrupt,
660	kCpumMsrWrFn_Ia32ThermStatus,
661	kCpumMsrWrFn_Ia32Therm2Ctl,
662	kCpumMsrWrFn_Ia32MiscEnable,
663	kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
664	kCpumMsrWrFn_Ia32McNCtl2, /*< Takes register number of start of range. /
665	kCpumMsrWrFn_Ia32DsArea,
666	kCpumMsrWrFn_Ia32TscDeadline,
667	kCpumMsrWrFn_Ia32X2ApicN,
668	kCpumMsrWrFn_Ia32DebugInterface,
669
670	kCpumMsrWrFn_Amd64Efer,
671	kCpumMsrWrFn_Amd64SyscallTarget,
672	kCpumMsrWrFn_Amd64LongSyscallTarget,
673	kCpumMsrWrFn_Amd64CompSyscallTarget,
674	kCpumMsrWrFn_Amd64SyscallFlagMask,
675	kCpumMsrWrFn_Amd64FsBase,
676	kCpumMsrWrFn_Amd64GsBase,
677	kCpumMsrWrFn_Amd64KernelGsBase,
678	kCpumMsrWrFn_Amd64TscAux,
679	kCpumMsrWrFn_IntelEblCrPowerOn,
680	kCpumMsrWrFn_IntelP4EbcHardPowerOn,
681	kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
682	kCpumMsrWrFn_IntelP4EbcFrequencyId,
683	kCpumMsrWrFn_IntelFlexRatio,
684	kCpumMsrWrFn_IntelPkgCStConfigControl,
685	kCpumMsrWrFn_IntelPmgIoCaptureBase,
686	kCpumMsrWrFn_IntelLastBranchFromToN,
687	kCpumMsrWrFn_IntelLastBranchFromN,
688	kCpumMsrWrFn_IntelLastBranchToN,
689	kCpumMsrWrFn_IntelLastBranchTos,
690	kCpumMsrWrFn_IntelBblCrCtl,
691	kCpumMsrWrFn_IntelBblCrCtl3,
692	kCpumMsrWrFn_IntelI7TemperatureTarget,
693	kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /*< Takes register number. /
694	kCpumMsrWrFn_IntelI7MiscPwrMgmt,
695	kCpumMsrWrFn_IntelP6CrN,
696	kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
697	kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
698	kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
699	kCpumMsrWrFn_IntelI7SandyAesNiCtl,
700	kCpumMsrWrFn_IntelI7TurboRatioLimit,
701	kCpumMsrWrFn_IntelI7LbrSelect,
702	kCpumMsrWrFn_IntelI7SandyErrorControl,
703	kCpumMsrWrFn_IntelI7PowerCtl,
704	kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
705	kCpumMsrWrFn_IntelI7PebsLdLat,
706	kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
707	kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
708	kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
709	kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
710	kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
711	kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
712	kCpumMsrWrFn_IntelI7RaplPp0Policy,
713	kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
714	kCpumMsrWrFn_IntelI7RaplPp1Policy,
715	kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
716	kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
717	kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
718	kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
719	kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
720	kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
721	kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
722	kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
723	kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
724	kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
725	kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
726	kCpumMsrWrFn_IntelCore1ExtConfig,
727	kCpumMsrWrFn_IntelCore1DtsCalControl,
728	kCpumMsrWrFn_IntelCore2PeciControl,
729
730	kCpumMsrWrFn_P6LastIntFromIp,
731	kCpumMsrWrFn_P6LastIntToIp,
732
733	kCpumMsrWrFn_AmdFam15hTscRate,
734	kCpumMsrWrFn_AmdFam15hLwpCfg,
735	kCpumMsrWrFn_AmdFam15hLwpCbAddr,
736	kCpumMsrWrFn_AmdFam10hMc4MiscN,
737	kCpumMsrWrFn_AmdK8PerfCtlN,
738	kCpumMsrWrFn_AmdK8PerfCtrN,
739	kCpumMsrWrFn_AmdK8SysCfg,
740	kCpumMsrWrFn_AmdK8HwCr,
741	kCpumMsrWrFn_AmdK8IorrBaseN,
742	kCpumMsrWrFn_AmdK8IorrMaskN,
743	kCpumMsrWrFn_AmdK8TopOfMemN,
744	kCpumMsrWrFn_AmdK8NbCfg1,
745	kCpumMsrWrFn_AmdK8McXcptRedir,
746	kCpumMsrWrFn_AmdK8CpuNameN,
747	kCpumMsrWrFn_AmdK8HwThermalCtrl,
748	kCpumMsrWrFn_AmdK8SwThermalCtrl,
749	kCpumMsrWrFn_AmdK8FidVidControl,
750	kCpumMsrWrFn_AmdK8McCtlMaskN,
751	kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
752	kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
753	kCpumMsrWrFn_AmdK8IntPendingMessage,
754	kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
755	kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
756	kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
757	kCpumMsrWrFn_AmdFam10hPStateControl,
758	kCpumMsrWrFn_AmdFam10hPStateStatus,
759	kCpumMsrWrFn_AmdFam10hPStateN,
760	kCpumMsrWrFn_AmdFam10hCofVidControl,
761	kCpumMsrWrFn_AmdFam10hCofVidStatus,
762	kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
763	kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
764	kCpumMsrWrFn_AmdK8SmmBase,
765	kCpumMsrWrFn_AmdK8SmmAddr,
766	kCpumMsrWrFn_AmdK8SmmMask,
767	kCpumMsrWrFn_AmdK8VmCr,
768	kCpumMsrWrFn_AmdK8IgnNe,
769	kCpumMsrWrFn_AmdK8SmmCtl,
770	kCpumMsrWrFn_AmdK8VmHSavePa,
771	kCpumMsrWrFn_AmdFam10hVmLockKey,
772	kCpumMsrWrFn_AmdFam10hSmmLockKey,
773	kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
774	kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
775	kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
776	kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
777	kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
778	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
779	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
780	kCpumMsrWrFn_AmdK7MicrocodeCtl,
781	kCpumMsrWrFn_AmdK7ClusterIdMaybe,
782	kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
783	kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
784	kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
785	kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
786	kCpumMsrWrFn_AmdK8PatchLoader,
787	kCpumMsrWrFn_AmdK7DebugStatusMaybe,
788	kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
789	kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
790	kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
791	kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
792	kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
793	kCpumMsrWrFn_AmdK7NodeId,
794	kCpumMsrWrFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
795	kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
796	kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
797	kCpumMsrWrFn_AmdK7LoadStoreCfg,
798	kCpumMsrWrFn_AmdK7InstrCacheCfg,
799	kCpumMsrWrFn_AmdK7DataCacheCfg,
800	kCpumMsrWrFn_AmdK7BusUnitCfg,
801	kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
802	kCpumMsrWrFn_AmdFam15hFpuCfg,
803	kCpumMsrWrFn_AmdFam15hDecoderCfg,
804	kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
805	kCpumMsrWrFn_AmdFam15hCombUnitCfg,
806	kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
807	kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
808	kCpumMsrWrFn_AmdFam15hExecUnitCfg,
809	kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
810	kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
811	kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
812	kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
813	kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
814	kCpumMsrWrFn_AmdFam10hIbsOpRip,
815	kCpumMsrWrFn_AmdFam10hIbsOpData,
816	kCpumMsrWrFn_AmdFam10hIbsOpData2,
817	kCpumMsrWrFn_AmdFam10hIbsOpData3,
818	kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
819	kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
820	kCpumMsrWrFn_AmdFam10hIbsCtl,
821	kCpumMsrWrFn_AmdFam14hIbsBrTarget,
822
823	kCpumMsrWrFn_Gim,
824
825	/** End of valid MSR write function indexes. */
826	kCpumMsrWrFn_End
827	} CPUMMSRWRFN;
828
829	/**
830	* MSR range.
831	*/
832	typedef struct CPUMMSRRANGE
833	{
834	/** The first MSR. [0] */
835	uint32_t uFirst;
836	/** The last MSR. [4] */
837	uint32_t uLast;
838	/** The read function (CPUMMSRRDFN). [8] */
839	uint16_t enmRdFn;
840	/** The write function (CPUMMSRWRFN). [10] */
841	uint16_t enmWrFn;
842	/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
843	* UINT16_MAX if not used by the read and write functions. [12] */
844	uint16_t offCpumCpu;
845	/** Reserved for future hacks. [14] */
846	uint16_t fReserved;
847	/** The init/read value. [16]
848	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
849	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
850	* offset into CPUM. */
851	uint64_t uValue;
852	/** The bits to ignore when writing. [24] */
853	uint64_t fWrIgnMask;
854	/** The bits that will cause a GP(0) when writing. [32]
855	* This is always checked prior to calling the write function. Using
856	* UINT64_MAX effectively marks the MSR as read-only. */
857	uint64_t fWrGpMask;
858	/** The register name, if applicable. [40] */
859	char szName[56];
860
861	#ifdef VBOX_WITH_STATISTICS
862	/** The number of reads. */
863	STAMCOUNTER cReads;
864	/** The number of writes. */
865	STAMCOUNTER cWrites;
866	/** The number of times ignored bits were written. */
867	STAMCOUNTER cIgnoredBits;
868	/** The number of GPs generated. */
869	STAMCOUNTER cGps;
870	#endif
871	} CPUMMSRRANGE;
872	#ifdef VBOX_WITH_STATISTICS
873	AssertCompileSize(CPUMMSRRANGE, 128);
874	#else
875	AssertCompileSize(CPUMMSRRANGE, 96);
876	#endif
877	/** Pointer to an MSR range. */
878	typedef CPUMMSRRANGE *PCPUMMSRRANGE;
879	/** Pointer to a const MSR range. */
880	typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
881
882
883	/** @name Guest Register Getters.
884	* @{ */
885	VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
886	VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
887	VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
888	VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
889	VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t pGCPtrBase, uint32_t pcbLimit);
890	VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
891	VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
892	VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
893	VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
894	VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
895	VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
896	VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
897	VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
898	VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
899	VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
900	VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
901	VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
902	VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
903	VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
904	VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
905	VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
906	VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
907	VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
908	VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
909	VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
910	VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
911	VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
912	VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
913	VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
914	VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
915	VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
916	VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
917	VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
918	VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
919	VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
920	VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
921	VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
922	VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
923	VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
924	VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
925	VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
926	VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
927	VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
928	VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
929	/** @} */
930
931	/** @name Guest Register Setters.
932	* @{ */
933	VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
934	VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
935	VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
936	VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
937	VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
938	VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
939	VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
940	VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
941	VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
942	VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
943	VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
944	VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
945	VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
946	VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
947	VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
948	VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
949	VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
950	VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
951	VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
952	VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
953	VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
954	VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
955	VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
956	VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
957	VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
958	VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
959	VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
960	VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
961	VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
962	VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
963	VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
964	VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
965	VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
966	VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
967	VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
968	VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
969	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
970	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
971	VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
972	VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu);
973	/** @} */
974
975
976	/** @name Misc Guest Predicate Functions.
977	* @{ */
978
979	VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
980	VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
981	VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
982	VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
983	VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
984	VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
985	VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
986	VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
987	VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
988	VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
989	VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
990	VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
991	VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
992	VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
993
994	#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
995
996	/**
997	* Tests if the guest is running in real mode or not.
998	*
999	* @returns true if in real mode, otherwise false.
1000	* @param pCtx Current CPU context
1001	*/
1002	DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
1003	{
1004	return !(pCtx->cr0 & X86_CR0_PE);
1005	}
1006
1007	/**
1008	* Tests if the guest is running in real or virtual 8086 mode.
1009	*
1010	* @returns @c true if it is, @c false if not.
1011	* @param pCtx Current CPU context
1012	*/
1013	DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
1014	{
1015	return !(pCtx->cr0 & X86_CR0_PE)
1016	\|\| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1017	}
1018
1019	/**
1020	* Tests if the guest is running in virtual 8086 mode.
1021	*
1022	* @returns @c true if it is, @c false if not.
1023	* @param pCtx Current CPU context
1024	*/
1025	DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCPUMCTX pCtx)
1026	{
1027	return (pCtx->eflags.Bits.u1VM == 1);
1028	}
1029
1030	/**
1031	* Tests if the guest is running in paged protected or not.
1032	*
1033	* @returns true if in paged protected mode, otherwise false.
1034	* @param pVM The VM handle.
1035	*/
1036	DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1037	{
1038	return (pCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
1039	}
1040
1041	/**
1042	* Tests if the guest is running in long mode or not.
1043	*
1044	* @returns true if in long mode, otherwise false.
1045	* @param pCtx Current CPU context
1046	*/
1047	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
1048	{
1049	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1050	}
1051
1052	VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1053
1054	/**
1055	* Tests if the guest is running in 64 bits mode or not.
1056	*
1057	* @returns true if in 64 bits protected mode, otherwise false.
1058	* @param pVCpu The current virtual CPU.
1059	* @param pCtx Current CPU context
1060	*/
1061	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1062	{
1063	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1064	return false;
1065	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1066	return CPUMIsGuestIn64BitCodeSlow(pCtx);
1067	return pCtx->cs.Attr.n.u1Long;
1068	}
1069
1070	/**
1071	* Tests if the guest has paging enabled or not.
1072	*
1073	* @returns true if paging is enabled, otherwise false.
1074	* @param pCtx Current CPU context
1075	*/
1076	DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCPUMCTX pCtx)
1077	{
1078	return !!(pCtx->cr0 & X86_CR0_PG);
1079	}
1080
1081	/**
1082	* Tests if the guest is running in PAE mode or not.
1083	*
1084	* @returns true if in PAE mode, otherwise false.
1085	* @param pCtx Current CPU context
1086	*/
1087	DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
1088	{
1089	/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1090	than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1091	return ( (pCtx->cr4 & X86_CR4_PAE)
1092	&& CPUMIsGuestPagingEnabledEx(pCtx)
1093	&& !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1094	}
1095
1096	#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
1097
1098	/** @} */
1099
1100
1101	/** @name Hypervisor Register Getters.
1102	* @{ */
1103	VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
1104	VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
1105	VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
1106	VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
1107	VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
1108	VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
1109	#if 0 /* these are not correct. */
1110	VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
1111	VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
1112	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1113	VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
1114	#endif
1115	/** This register is only saved on fatal traps. */
1116	VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
1117	VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
1118	/** This register is only saved on fatal traps. */
1119	VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
1120	/** This register is only saved on fatal traps. */
1121	VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
1122	VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
1123	VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
1124	VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
1125	VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
1126	VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
1127	VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
1128	VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
1129	VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1130	VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1131	VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
1132	VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
1133	VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
1134	VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
1135	VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
1136	VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
1137	VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
1138	VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
1139	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1140	/** @} */
1141
1142	/** @name Hypervisor Register Setters.
1143	* @{ */
1144	VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1145	VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
1146	VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1147	VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
1148	VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
1149	VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
1150	VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
1151	VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
1152	VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
1153	VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
1154	VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
1155	VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
1156	VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
1157	VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
1158	VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
1159	VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
1160	VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
1161	VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
1162	VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
1163	VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
1164	VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
1165	VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1166	VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper);
1167	/** @} */
1168
1169	VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
1170	VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
1171	VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
1172	VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
1173	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
1174	VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
1175	VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
1176	VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc);
1177	VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
1178	VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
1179
1180	/** @name Changed flags.
1181	* These flags are used to keep track of which important register that
1182	* have been changed since last they were reset. The only one allowed
1183	* to clear them is REM!
1184	* @{
1185	*/
1186	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
1187	#define CPUM_CHANGED_CR0 RT_BIT(1)
1188	#define CPUM_CHANGED_CR4 RT_BIT(2)
1189	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
1190	#define CPUM_CHANGED_CR3 RT_BIT(4)
1191	#define CPUM_CHANGED_GDTR RT_BIT(5)
1192	#define CPUM_CHANGED_IDTR RT_BIT(6)
1193	#define CPUM_CHANGED_LDTR RT_BIT(7)
1194	#define CPUM_CHANGED_TR RT_BIT(8) /*@< Currently unused. /
1195	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
1196	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /*@< Currently unused. /
1197	#define CPUM_CHANGED_CPUID RT_BIT(11)
1198	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
1199	\| CPUM_CHANGED_CR0 \
1200	\| CPUM_CHANGED_CR4 \
1201	\| CPUM_CHANGED_GLOBAL_TLB_FLUSH \
1202	\| CPUM_CHANGED_CR3 \
1203	\| CPUM_CHANGED_GDTR \
1204	\| CPUM_CHANGED_IDTR \
1205	\| CPUM_CHANGED_LDTR \
1206	\| CPUM_CHANGED_TR \
1207	\| CPUM_CHANGED_SYSENTER_MSR \
1208	\| CPUM_CHANGED_HIDDEN_SEL_REGS \
1209	\| CPUM_CHANGED_CPUID )
1210	/** @} */
1211
1212	VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags);
1213	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
1214	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
1215	VMMDECL(bool) CPUMSupportsFXSR(PVM pVM);
1216	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
1217	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
1218	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
1219	VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu);
1220	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
1221	VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
1222	VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
1223	VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
1224	VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
1225	VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
1226	VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
1227	VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
1228	VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
1229	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
1230
1231	/** @name Typical scalable bus frequency values.
1232	* @{ */
1233	/** Special internal value indicating that we don't know the frequency.
1234	* @internal */
1235	#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
1236	#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
1237	#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
1238	#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
1239	#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
1240	#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
1241	#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
1242	#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
1243	/** @} */
1244
1245
1246	#ifdef IN_RING3
1247	/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
1248	* @ingroup grp_cpum
1249	* @{
1250	*/
1251
1252	VMMR3DECL(int) CPUMR3Init(PVM pVM);
1253	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM);
1254	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM);
1255	VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
1256	VMMR3DECL(int) CPUMR3Term(PVM pVM);
1257	VMMR3DECL(void) CPUMR3Reset(PVM pVM);
1258	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1259	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
1260	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
1261	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
1262	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM);
1263	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM);
1264	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM);
1265	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM);
1266
1267	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
1268	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
1269	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
1270	uint8_t bModel, uint8_t bStepping);
1271	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
1272	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves);
1273	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
1274	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUKNOWNCPUID enmUnknownMethod);
1275	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1276	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
1277
1278	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
1279
1280	/** @} */
1281	#endif /* IN_RING3 */
1282
1283	#ifdef IN_RC
1284	/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
1285	* @ingroup grp_cpum
1286	* @{
1287	*/
1288
1289	/**
1290	* Calls a guest trap/interrupt handler directly
1291	*
1292	* Assumes a trap stack frame has already been setup on the guest's stack!
1293	* This function does not return!
1294	*
1295	* @param pRegFrame Original trap/interrupt context
1296	* @param selCS Code selector of handler
1297	* @param pHandler GC virtual address of handler
1298	* @param eflags Callee's EFLAGS
1299	* @param selSS Stack selector for handler
1300	* @param pEsp Stack address for handler
1301	*/
1302	DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
1303	uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1304
1305	/**
1306	* Call guest V86 code directly.
1307	*
1308	* This function does not return!
1309	*
1310	* @param pRegFrame Original trap/interrupt context
1311	*/
1312	DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1313
1314	VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
1315	VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
1316	#ifdef VBOX_WITH_RAW_RING1
1317	VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
1318	#endif
1319
1320	/** @} */
1321	#endif /* IN_RC */
1322
1323	#ifdef IN_RING0
1324	/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
1325	* @ingroup grp_cpum
1326	* @{
1327	*/
1328	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
1329	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
1330	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM);
1331	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1332	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1333	VMMR0_INT_DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1334	VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
1335	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6);
1336	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6);
1337
1338	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6);
1339	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6);
1340	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1341	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, RTCPUID idHostCpu);
1342	#endif
1343
1344	/** @} */
1345	#endif /* IN_RING0 */
1346
1347	/** @} */
1348	RT_C_DECLS_END
1349
1350
1351	#endif
1352

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source: vbox/trunk/include/VBox/vmm/cpum.h@ 52664

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