cpum.h@ 97150

Last change on this file since 97150 was 97096, checked in by vboxsync, 2 years ago
VMM/CPUM: Some code tweaking...
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpum_h
37	#define VBOX_INCLUDED_vmm_cpum_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <iprt/x86.h>
43	#include <VBox/types.h>
44	#include <VBox/vmm/cpumctx.h>
45	#include <VBox/vmm/stam.h>
46	#include <VBox/vmm/vmapi.h>
47	#include <VBox/vmm/hm_svm.h>
48	#include <VBox/vmm/hm_vmx.h>
49
50	RT_C_DECLS_BEGIN
51
52	/** @defgroup grp_cpum The CPU Monitor / Manager API
53	* @ingroup grp_vmm
54	* @{
55	*/
56
57	/**
58	* CPUID feature to set or clear.
59	*/
60	typedef enum CPUMCPUIDFEATURE
61	{
62	CPUMCPUIDFEATURE_INVALID = 0,
63	/** The APIC feature bit. (Std+Ext)
64	* Note! There is a per-cpu flag for masking this CPUID feature bit when the
65	* APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
66	* at VM construction time like all the others. This didn't used to be
67	* that way, this is new with 5.1. */
68	CPUMCPUIDFEATURE_APIC,
69	/** The sysenter/sysexit feature bit. (Std) */
70	CPUMCPUIDFEATURE_SEP,
71	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
72	CPUMCPUIDFEATURE_SYSCALL,
73	/** The PAE feature bit. (Std+Ext) */
74	CPUMCPUIDFEATURE_PAE,
75	/** The NX feature bit. (Ext) */
76	CPUMCPUIDFEATURE_NX,
77	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
78	CPUMCPUIDFEATURE_LAHF,
79	/** The LONG MODE feature bit. (Ext) */
80	CPUMCPUIDFEATURE_LONG_MODE,
81	/** The x2APIC feature bit. (Std) */
82	CPUMCPUIDFEATURE_X2APIC,
83	/** The RDTSCP feature bit. (Ext) */
84	CPUMCPUIDFEATURE_RDTSCP,
85	/** The Hypervisor Present bit. (Std) */
86	CPUMCPUIDFEATURE_HVP,
87	/** The speculation control feature bits. (StExt) */
88	CPUMCPUIDFEATURE_SPEC_CTRL,
89	/** 32bit hackishness. */
90	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
91	} CPUMCPUIDFEATURE;
92
93	/**
94	* CPU Vendor.
95	*/
96	typedef enum CPUMCPUVENDOR
97	{
98	CPUMCPUVENDOR_INVALID = 0,
99	CPUMCPUVENDOR_INTEL,
100	CPUMCPUVENDOR_AMD,
101	CPUMCPUVENDOR_VIA,
102	CPUMCPUVENDOR_CYRIX,
103	CPUMCPUVENDOR_SHANGHAI,
104	CPUMCPUVENDOR_HYGON,
105	CPUMCPUVENDOR_UNKNOWN,
106	/** 32bit hackishness. */
107	CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
108	} CPUMCPUVENDOR;
109
110
111	/**
112	* X86 and AMD64 CPU microarchitectures and in processor generations.
113	*
114	* @remarks The separation here is sometimes a little bit too finely grained,
115	* and the differences is more like processor generation than micro
116	* arch. This can be useful, so we'll provide functions for getting at
117	* more coarse grained info.
118	*/
119	typedef enum CPUMMICROARCH
120	{
121	kCpumMicroarch_Invalid = 0,
122
123	kCpumMicroarch_Intel_First,
124
125	kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
126	kCpumMicroarch_Intel_80186,
127	kCpumMicroarch_Intel_80286,
128	kCpumMicroarch_Intel_80386,
129	kCpumMicroarch_Intel_80486,
130	kCpumMicroarch_Intel_P5,
131
132	kCpumMicroarch_Intel_P6_Core_Atom_First,
133	kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
134	kCpumMicroarch_Intel_P6_II,
135	kCpumMicroarch_Intel_P6_III,
136
137	kCpumMicroarch_Intel_P6_M_Banias,
138	kCpumMicroarch_Intel_P6_M_Dothan,
139	kCpumMicroarch_Intel_Core_Yonah, /*< Core, also known as Enhanced Pentium M. /
140
141	kCpumMicroarch_Intel_Core2_First,
142	kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /*< 65nm, Merom/Conroe/Kentsfield/Tigerton /
143	kCpumMicroarch_Intel_Core2_Penryn, /*< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown /
144	kCpumMicroarch_Intel_Core2_End,
145
146	kCpumMicroarch_Intel_Core7_First,
147	kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
148	kCpumMicroarch_Intel_Core7_Westmere,
149	kCpumMicroarch_Intel_Core7_SandyBridge,
150	kCpumMicroarch_Intel_Core7_IvyBridge,
151	kCpumMicroarch_Intel_Core7_Haswell,
152	kCpumMicroarch_Intel_Core7_Broadwell,
153	kCpumMicroarch_Intel_Core7_Skylake,
154	kCpumMicroarch_Intel_Core7_KabyLake,
155	kCpumMicroarch_Intel_Core7_CoffeeLake,
156	kCpumMicroarch_Intel_Core7_WhiskeyLake,
157	kCpumMicroarch_Intel_Core7_CascadeLake,
158	kCpumMicroarch_Intel_Core7_CannonLake, /*< Limited 10nm. /
159	kCpumMicroarch_Intel_Core7_CometLake, /*< 10th gen, 14nm desktop + high power mobile. /
160	kCpumMicroarch_Intel_Core7_IceLake, /*< 10th gen, 10nm mobile and some Xeons. Actually 'Sunny Cove' march. /
161	kCpumMicroarch_Intel_Core7_SunnyCove = kCpumMicroarch_Intel_Core7_IceLake,
162	kCpumMicroarch_Intel_Core7_RocketLake, /*< 11th gen, 14nm desktop + high power mobile. Aka 'Cypress Cove', backport of 'Willow Cove' to 14nm. /
163	kCpumMicroarch_Intel_Core7_CypressCove = kCpumMicroarch_Intel_Core7_RocketLake,
164	kCpumMicroarch_Intel_Core7_TigerLake, /*< 11th gen, 10nm mobile. Actually 'Willow Cove' march. /
165	kCpumMicroarch_Intel_Core7_WillowCove = kCpumMicroarch_Intel_Core7_TigerLake,
166	kCpumMicroarch_Intel_Core7_AlderLake, /*< 12th gen, 10nm all platforms(?). /
167	kCpumMicroarch_Intel_Core7_SapphireRapids, /*< 12th? gen, 10nm server? /
168	kCpumMicroarch_Intel_Core7_End,
169
170	kCpumMicroarch_Intel_Atom_First,
171	kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
172	kCpumMicroarch_Intel_Atom_Lincroft, /*< Second generation bonnell (44nm). /
173	kCpumMicroarch_Intel_Atom_Saltwell, /*< 32nm shrink of Bonnell. /
174	kCpumMicroarch_Intel_Atom_Silvermont, /*< 22nm /
175	kCpumMicroarch_Intel_Atom_Airmount, /*< 14nm /
176	kCpumMicroarch_Intel_Atom_Goldmont, /*< 14nm /
177	kCpumMicroarch_Intel_Atom_GoldmontPlus, /*< 14nm /
178	kCpumMicroarch_Intel_Atom_Unknown,
179	kCpumMicroarch_Intel_Atom_End,
180
181
182	kCpumMicroarch_Intel_Phi_First,
183	kCpumMicroarch_Intel_Phi_KnightsFerry = kCpumMicroarch_Intel_Phi_First,
184	kCpumMicroarch_Intel_Phi_KnightsCorner,
185	kCpumMicroarch_Intel_Phi_KnightsLanding,
186	kCpumMicroarch_Intel_Phi_KnightsHill,
187	kCpumMicroarch_Intel_Phi_KnightsMill,
188	kCpumMicroarch_Intel_Phi_End,
189
190	kCpumMicroarch_Intel_P6_Core_Atom_End,
191
192	kCpumMicroarch_Intel_NB_First,
193	kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /*< 180nm /
194	kCpumMicroarch_Intel_NB_Northwood, /*< 130nm /
195	kCpumMicroarch_Intel_NB_Prescott, /*< 90nm /
196	kCpumMicroarch_Intel_NB_Prescott2M, /*< 90nm /
197	kCpumMicroarch_Intel_NB_CedarMill, /*< 65nm /
198	kCpumMicroarch_Intel_NB_Gallatin, /*< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). /
199	kCpumMicroarch_Intel_NB_Unknown,
200	kCpumMicroarch_Intel_NB_End,
201
202	kCpumMicroarch_Intel_Unknown,
203	kCpumMicroarch_Intel_End,
204
205	kCpumMicroarch_AMD_First,
206	kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
207	kCpumMicroarch_AMD_Am386,
208	kCpumMicroarch_AMD_Am486,
209	kCpumMicroarch_AMD_Am486Enh, /*< Covers Am5x86 as well. /
210	kCpumMicroarch_AMD_K5,
211	kCpumMicroarch_AMD_K6,
212
213	kCpumMicroarch_AMD_K7_First,
214	kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
215	kCpumMicroarch_AMD_K7_Spitfire,
216	kCpumMicroarch_AMD_K7_Thunderbird,
217	kCpumMicroarch_AMD_K7_Morgan,
218	kCpumMicroarch_AMD_K7_Thoroughbred,
219	kCpumMicroarch_AMD_K7_Barton,
220	kCpumMicroarch_AMD_K7_Unknown,
221	kCpumMicroarch_AMD_K7_End,
222
223	kCpumMicroarch_AMD_K8_First,
224	kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /*< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin /
225	kCpumMicroarch_AMD_K8_90nm, /*< 90nm shrink /
226	kCpumMicroarch_AMD_K8_90nm_DualCore, /*< 90nm with two cores. /
227	kCpumMicroarch_AMD_K8_90nm_AMDV, /*< 90nm with AMD-V (usually) and two cores (usually). /
228	kCpumMicroarch_AMD_K8_65nm, /*< 65nm shrink. /
229	kCpumMicroarch_AMD_K8_End,
230
231	kCpumMicroarch_AMD_K10,
232	kCpumMicroarch_AMD_K10_Lion,
233	kCpumMicroarch_AMD_K10_Llano,
234	kCpumMicroarch_AMD_Bobcat,
235	kCpumMicroarch_AMD_Jaguar,
236
237	kCpumMicroarch_AMD_15h_First,
238	kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
239	kCpumMicroarch_AMD_15h_Piledriver,
240	kCpumMicroarch_AMD_15h_Steamroller, /*< Yet to be released, might have different family. /
241	kCpumMicroarch_AMD_15h_Excavator, /*< Yet to be released, might have different family. /
242	kCpumMicroarch_AMD_15h_Unknown,
243	kCpumMicroarch_AMD_15h_End,
244
245	kCpumMicroarch_AMD_16h_First,
246	kCpumMicroarch_AMD_16h_End,
247
248	kCpumMicroarch_AMD_Zen_First,
249	kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
250	kCpumMicroarch_AMD_Zen_End,
251
252	kCpumMicroarch_AMD_Unknown,
253	kCpumMicroarch_AMD_End,
254
255	kCpumMicroarch_Hygon_First,
256	kCpumMicroarch_Hygon_Dhyana = kCpumMicroarch_Hygon_First,
257	kCpumMicroarch_Hygon_Unknown,
258	kCpumMicroarch_Hygon_End,
259
260	kCpumMicroarch_VIA_First,
261	kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
262	kCpumMicroarch_Centaur_C2,
263	kCpumMicroarch_Centaur_C3,
264	kCpumMicroarch_VIA_C3_M2,
265	kCpumMicroarch_VIA_C3_C5A, /*< 180nm Samuel - Cyrix III, C3, 1GigaPro. /
266	kCpumMicroarch_VIA_C3_C5B, /*< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. /
267	kCpumMicroarch_VIA_C3_C5C, /*< 130nm Ezra - C3, Eden ESP. /
268	kCpumMicroarch_VIA_C3_C5N, /*< 130nm Ezra-T - C3. /
269	kCpumMicroarch_VIA_C3_C5XL, /*< 130nm Nehemiah - C3, Eden ESP, Eden-N. /
270	kCpumMicroarch_VIA_C3_C5P, /*< 130nm Nehemiah+ - C3. /
271	kCpumMicroarch_VIA_C7_C5J, /*< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. /
272	kCpumMicroarch_VIA_Isaiah,
273	kCpumMicroarch_VIA_Unknown,
274	kCpumMicroarch_VIA_End,
275
276	kCpumMicroarch_Shanghai_First,
277	kCpumMicroarch_Shanghai_Wudaokou = kCpumMicroarch_Shanghai_First,
278	kCpumMicroarch_Shanghai_Unknown,
279	kCpumMicroarch_Shanghai_End,
280
281	kCpumMicroarch_Cyrix_First,
282	kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
283	kCpumMicroarch_Cyrix_M1,
284	kCpumMicroarch_Cyrix_MediaGX,
285	kCpumMicroarch_Cyrix_MediaGXm,
286	kCpumMicroarch_Cyrix_M2,
287	kCpumMicroarch_Cyrix_Unknown,
288	kCpumMicroarch_Cyrix_End,
289
290	kCpumMicroarch_NEC_First,
291	kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
292	kCpumMicroarch_NEC_V30,
293	kCpumMicroarch_NEC_End,
294
295	kCpumMicroarch_Unknown,
296
297	kCpumMicroarch_32BitHack = 0x7fffffff
298	} CPUMMICROARCH;
299
300
301	/** Predicate macro for catching netburst CPUs. */
302	#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
303	((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
304
305	/** Predicate macro for catching Core7 CPUs. */
306	#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
307	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
308
309	/** Predicate macro for catching Core 2 CPUs. */
310	#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
311	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
312
313	/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
314	#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
315	((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
316
317	/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
318	#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
319	((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
320
321	/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
322	#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
323
324	/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
325	#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
326
327	/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
328	#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
329
330	/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
331	#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
332
333	/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
334	* decendants). */
335	#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
336	((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
337
338	/** Predicate macro for catching AMD Family 16H CPUs. */
339	#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
340	((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
341
342	/** Predicate macro for catching AMD Zen Family CPUs. */
343	#define CPUMMICROARCH_IS_AMD_FAM_ZEN(a_enmMicroarch) \
344	((a_enmMicroarch) >= kCpumMicroarch_AMD_Zen_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_Zen_End)
345
346
347	/**
348	* CPUID leaf.
349	*
350	* @remarks This structure is used by the patch manager and is therefore
351	* more or less set in stone.
352	*/
353	typedef struct CPUMCPUIDLEAF
354	{
355	/** The leaf number. */
356	uint32_t uLeaf;
357	/** The sub-leaf number. */
358	uint32_t uSubLeaf;
359	/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
360	uint32_t fSubLeafMask;
361
362	/** The EAX value. */
363	uint32_t uEax;
364	/** The EBX value. */
365	uint32_t uEbx;
366	/** The ECX value. */
367	uint32_t uEcx;
368	/** The EDX value. */
369	uint32_t uEdx;
370
371	/** Flags. */
372	uint32_t fFlags;
373	} CPUMCPUIDLEAF;
374	#ifndef VBOX_FOR_DTRACE_LIB
375	AssertCompileSize(CPUMCPUIDLEAF, 32);
376	#endif
377	/** Pointer to a CPUID leaf. */
378	typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
379	/** Pointer to a const CPUID leaf. */
380	typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
381
382	/** @name CPUMCPUIDLEAF::fFlags
383	* @{ */
384	/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
385	* and EDX containing the extended APIC ID. */
386	#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
387	/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
388	#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
389	/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
390	#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
391	/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
392	#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
393	/** Mask of the valid flags. */
394	#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
395	/** @} */
396
397	/**
398	* Method used to deal with unknown CPUID leaves.
399	* @remarks Used in patch code.
400	*/
401	typedef enum CPUMUNKNOWNCPUID
402	{
403	/** Invalid zero value. */
404	CPUMUNKNOWNCPUID_INVALID = 0,
405	/** Use given default values (DefCpuId). */
406	CPUMUNKNOWNCPUID_DEFAULTS,
407	/** Return the last standard leaf.
408	* Intel Sandy Bridge has been observed doing this. */
409	CPUMUNKNOWNCPUID_LAST_STD_LEAF,
410	/** Return the last standard leaf, with ecx observed.
411	* Intel Sandy Bridge has been observed doing this. */
412	CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
413	/** The register values are passed thru unmodified. */
414	CPUMUNKNOWNCPUID_PASSTHRU,
415	/** End of valid value. */
416	CPUMUNKNOWNCPUID_END,
417	/** Ensure 32-bit type. */
418	CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
419	} CPUMUNKNOWNCPUID;
420	/** Pointer to unknown CPUID leaf method. */
421	typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
422
423
424	/**
425	* The register set returned by a CPUID operation.
426	*/
427	typedef struct CPUMCPUID
428	{
429	uint32_t uEax;
430	uint32_t uEbx;
431	uint32_t uEcx;
432	uint32_t uEdx;
433	} CPUMCPUID;
434	/** Pointer to a CPUID leaf. */
435	typedef CPUMCPUID *PCPUMCPUID;
436	/** Pointer to a const CPUID leaf. */
437	typedef const CPUMCPUID *PCCPUMCPUID;
438
439
440	/**
441	* MSR read functions.
442	*/
443	typedef enum CPUMMSRRDFN
444	{
445	/** Invalid zero value. */
446	kCpumMsrRdFn_Invalid = 0,
447	/** Return the CPUMMSRRANGE::uValue. */
448	kCpumMsrRdFn_FixedValue,
449	/** Alias to the MSR range starting at the MSR given by
450	* CPUMMSRRANGE::uValue. Must be used in pair with
451	* kCpumMsrWrFn_MsrAlias. */
452	kCpumMsrRdFn_MsrAlias,
453	/** Write only register, GP all read attempts. */
454	kCpumMsrRdFn_WriteOnly,
455
456	kCpumMsrRdFn_Ia32P5McAddr,
457	kCpumMsrRdFn_Ia32P5McType,
458	kCpumMsrRdFn_Ia32TimestampCounter,
459	kCpumMsrRdFn_Ia32PlatformId, /*< Takes real CPU value for reference. /
460	kCpumMsrRdFn_Ia32ApicBase,
461	kCpumMsrRdFn_Ia32FeatureControl,
462	kCpumMsrRdFn_Ia32BiosSignId, /*< Range value returned. /
463	kCpumMsrRdFn_Ia32SmmMonitorCtl,
464	kCpumMsrRdFn_Ia32PmcN,
465	kCpumMsrRdFn_Ia32MonitorFilterLineSize,
466	kCpumMsrRdFn_Ia32MPerf,
467	kCpumMsrRdFn_Ia32APerf,
468	kCpumMsrRdFn_Ia32MtrrCap, /*< Takes real CPU value for reference. /
469	kCpumMsrRdFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
470	kCpumMsrRdFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
471	kCpumMsrRdFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
472	kCpumMsrRdFn_Ia32MtrrDefType,
473	kCpumMsrRdFn_Ia32Pat,
474	kCpumMsrRdFn_Ia32SysEnterCs,
475	kCpumMsrRdFn_Ia32SysEnterEsp,
476	kCpumMsrRdFn_Ia32SysEnterEip,
477	kCpumMsrRdFn_Ia32McgCap,
478	kCpumMsrRdFn_Ia32McgStatus,
479	kCpumMsrRdFn_Ia32McgCtl,
480	kCpumMsrRdFn_Ia32DebugCtl,
481	kCpumMsrRdFn_Ia32SmrrPhysBase,
482	kCpumMsrRdFn_Ia32SmrrPhysMask,
483	kCpumMsrRdFn_Ia32PlatformDcaCap,
484	kCpumMsrRdFn_Ia32CpuDcaCap,
485	kCpumMsrRdFn_Ia32Dca0Cap,
486	kCpumMsrRdFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
487	kCpumMsrRdFn_Ia32PerfStatus, /*< Range value returned. /
488	kCpumMsrRdFn_Ia32PerfCtl, /*< Range value returned. /
489	kCpumMsrRdFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
490	kCpumMsrRdFn_Ia32PerfCapabilities, /*< Takes reference value. /
491	kCpumMsrRdFn_Ia32FixedCtrCtrl,
492	kCpumMsrRdFn_Ia32PerfGlobalStatus, /*< Takes reference value. /
493	kCpumMsrRdFn_Ia32PerfGlobalCtrl,
494	kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
495	kCpumMsrRdFn_Ia32PebsEnable,
496	kCpumMsrRdFn_Ia32ClockModulation, /*< Range value returned. /
497	kCpumMsrRdFn_Ia32ThermInterrupt, /*< Range value returned. /
498	kCpumMsrRdFn_Ia32ThermStatus, /*< Range value returned. /
499	kCpumMsrRdFn_Ia32Therm2Ctl, /*< Range value returned. /
500	kCpumMsrRdFn_Ia32MiscEnable, /*< Range value returned. /
501	kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
502	kCpumMsrRdFn_Ia32McNCtl2, /*< Takes register number of start of range. /
503	kCpumMsrRdFn_Ia32DsArea,
504	kCpumMsrRdFn_Ia32TscDeadline,
505	kCpumMsrRdFn_Ia32X2ApicN,
506	kCpumMsrRdFn_Ia32DebugInterface,
507	kCpumMsrRdFn_Ia32VmxBasic, /*< Takes real value as reference. /
508	kCpumMsrRdFn_Ia32VmxPinbasedCtls, /*< Takes real value as reference. /
509	kCpumMsrRdFn_Ia32VmxProcbasedCtls, /*< Takes real value as reference. /
510	kCpumMsrRdFn_Ia32VmxExitCtls, /*< Takes real value as reference. /
511	kCpumMsrRdFn_Ia32VmxEntryCtls, /*< Takes real value as reference. /
512	kCpumMsrRdFn_Ia32VmxMisc, /*< Takes real value as reference. /
513	kCpumMsrRdFn_Ia32VmxCr0Fixed0, /*< Takes real value as reference. /
514	kCpumMsrRdFn_Ia32VmxCr0Fixed1, /*< Takes real value as reference. /
515	kCpumMsrRdFn_Ia32VmxCr4Fixed0, /*< Takes real value as reference. /
516	kCpumMsrRdFn_Ia32VmxCr4Fixed1, /*< Takes real value as reference. /
517	kCpumMsrRdFn_Ia32VmxVmcsEnum, /*< Takes real value as reference. /
518	kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /*< Takes real value as reference. /
519	kCpumMsrRdFn_Ia32VmxEptVpidCap, /*< Takes real value as reference. /
520	kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /*< Takes real value as reference. /
521	kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /*< Takes real value as reference. /
522	kCpumMsrRdFn_Ia32VmxTrueExitCtls, /*< Takes real value as reference. /
523	kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /*< Takes real value as reference. /
524	kCpumMsrRdFn_Ia32VmxVmFunc, /*< Takes real value as reference. /
525	kCpumMsrRdFn_Ia32SpecCtrl,
526	kCpumMsrRdFn_Ia32ArchCapabilities,
527
528	kCpumMsrRdFn_Amd64Efer,
529	kCpumMsrRdFn_Amd64SyscallTarget,
530	kCpumMsrRdFn_Amd64LongSyscallTarget,
531	kCpumMsrRdFn_Amd64CompSyscallTarget,
532	kCpumMsrRdFn_Amd64SyscallFlagMask,
533	kCpumMsrRdFn_Amd64FsBase,
534	kCpumMsrRdFn_Amd64GsBase,
535	kCpumMsrRdFn_Amd64KernelGsBase,
536	kCpumMsrRdFn_Amd64TscAux,
537
538	kCpumMsrRdFn_IntelEblCrPowerOn,
539	kCpumMsrRdFn_IntelI7CoreThreadCount,
540	kCpumMsrRdFn_IntelP4EbcHardPowerOn,
541	kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
542	kCpumMsrRdFn_IntelP4EbcFrequencyId,
543	kCpumMsrRdFn_IntelP6FsbFrequency, /*< Takes real value as reference. /
544	kCpumMsrRdFn_IntelPlatformInfo,
545	kCpumMsrRdFn_IntelFlexRatio, /*< Takes real value as reference. /
546	kCpumMsrRdFn_IntelPkgCStConfigControl,
547	kCpumMsrRdFn_IntelPmgIoCaptureBase,
548	kCpumMsrRdFn_IntelLastBranchFromToN,
549	kCpumMsrRdFn_IntelLastBranchFromN,
550	kCpumMsrRdFn_IntelLastBranchToN,
551	kCpumMsrRdFn_IntelLastBranchTos,
552	kCpumMsrRdFn_IntelBblCrCtl,
553	kCpumMsrRdFn_IntelBblCrCtl3,
554	kCpumMsrRdFn_IntelI7TemperatureTarget, /*< Range value returned. /
555	kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/*< Takes register number. /
556	kCpumMsrRdFn_IntelI7MiscPwrMgmt,
557	kCpumMsrRdFn_IntelP6CrN,
558	kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
559	kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
560	kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
561	kCpumMsrRdFn_IntelI7SandyAesNiCtl,
562	kCpumMsrRdFn_IntelI7TurboRatioLimit, /*< Returns range value. /
563	kCpumMsrRdFn_IntelI7LbrSelect,
564	kCpumMsrRdFn_IntelI7SandyErrorControl,
565	kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/*< Returns range value. /
566	kCpumMsrRdFn_IntelI7PowerCtl,
567	kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
568	kCpumMsrRdFn_IntelI7PebsLdLat,
569	kCpumMsrRdFn_IntelI7PkgCnResidencyN, /*< Takes C-state number. /
570	kCpumMsrRdFn_IntelI7CoreCnResidencyN, /*< Takes C-state number. /
571	kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/*< Takes real value as reference. /
572	kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /*< Takes real value as reference. /
573	kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /*< Takes real value as reference. /
574	kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /*< Takes real value as reference. /
575	kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /*< Takes real value as reference. /
576	kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /*< Takes real value as reference. /
577	kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /*< Takes real value as reference. /
578	kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /*< Takes real value as reference. /
579	kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /*< Takes real value as reference. /
580	kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /*< Takes real value as reference. /
581	kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/*< Takes real value as reference. /
582	kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /*< Takes real value as reference. /
583	kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /*< Takes real value as reference. /
584	kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /*< Takes real value as reference. /
585	kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /*< Takes real value as reference. /
586	kCpumMsrRdFn_IntelI7RaplPp0Policy, /*< Takes real value as reference. /
587	kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /*< Takes real value as reference. /
588	kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /*< Takes real value as reference. /
589	kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /*< Takes real value as reference. /
590	kCpumMsrRdFn_IntelI7RaplPp1Policy, /*< Takes real value as reference. /
591	kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /*< Takes real value as reference. /
592	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /*< Takes real value as reference. /
593	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /*< Takes real value as reference. /
594	kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
595	kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
596	kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
597	kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
598	kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
599	kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
600	kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
601	kCpumMsrRdFn_IntelI7UncCBoxConfig,
602	kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
603	kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
604	kCpumMsrRdFn_IntelI7SmiCount,
605	kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /*< Range value returned. /
606	kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
607	kCpumMsrRdFn_IntelCore1ExtConfig,
608	kCpumMsrRdFn_IntelCore1DtsCalControl,
609	kCpumMsrRdFn_IntelCore2PeciControl,
610	kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
611
612	kCpumMsrRdFn_P6LastBranchFromIp,
613	kCpumMsrRdFn_P6LastBranchToIp,
614	kCpumMsrRdFn_P6LastIntFromIp,
615	kCpumMsrRdFn_P6LastIntToIp,
616
617	kCpumMsrRdFn_AmdFam15hTscRate,
618	kCpumMsrRdFn_AmdFam15hLwpCfg,
619	kCpumMsrRdFn_AmdFam15hLwpCbAddr,
620	kCpumMsrRdFn_AmdFam10hMc4MiscN,
621	kCpumMsrRdFn_AmdK8PerfCtlN,
622	kCpumMsrRdFn_AmdK8PerfCtrN,
623	kCpumMsrRdFn_AmdK8SysCfg, /*< Range value returned. /
624	kCpumMsrRdFn_AmdK8HwCr,
625	kCpumMsrRdFn_AmdK8IorrBaseN,
626	kCpumMsrRdFn_AmdK8IorrMaskN,
627	kCpumMsrRdFn_AmdK8TopOfMemN,
628	kCpumMsrRdFn_AmdK8NbCfg1,
629	kCpumMsrRdFn_AmdK8McXcptRedir,
630	kCpumMsrRdFn_AmdK8CpuNameN,
631	kCpumMsrRdFn_AmdK8HwThermalCtrl, /*< Range value returned. /
632	kCpumMsrRdFn_AmdK8SwThermalCtrl,
633	kCpumMsrRdFn_AmdK8FidVidControl, /*< Range value returned. /
634	kCpumMsrRdFn_AmdK8FidVidStatus, /*< Range value returned. /
635	kCpumMsrRdFn_AmdK8McCtlMaskN,
636	kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
637	kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
638	kCpumMsrRdFn_AmdK8IntPendingMessage,
639	kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
640	kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
641	kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
642	kCpumMsrRdFn_AmdFam10hPStateCurLimit, /*< Returns range value. /
643	kCpumMsrRdFn_AmdFam10hPStateControl, /*< Returns range value. /
644	kCpumMsrRdFn_AmdFam10hPStateStatus, /*< Returns range value. /
645	kCpumMsrRdFn_AmdFam10hPStateN, /*< Returns range value. This isn't an register index! /
646	kCpumMsrRdFn_AmdFam10hCofVidControl, /*< Returns range value. /
647	kCpumMsrRdFn_AmdFam10hCofVidStatus, /*< Returns range value. /
648	kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
649	kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
650	kCpumMsrRdFn_AmdK8SmmBase,
651	kCpumMsrRdFn_AmdK8SmmAddr,
652	kCpumMsrRdFn_AmdK8SmmMask,
653	kCpumMsrRdFn_AmdK8VmCr,
654	kCpumMsrRdFn_AmdK8IgnNe,
655	kCpumMsrRdFn_AmdK8SmmCtl,
656	kCpumMsrRdFn_AmdK8VmHSavePa,
657	kCpumMsrRdFn_AmdFam10hVmLockKey,
658	kCpumMsrRdFn_AmdFam10hSmmLockKey,
659	kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
660	kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
661	kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
662	kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
663	kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
664	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
665	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
666	kCpumMsrRdFn_AmdK7MicrocodeCtl, /*< Returns range value. /
667	kCpumMsrRdFn_AmdK7ClusterIdMaybe, /*< Returns range value. /
668	kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
669	kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
670	kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
671	kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
672	kCpumMsrRdFn_AmdK8PatchLevel, /*< Returns range value. /
673	kCpumMsrRdFn_AmdK7DebugStatusMaybe,
674	kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
675	kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
676	kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
677	kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
678	kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
679	kCpumMsrRdFn_AmdK7NodeId,
680	kCpumMsrRdFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
681	kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
682	kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
683	kCpumMsrRdFn_AmdK7LoadStoreCfg,
684	kCpumMsrRdFn_AmdK7InstrCacheCfg,
685	kCpumMsrRdFn_AmdK7DataCacheCfg,
686	kCpumMsrRdFn_AmdK7BusUnitCfg,
687	kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
688	kCpumMsrRdFn_AmdFam15hFpuCfg,
689	kCpumMsrRdFn_AmdFam15hDecoderCfg,
690	kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
691	kCpumMsrRdFn_AmdFam15hCombUnitCfg,
692	kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
693	kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
694	kCpumMsrRdFn_AmdFam15hExecUnitCfg,
695	kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
696	kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
697	kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
698	kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
699	kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
700	kCpumMsrRdFn_AmdFam10hIbsOpRip,
701	kCpumMsrRdFn_AmdFam10hIbsOpData,
702	kCpumMsrRdFn_AmdFam10hIbsOpData2,
703	kCpumMsrRdFn_AmdFam10hIbsOpData3,
704	kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
705	kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
706	kCpumMsrRdFn_AmdFam10hIbsCtl,
707	kCpumMsrRdFn_AmdFam14hIbsBrTarget,
708
709	kCpumMsrRdFn_Gim,
710
711	/** End of valid MSR read function indexes. */
712	kCpumMsrRdFn_End
713	} CPUMMSRRDFN;
714
715	/**
716	* MSR write functions.
717	*/
718	typedef enum CPUMMSRWRFN
719	{
720	/** Invalid zero value. */
721	kCpumMsrWrFn_Invalid = 0,
722	/** Writes are ignored, the fWrGpMask is observed though. */
723	kCpumMsrWrFn_IgnoreWrite,
724	/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
725	kCpumMsrWrFn_ReadOnly,
726	/** Alias to the MSR range starting at the MSR given by
727	* CPUMMSRRANGE::uValue. Must be used in pair with
728	* kCpumMsrRdFn_MsrAlias. */
729	kCpumMsrWrFn_MsrAlias,
730
731	kCpumMsrWrFn_Ia32P5McAddr,
732	kCpumMsrWrFn_Ia32P5McType,
733	kCpumMsrWrFn_Ia32TimestampCounter,
734	kCpumMsrWrFn_Ia32ApicBase,
735	kCpumMsrWrFn_Ia32FeatureControl,
736	kCpumMsrWrFn_Ia32BiosSignId,
737	kCpumMsrWrFn_Ia32BiosUpdateTrigger,
738	kCpumMsrWrFn_Ia32SmmMonitorCtl,
739	kCpumMsrWrFn_Ia32PmcN,
740	kCpumMsrWrFn_Ia32MonitorFilterLineSize,
741	kCpumMsrWrFn_Ia32MPerf,
742	kCpumMsrWrFn_Ia32APerf,
743	kCpumMsrWrFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
744	kCpumMsrWrFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
745	kCpumMsrWrFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
746	kCpumMsrWrFn_Ia32MtrrDefType,
747	kCpumMsrWrFn_Ia32Pat,
748	kCpumMsrWrFn_Ia32SysEnterCs,
749	kCpumMsrWrFn_Ia32SysEnterEsp,
750	kCpumMsrWrFn_Ia32SysEnterEip,
751	kCpumMsrWrFn_Ia32McgStatus,
752	kCpumMsrWrFn_Ia32McgCtl,
753	kCpumMsrWrFn_Ia32DebugCtl,
754	kCpumMsrWrFn_Ia32SmrrPhysBase,
755	kCpumMsrWrFn_Ia32SmrrPhysMask,
756	kCpumMsrWrFn_Ia32PlatformDcaCap,
757	kCpumMsrWrFn_Ia32Dca0Cap,
758	kCpumMsrWrFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
759	kCpumMsrWrFn_Ia32PerfStatus,
760	kCpumMsrWrFn_Ia32PerfCtl,
761	kCpumMsrWrFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
762	kCpumMsrWrFn_Ia32PerfCapabilities,
763	kCpumMsrWrFn_Ia32FixedCtrCtrl,
764	kCpumMsrWrFn_Ia32PerfGlobalStatus,
765	kCpumMsrWrFn_Ia32PerfGlobalCtrl,
766	kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
767	kCpumMsrWrFn_Ia32PebsEnable,
768	kCpumMsrWrFn_Ia32ClockModulation,
769	kCpumMsrWrFn_Ia32ThermInterrupt,
770	kCpumMsrWrFn_Ia32ThermStatus,
771	kCpumMsrWrFn_Ia32Therm2Ctl,
772	kCpumMsrWrFn_Ia32MiscEnable,
773	kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
774	kCpumMsrWrFn_Ia32McNCtl2, /*< Takes register number of start of range. /
775	kCpumMsrWrFn_Ia32DsArea,
776	kCpumMsrWrFn_Ia32TscDeadline,
777	kCpumMsrWrFn_Ia32X2ApicN,
778	kCpumMsrWrFn_Ia32DebugInterface,
779	kCpumMsrWrFn_Ia32SpecCtrl,
780	kCpumMsrWrFn_Ia32PredCmd,
781	kCpumMsrWrFn_Ia32FlushCmd,
782
783	kCpumMsrWrFn_Amd64Efer,
784	kCpumMsrWrFn_Amd64SyscallTarget,
785	kCpumMsrWrFn_Amd64LongSyscallTarget,
786	kCpumMsrWrFn_Amd64CompSyscallTarget,
787	kCpumMsrWrFn_Amd64SyscallFlagMask,
788	kCpumMsrWrFn_Amd64FsBase,
789	kCpumMsrWrFn_Amd64GsBase,
790	kCpumMsrWrFn_Amd64KernelGsBase,
791	kCpumMsrWrFn_Amd64TscAux,
792	kCpumMsrWrFn_IntelEblCrPowerOn,
793	kCpumMsrWrFn_IntelP4EbcHardPowerOn,
794	kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
795	kCpumMsrWrFn_IntelP4EbcFrequencyId,
796	kCpumMsrWrFn_IntelFlexRatio,
797	kCpumMsrWrFn_IntelPkgCStConfigControl,
798	kCpumMsrWrFn_IntelPmgIoCaptureBase,
799	kCpumMsrWrFn_IntelLastBranchFromToN,
800	kCpumMsrWrFn_IntelLastBranchFromN,
801	kCpumMsrWrFn_IntelLastBranchToN,
802	kCpumMsrWrFn_IntelLastBranchTos,
803	kCpumMsrWrFn_IntelBblCrCtl,
804	kCpumMsrWrFn_IntelBblCrCtl3,
805	kCpumMsrWrFn_IntelI7TemperatureTarget,
806	kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /*< Takes register number. /
807	kCpumMsrWrFn_IntelI7MiscPwrMgmt,
808	kCpumMsrWrFn_IntelP6CrN,
809	kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
810	kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
811	kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
812	kCpumMsrWrFn_IntelI7SandyAesNiCtl,
813	kCpumMsrWrFn_IntelI7TurboRatioLimit,
814	kCpumMsrWrFn_IntelI7LbrSelect,
815	kCpumMsrWrFn_IntelI7SandyErrorControl,
816	kCpumMsrWrFn_IntelI7PowerCtl,
817	kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
818	kCpumMsrWrFn_IntelI7PebsLdLat,
819	kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
820	kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
821	kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /*< R/O but found writable bits on a Silvermont CPU here. /
822	kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
823	kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /*< R/O but found writable bits on a Silvermont CPU here. /
824	kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
825	kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
826	kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
827	kCpumMsrWrFn_IntelI7RaplPp0Policy,
828	kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
829	kCpumMsrWrFn_IntelI7RaplPp1Policy,
830	kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
831	kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
832	kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
833	kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
834	kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
835	kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
836	kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
837	kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
838	kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
839	kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
840	kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
841	kCpumMsrWrFn_IntelCore1ExtConfig,
842	kCpumMsrWrFn_IntelCore1DtsCalControl,
843	kCpumMsrWrFn_IntelCore2PeciControl,
844
845	kCpumMsrWrFn_P6LastIntFromIp,
846	kCpumMsrWrFn_P6LastIntToIp,
847
848	kCpumMsrWrFn_AmdFam15hTscRate,
849	kCpumMsrWrFn_AmdFam15hLwpCfg,
850	kCpumMsrWrFn_AmdFam15hLwpCbAddr,
851	kCpumMsrWrFn_AmdFam10hMc4MiscN,
852	kCpumMsrWrFn_AmdK8PerfCtlN,
853	kCpumMsrWrFn_AmdK8PerfCtrN,
854	kCpumMsrWrFn_AmdK8SysCfg,
855	kCpumMsrWrFn_AmdK8HwCr,
856	kCpumMsrWrFn_AmdK8IorrBaseN,
857	kCpumMsrWrFn_AmdK8IorrMaskN,
858	kCpumMsrWrFn_AmdK8TopOfMemN,
859	kCpumMsrWrFn_AmdK8NbCfg1,
860	kCpumMsrWrFn_AmdK8McXcptRedir,
861	kCpumMsrWrFn_AmdK8CpuNameN,
862	kCpumMsrWrFn_AmdK8HwThermalCtrl,
863	kCpumMsrWrFn_AmdK8SwThermalCtrl,
864	kCpumMsrWrFn_AmdK8FidVidControl,
865	kCpumMsrWrFn_AmdK8McCtlMaskN,
866	kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
867	kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
868	kCpumMsrWrFn_AmdK8IntPendingMessage,
869	kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
870	kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
871	kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
872	kCpumMsrWrFn_AmdFam10hPStateControl,
873	kCpumMsrWrFn_AmdFam10hPStateStatus,
874	kCpumMsrWrFn_AmdFam10hPStateN,
875	kCpumMsrWrFn_AmdFam10hCofVidControl,
876	kCpumMsrWrFn_AmdFam10hCofVidStatus,
877	kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
878	kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
879	kCpumMsrWrFn_AmdK8SmmBase,
880	kCpumMsrWrFn_AmdK8SmmAddr,
881	kCpumMsrWrFn_AmdK8SmmMask,
882	kCpumMsrWrFn_AmdK8VmCr,
883	kCpumMsrWrFn_AmdK8IgnNe,
884	kCpumMsrWrFn_AmdK8SmmCtl,
885	kCpumMsrWrFn_AmdK8VmHSavePa,
886	kCpumMsrWrFn_AmdFam10hVmLockKey,
887	kCpumMsrWrFn_AmdFam10hSmmLockKey,
888	kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
889	kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
890	kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
891	kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
892	kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
893	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
894	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
895	kCpumMsrWrFn_AmdK7MicrocodeCtl,
896	kCpumMsrWrFn_AmdK7ClusterIdMaybe,
897	kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
898	kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
899	kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
900	kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
901	kCpumMsrWrFn_AmdK8PatchLoader,
902	kCpumMsrWrFn_AmdK7DebugStatusMaybe,
903	kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
904	kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
905	kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
906	kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
907	kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
908	kCpumMsrWrFn_AmdK7NodeId,
909	kCpumMsrWrFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
910	kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
911	kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
912	kCpumMsrWrFn_AmdK7LoadStoreCfg,
913	kCpumMsrWrFn_AmdK7InstrCacheCfg,
914	kCpumMsrWrFn_AmdK7DataCacheCfg,
915	kCpumMsrWrFn_AmdK7BusUnitCfg,
916	kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
917	kCpumMsrWrFn_AmdFam15hFpuCfg,
918	kCpumMsrWrFn_AmdFam15hDecoderCfg,
919	kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
920	kCpumMsrWrFn_AmdFam15hCombUnitCfg,
921	kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
922	kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
923	kCpumMsrWrFn_AmdFam15hExecUnitCfg,
924	kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
925	kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
926	kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
927	kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
928	kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
929	kCpumMsrWrFn_AmdFam10hIbsOpRip,
930	kCpumMsrWrFn_AmdFam10hIbsOpData,
931	kCpumMsrWrFn_AmdFam10hIbsOpData2,
932	kCpumMsrWrFn_AmdFam10hIbsOpData3,
933	kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
934	kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
935	kCpumMsrWrFn_AmdFam10hIbsCtl,
936	kCpumMsrWrFn_AmdFam14hIbsBrTarget,
937
938	kCpumMsrWrFn_Gim,
939
940	/** End of valid MSR write function indexes. */
941	kCpumMsrWrFn_End
942	} CPUMMSRWRFN;
943
944	/**
945	* MSR range.
946	*/
947	typedef struct CPUMMSRRANGE
948	{
949	/** The first MSR. [0] */
950	uint32_t uFirst;
951	/** The last MSR. [4] */
952	uint32_t uLast;
953	/** The read function (CPUMMSRRDFN). [8] */
954	uint16_t enmRdFn;
955	/** The write function (CPUMMSRWRFN). [10] */
956	uint16_t enmWrFn;
957	/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
958	* UINT16_MAX if not used by the read and write functions. [12] */
959	uint32_t offCpumCpu : 24;
960	/** Reserved for future hacks. [15] */
961	uint32_t fReserved : 8;
962	/** The init/read value. [16]
963	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
964	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
965	* offset into CPUM. */
966	uint64_t uValue;
967	/** The bits to ignore when writing. [24] */
968	uint64_t fWrIgnMask;
969	/** The bits that will cause a GP(0) when writing. [32]
970	* This is always checked prior to calling the write function. Using
971	* UINT64_MAX effectively marks the MSR as read-only. */
972	uint64_t fWrGpMask;
973	/** The register name, if applicable. [40] */
974	char szName[56];
975
976	/** The number of reads. */
977	STAMCOUNTER cReads;
978	/** The number of writes. */
979	STAMCOUNTER cWrites;
980	/** The number of times ignored bits were written. */
981	STAMCOUNTER cIgnoredBits;
982	/** The number of GPs generated. */
983	STAMCOUNTER cGps;
984	} CPUMMSRRANGE;
985	#ifndef VBOX_FOR_DTRACE_LIB
986	AssertCompileSize(CPUMMSRRANGE, 128);
987	#endif
988	/** Pointer to an MSR range. */
989	typedef CPUMMSRRANGE *PCPUMMSRRANGE;
990	/** Pointer to a const MSR range. */
991	typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
992
993
994	/**
995	* MSRs which are required while exploding features.
996	*/
997	typedef struct CPUMMSRS
998	{
999	union
1000	{
1001	VMXMSRS vmx;
1002	SVMMSRS svm;
1003	} hwvirt;
1004	} CPUMMSRS;
1005	/** Pointer to an CPUMMSRS struct. */
1006	typedef CPUMMSRS *PCPUMMSRS;
1007	/** Pointer to a const CPUMMSRS struct. */
1008	typedef CPUMMSRS const *PCCPUMMSRS;
1009
1010
1011	/**
1012	* CPU features and quirks.
1013	* This is mostly exploded CPUID info.
1014	*/
1015	typedef struct CPUMFEATURES
1016	{
1017	/** The CPU vendor (CPUMCPUVENDOR). */
1018	uint8_t enmCpuVendor;
1019	/** The CPU family. */
1020	uint8_t uFamily;
1021	/** The CPU model. */
1022	uint8_t uModel;
1023	/** The CPU stepping. */
1024	uint8_t uStepping;
1025	/** The microarchitecture. */
1026	#ifndef VBOX_FOR_DTRACE_LIB
1027	CPUMMICROARCH enmMicroarch;
1028	#else
1029	uint32_t enmMicroarch;
1030	#endif
1031	/** The maximum physical address width of the CPU. */
1032	uint8_t cMaxPhysAddrWidth;
1033	/** The maximum linear address width of the CPU. */
1034	uint8_t cMaxLinearAddrWidth;
1035	/** Max size of the extended state (or FPU state if no XSAVE). */
1036	uint16_t cbMaxExtendedState;
1037
1038	/** Supports MSRs. */
1039	uint32_t fMsr : 1;
1040	/** Supports the page size extension (4/2 MB pages). */
1041	uint32_t fPse : 1;
1042	/** Supports 36-bit page size extension (4 MB pages can map memory above
1043	* 4GB). */
1044	uint32_t fPse36 : 1;
1045	/** Supports physical address extension (PAE). */
1046	uint32_t fPae : 1;
1047	/** Supports page-global extension (PGE). */
1048	uint32_t fPge : 1;
1049	/** Page attribute table (PAT) support (page level cache control). */
1050	uint32_t fPat : 1;
1051	/** Supports the FXSAVE and FXRSTOR instructions. */
1052	uint32_t fFxSaveRstor : 1;
1053	/** Supports the XSAVE and XRSTOR instructions. */
1054	uint32_t fXSaveRstor : 1;
1055	/** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
1056	uint32_t fOpSysXSaveRstor : 1;
1057	/** Supports MMX. */
1058	uint32_t fMmx : 1;
1059	/** Supports AMD extensions to MMX instructions. */
1060	uint32_t fAmdMmxExts : 1;
1061	/** Supports SSE. */
1062	uint32_t fSse : 1;
1063	/** Supports SSE2. */
1064	uint32_t fSse2 : 1;
1065	/** Supports SSE3. */
1066	uint32_t fSse3 : 1;
1067	/** Supports SSSE3. */
1068	uint32_t fSsse3 : 1;
1069	/** Supports SSE4.1. */
1070	uint32_t fSse41 : 1;
1071	/** Supports SSE4.2. */
1072	uint32_t fSse42 : 1;
1073	/** Supports AVX. */
1074	uint32_t fAvx : 1;
1075	/** Supports AVX2. */
1076	uint32_t fAvx2 : 1;
1077	/** Supports AVX512 foundation. */
1078	uint32_t fAvx512Foundation : 1;
1079	/** Supports RDTSC. */
1080	uint32_t fTsc : 1;
1081	/** Intel SYSENTER/SYSEXIT support */
1082	uint32_t fSysEnter : 1;
1083	/** First generation APIC. */
1084	uint32_t fApic : 1;
1085	/** Second generation APIC. */
1086	uint32_t fX2Apic : 1;
1087	/** Hypervisor present. */
1088	uint32_t fHypervisorPresent : 1;
1089	/** MWAIT & MONITOR instructions supported. */
1090	uint32_t fMonitorMWait : 1;
1091	/** MWAIT Extensions present. */
1092	uint32_t fMWaitExtensions : 1;
1093	/** Supports CMPXCHG16B in 64-bit mode. */
1094	uint32_t fMovCmpXchg16b : 1;
1095	/** Supports CLFLUSH. */
1096	uint32_t fClFlush : 1;
1097	/** Supports CLFLUSHOPT. */
1098	uint32_t fClFlushOpt : 1;
1099	/** Supports IA32_PRED_CMD.IBPB. */
1100	uint32_t fIbpb : 1;
1101	/** Supports IA32_SPEC_CTRL.IBRS. */
1102	uint32_t fIbrs : 1;
1103	/** Supports IA32_SPEC_CTRL.STIBP. */
1104	uint32_t fStibp : 1;
1105	/** Supports IA32_FLUSH_CMD. */
1106	uint32_t fFlushCmd : 1;
1107	/** Supports IA32_ARCH_CAP. */
1108	uint32_t fArchCap : 1;
1109	/** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
1110	uint32_t fMdsClear : 1;
1111	/** Supports PCID. */
1112	uint32_t fPcid : 1;
1113	/** Supports INVPCID. */
1114	uint32_t fInvpcid : 1;
1115	/** Supports read/write FSGSBASE instructions. */
1116	uint32_t fFsGsBase : 1;
1117	/** Support BMI1 instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, and TZCNT). */
1118	uint32_t fBmi1 : 1;
1119	/** Support BMI2 instructions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX,
1120	* and SHLX). */
1121	uint32_t fBmi2 : 1;
1122	/** Support POPCNT instruction. */
1123	uint32_t fPopCnt : 1;
1124	/** Support RDRAND instruction. */
1125	uint32_t fRdRand : 1;
1126	/** Support RDSEED instruction. */
1127	uint32_t fRdSeed : 1;
1128	/** Support PCLMULQDQ instruction. */
1129	uint32_t fPclMul : 1;
1130	/** Supports AES-NI (six AESxxx instructions). */
1131	uint32_t fAesNi : 1;
1132
1133	/** Supports AMD 3DNow instructions. */
1134	uint32_t f3DNow : 1;
1135	/** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
1136	uint32_t f3DNowPrefetch : 1;
1137
1138	/** AMD64: Supports long mode. */
1139	uint32_t fLongMode : 1;
1140	/** AMD64: SYSCALL/SYSRET support. */
1141	uint32_t fSysCall : 1;
1142	/** AMD64: No-execute page table bit. */
1143	uint32_t fNoExecute : 1;
1144	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
1145	uint32_t fLahfSahf : 1;
1146	/** AMD64: Supports RDTSCP. */
1147	uint32_t fRdTscP : 1;
1148	/** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
1149	uint32_t fMovCr8In32Bit : 1;
1150	/** AMD64: Supports XOP (similar to VEX3/AVX). */
1151	uint32_t fXop : 1;
1152	/** AMD64: Supports ABM, i.e. the LZCNT instruction. */
1153	uint32_t fAbm : 1;
1154	/** AMD64: Supports TBM (BEXTR, BLCFILL, BLCI, BLCIC, BLCMSK, BLCS,
1155	* BLSFILL, BLSIC, T1MSKC, and TZMSK). */
1156	uint32_t fTbm : 1;
1157
1158	/** Indicates that FPU instruction and data pointers may leak.
1159	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
1160	* is only saved and restored if an exception is pending. */
1161	uint32_t fLeakyFxSR : 1;
1162
1163	/** AMD64: Supports AMD SVM. */
1164	uint32_t fSvm : 1;
1165
1166	/** Support for Intel VMX. */
1167	uint32_t fVmx : 1;
1168
1169	/** Indicates that speculative execution control CPUID bits and MSRs are exposed.
1170	* The details are different for Intel and AMD but both have similar
1171	* functionality. */
1172	uint32_t fSpeculationControl : 1;
1173
1174	/** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
1175	* @remarks Only safe use after CPUM ring-0 init! */
1176	uint32_t fArchRdclNo : 1;
1177	/** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
1178	* @remarks Only safe use after CPUM ring-0 init! */
1179	uint32_t fArchIbrsAll : 1;
1180	/** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
1181	* @remarks Only safe use after CPUM ring-0 init! */
1182	uint32_t fArchRsbOverride : 1;
1183	/** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
1184	* @remarks Only safe use after CPUM ring-0 init! */
1185	uint32_t fArchVmmNeedNotFlushL1d : 1;
1186	/** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4).
1187	* @remarks Only safe use after CPUM ring-0 init! */
1188	uint32_t fArchMdsNo : 1;
1189
1190	/** Alignment padding / reserved for future use (96 bits total, plus 12 bytes
1191	* prior to the bit fields -> total of 24 bytes) */
1192	uint32_t fPadding0 : 30;
1193
1194
1195	/** @name SVM
1196	* @{ */
1197	/** SVM: Supports Nested-paging. */
1198	uint32_t fSvmNestedPaging : 1;
1199	/** SVM: Support LBR (Last Branch Record) virtualization. */
1200	uint32_t fSvmLbrVirt : 1;
1201	/** SVM: Supports SVM lock. */
1202	uint32_t fSvmSvmLock : 1;
1203	/** SVM: Supports Next RIP save. */
1204	uint32_t fSvmNextRipSave : 1;
1205	/** SVM: Supports TSC rate MSR. */
1206	uint32_t fSvmTscRateMsr : 1;
1207	/** SVM: Supports VMCB clean bits. */
1208	uint32_t fSvmVmcbClean : 1;
1209	/** SVM: Supports Flush-by-ASID. */
1210	uint32_t fSvmFlusbByAsid : 1;
1211	/** SVM: Supports decode assist. */
1212	uint32_t fSvmDecodeAssists : 1;
1213	/** SVM: Supports Pause filter. */
1214	uint32_t fSvmPauseFilter : 1;
1215	/** SVM: Supports Pause filter threshold. */
1216	uint32_t fSvmPauseFilterThreshold : 1;
1217	/** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
1218	uint32_t fSvmAvic : 1;
1219	/** SVM: Supports Virtualized VMSAVE/VMLOAD. */
1220	uint32_t fSvmVirtVmsaveVmload : 1;
1221	/** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
1222	uint32_t fSvmVGif : 1;
1223	/** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
1224	uint32_t fSvmGmet : 1;
1225	/** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */
1226	uint32_t fSvmSSSCheck : 1;
1227	/** SVM: Supports SPEC_CTRL virtualization. */
1228	uint32_t fSvmSpecCtrl : 1;
1229	/** SVM: Supports HOST_MCE_OVERRIDE. */
1230	uint32_t fSvmHostMceOverride : 1;
1231	/** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */
1232	uint32_t fSvmTlbiCtl : 1;
1233	/** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */
1234	uint32_t fSvmPadding0 : 14;
1235	/** SVM: Maximum supported ASID. */
1236	uint32_t uSvmMaxAsid;
1237	/** @} */
1238
1239
1240	/** VMX: Maximum physical address width. */
1241	uint32_t cVmxMaxPhysAddrWidth : 8;
1242
1243	/** @name VMX basic controls.
1244	* @{ */
1245	/** VMX: Supports INS/OUTS VM-exit instruction info. */
1246	uint32_t fVmxInsOutInfo : 1;
1247	/** @} */
1248
1249	/** @name VMX Pin-based controls.
1250	* @{ */
1251	/** VMX: Supports external interrupt VM-exit. */
1252	uint32_t fVmxExtIntExit : 1;
1253	/** VMX: Supports NMI VM-exit. */
1254	uint32_t fVmxNmiExit : 1;
1255	/** VMX: Supports Virtual NMIs. */
1256	uint32_t fVmxVirtNmi : 1;
1257	/** VMX: Supports preemption timer. */
1258	uint32_t fVmxPreemptTimer : 1;
1259	/** VMX: Supports posted interrupts. */
1260	uint32_t fVmxPostedInt : 1;
1261	/** @} */
1262
1263	/** @name VMX Processor-based controls.
1264	* @{ */
1265	/** VMX: Supports Interrupt-window exiting. */
1266	uint32_t fVmxIntWindowExit : 1;
1267	/** VMX: Supports TSC offsetting. */
1268	uint32_t fVmxTscOffsetting : 1;
1269	/** VMX: Supports HLT exiting. */
1270	uint32_t fVmxHltExit : 1;
1271	/** VMX: Supports INVLPG exiting. */
1272	uint32_t fVmxInvlpgExit : 1;
1273	/** VMX: Supports MWAIT exiting. */
1274	uint32_t fVmxMwaitExit : 1;
1275	/** VMX: Supports RDPMC exiting. */
1276	uint32_t fVmxRdpmcExit : 1;
1277	/** VMX: Supports RDTSC exiting. */
1278	uint32_t fVmxRdtscExit : 1;
1279	/** VMX: Supports CR3-load exiting. */
1280	uint32_t fVmxCr3LoadExit : 1;
1281	/** VMX: Supports CR3-store exiting. */
1282	uint32_t fVmxCr3StoreExit : 1;
1283	/** VMX: Supports tertiary processor-based VM-execution controls. */
1284	uint32_t fVmxTertiaryExecCtls : 1;
1285	/** VMX: Supports CR8-load exiting. */
1286	uint32_t fVmxCr8LoadExit : 1;
1287	/** VMX: Supports CR8-store exiting. */
1288	uint32_t fVmxCr8StoreExit : 1;
1289	/** VMX: Supports TPR shadow. */
1290	uint32_t fVmxUseTprShadow : 1;
1291	/** VMX: Supports NMI-window exiting. */
1292	uint32_t fVmxNmiWindowExit : 1;
1293	/** VMX: Supports Mov-DRx exiting. */
1294	uint32_t fVmxMovDRxExit : 1;
1295	/** VMX: Supports Unconditional I/O exiting. */
1296	uint32_t fVmxUncondIoExit : 1;
1297	/** VMX: Supportgs I/O bitmaps. */
1298	uint32_t fVmxUseIoBitmaps : 1;
1299	/** VMX: Supports Monitor Trap Flag. */
1300	uint32_t fVmxMonitorTrapFlag : 1;
1301	/** VMX: Supports MSR bitmap. */
1302	uint32_t fVmxUseMsrBitmaps : 1;
1303	/** VMX: Supports MONITOR exiting. */
1304	uint32_t fVmxMonitorExit : 1;
1305	/** VMX: Supports PAUSE exiting. */
1306	uint32_t fVmxPauseExit : 1;
1307	/** VMX: Supports secondary processor-based VM-execution controls. */
1308	uint32_t fVmxSecondaryExecCtls : 1;
1309	/** @} */
1310
1311	/** @name VMX Secondary processor-based controls.
1312	* @{ */
1313	/** VMX: Supports virtualize-APIC access. */
1314	uint32_t fVmxVirtApicAccess : 1;
1315	/** VMX: Supports EPT (Extended Page Tables). */
1316	uint32_t fVmxEpt : 1;
1317	/** VMX: Supports descriptor-table exiting. */
1318	uint32_t fVmxDescTableExit : 1;
1319	/** VMX: Supports RDTSCP. */
1320	uint32_t fVmxRdtscp : 1;
1321	/** VMX: Supports virtualize-x2APIC mode. */
1322	uint32_t fVmxVirtX2ApicMode : 1;
1323	/** VMX: Supports VPID. */
1324	uint32_t fVmxVpid : 1;
1325	/** VMX: Supports WBIND exiting. */
1326	uint32_t fVmxWbinvdExit : 1;
1327	/** VMX: Supports Unrestricted guest. */
1328	uint32_t fVmxUnrestrictedGuest : 1;
1329	/** VMX: Supports APIC-register virtualization. */
1330	uint32_t fVmxApicRegVirt : 1;
1331	/** VMX: Supports virtual-interrupt delivery. */
1332	uint32_t fVmxVirtIntDelivery : 1;
1333	/** VMX: Supports Pause-loop exiting. */
1334	uint32_t fVmxPauseLoopExit : 1;
1335	/** VMX: Supports RDRAND exiting. */
1336	uint32_t fVmxRdrandExit : 1;
1337	/** VMX: Supports INVPCID. */
1338	uint32_t fVmxInvpcid : 1;
1339	/** VMX: Supports VM functions. */
1340	uint32_t fVmxVmFunc : 1;
1341	/** VMX: Supports VMCS shadowing. */
1342	uint32_t fVmxVmcsShadowing : 1;
1343	/** VMX: Supports RDSEED exiting. */
1344	uint32_t fVmxRdseedExit : 1;
1345	/** VMX: Supports PML. */
1346	uint32_t fVmxPml : 1;
1347	/** VMX: Supports EPT-violations \#VE. */
1348	uint32_t fVmxEptXcptVe : 1;
1349	/** VMX: Supports conceal VMX from PT. */
1350	uint32_t fVmxConcealVmxFromPt : 1;
1351	/** VMX: Supports XSAVES/XRSTORS. */
1352	uint32_t fVmxXsavesXrstors : 1;
1353	/** VMX: Supports mode-based execute control for EPT. */
1354	uint32_t fVmxModeBasedExecuteEpt : 1;
1355	/** VMX: Supports sub-page write permissions for EPT. */
1356	uint32_t fVmxSppEpt : 1;
1357	/** VMX: Supports Intel PT to output guest-physical addresses for EPT. */
1358	uint32_t fVmxPtEpt : 1;
1359	/** VMX: Supports TSC scaling. */
1360	uint32_t fVmxUseTscScaling : 1;
1361	/** VMX: Supports TPAUSE, UMONITOR, or UMWAIT. */
1362	uint32_t fVmxUserWaitPause : 1;
1363	/** VMX: Supports enclave (ENCLV) exiting. */
1364	uint32_t fVmxEnclvExit : 1;
1365	/** @} */
1366
1367	/** @name VMX Tertiary processor-based controls.
1368	* @{ */
1369	/** VMX: Supports LOADIWKEY exiting. */
1370	uint32_t fVmxLoadIwKeyExit : 1;
1371	/** @} */
1372
1373	/** @name VMX VM-entry controls.
1374	* @{ */
1375	/** VMX: Supports load-debug controls on VM-entry. */
1376	uint32_t fVmxEntryLoadDebugCtls : 1;
1377	/** VMX: Supports IA32e mode guest. */
1378	uint32_t fVmxIa32eModeGuest : 1;
1379	/** VMX: Supports load guest EFER MSR on VM-entry. */
1380	uint32_t fVmxEntryLoadEferMsr : 1;
1381	/** VMX: Supports load guest PAT MSR on VM-entry. */
1382	uint32_t fVmxEntryLoadPatMsr : 1;
1383	/** @} */
1384
1385	/** @name VMX VM-exit controls.
1386	* @{ */
1387	/** VMX: Supports save debug controls on VM-exit. */
1388	uint32_t fVmxExitSaveDebugCtls : 1;
1389	/** VMX: Supports host-address space size. */
1390	uint32_t fVmxHostAddrSpaceSize : 1;
1391	/** VMX: Supports acknowledge external interrupt on VM-exit. */
1392	uint32_t fVmxExitAckExtInt : 1;
1393	/** VMX: Supports save guest PAT MSR on VM-exit. */
1394	uint32_t fVmxExitSavePatMsr : 1;
1395	/** VMX: Supports load hsot PAT MSR on VM-exit. */
1396	uint32_t fVmxExitLoadPatMsr : 1;
1397	/** VMX: Supports save guest EFER MSR on VM-exit. */
1398	uint32_t fVmxExitSaveEferMsr : 1;
1399	/** VMX: Supports load host EFER MSR on VM-exit. */
1400	uint32_t fVmxExitLoadEferMsr : 1;
1401	/** VMX: Supports save VMX preemption timer on VM-exit. */
1402	uint32_t fVmxSavePreemptTimer : 1;
1403	/** @} */
1404
1405	/** @name VMX Miscellaneous data.
1406	* @{ */
1407	/** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
1408	uint32_t fVmxExitSaveEferLma : 1;
1409	/** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
1410	uint32_t fVmxPt : 1;
1411	/** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1412	* VMWRITE cannot modify read-only VM-exit information fields. */
1413	uint32_t fVmxVmwriteAll : 1;
1414	/** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
1415	* length instructions. */
1416	uint32_t fVmxEntryInjectSoftInt : 1;
1417	/** @} */
1418
1419	/** VMX: Padding / reserved for future features. */
1420	uint32_t fVmxPadding0 : 17;
1421	/** VMX: Padding / reserved for future, making it a total of 128 bits. */
1422	uint32_t fVmxPadding1;
1423	} CPUMFEATURES;
1424	#ifndef VBOX_FOR_DTRACE_LIB
1425	AssertCompileSize(CPUMFEATURES, 48);
1426	#endif
1427	/** Pointer to a CPU feature structure. */
1428	typedef CPUMFEATURES *PCPUMFEATURES;
1429	/** Pointer to a const CPU feature structure. */
1430	typedef CPUMFEATURES const *PCCPUMFEATURES;
1431
1432	/**
1433	* Chameleon wrapper structure for the host CPU features.
1434	*
1435	* This is used for the globally readable g_CpumHostFeatures variable, which is
1436	* initialized once during VMMR0 load for ring-0 and during CPUMR3Init in
1437	* ring-3. To reflect this immutability after load/init, we use this wrapper
1438	* structure to switch it between const and non-const depending on the context.
1439	* Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).
1440	*/
1441	typedef struct CPUHOSTFEATURES
1442	{
1443	CPUMFEATURES
1444	#ifndef CPUM_WITH_NONCONST_HOST_FEATURES
1445	const
1446	#endif
1447	s;
1448	} CPUHOSTFEATURES;
1449	/** Pointer to a const host CPU feature structure. */
1450	typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
1451
1452	/** Host CPU features.
1453	* @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after
1454	* module init. */
1455	extern CPUHOSTFEATURES g_CpumHostFeatures;
1456
1457
1458	/**
1459	* CPU database entry.
1460	*/
1461	typedef struct CPUMDBENTRY
1462	{
1463	/** The CPU name. */
1464	const char *pszName;
1465	/** The full CPU name. */
1466	const char *pszFullName;
1467	/** The CPU vendor (CPUMCPUVENDOR). */
1468	uint8_t enmVendor;
1469	/** The CPU family. */
1470	uint8_t uFamily;
1471	/** The CPU model. */
1472	uint8_t uModel;
1473	/** The CPU stepping. */
1474	uint8_t uStepping;
1475	/** The microarchitecture. */
1476	CPUMMICROARCH enmMicroarch;
1477	/** Scalable bus frequency used for reporting other frequencies. */
1478	uint64_t uScalableBusFreq;
1479	/** Flags - CPUMDB_F_XXX. */
1480	uint32_t fFlags;
1481	/** The maximum physical address with of the CPU. This should correspond to
1482	* the value in CPUID leaf 0x80000008 when present. */
1483	uint8_t cMaxPhysAddrWidth;
1484	/** The MXCSR mask. */
1485	uint32_t fMxCsrMask;
1486	/** Pointer to an array of CPUID leaves. */
1487	PCCPUMCPUIDLEAF paCpuIdLeaves;
1488	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
1489	uint32_t cCpuIdLeaves;
1490	/** The method used to deal with unknown CPUID leaves. */
1491	CPUMUNKNOWNCPUID enmUnknownCpuId;
1492	/** The default unknown CPUID value. */
1493	CPUMCPUID DefUnknownCpuId;
1494
1495	/** MSR mask. Several microarchitectures ignore the higher bits of ECX in
1496	* the RDMSR and WRMSR instructions. */
1497	uint32_t fMsrMask;
1498
1499	/** The number of ranges in the table pointed to b paMsrRanges. */
1500	uint32_t cMsrRanges;
1501	/** MSR ranges for this CPU. */
1502	PCCPUMMSRRANGE paMsrRanges;
1503	} CPUMDBENTRY;
1504	/** Pointer to a const CPU database entry. */
1505	typedef CPUMDBENTRY const *PCCPUMDBENTRY;
1506
1507	/** @name CPUMDB_F_XXX - CPUDBENTRY::fFlags
1508	* @{ */
1509	/** Should execute all in IEM.
1510	* @todo Implement this - currently done in Main... */
1511	#define CPUMDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
1512	/** @} */
1513
1514
1515
1516	#ifndef VBOX_FOR_DTRACE_LIB
1517
1518	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1519	VMMDECL(int) CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves);
1520	VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1521	#endif
1522
1523	/** @name Guest Register Getters.
1524	* @{ */
1525	VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR);
1526	VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit);
1527	VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden);
1528	VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu);
1529	VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t pGCPtrBase, uint32_t pcbLimit);
1530	VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu);
1531	VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu);
1532	VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu);
1533	VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu);
1534	VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu);
1535	VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue);
1536	VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu);
1537	VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu);
1538	VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu);
1539	VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu);
1540	VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu);
1541	VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu);
1542	VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu);
1543	VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu);
1544	VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu);
1545	VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu);
1546	VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu);
1547	VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu);
1548	VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu);
1549	VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu);
1550	VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu);
1551	VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu);
1552	VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu);
1553	VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
1554	VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
1555	VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu);
1556	VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu);
1557	VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu);
1558	VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu);
1559	VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu);
1560	VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu);
1561	VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1562	VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t iLeaf, uint32_t iSubLeaf, int f64BitMode,
1563	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
1564	VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu);
1565	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatCtrl(PCVMCPUCC pVCpu);
1566	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu);
1567	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPUCC pVCpu);
1568	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPUCC pVCpu);
1569	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue);
1570	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue);
1571	VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1572	VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM);
1573	VMMDECL(void) CPUMGetGuestAddrWidths(PCVM pVM, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth);
1574	VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1575	VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM);
1576	/** @} */
1577
1578	/** @name Guest Register Setters.
1579	* @{ */
1580	VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1581	VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1582	VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1583	VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1584	VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0);
1585	VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1586	VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1587	VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1588	VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0);
1589	VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1);
1590	VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2);
1591	VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3);
1592	VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1593	VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7);
1594	VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value);
1595	VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue);
1596	VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1597	VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1598	VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1599	VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1600	VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1601	VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1602	VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1603	VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1604	VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1605	VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1606	VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1607	VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1608	VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1609	VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1610	VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1611	VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1612	VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1613	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1614	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1615	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1616	VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
1617	VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1618	VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue);
1619	VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu);
1620	VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue);
1621	VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu);
1622	VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM);
1623	VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes);
1624	VMM_INT_DECL(void) CPUMGetGuestPaePdpes(PVMCPU pVCpu, PX86PDPE paPaePdpes);
1625	/** @} */
1626
1627
1628	/** @name Misc Guest Predicate Functions.
1629	* @{ */
1630	VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1631	VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu);
1632	VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu);
1633	VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu);
1634	VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu);
1635	VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu);
1636	VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu);
1637	VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu);
1638	VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu);
1639	VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu);
1640	VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu);
1641	/** @} */
1642
1643	/** @name Nested Hardware-Virtualization Helpers.
1644	* @{ */
1645	VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu);
1646	VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu);
1647	VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1648	VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1649
1650	/* SVM helpers. */
1651	VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1652	VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1653	VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx);
1654	VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx);
1655	VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
1656	VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1657	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
1658	PSVMIOIOEXITINFO pIoExitInfo);
1659	VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint8_t puMsrpmBit);
1660
1661	/* VMX helpers. */
1662	VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField);
1663	VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess);
1664	VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3);
1665	VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc);
1666	VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick);
1667	VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu);
1668	VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr);
1669	VMM_INT_DECL(bool) CPUMIsGuestVmxEptPagingEnabled(PCVMCPUCC pVCpu);
1670	VMM_INT_DECL(bool) CPUMIsGuestVmxEptPaePagingEnabled(PCVMCPUCC pVCpu);
1671	VMM_INT_DECL(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCVMCPUCC pVCpu);
1672	/** @} */
1673
1674	/** @name Externalized State Helpers.
1675	* @{ */
1676	/** @def CPUM_ASSERT_NOT_EXTRN
1677	* Macro for asserting that @a a_fNotExtrn are present.
1678	*
1679	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1680	* @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
1681	*
1682	* @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1683	*/
1684	#define CPUM_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
1685	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fNotExtrn)), \
1686	("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fNotExtrn)))
1687
1688	/** @def CPUM_IMPORT_EXTRN_RET
1689	* Macro for making sure the state specified by @a fExtrnImport is present,
1690	* calling CPUMImportGuestStateOnDemand() to get it if necessary.
1691	*
1692	* Will return if CPUMImportGuestStateOnDemand() fails.
1693	*
1694	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1695	* @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1696	* @thread EMT(a_pVCpu)
1697	*
1698	* @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1699	*/
1700	#define CPUM_IMPORT_EXTRN_RET(a_pVCpu, a_fExtrnImport) \
1701	do { \
1702	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1703	{ /* already present, consider this likely */ } \
1704	else \
1705	{ \
1706	int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1707	AssertRCReturn(rcCpumImport, rcCpumImport); \
1708	} \
1709	} while (0)
1710
1711	/** @def CPUM_IMPORT_EXTRN_RCSTRICT
1712	* Macro for making sure the state specified by @a fExtrnImport is present,
1713	* calling CPUMImportGuestStateOnDemand() to get it if necessary.
1714	*
1715	* Will update a_rcStrict if CPUMImportGuestStateOnDemand() fails.
1716	*
1717	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1718	* @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1719	* @param a_rcStrict Strict status code variable to update on failure.
1720	* @thread EMT(a_pVCpu)
1721	*
1722	* @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1723	*/
1724	#define CPUM_IMPORT_EXTRN_RCSTRICT(a_pVCpu, a_fExtrnImport, a_rcStrict) \
1725	do { \
1726	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1727	{ /* already present, consider this likely */ } \
1728	else \
1729	{ \
1730	int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1731	AssertStmt(RT_SUCCESS(rcCpumImport) \|\| RT_FAILURE_NP(a_rcStrict), a_rcStrict = rcCpumImport); \
1732	} \
1733	} while (0)
1734
1735	VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport);
1736	/** @} */
1737
1738	#if !defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS) \|\| defined(DOXYGEN_RUNNING)
1739	/** @name Inlined Guest Getters and predicates Functions.
1740	* @{ */
1741
1742	/**
1743	* Gets valid CR0 bits for the guest.
1744	*
1745	* @returns Valid CR0 bits.
1746	*/
1747	DECLINLINE(uint64_t) CPUMGetGuestCR0ValidMask(void)
1748	{
1749	return ( X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS
1750	\| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_WP \| X86_CR0_AM
1751	\| X86_CR0_NW \| X86_CR0_CD \| X86_CR0_PG);
1752	}
1753
1754	/**
1755	* Tests if the guest is running in real mode or not.
1756	*
1757	* @returns true if in real mode, otherwise false.
1758	* @param pCtx Current CPU context.
1759	*/
1760	DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCCPUMCTX pCtx)
1761	{
1762	return !(pCtx->cr0 & X86_CR0_PE);
1763	}
1764
1765	/**
1766	* Tests if the guest is running in real or virtual 8086 mode.
1767	*
1768	* @returns @c true if it is, @c false if not.
1769	* @param pCtx Current CPU context.
1770	*/
1771	DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCCPUMCTX pCtx)
1772	{
1773	return !(pCtx->cr0 & X86_CR0_PE)
1774	\|\| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1775	}
1776
1777	/**
1778	* Tests if the guest is running in virtual 8086 mode.
1779	*
1780	* @returns @c true if it is, @c false if not.
1781	* @param pCtx Current CPU context.
1782	*/
1783	DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCCPUMCTX pCtx)
1784	{
1785	return (pCtx->eflags.Bits.u1VM == 1);
1786	}
1787
1788	/**
1789	* Tests if the guest is running in paged protected or not.
1790	*
1791	* @returns true if in paged protected mode, otherwise false.
1792	* @param pCtx Current CPU context.
1793	*/
1794	DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1795	{
1796	return (pCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
1797	}
1798
1799	/**
1800	* Tests if the guest is running in long mode or not.
1801	*
1802	* @returns true if in long mode, otherwise false.
1803	* @param pCtx Current CPU context.
1804	*/
1805	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCCPUMCTX pCtx)
1806	{
1807	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1808	}
1809
1810	VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1811
1812	/**
1813	* Tests if the guest is running in 64 bits mode or not.
1814	*
1815	* @returns true if in 64 bits protected mode, otherwise false.
1816	* @param pCtx Current CPU context.
1817	*/
1818	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1819	{
1820	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1821	return false;
1822	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1823	return CPUMIsGuestIn64BitCodeSlow(pCtx);
1824	return pCtx->cs.Attr.n.u1Long;
1825	}
1826
1827	/**
1828	* Tests if the guest has paging enabled or not.
1829	*
1830	* @returns true if paging is enabled, otherwise false.
1831	* @param pCtx Current CPU context.
1832	*/
1833	DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCCPUMCTX pCtx)
1834	{
1835	return !!(pCtx->cr0 & X86_CR0_PG);
1836	}
1837
1838	/**
1839	* Tests if PAE paging is enabled given the relevant control registers.
1840	*
1841	* @returns @c true if in PAE mode, @c false otherwise.
1842	* @param uCr0 The CR0 value.
1843	* @param uCr4 The CR4 value.
1844	* @param uEferMsr The EFER value.
1845	*/
1846	DECLINLINE(bool) CPUMIsPaePagingEnabled(uint64_t uCr0, uint64_t uCr4, uint64_t uEferMsr)
1847	{
1848	/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1849	than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1850	return ( (uCr4 & X86_CR4_PAE)
1851	&& (uCr0 & X86_CR0_PG)
1852	&& !(uEferMsr & MSR_K6_EFER_LMA));
1853	}
1854
1855	/**
1856	* Tests if the guest is running in PAE mode or not.
1857	*
1858	* @returns @c true if in PAE mode, @c false otherwise.
1859	* @param pCtx Current CPU context.
1860	*/
1861	DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCCPUMCTX pCtx)
1862	{
1863	return CPUMIsPaePagingEnabled(pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
1864	}
1865
1866	/**
1867	* Tests if the guest has AMD SVM enabled or not.
1868	*
1869	* @returns true if SMV is enabled, otherwise false.
1870	* @param pCtx Current CPU context.
1871	*/
1872	DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1873	{
1874	return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1875	}
1876
1877	/**
1878	* Tests if the guest has Intel VT-x enabled or not.
1879	*
1880	* @returns true if VMX is enabled, otherwise false.
1881	* @param pCtx Current CPU context.
1882	*/
1883	DECLINLINE(bool) CPUMIsGuestVmxEnabled(PCCPUMCTX pCtx)
1884	{
1885	return RT_BOOL(pCtx->cr4 & X86_CR4_VMXE);
1886	}
1887
1888	/**
1889	* Returns the guest's global-interrupt (GIF) flag.
1890	*
1891	* @returns true when global-interrupts are enabled, otherwise false.
1892	* @param pCtx Current CPU context.
1893	*/
1894	DECLINLINE(bool) CPUMGetGuestGif(PCCPUMCTX pCtx)
1895	{
1896	return pCtx->hwvirt.fGif;
1897	}
1898
1899	/**
1900	* Sets the guest's global-interrupt flag (GIF).
1901	*
1902	* @param pCtx Current CPU context.
1903	* @param fGif The value to set.
1904	*/
1905	DECLINLINE(void) CPUMSetGuestGif(PCPUMCTX pCtx, bool fGif)
1906	{
1907	pCtx->hwvirt.fGif = fGif;
1908	}
1909
1910	/**
1911	* Checks if we are executing inside an SVM nested hardware-virtualized guest.
1912	*
1913	* @returns @c true if in SVM nested-guest mode, @c false otherwise.
1914	* @param pCtx Current CPU context.
1915	*/
1916	DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
1917	{
1918	/*
1919	* With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
1920	* See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
1921	*/
1922	#ifndef IN_RC
1923	if ( pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM
1924	\|\| !(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN))
1925	return false;
1926	return true;
1927	#else
1928	NOREF(pCtx);
1929	return false;
1930	#endif
1931	}
1932
1933	/**
1934	* Checks if the guest is in VMX non-root operation.
1935	*
1936	* @returns @c true if in VMX non-root operation, @c false otherwise.
1937	* @param pCtx Current CPU context.
1938	*/
1939	DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx)
1940	{
1941	#ifndef IN_RC
1942	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
1943	return false;
1944	Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode \|\| pCtx->hwvirt.vmx.fInVmxRootMode);
1945	return pCtx->hwvirt.vmx.fInVmxNonRootMode;
1946	#else
1947	NOREF(pCtx);
1948	return false;
1949	#endif
1950	}
1951
1952	/**
1953	* Checks if we are executing inside an SVM or VMX nested hardware-virtualized
1954	* guest.
1955	*
1956	* @returns @c true if in nested-guest mode, @c false otherwise.
1957	* @param pCtx Current CPU context.
1958	*/
1959	DECLINLINE(bool) CPUMIsGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
1960	{
1961	#if 0
1962	return CPUMIsGuestInVmxNonRootMode(pCtx) \|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
1963	#else
1964	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
1965	return false;
1966	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
1967	{
1968	Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode \|\| pCtx->hwvirt.vmx.fInVmxRootMode);
1969	return pCtx->hwvirt.vmx.fInVmxNonRootMode;
1970	}
1971	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1972	return RT_BOOL(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN);
1973	#endif
1974	}
1975
1976	/**
1977	* Checks if we are executing inside an SVM or VMX nested hardware-virtualized
1978	* guest.
1979	*
1980	* @retval CPUMHWVIRT_NONE if not in SVM or VMX non-root mode.
1981	* @retval CPUMHWVIRT_VMX if in VMX non-root mode.
1982	* @retval CPUMHWVIRT_SVM if in SVM non-root mode.
1983	* @param pCtx Current CPU context.
1984	*/
1985	DECLINLINE(CPUMHWVIRT) CPUMGetGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
1986	{
1987	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
1988	return CPUMHWVIRT_NONE;
1989	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
1990	{
1991	Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode \|\| pCtx->hwvirt.vmx.fInVmxRootMode);
1992	return pCtx->hwvirt.vmx.fInVmxNonRootMode ? CPUMHWVIRT_VMX : CPUMHWVIRT_NONE;
1993	}
1994	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1995	return pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN ? CPUMHWVIRT_SVM : CPUMHWVIRT_NONE;
1996	}
1997
1998	/**
1999	* Checks if the guest is in VMX root operation.
2000	*
2001	* @returns @c true if in VMX root operation, @c false otherwise.
2002	* @param pCtx Current CPU context.
2003	*/
2004	DECLINLINE(bool) CPUMIsGuestInVmxRootMode(PCCPUMCTX pCtx)
2005	{
2006	#ifndef IN_RC
2007	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
2008	return false;
2009	return pCtx->hwvirt.vmx.fInVmxRootMode;
2010	#else
2011	NOREF(pCtx);
2012	return false;
2013	#endif
2014	}
2015
2016	# ifndef IN_RC
2017
2018	/**
2019	* Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
2020	* active.
2021	*
2022	* @returns @c true if in intercept is set, @c false otherwise.
2023	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2024	* @param pCtx Current CPU context.
2025	* @param fIntercept The SVM control/instruction intercept, see
2026	* SVM_CTRL_INTERCEPT_*.
2027	*/
2028	DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint64_t fIntercept)
2029	{
2030	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2031	return false;
2032	uint64_t u64Intercepts;
2033	if (!HMGetGuestSvmCtrlIntercepts(pVCpu, &u64Intercepts))
2034	u64Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl;
2035	return RT_BOOL(u64Intercepts & fIntercept);
2036	}
2037
2038	/**
2039	* Checks if the nested-guest VMCB has the specified CR read intercept active.
2040	*
2041	* @returns @c true if in intercept is set, @c false otherwise.
2042	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2043	* @param pCtx Current CPU context.
2044	* @param uCr The CR register number (0 to 15).
2045	*/
2046	DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
2047	{
2048	Assert(uCr < 16);
2049	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2050	return false;
2051	uint16_t u16Intercepts;
2052	if (!HMGetGuestSvmReadCRxIntercepts(pVCpu, &u16Intercepts))
2053	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdCRx;
2054	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
2055	}
2056
2057	/**
2058	* Checks if the nested-guest VMCB has the specified CR write intercept active.
2059	*
2060	* @returns @c true if in intercept is set, @c false otherwise.
2061	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2062	* @param pCtx Current CPU context.
2063	* @param uCr The CR register number (0 to 15).
2064	*/
2065	DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
2066	{
2067	Assert(uCr < 16);
2068	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2069	return false;
2070	uint16_t u16Intercepts;
2071	if (!HMGetGuestSvmWriteCRxIntercepts(pVCpu, &u16Intercepts))
2072	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrCRx;
2073	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
2074	}
2075
2076	/**
2077	* Checks if the nested-guest VMCB has the specified DR read intercept active.
2078	*
2079	* @returns @c true if in intercept is set, @c false otherwise.
2080	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2081	* @param pCtx Current CPU context.
2082	* @param uDr The DR register number (0 to 15).
2083	*/
2084	DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
2085	{
2086	Assert(uDr < 16);
2087	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2088	return false;
2089	uint16_t u16Intercepts;
2090	if (!HMGetGuestSvmReadDRxIntercepts(pVCpu, &u16Intercepts))
2091	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdDRx;
2092	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
2093	}
2094
2095	/**
2096	* Checks if the nested-guest VMCB has the specified DR write intercept active.
2097	*
2098	* @returns @c true if in intercept is set, @c false otherwise.
2099	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2100	* @param pCtx Current CPU context.
2101	* @param uDr The DR register number (0 to 15).
2102	*/
2103	DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
2104	{
2105	Assert(uDr < 16);
2106	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2107	return false;
2108	uint16_t u16Intercepts;
2109	if (!HMGetGuestSvmWriteDRxIntercepts(pVCpu, &u16Intercepts))
2110	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrDRx;
2111	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
2112	}
2113
2114	/**
2115	* Checks if the nested-guest VMCB has the specified exception intercept active.
2116	*
2117	* @returns @c true if in intercept is active, @c false otherwise.
2118	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2119	* @param pCtx Current CPU context.
2120	* @param uVector The exception / interrupt vector.
2121	*/
2122	DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
2123	{
2124	Assert(uVector <= X86_XCPT_LAST);
2125	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2126	return false;
2127	uint32_t u32Intercepts;
2128	if (!HMGetGuestSvmXcptIntercepts(pVCpu, &u32Intercepts))
2129	u32Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u32InterceptXcpt;
2130	return RT_BOOL(u32Intercepts & RT_BIT(uVector));
2131	}
2132
2133	/**
2134	* Checks if the nested-guest VMCB has virtual-interrupt masking enabled.
2135	*
2136	* @returns @c true if virtual-interrupts are masked, @c false otherwise.
2137	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2138	* @param pCtx Current CPU context.
2139	*
2140	* @remarks Should only be called when SVM feature is exposed to the guest.
2141	*/
2142	DECLINLINE(bool) CPUMIsGuestSvmVirtIntrMasking(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2143	{
2144	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2145	return false;
2146	bool fVIntrMasking;
2147	if (!HMGetGuestSvmVirtIntrMasking(pVCpu, &fVIntrMasking))
2148	fVIntrMasking = pCtx->hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u1VIntrMasking;
2149	return fVIntrMasking;
2150	}
2151
2152	/**
2153	* Checks if the nested-guest VMCB has nested-paging enabled.
2154	*
2155	* @returns @c true if nested-paging is enabled, @c false otherwise.
2156	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2157	* @param pCtx Current CPU context.
2158	*
2159	* @remarks Should only be called when SVM feature is exposed to the guest.
2160	*/
2161	DECLINLINE(bool) CPUMIsGuestSvmNestedPagingEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2162	{
2163	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2164	return false;
2165	bool fNestedPaging;
2166	if (!HMGetGuestSvmNestedPaging(pVCpu, &fNestedPaging))
2167	fNestedPaging = pCtx->hwvirt.svm.Vmcb.ctrl.NestedPagingCtrl.n.u1NestedPaging;
2168	return fNestedPaging;
2169	}
2170
2171	/**
2172	* Gets the nested-guest VMCB pause-filter count.
2173	*
2174	* @returns The pause-filter count.
2175	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2176	* @param pCtx Current CPU context.
2177	*
2178	* @remarks Should only be called when SVM feature is exposed to the guest.
2179	*/
2180	DECLINLINE(uint16_t) CPUMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2181	{
2182	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2183	return false;
2184	uint16_t u16PauseFilterCount;
2185	if (!HMGetGuestSvmPauseFilterCount(pVCpu, &u16PauseFilterCount))
2186	u16PauseFilterCount = pCtx->hwvirt.svm.Vmcb.ctrl.u16PauseFilterCount;
2187	return u16PauseFilterCount;
2188	}
2189
2190	/**
2191	* Updates the NextRIP (NRIP) field in the nested-guest VMCB.
2192	*
2193	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2194	* @param pCtx Current CPU context.
2195	* @param cbInstr The length of the current instruction in bytes.
2196	*
2197	* @remarks Should only be called when SVM feature is exposed to the guest.
2198	*/
2199	DECLINLINE(void) CPUMGuestSvmUpdateNRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbInstr)
2200	{
2201	RT_NOREF(pVCpu);
2202	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2203	pCtx->hwvirt.svm.Vmcb.ctrl.u64NextRIP = pCtx->rip + cbInstr;
2204	}
2205
2206	/**
2207	* Checks whether one of the given Pin-based VM-execution controls are set when
2208	* executing a nested-guest.
2209	*
2210	* @returns @c true if set, @c false otherwise.
2211	* @param pCtx Current CPU context.
2212	* @param uPinCtls The Pin-based VM-execution controls to check.
2213	*
2214	* @remarks This does not check if all given controls are set if more than one
2215	* control is passed in @a uPinCtl.
2216	*/
2217	DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls)
2218	{
2219	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2220	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & uPinCtls);
2221	}
2222
2223	/**
2224	* Checks whether one of the given Processor-based VM-execution controls are set
2225	* when executing a nested-guest.
2226	*
2227	* @returns @c true if set, @c false otherwise.
2228	* @param pCtx Current CPU context.
2229	* @param uProcCtls The Processor-based VM-execution controls to check.
2230	*
2231	* @remarks This does not check if all given controls are set if more than one
2232	* control is passed in @a uProcCtls.
2233	*/
2234	DECLINLINE(bool) CPUMIsGuestVmxProcCtlsSet(PCCPUMCTX pCtx, uint32_t uProcCtls)
2235	{
2236	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2237	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls & uProcCtls);
2238	}
2239
2240	/**
2241	* Checks whether one of the given Secondary Processor-based VM-execution controls
2242	* are set when executing a nested-guest.
2243	*
2244	* @returns @c true if set, @c false otherwise.
2245	* @param pCtx Current CPU context.
2246	* @param uProcCtls2 The Secondary Processor-based VM-execution controls to
2247	* check.
2248	*
2249	* @remarks This does not check if all given controls are set if more than one
2250	* control is passed in @a uProcCtls2.
2251	*/
2252	DECLINLINE(bool) CPUMIsGuestVmxProcCtls2Set(PCCPUMCTX pCtx, uint32_t uProcCtls2)
2253	{
2254	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2255	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls2 & uProcCtls2);
2256	}
2257
2258	/**
2259	* Checks whether one of the given Tertiary Processor-based VM-execution controls
2260	* are set when executing a nested-guest.
2261	*
2262	* @returns @c true if set, @c false otherwise.
2263	* @param pCtx Current CPU context.
2264	* @param uProcCtls3 The Tertiary Processor-based VM-execution controls to
2265	* check.
2266	*
2267	* @remarks This does not check if all given controls are set if more than one
2268	* control is passed in @a uProcCtls3.
2269	*/
2270	DECLINLINE(bool) CPUMIsGuestVmxProcCtls3Set(PCCPUMCTX pCtx, uint64_t uProcCtls3)
2271	{
2272	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2273	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u64ProcCtls3.u & uProcCtls3);
2274	}
2275
2276	/**
2277	* Checks whether one of the given VM-exit controls are set when executing a
2278	* nested-guest.
2279	*
2280	* @returns @c true if set, @c false otherwise.
2281	* @param pCtx Current CPU context.
2282	* @param uExitCtls The VM-exit controls to check.
2283	*
2284	* @remarks This does not check if all given controls are set if more than one
2285	* control is passed in @a uExitCtls.
2286	*/
2287	DECLINLINE(bool) CPUMIsGuestVmxExitCtlsSet(PCCPUMCTX pCtx, uint32_t uExitCtls)
2288	{
2289	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2290	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ExitCtls & uExitCtls);
2291	}
2292
2293	/**
2294	* Checks whether one of the given VM-entry controls are set when executing a
2295	* nested-guest.
2296	*
2297	* @returns @c true if set, @c false otherwise.
2298	* @param pCtx Current CPU context.
2299	* @param uEntryCtls The VM-entry controls to check.
2300	*
2301	* @remarks This does not check if all given controls are set if more than one
2302	* control is passed in @a uEntryCtls.
2303	*/
2304	DECLINLINE(bool) CPUMIsGuestVmxEntryCtlsSet(PCCPUMCTX pCtx, uint32_t uEntryCtls)
2305	{
2306	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2307	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32EntryCtls & uEntryCtls);
2308	}
2309
2310	/**
2311	* Checks whether events injected in the nested-guest are subject to VM-exit checks.
2312	*
2313	* @returns @c true if set, @c false otherwise.
2314	* @param pCtx Current CPU context.
2315	*/
2316	DECLINLINE(bool) CPUMIsGuestVmxInterceptEvents(PCCPUMCTX pCtx)
2317	{
2318	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2319	return pCtx->hwvirt.vmx.fInterceptEvents;
2320	}
2321
2322	/**
2323	* Sets whether events injected in the nested-guest are subject to VM-exit checks.
2324	*
2325	* @param pCtx Current CPU context.
2326	* @param fIntercept Whether to subject injected events to VM-exits or not.
2327	*/
2328	DECLINLINE(void) CPUMSetGuestVmxInterceptEvents(PCPUMCTX pCtx, bool fInterceptEvents)
2329	{
2330	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2331	pCtx->hwvirt.vmx.fInterceptEvents = fInterceptEvents;
2332	}
2333
2334	/**
2335	* Checks whether the given exception causes a VM-exit.
2336	*
2337	* The exception type include hardware exceptions, software exceptions (#BP, #OF)
2338	* and privileged software exceptions (#DB generated by INT1/ICEBP).
2339	*
2340	* Software interrupts do -not- cause VM-exits and hence must not be used with this
2341	* function.
2342	*
2343	* @returns @c true if the exception causes a VM-exit, @c false otherwise.
2344	* @param pCtx Current CPU context.
2345	* @param uVector The exception vector.
2346	* @param uErrCode The error code associated with the exception. Pass 0 if not
2347	* applicable.
2348	*/
2349	DECLINLINE(bool) CPUMIsGuestVmxXcptInterceptSet(PCCPUMCTX pCtx, uint8_t uVector, uint32_t uErrCode)
2350	{
2351	Assert(uVector <= X86_XCPT_LAST);
2352
2353	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2354
2355	/* NMIs have a dedicated VM-execution control for causing VM-exits. */
2356	if (uVector == X86_XCPT_NMI)
2357	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
2358
2359	/* Page-faults are subject to masking using its error code. */
2360	uint32_t fXcptBitmap = pCtx->hwvirt.vmx.Vmcs.u32XcptBitmap;
2361	if (uVector == X86_XCPT_PF)
2362	{
2363	uint32_t const fXcptPFMask = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMask;
2364	uint32_t const fXcptPFMatch = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMatch;
2365	if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
2366	fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
2367	}
2368
2369	/* Consult the exception bitmap for all other exceptions. */
2370	if (fXcptBitmap & RT_BIT(uVector))
2371	return true;
2372	return false;
2373	}
2374
2375
2376	/**
2377	* Checks whether the guest is in VMX non-root mode and using EPT paging.
2378	*
2379	* @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
2380	* @param pCtx Current CPU context.
2381	*/
2382	DECLINLINE(bool) CPUMIsGuestVmxEptPagingEnabledEx(PCCPUMCTX pCtx)
2383	{
2384	return CPUMIsGuestInVmxNonRootMode(pCtx)
2385	&& CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_EPT);
2386	}
2387
2388
2389	/**
2390	* Implements VMSucceed for VMX instruction success.
2391	*
2392	* @param pCtx Current CPU context.
2393	*/
2394	DECLINLINE(void) CPUMSetGuestVmxVmSucceed(PCPUMCTX pCtx)
2395	{
2396	pCtx->eflags.u32 &= ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF);
2397	}
2398
2399	/**
2400	* Implements VMFailInvalid for VMX instruction failure.
2401	*
2402	* @param pCtx Current CPU context.
2403	*/
2404	DECLINLINE(void) CPUMSetGuestVmxVmFailInvalid(PCPUMCTX pCtx)
2405	{
2406	pCtx->eflags.u32 &= ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF);
2407	pCtx->eflags.u32 \|= X86_EFL_CF;
2408	}
2409
2410	/**
2411	* Implements VMFailValid for VMX instruction failure.
2412	*
2413	* @param pCtx Current CPU context.
2414	* @param enmInsErr The VM instruction error.
2415	*/
2416	DECLINLINE(void) CPUMSetGuestVmxVmFailValid(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2417	{
2418	pCtx->eflags.u32 &= ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF);
2419	pCtx->eflags.u32 \|= X86_EFL_ZF;
2420	pCtx->hwvirt.vmx.Vmcs.u32RoVmInstrError = enmInsErr;
2421	}
2422
2423	/**
2424	* Implements VMFail for VMX instruction failure.
2425	*
2426	* @param pCtx Current CPU context.
2427	* @param enmInsErr The VM instruction error.
2428	*/
2429	DECLINLINE(void) CPUMSetGuestVmxVmFail(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2430	{
2431	if (pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS)
2432	CPUMSetGuestVmxVmFailValid(pCtx, enmInsErr);
2433	else
2434	CPUMSetGuestVmxVmFailInvalid(pCtx);
2435	}
2436
2437	/**
2438	* Returns the guest-physical address of the APIC-access page when executing a
2439	* nested-guest.
2440	*
2441	* @returns The APIC-access page guest-physical address.
2442	* @param pCtx Current CPU context.
2443	*/
2444	DECLINLINE(uint64_t) CPUMGetGuestVmxApicAccessPageAddrEx(PCCPUMCTX pCtx)
2445	{
2446	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2447	return pCtx->hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
2448	}
2449
2450	/**
2451	* Gets the nested-guest CR0 subject to the guest/host mask and the read-shadow.
2452	*
2453	* @returns The nested-guest CR0.
2454	* @param pCtx Current CPU context.
2455	* @param fGstHostMask The CR0 guest/host mask to use.
2456	*/
2457	DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr0(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2458	{
2459	/*
2460	* For each CR0 bit owned by the host, the corresponding bit from the
2461	* CR0 read shadow is loaded. For each CR0 bit that is not owned by the host,
2462	* the corresponding bit from the guest CR0 is loaded.
2463	*
2464	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2465	*/
2466	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2467	uint64_t const uGstCr0 = pCtx->cr0;
2468	uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2469	return (fReadShadow & fGstHostMask) \| (uGstCr0 & ~fGstHostMask);
2470	}
2471
2472	/**
2473	* Gets the nested-guest CR4 subject to the guest/host mask and the read-shadow.
2474	*
2475	* @returns The nested-guest CR4.
2476	* @param pCtx Current CPU context.
2477	* @param fGstHostMask The CR4 guest/host mask to use.
2478	*/
2479	DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr4(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2480	{
2481	/*
2482	* For each CR4 bit owned by the host, the corresponding bit from the
2483	* CR4 read shadow is loaded. For each CR4 bit that is not owned by the host,
2484	* the corresponding bit from the guest CR4 is loaded.
2485	*
2486	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2487	*/
2488	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2489	uint64_t const uGstCr4 = pCtx->cr4;
2490	uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2491	return (fReadShadow & fGstHostMask) \| (uGstCr4 & ~fGstHostMask);
2492	}
2493
2494	/**
2495	* Checks whether the LMSW access causes a VM-exit or not.
2496	*
2497	* @returns @c true if the LMSW access causes a VM-exit, @c false otherwise.
2498	* @param pCtx Current CPU context.
2499	* @param uNewMsw The LMSW source operand (the Machine Status Word).
2500	*/
2501	DECLINLINE(bool) CPUMIsGuestVmxLmswInterceptSet(PCCPUMCTX pCtx, uint16_t uNewMsw)
2502	{
2503	/*
2504	* LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
2505	*
2506	* See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
2507	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2508	*/
2509	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2510
2511	uint32_t const fGstHostMask = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2512	uint32_t const fReadShadow = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2513
2514	/*
2515	* LMSW can never clear CR0.PE but it may set it. Hence, we handle the
2516	* CR0.PE case first, before the rest of the bits in the MSW.
2517	*
2518	* If CR0.PE is owned by the host and CR0.PE differs between the
2519	* MSW (source operand) and the read-shadow, we must cause a VM-exit.
2520	*/
2521	if ( (fGstHostMask & X86_CR0_PE)
2522	&& (uNewMsw & X86_CR0_PE)
2523	&& !(fReadShadow & X86_CR0_PE))
2524	return true;
2525
2526	/*
2527	* If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
2528	* bits differ between the MSW (source operand) and the read-shadow, we must
2529	* cause a VM-exit.
2530	*/
2531	uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS);
2532	if ((fReadShadow & fGstHostLmswMask) != (uNewMsw & fGstHostLmswMask))
2533	return true;
2534
2535	return false;
2536	}
2537
2538	/**
2539	* Checks whether the Mov-to-CR0/CR4 access causes a VM-exit or not.
2540	*
2541	* @returns @c true if the Mov CRX access causes a VM-exit, @c false otherwise.
2542	* @param pCtx Current CPU context.
2543	* @param iCrReg The control register number (must be 0 or 4).
2544	* @param uNewCrX The CR0/CR4 value being written.
2545	*/
2546	DECLINLINE(bool) CPUMIsGuestVmxMovToCr0Cr4InterceptSet(PCCPUMCTX pCtx, uint8_t iCrReg, uint64_t uNewCrX)
2547	{
2548	/*
2549	* For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
2550	* corresponding bits differ between the source operand and the read-shadow,
2551	* we must cause a VM-exit.
2552	*
2553	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2554	*/
2555	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2556	Assert(iCrReg == 0 \|\| iCrReg == 4);
2557
2558	uint64_t fGstHostMask;
2559	uint64_t fReadShadow;
2560	if (iCrReg == 0)
2561	{
2562	fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2563	fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2564	}
2565	else
2566	{
2567	fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2568	fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2569	}
2570
2571	if ((fReadShadow & fGstHostMask) != (uNewCrX & fGstHostMask))
2572	{
2573	Assert(fGstHostMask != 0);
2574	return true;
2575	}
2576
2577	return false;
2578	}
2579
2580	/**
2581	* Returns whether the guest has an active, current VMCS.
2582	*
2583	* @returns @c true if the guest has an active, current VMCS, @c false otherwise.
2584	* @param pCtx Current CPU context.
2585	*/
2586	DECLINLINE(bool) CPUMIsGuestVmxCurrentVmcsValid(PCCPUMCTX pCtx)
2587	{
2588	return pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS;
2589	}
2590
2591	# endif /* !IN_RC */
2592
2593	/**
2594	* Checks whether the VMX nested-guest is in a state to receive physical (APIC)
2595	* interrupts.
2596	*
2597	* @returns @c true if it's ready, @c false otherwise.
2598	* @param pCtx The guest-CPU context.
2599	*/
2600	DECLINLINE(bool) CPUMIsGuestVmxPhysIntrEnabled(PCCPUMCTX pCtx)
2601	{
2602	#ifdef IN_RC
2603	AssertReleaseFailedReturn(false);
2604	#else
2605	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2606	if (CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_EXT_INT_EXIT))
2607	return true;
2608	return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2609	#endif
2610	}
2611
2612	/**
2613	* Checks whether the VMX nested-guest is blocking virtual-NMIs.
2614	*
2615	* @returns @c true if it's blocked, @c false otherwise.
2616	* @param pCtx The guest-CPU context.
2617	*/
2618	DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx)
2619	{
2620	#ifdef IN_RC
2621	RT_NOREF(pCtx);
2622	AssertReleaseFailedReturn(false);
2623	#else
2624	/*
2625	* Return the state of virtual-NMI blocking, if we are executing a
2626	* VMX nested-guest with virtual-NMIs enabled.
2627	*/
2628	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2629	Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2630	return pCtx->hwvirt.vmx.fVirtNmiBlocking;
2631	#endif
2632	}
2633
2634	/**
2635	* Sets or clears VMX nested-guest virtual-NMI blocking.
2636	*
2637	* @param pCtx The guest-CPU context.
2638	* @param fBlocking Whether virtual-NMI blocking is in effect or not.
2639	*/
2640	DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking)
2641	{
2642	#ifdef IN_RC
2643	RT_NOREF2(pCtx, fBlocking);
2644	AssertReleaseFailedReturnVoid();
2645	#else
2646	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2647	Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2648	pCtx->hwvirt.vmx.fVirtNmiBlocking = fBlocking;
2649	#endif
2650	}
2651
2652	/**
2653	* Checks whether the VMX nested-guest is in a state to receive virtual interrupts
2654	* (those injected with the "virtual-interrupt delivery" feature).
2655	*
2656	* @returns @c true if it's ready, @c false otherwise.
2657	* @param pCtx The guest-CPU context.
2658	*/
2659	DECLINLINE(bool) CPUMIsGuestVmxVirtIntrEnabled(PCCPUMCTX pCtx)
2660	{
2661	#ifdef IN_RC
2662	RT_NOREF2(pCtx);
2663	AssertReleaseFailedReturn(false);
2664	#else
2665	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2666	return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2667	#endif
2668	}
2669
2670	/** @} */
2671	#endif /* !IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS \|\| DOXYGEN_RUNNING */
2672
2673
2674
2675	/** @name Hypervisor Register Getters.
2676	* @{ */
2677	VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
2678	VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
2679	VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
2680	VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
2681	VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
2682	VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
2683	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
2684	/** @} */
2685
2686	/** @name Hypervisor Register Setters.
2687	* @{ */
2688	VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
2689	VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
2690	VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
2691	VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
2692	VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
2693	VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
2694	VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
2695	VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg);
2696	/** @} */
2697
2698	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
2699	#ifdef VBOX_INCLUDED_vmm_cpumctx_h
2700	VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
2701	#endif
2702	VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
2703
2704	/** @name Changed flags.
2705	* These flags are used to keep track of which important register that
2706	* have been changed since last they were reset. The only one allowed
2707	* to clear them is REM!
2708	*
2709	* @todo This is obsolete, but remains as it will be refactored for coordinating
2710	* IEM and NEM/HM later. Probably.
2711	* @{
2712	*/
2713	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
2714	#define CPUM_CHANGED_CR0 RT_BIT(1)
2715	#define CPUM_CHANGED_CR4 RT_BIT(2)
2716	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
2717	#define CPUM_CHANGED_CR3 RT_BIT(4)
2718	#define CPUM_CHANGED_GDTR RT_BIT(5)
2719	#define CPUM_CHANGED_IDTR RT_BIT(6)
2720	#define CPUM_CHANGED_LDTR RT_BIT(7)
2721	#define CPUM_CHANGED_TR RT_BIT(8) /*@< Currently unused. /
2722	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
2723	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /*@< Currently unused. /
2724	#define CPUM_CHANGED_CPUID RT_BIT(11)
2725	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
2726	\| CPUM_CHANGED_CR0 \
2727	\| CPUM_CHANGED_CR4 \
2728	\| CPUM_CHANGED_GLOBAL_TLB_FLUSH \
2729	\| CPUM_CHANGED_CR3 \
2730	\| CPUM_CHANGED_GDTR \
2731	\| CPUM_CHANGED_IDTR \
2732	\| CPUM_CHANGED_LDTR \
2733	\| CPUM_CHANGED_TR \
2734	\| CPUM_CHANGED_SYSENTER_MSR \
2735	\| CPUM_CHANGED_HIDDEN_SEL_REGS \
2736	\| CPUM_CHANGED_CPUID )
2737	/** @} */
2738
2739	VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
2740	VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
2741	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
2742	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
2743	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
2744	VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
2745	VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
2746	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
2747	VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
2748	VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
2749	VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
2750	VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
2751	VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
2752	VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
2753	VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
2754	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
2755	VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM);
2756	VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
2757	uint64_t *puValidEfer);
2758	VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
2759	VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue);
2760
2761
2762	/** Guest CPU interruptibility level, see CPUMGetGuestInterruptibility(). */
2763	typedef enum CPUMINTERRUPTIBILITY
2764	{
2765	CPUMINTERRUPTIBILITY_INVALID = 0,
2766	CPUMINTERRUPTIBILITY_UNRESTRAINED,
2767	CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED,
2768	CPUMINTERRUPTIBILITY_INT_DISABLED,
2769	CPUMINTERRUPTIBILITY_INT_INHIBITED,
2770	CPUMINTERRUPTIBILITY_NMI_INHIBIT,
2771	CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT,
2772	CPUMINTERRUPTIBILITY_END,
2773	CPUMINTERRUPTIBILITY_32BIT_HACK = 0x7fffffff
2774	} CPUMINTERRUPTIBILITY;
2775
2776	VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu);
2777	VMM_INT_DECL(bool) CPUMIsGuestNmiBlocking(PCVMCPU pVCpu);
2778	VMM_INT_DECL(void) CPUMSetGuestNmiBlocking(PVMCPU pVCpu, bool fBlock);
2779
2780	/** @name Typical scalable bus frequency values.
2781	* @{ */
2782	/** Special internal value indicating that we don't know the frequency.
2783	* @internal */
2784	#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
2785	#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
2786	#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
2787	#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
2788	#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
2789	#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
2790	#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
2791	#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
2792	/** @} */
2793
2794
2795	#ifdef IN_RING3
2796	/** @defgroup grp_cpum_r3 The CPUM ring-3 API
2797	* @{
2798	*/
2799
2800	VMMR3DECL(int) CPUMR3Init(PVM pVM);
2801	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
2802	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM);
2803	VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
2804	VMMR3DECL(int) CPUMR3Term(PVM pVM);
2805	VMMR3DECL(void) CPUMR3Reset(PVM pVM);
2806	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
2807	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
2808	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
2809
2810	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
2811	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
2812	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves);
2813	VMMDECL(CPUMMICROARCH) CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
2814	uint8_t bModel, uint8_t bStepping);
2815	VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
2816	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
2817	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
2818	VMMR3DECL(const char *) CPUMCpuVendorName(CPUMCPUVENDOR enmVendor);
2819	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2820	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
2821	#endif
2822
2823	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
2824
2825	VMMR3DECL(uint32_t) CPUMR3DbGetEntries(void);
2826	/** Pointer to CPUMR3DbGetEntries. */
2827	typedef DECLCALLBACKPTR(uint32_t, PFNCPUMDBGETENTRIES, (void));
2828	VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByIndex(uint32_t idxCpuDb);
2829	/** Pointer to CPUMR3DbGetEntryByIndex. */
2830	typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYINDEX, (uint32_t idxCpuDb));
2831	VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByName(const char *pszName);
2832	/** Pointer to CPUMR3DbGetEntryByName. */
2833	typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYNAME, (const char *pszName));
2834
2835	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu);
2836	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu);
2837	/** @} */
2838	#endif /* IN_RING3 */
2839
2840	#ifdef IN_RING0
2841	/** @defgroup grp_cpum_r0 The CPUM ring-0 API
2842	* @{
2843	*/
2844	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
2845	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
2846	VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM);
2847	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM);
2848	DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPUCC pVCpu);
2849	DECLASM(void) CPUMR0TouchHostFpu(void);
2850	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu);
2851	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu);
2852	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu);
2853	VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVMCC pVM, PVMCPUCC pVCpu);
2854	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6);
2855	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6);
2856
2857	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6);
2858	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6);
2859	/** @} */
2860	#endif /* IN_RING0 */
2861
2862	/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
2863	* @{
2864	*/
2865	VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPUCC pVCpu);
2866	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPUCC pVCpu);
2867	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPUCC pVCpu);
2868	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPUCC pVCpu);
2869	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPUCC pVCpu);
2870	/** @} */
2871
2872
2873	#endif /* !VBOX_FOR_DTRACE_LIB */
2874	/** @} */
2875	RT_C_DECLS_END
2876
2877
2878	#endif /* !VBOX_INCLUDED_vmm_cpum_h */
2879

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source: vbox/trunk/include/VBox/vmm/cpum.h@ 97150

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