VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum-x86-amd64.h@ 99814

Last change on this file since 99814 was 99814, checked in by vboxsync, 19 months ago

IEM: Added a separate CPU flag to enable VEX decoding to allow BMI1/2 to be enabled without AVX (see bugref:5653).
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_vmm_cpum_x86_amd64_h
37#define VBOX_INCLUDED_vmm_cpum_x86_amd64_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <iprt/x86.h>
43#include <VBox/vmm/hm_svm.h>
44#include <VBox/vmm/hm_vmx.h>
45
46RT_C_DECLS_BEGIN
47
48/** @defgroup grp_cpum The CPU Monitor / Manager API
49 * @ingroup grp_vmm
50 * @{
51 */
52
53/**
54 * CPUID feature to set or clear.
55 */
56typedef enum CPUMCPUIDFEATURE
57{
58 CPUMCPUIDFEATURE_INVALID = 0,
59 /** The APIC feature bit. (Std+Ext)
60 * Note! There is a per-cpu flag for masking this CPUID feature bit when the
61 * APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
62 * at VM construction time like all the others. This didn't used to be
63 * that way, this is new with 5.1. */
64 CPUMCPUIDFEATURE_APIC,
65 /** The sysenter/sysexit feature bit. (Std) */
66 CPUMCPUIDFEATURE_SEP,
67 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
68 CPUMCPUIDFEATURE_SYSCALL,
69 /** The PAE feature bit. (Std+Ext) */
70 CPUMCPUIDFEATURE_PAE,
71 /** The NX feature bit. (Ext) */
72 CPUMCPUIDFEATURE_NX,
73 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
74 CPUMCPUIDFEATURE_LAHF,
75 /** The LONG MODE feature bit. (Ext) */
76 CPUMCPUIDFEATURE_LONG_MODE,
77 /** The x2APIC feature bit. (Std) */
78 CPUMCPUIDFEATURE_X2APIC,
79 /** The RDTSCP feature bit. (Ext) */
80 CPUMCPUIDFEATURE_RDTSCP,
81 /** The Hypervisor Present bit. (Std) */
82 CPUMCPUIDFEATURE_HVP,
83 /** The speculation control feature bits. (StExt) */
84 CPUMCPUIDFEATURE_SPEC_CTRL,
85 /** 32bit hackishness. */
86 CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
87} CPUMCPUIDFEATURE;
88
89
90/**
91 * CPUID leaf.
92 *
93 * @remarks This structure is used by the patch manager and is therefore
94 * more or less set in stone.
95 */
96typedef struct CPUMCPUIDLEAF
97{
98 /** The leaf number. */
99 uint32_t uLeaf;
100 /** The sub-leaf number. */
101 uint32_t uSubLeaf;
102 /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
103 uint32_t fSubLeafMask;
104
105 /** The EAX value. */
106 uint32_t uEax;
107 /** The EBX value. */
108 uint32_t uEbx;
109 /** The ECX value. */
110 uint32_t uEcx;
111 /** The EDX value. */
112 uint32_t uEdx;
113
114 /** Flags. */
115 uint32_t fFlags;
116} CPUMCPUIDLEAF;
117#ifndef VBOX_FOR_DTRACE_LIB
118AssertCompileSize(CPUMCPUIDLEAF, 32);
119#endif
120/** Pointer to a CPUID leaf. */
121typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
122/** Pointer to a const CPUID leaf. */
123typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
124
125/** @name CPUMCPUIDLEAF::fFlags
126 * @{ */
127/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
128 * and EDX containing the extended APIC ID. */
129#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
130/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
131#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
132/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
133#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
134/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
135#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
136/** Mask of the valid flags. */
137#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
138/** @} */
139
140/**
141 * Method used to deal with unknown CPUID leaves.
142 * @remarks Used in patch code.
143 */
144typedef enum CPUMUNKNOWNCPUID
145{
146 /** Invalid zero value. */
147 CPUMUNKNOWNCPUID_INVALID = 0,
148 /** Use given default values (DefCpuId). */
149 CPUMUNKNOWNCPUID_DEFAULTS,
150 /** Return the last standard leaf.
151 * Intel Sandy Bridge has been observed doing this. */
152 CPUMUNKNOWNCPUID_LAST_STD_LEAF,
153 /** Return the last standard leaf, with ecx observed.
154 * Intel Sandy Bridge has been observed doing this. */
155 CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
156 /** The register values are passed thru unmodified. */
157 CPUMUNKNOWNCPUID_PASSTHRU,
158 /** End of valid value. */
159 CPUMUNKNOWNCPUID_END,
160 /** Ensure 32-bit type. */
161 CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
162} CPUMUNKNOWNCPUID;
163/** Pointer to unknown CPUID leaf method. */
164typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
165
166
167/**
168 * The register set returned by a CPUID operation.
169 */
170typedef struct CPUMCPUID
171{
172 uint32_t uEax;
173 uint32_t uEbx;
174 uint32_t uEcx;
175 uint32_t uEdx;
176} CPUMCPUID;
177/** Pointer to a CPUID leaf. */
178typedef CPUMCPUID *PCPUMCPUID;
179/** Pointer to a const CPUID leaf. */
180typedef const CPUMCPUID *PCCPUMCPUID;
181
182
183/**
184 * MSR read functions.
185 */
186typedef enum CPUMMSRRDFN
187{
188 /** Invalid zero value. */
189 kCpumMsrRdFn_Invalid = 0,
190 /** Return the CPUMMSRRANGE::uValue. */
191 kCpumMsrRdFn_FixedValue,
192 /** Alias to the MSR range starting at the MSR given by
193 * CPUMMSRRANGE::uValue. Must be used in pair with
194 * kCpumMsrWrFn_MsrAlias. */
195 kCpumMsrRdFn_MsrAlias,
196 /** Write only register, GP all read attempts. */
197 kCpumMsrRdFn_WriteOnly,
198
199 kCpumMsrRdFn_Ia32P5McAddr,
200 kCpumMsrRdFn_Ia32P5McType,
201 kCpumMsrRdFn_Ia32TimestampCounter,
202 kCpumMsrRdFn_Ia32PlatformId, /**< Takes real CPU value for reference. */
203 kCpumMsrRdFn_Ia32ApicBase,
204 kCpumMsrRdFn_Ia32FeatureControl,
205 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
206 kCpumMsrRdFn_Ia32SmmMonitorCtl,
207 kCpumMsrRdFn_Ia32PmcN,
208 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
209 kCpumMsrRdFn_Ia32MPerf,
210 kCpumMsrRdFn_Ia32APerf,
211 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
212 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
213 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
214 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
215 kCpumMsrRdFn_Ia32MtrrDefType,
216 kCpumMsrRdFn_Ia32Pat,
217 kCpumMsrRdFn_Ia32SysEnterCs,
218 kCpumMsrRdFn_Ia32SysEnterEsp,
219 kCpumMsrRdFn_Ia32SysEnterEip,
220 kCpumMsrRdFn_Ia32McgCap,
221 kCpumMsrRdFn_Ia32McgStatus,
222 kCpumMsrRdFn_Ia32McgCtl,
223 kCpumMsrRdFn_Ia32DebugCtl,
224 kCpumMsrRdFn_Ia32SmrrPhysBase,
225 kCpumMsrRdFn_Ia32SmrrPhysMask,
226 kCpumMsrRdFn_Ia32PlatformDcaCap,
227 kCpumMsrRdFn_Ia32CpuDcaCap,
228 kCpumMsrRdFn_Ia32Dca0Cap,
229 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
230 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
231 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
232 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
233 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
234 kCpumMsrRdFn_Ia32FixedCtrCtrl,
235 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
236 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
237 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
238 kCpumMsrRdFn_Ia32PebsEnable,
239 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
240 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
241 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
242 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
243 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
244 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
245 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
246 kCpumMsrRdFn_Ia32DsArea,
247 kCpumMsrRdFn_Ia32TscDeadline,
248 kCpumMsrRdFn_Ia32X2ApicN,
249 kCpumMsrRdFn_Ia32DebugInterface,
250 kCpumMsrRdFn_Ia32VmxBasic, /**< Takes real value as reference. */
251 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
252 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
253 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
254 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
255 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
256 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
257 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
258 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
259 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
260 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
261 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
262 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
263 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
264 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
265 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
266 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
267 kCpumMsrRdFn_Ia32VmxVmFunc, /**< Takes real value as reference. */
268 kCpumMsrRdFn_Ia32SpecCtrl,
269 kCpumMsrRdFn_Ia32ArchCapabilities,
270
271 kCpumMsrRdFn_Amd64Efer,
272 kCpumMsrRdFn_Amd64SyscallTarget,
273 kCpumMsrRdFn_Amd64LongSyscallTarget,
274 kCpumMsrRdFn_Amd64CompSyscallTarget,
275 kCpumMsrRdFn_Amd64SyscallFlagMask,
276 kCpumMsrRdFn_Amd64FsBase,
277 kCpumMsrRdFn_Amd64GsBase,
278 kCpumMsrRdFn_Amd64KernelGsBase,
279 kCpumMsrRdFn_Amd64TscAux,
280
281 kCpumMsrRdFn_IntelEblCrPowerOn,
282 kCpumMsrRdFn_IntelI7CoreThreadCount,
283 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
284 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
285 kCpumMsrRdFn_IntelP4EbcFrequencyId,
286 kCpumMsrRdFn_IntelP6FsbFrequency, /**< Takes real value as reference. */
287 kCpumMsrRdFn_IntelPlatformInfo,
288 kCpumMsrRdFn_IntelFlexRatio, /**< Takes real value as reference. */
289 kCpumMsrRdFn_IntelPkgCStConfigControl,
290 kCpumMsrRdFn_IntelPmgIoCaptureBase,
291 kCpumMsrRdFn_IntelLastBranchFromToN,
292 kCpumMsrRdFn_IntelLastBranchFromN,
293 kCpumMsrRdFn_IntelLastBranchToN,
294 kCpumMsrRdFn_IntelLastBranchTos,
295 kCpumMsrRdFn_IntelBblCrCtl,
296 kCpumMsrRdFn_IntelBblCrCtl3,
297 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
298 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
299 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
300 kCpumMsrRdFn_IntelP6CrN,
301 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
302 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
303 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
304 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
305 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
306 kCpumMsrRdFn_IntelI7LbrSelect,
307 kCpumMsrRdFn_IntelI7SandyErrorControl,
308 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
309 kCpumMsrRdFn_IntelI7PowerCtl,
310 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
311 kCpumMsrRdFn_IntelI7PebsLdLat,
312 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
313 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
314 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
315 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
316 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
317 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
318 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
319 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
320 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
321 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
322 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
323 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
324 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
325 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
326 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
327 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
328 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
329 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
330 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
331 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
332 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
333 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
334 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
335 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
336 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
337 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
338 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
339 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
340 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
341 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
342 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
343 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
344 kCpumMsrRdFn_IntelI7UncCBoxConfig,
345 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
346 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
347 kCpumMsrRdFn_IntelI7SmiCount,
348 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
349 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
350 kCpumMsrRdFn_IntelCore1ExtConfig,
351 kCpumMsrRdFn_IntelCore1DtsCalControl,
352 kCpumMsrRdFn_IntelCore2PeciControl,
353 kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
354
355 kCpumMsrRdFn_P6LastBranchFromIp,
356 kCpumMsrRdFn_P6LastBranchToIp,
357 kCpumMsrRdFn_P6LastIntFromIp,
358 kCpumMsrRdFn_P6LastIntToIp,
359
360 kCpumMsrRdFn_AmdFam15hTscRate,
361 kCpumMsrRdFn_AmdFam15hLwpCfg,
362 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
363 kCpumMsrRdFn_AmdFam10hMc4MiscN,
364 kCpumMsrRdFn_AmdK8PerfCtlN,
365 kCpumMsrRdFn_AmdK8PerfCtrN,
366 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
367 kCpumMsrRdFn_AmdK8HwCr,
368 kCpumMsrRdFn_AmdK8IorrBaseN,
369 kCpumMsrRdFn_AmdK8IorrMaskN,
370 kCpumMsrRdFn_AmdK8TopOfMemN,
371 kCpumMsrRdFn_AmdK8NbCfg1,
372 kCpumMsrRdFn_AmdK8McXcptRedir,
373 kCpumMsrRdFn_AmdK8CpuNameN,
374 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
375 kCpumMsrRdFn_AmdK8SwThermalCtrl,
376 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
377 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
378 kCpumMsrRdFn_AmdK8McCtlMaskN,
379 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
380 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
381 kCpumMsrRdFn_AmdK8IntPendingMessage,
382 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
383 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
384 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
385 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
386 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
387 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
388 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
389 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
390 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
391 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
392 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
393 kCpumMsrRdFn_AmdK8SmmBase,
394 kCpumMsrRdFn_AmdK8SmmAddr,
395 kCpumMsrRdFn_AmdK8SmmMask,
396 kCpumMsrRdFn_AmdK8VmCr,
397 kCpumMsrRdFn_AmdK8IgnNe,
398 kCpumMsrRdFn_AmdK8SmmCtl,
399 kCpumMsrRdFn_AmdK8VmHSavePa,
400 kCpumMsrRdFn_AmdFam10hVmLockKey,
401 kCpumMsrRdFn_AmdFam10hSmmLockKey,
402 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
403 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
404 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
405 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
406 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
407 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
408 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
409 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
410 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
411 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
412 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
413 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
414 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
415 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
416 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
417 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
418 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
419 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
420 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
421 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
422 kCpumMsrRdFn_AmdK7NodeId,
423 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
424 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
425 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
426 kCpumMsrRdFn_AmdK7LoadStoreCfg,
427 kCpumMsrRdFn_AmdK7InstrCacheCfg,
428 kCpumMsrRdFn_AmdK7DataCacheCfg,
429 kCpumMsrRdFn_AmdK7BusUnitCfg,
430 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
431 kCpumMsrRdFn_AmdFam15hFpuCfg,
432 kCpumMsrRdFn_AmdFam15hDecoderCfg,
433 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
434 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
435 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
436 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
437 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
438 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
439 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
440 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
441 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
442 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
443 kCpumMsrRdFn_AmdFam10hIbsOpRip,
444 kCpumMsrRdFn_AmdFam10hIbsOpData,
445 kCpumMsrRdFn_AmdFam10hIbsOpData2,
446 kCpumMsrRdFn_AmdFam10hIbsOpData3,
447 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
448 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
449 kCpumMsrRdFn_AmdFam10hIbsCtl,
450 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
451
452 kCpumMsrRdFn_Gim,
453
454 /** End of valid MSR read function indexes. */
455 kCpumMsrRdFn_End
456} CPUMMSRRDFN;
457
458/**
459 * MSR write functions.
460 */
461typedef enum CPUMMSRWRFN
462{
463 /** Invalid zero value. */
464 kCpumMsrWrFn_Invalid = 0,
465 /** Writes are ignored, the fWrGpMask is observed though. */
466 kCpumMsrWrFn_IgnoreWrite,
467 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
468 kCpumMsrWrFn_ReadOnly,
469 /** Alias to the MSR range starting at the MSR given by
470 * CPUMMSRRANGE::uValue. Must be used in pair with
471 * kCpumMsrRdFn_MsrAlias. */
472 kCpumMsrWrFn_MsrAlias,
473
474 kCpumMsrWrFn_Ia32P5McAddr,
475 kCpumMsrWrFn_Ia32P5McType,
476 kCpumMsrWrFn_Ia32TimestampCounter,
477 kCpumMsrWrFn_Ia32ApicBase,
478 kCpumMsrWrFn_Ia32FeatureControl,
479 kCpumMsrWrFn_Ia32BiosSignId,
480 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
481 kCpumMsrWrFn_Ia32SmmMonitorCtl,
482 kCpumMsrWrFn_Ia32PmcN,
483 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
484 kCpumMsrWrFn_Ia32MPerf,
485 kCpumMsrWrFn_Ia32APerf,
486 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
487 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
488 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
489 kCpumMsrWrFn_Ia32MtrrDefType,
490 kCpumMsrWrFn_Ia32Pat,
491 kCpumMsrWrFn_Ia32SysEnterCs,
492 kCpumMsrWrFn_Ia32SysEnterEsp,
493 kCpumMsrWrFn_Ia32SysEnterEip,
494 kCpumMsrWrFn_Ia32McgStatus,
495 kCpumMsrWrFn_Ia32McgCtl,
496 kCpumMsrWrFn_Ia32DebugCtl,
497 kCpumMsrWrFn_Ia32SmrrPhysBase,
498 kCpumMsrWrFn_Ia32SmrrPhysMask,
499 kCpumMsrWrFn_Ia32PlatformDcaCap,
500 kCpumMsrWrFn_Ia32Dca0Cap,
501 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
502 kCpumMsrWrFn_Ia32PerfStatus,
503 kCpumMsrWrFn_Ia32PerfCtl,
504 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
505 kCpumMsrWrFn_Ia32PerfCapabilities,
506 kCpumMsrWrFn_Ia32FixedCtrCtrl,
507 kCpumMsrWrFn_Ia32PerfGlobalStatus,
508 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
509 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
510 kCpumMsrWrFn_Ia32PebsEnable,
511 kCpumMsrWrFn_Ia32ClockModulation,
512 kCpumMsrWrFn_Ia32ThermInterrupt,
513 kCpumMsrWrFn_Ia32ThermStatus,
514 kCpumMsrWrFn_Ia32Therm2Ctl,
515 kCpumMsrWrFn_Ia32MiscEnable,
516 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
517 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
518 kCpumMsrWrFn_Ia32DsArea,
519 kCpumMsrWrFn_Ia32TscDeadline,
520 kCpumMsrWrFn_Ia32X2ApicN,
521 kCpumMsrWrFn_Ia32DebugInterface,
522 kCpumMsrWrFn_Ia32SpecCtrl,
523 kCpumMsrWrFn_Ia32PredCmd,
524 kCpumMsrWrFn_Ia32FlushCmd,
525
526 kCpumMsrWrFn_Amd64Efer,
527 kCpumMsrWrFn_Amd64SyscallTarget,
528 kCpumMsrWrFn_Amd64LongSyscallTarget,
529 kCpumMsrWrFn_Amd64CompSyscallTarget,
530 kCpumMsrWrFn_Amd64SyscallFlagMask,
531 kCpumMsrWrFn_Amd64FsBase,
532 kCpumMsrWrFn_Amd64GsBase,
533 kCpumMsrWrFn_Amd64KernelGsBase,
534 kCpumMsrWrFn_Amd64TscAux,
535 kCpumMsrWrFn_IntelEblCrPowerOn,
536 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
537 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
538 kCpumMsrWrFn_IntelP4EbcFrequencyId,
539 kCpumMsrWrFn_IntelFlexRatio,
540 kCpumMsrWrFn_IntelPkgCStConfigControl,
541 kCpumMsrWrFn_IntelPmgIoCaptureBase,
542 kCpumMsrWrFn_IntelLastBranchFromToN,
543 kCpumMsrWrFn_IntelLastBranchFromN,
544 kCpumMsrWrFn_IntelLastBranchToN,
545 kCpumMsrWrFn_IntelLastBranchTos,
546 kCpumMsrWrFn_IntelBblCrCtl,
547 kCpumMsrWrFn_IntelBblCrCtl3,
548 kCpumMsrWrFn_IntelI7TemperatureTarget,
549 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
550 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
551 kCpumMsrWrFn_IntelP6CrN,
552 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
553 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
554 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
555 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
556 kCpumMsrWrFn_IntelI7TurboRatioLimit,
557 kCpumMsrWrFn_IntelI7LbrSelect,
558 kCpumMsrWrFn_IntelI7SandyErrorControl,
559 kCpumMsrWrFn_IntelI7PowerCtl,
560 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
561 kCpumMsrWrFn_IntelI7PebsLdLat,
562 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
563 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
564 kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /**< R/O but found writable bits on a Silvermont CPU here. */
565 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
566 kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /**< R/O but found writable bits on a Silvermont CPU here. */
567 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
568 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
569 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
570 kCpumMsrWrFn_IntelI7RaplPp0Policy,
571 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
572 kCpumMsrWrFn_IntelI7RaplPp1Policy,
573 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
574 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
575 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
576 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
577 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
578 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
579 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
580 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
581 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
582 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
583 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
584 kCpumMsrWrFn_IntelCore1ExtConfig,
585 kCpumMsrWrFn_IntelCore1DtsCalControl,
586 kCpumMsrWrFn_IntelCore2PeciControl,
587
588 kCpumMsrWrFn_P6LastIntFromIp,
589 kCpumMsrWrFn_P6LastIntToIp,
590
591 kCpumMsrWrFn_AmdFam15hTscRate,
592 kCpumMsrWrFn_AmdFam15hLwpCfg,
593 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
594 kCpumMsrWrFn_AmdFam10hMc4MiscN,
595 kCpumMsrWrFn_AmdK8PerfCtlN,
596 kCpumMsrWrFn_AmdK8PerfCtrN,
597 kCpumMsrWrFn_AmdK8SysCfg,
598 kCpumMsrWrFn_AmdK8HwCr,
599 kCpumMsrWrFn_AmdK8IorrBaseN,
600 kCpumMsrWrFn_AmdK8IorrMaskN,
601 kCpumMsrWrFn_AmdK8TopOfMemN,
602 kCpumMsrWrFn_AmdK8NbCfg1,
603 kCpumMsrWrFn_AmdK8McXcptRedir,
604 kCpumMsrWrFn_AmdK8CpuNameN,
605 kCpumMsrWrFn_AmdK8HwThermalCtrl,
606 kCpumMsrWrFn_AmdK8SwThermalCtrl,
607 kCpumMsrWrFn_AmdK8FidVidControl,
608 kCpumMsrWrFn_AmdK8McCtlMaskN,
609 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
610 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
611 kCpumMsrWrFn_AmdK8IntPendingMessage,
612 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
613 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
614 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
615 kCpumMsrWrFn_AmdFam10hPStateControl,
616 kCpumMsrWrFn_AmdFam10hPStateStatus,
617 kCpumMsrWrFn_AmdFam10hPStateN,
618 kCpumMsrWrFn_AmdFam10hCofVidControl,
619 kCpumMsrWrFn_AmdFam10hCofVidStatus,
620 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
621 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
622 kCpumMsrWrFn_AmdK8SmmBase,
623 kCpumMsrWrFn_AmdK8SmmAddr,
624 kCpumMsrWrFn_AmdK8SmmMask,
625 kCpumMsrWrFn_AmdK8VmCr,
626 kCpumMsrWrFn_AmdK8IgnNe,
627 kCpumMsrWrFn_AmdK8SmmCtl,
628 kCpumMsrWrFn_AmdK8VmHSavePa,
629 kCpumMsrWrFn_AmdFam10hVmLockKey,
630 kCpumMsrWrFn_AmdFam10hSmmLockKey,
631 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
632 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
633 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
634 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
635 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
636 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
637 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
638 kCpumMsrWrFn_AmdK7MicrocodeCtl,
639 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
640 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
641 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
642 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
643 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
644 kCpumMsrWrFn_AmdK8PatchLoader,
645 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
646 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
647 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
648 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
649 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
650 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
651 kCpumMsrWrFn_AmdK7NodeId,
652 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
653 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
654 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
655 kCpumMsrWrFn_AmdK7LoadStoreCfg,
656 kCpumMsrWrFn_AmdK7InstrCacheCfg,
657 kCpumMsrWrFn_AmdK7DataCacheCfg,
658 kCpumMsrWrFn_AmdK7BusUnitCfg,
659 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
660 kCpumMsrWrFn_AmdFam15hFpuCfg,
661 kCpumMsrWrFn_AmdFam15hDecoderCfg,
662 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
663 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
664 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
665 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
666 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
667 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
668 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
669 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
670 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
671 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
672 kCpumMsrWrFn_AmdFam10hIbsOpRip,
673 kCpumMsrWrFn_AmdFam10hIbsOpData,
674 kCpumMsrWrFn_AmdFam10hIbsOpData2,
675 kCpumMsrWrFn_AmdFam10hIbsOpData3,
676 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
677 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
678 kCpumMsrWrFn_AmdFam10hIbsCtl,
679 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
680
681 kCpumMsrWrFn_Gim,
682
683 /** End of valid MSR write function indexes. */
684 kCpumMsrWrFn_End
685} CPUMMSRWRFN;
686
687/**
688 * MSR range.
689 */
690typedef struct CPUMMSRRANGE
691{
692 /** The first MSR. [0] */
693 uint32_t uFirst;
694 /** The last MSR. [4] */
695 uint32_t uLast;
696 /** The read function (CPUMMSRRDFN). [8] */
697 uint16_t enmRdFn;
698 /** The write function (CPUMMSRWRFN). [10] */
699 uint16_t enmWrFn;
700 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
701 * UINT16_MAX if not used by the read and write functions. [12] */
702 uint32_t offCpumCpu : 24;
703 /** Reserved for future hacks. [15] */
704 uint32_t fReserved : 8;
705 /** The init/read value. [16]
706 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
707 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
708 * offset into CPUM. */
709 uint64_t uValue;
710 /** The bits to ignore when writing. [24] */
711 uint64_t fWrIgnMask;
712 /** The bits that will cause a GP(0) when writing. [32]
713 * This is always checked prior to calling the write function. Using
714 * UINT64_MAX effectively marks the MSR as read-only. */
715 uint64_t fWrGpMask;
716 /** The register name, if applicable. [40] */
717 char szName[56];
718
719 /** The number of reads. */
720 STAMCOUNTER cReads;
721 /** The number of writes. */
722 STAMCOUNTER cWrites;
723 /** The number of times ignored bits were written. */
724 STAMCOUNTER cIgnoredBits;
725 /** The number of GPs generated. */
726 STAMCOUNTER cGps;
727} CPUMMSRRANGE;
728#ifndef VBOX_FOR_DTRACE_LIB
729AssertCompileSize(CPUMMSRRANGE, 128);
730#endif
731/** Pointer to an MSR range. */
732typedef CPUMMSRRANGE *PCPUMMSRRANGE;
733/** Pointer to a const MSR range. */
734typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
735
736
737/**
738 * MSRs which are required while exploding features.
739 */
740typedef struct CPUMMSRS
741{
742 union
743 {
744 VMXMSRS vmx;
745 SVMMSRS svm;
746 } hwvirt;
747} CPUMMSRS;
748/** Pointer to an CPUMMSRS struct. */
749typedef CPUMMSRS *PCPUMMSRS;
750/** Pointer to a const CPUMMSRS struct. */
751typedef CPUMMSRS const *PCCPUMMSRS;
752
753
754/**
755 * CPU features and quirks.
756 * This is mostly exploded CPUID info.
757 */
758typedef struct CPUMFEATURES
759{
760 /** The CPU vendor (CPUMCPUVENDOR). */
761 uint8_t enmCpuVendor;
762 /** The CPU family. */
763 uint8_t uFamily;
764 /** The CPU model. */
765 uint8_t uModel;
766 /** The CPU stepping. */
767 uint8_t uStepping;
768 /** The microarchitecture. */
769#ifndef VBOX_FOR_DTRACE_LIB
770 CPUMMICROARCH enmMicroarch;
771#else
772 uint32_t enmMicroarch;
773#endif
774 /** The maximum physical address width of the CPU. */
775 uint8_t cMaxPhysAddrWidth;
776 /** The maximum linear address width of the CPU. */
777 uint8_t cMaxLinearAddrWidth;
778 /** Max size of the extended state (or FPU state if no XSAVE). */
779 uint16_t cbMaxExtendedState;
780
781 /** Supports MSRs. */
782 uint32_t fMsr : 1;
783 /** Supports the page size extension (4/2 MB pages). */
784 uint32_t fPse : 1;
785 /** Supports 36-bit page size extension (4 MB pages can map memory above
786 * 4GB). */
787 uint32_t fPse36 : 1;
788 /** Supports physical address extension (PAE). */
789 uint32_t fPae : 1;
790 /** Supports page-global extension (PGE). */
791 uint32_t fPge : 1;
792 /** Page attribute table (PAT) support (page level cache control). */
793 uint32_t fPat : 1;
794 /** Supports the FXSAVE and FXRSTOR instructions. */
795 uint32_t fFxSaveRstor : 1;
796 /** Supports the XSAVE and XRSTOR instructions. */
797 uint32_t fXSaveRstor : 1;
798 /** Supports the XSAVEOPT instruction. */
799 uint32_t fXSaveOpt : 1;
800 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
801 uint32_t fOpSysXSaveRstor : 1;
802 /** Supports MMX. */
803 uint32_t fMmx : 1;
804 /** Supports AMD extensions to MMX instructions. */
805 uint32_t fAmdMmxExts : 1;
806 /** Supports SSE. */
807 uint32_t fSse : 1;
808 /** Supports SSE2. */
809 uint32_t fSse2 : 1;
810 /** Supports SSE3. */
811 uint32_t fSse3 : 1;
812 /** Supports SSSE3. */
813 uint32_t fSsse3 : 1;
814 /** Supports SSE4.1. */
815 uint32_t fSse41 : 1;
816 /** Supports SSE4.2. */
817 uint32_t fSse42 : 1;
818 /** Supports AVX. */
819 uint32_t fAvx : 1;
820 /** Supports AVX2. */
821 uint32_t fAvx2 : 1;
822 /** Supports AVX512 foundation. */
823 uint32_t fAvx512Foundation : 1;
824 /** Supports RDTSC. */
825 uint32_t fTsc : 1;
826 /** Intel SYSENTER/SYSEXIT support */
827 uint32_t fSysEnter : 1;
828 /** First generation APIC. */
829 uint32_t fApic : 1;
830 /** Second generation APIC. */
831 uint32_t fX2Apic : 1;
832 /** Hypervisor present. */
833 uint32_t fHypervisorPresent : 1;
834 /** MWAIT & MONITOR instructions supported. */
835 uint32_t fMonitorMWait : 1;
836 /** MWAIT Extensions present. */
837 uint32_t fMWaitExtensions : 1;
838 /** Supports CMPXCHG16B in 64-bit mode. */
839 uint32_t fMovCmpXchg16b : 1;
840 /** Supports CLFLUSH. */
841 uint32_t fClFlush : 1;
842 /** Supports CLFLUSHOPT. */
843 uint32_t fClFlushOpt : 1;
844 /** Supports IA32_PRED_CMD.IBPB. */
845 uint32_t fIbpb : 1;
846 /** Supports IA32_SPEC_CTRL.IBRS. */
847 uint32_t fIbrs : 1;
848 /** Supports IA32_SPEC_CTRL.STIBP. */
849 uint32_t fStibp : 1;
850 /** Supports IA32_FLUSH_CMD. */
851 uint32_t fFlushCmd : 1;
852 /** Supports IA32_ARCH_CAP. */
853 uint32_t fArchCap : 1;
854 /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
855 uint32_t fMdsClear : 1;
856 /** Supports PCID. */
857 uint32_t fPcid : 1;
858 /** Supports INVPCID. */
859 uint32_t fInvpcid : 1;
860 /** Supports read/write FSGSBASE instructions. */
861 uint32_t fFsGsBase : 1;
862 /** Supports BMI1 instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, and TZCNT). */
863 uint32_t fBmi1 : 1;
864 /** Supports BMI2 instructions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX,
865 * and SHLX). */
866 uint32_t fBmi2 : 1;
867 /** Supports POPCNT instruction. */
868 uint32_t fPopCnt : 1;
869 /** Supports RDRAND instruction. */
870 uint32_t fRdRand : 1;
871 /** Supports RDSEED instruction. */
872 uint32_t fRdSeed : 1;
873 /** Supports Hardware Lock Elision (HLE). */
874 uint32_t fHle : 1;
875 /** Supports Restricted Transactional Memory (RTM - XBEGIN, XEND, XABORT). */
876 uint32_t fRtm : 1;
877 /** Supports PCLMULQDQ instruction. */
878 uint32_t fPclMul : 1;
879 /** Supports AES-NI (six AESxxx instructions). */
880 uint32_t fAesNi : 1;
881 /** Support MOVBE instruction. */
882 uint32_t fMovBe : 1;
883 /** Support SHA instructions. */
884 uint32_t fSha : 1;
885 /** Support ADX instructions. */
886 uint32_t fAdx : 1;
887
888 /** Supports AMD 3DNow instructions. */
889 uint32_t f3DNow : 1;
890 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
891 uint32_t f3DNowPrefetch : 1;
892
893 /** AMD64: Supports long mode. */
894 uint32_t fLongMode : 1;
895 /** AMD64: SYSCALL/SYSRET support. */
896 uint32_t fSysCall : 1;
897 /** AMD64: No-execute page table bit. */
898 uint32_t fNoExecute : 1;
899 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
900 uint32_t fLahfSahf : 1;
901 /** AMD64: Supports RDTSCP. */
902 uint32_t fRdTscP : 1;
903 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
904 uint32_t fMovCr8In32Bit : 1;
905 /** AMD64: Supports XOP (similar to VEX3/AVX). */
906 uint32_t fXop : 1;
907 /** AMD64: Supports ABM, i.e. the LZCNT instruction. */
908 uint32_t fAbm : 1;
909 /** AMD64: Supports TBM (BEXTR, BLCFILL, BLCI, BLCIC, BLCMSK, BLCS,
910 * BLSFILL, BLSIC, T1MSKC, and TZMSK). */
911 uint32_t fTbm : 1;
912
913 /** Indicates that FPU instruction and data pointers may leak.
914 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
915 * is only saved and restored if an exception is pending. */
916 uint32_t fLeakyFxSR : 1;
917
918 /** Supports VEX instruction encoding (AVX, BMI, etc.). */
919 uint32_t fVex : 1;
920
921 /** AMD64: Supports AMD SVM. */
922 uint32_t fSvm : 1;
923
924 /** Support for Intel VMX. */
925 uint32_t fVmx : 1;
926
927 /** Indicates that speculative execution control CPUID bits and MSRs are exposed.
928 * The details are different for Intel and AMD but both have similar
929 * functionality. */
930 uint32_t fSpeculationControl : 1;
931
932 /** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
933 * @remarks Only safe use after CPUM ring-0 init! */
934 uint32_t fArchRdclNo : 1;
935 /** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
936 * @remarks Only safe use after CPUM ring-0 init! */
937 uint32_t fArchIbrsAll : 1;
938 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
939 * @remarks Only safe use after CPUM ring-0 init! */
940 uint32_t fArchRsbOverride : 1;
941 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
942 * @remarks Only safe use after CPUM ring-0 init! */
943 uint32_t fArchVmmNeedNotFlushL1d : 1;
944 /** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4).
945 * @remarks Only safe use after CPUM ring-0 init! */
946 uint32_t fArchMdsNo : 1;
947
948 /** Alignment padding / reserved for future use (96 bits total, plus 12 bytes
949 * prior to the bit fields -> total of 24 bytes) */
950 uint32_t fPadding0 : 23;
951
952
953 /** @name SVM
954 * @{ */
955 /** SVM: Supports Nested-paging. */
956 uint32_t fSvmNestedPaging : 1;
957 /** SVM: Support LBR (Last Branch Record) virtualization. */
958 uint32_t fSvmLbrVirt : 1;
959 /** SVM: Supports SVM lock. */
960 uint32_t fSvmSvmLock : 1;
961 /** SVM: Supports Next RIP save. */
962 uint32_t fSvmNextRipSave : 1;
963 /** SVM: Supports TSC rate MSR. */
964 uint32_t fSvmTscRateMsr : 1;
965 /** SVM: Supports VMCB clean bits. */
966 uint32_t fSvmVmcbClean : 1;
967 /** SVM: Supports Flush-by-ASID. */
968 uint32_t fSvmFlusbByAsid : 1;
969 /** SVM: Supports decode assist. */
970 uint32_t fSvmDecodeAssists : 1;
971 /** SVM: Supports Pause filter. */
972 uint32_t fSvmPauseFilter : 1;
973 /** SVM: Supports Pause filter threshold. */
974 uint32_t fSvmPauseFilterThreshold : 1;
975 /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
976 uint32_t fSvmAvic : 1;
977 /** SVM: Supports Virtualized VMSAVE/VMLOAD. */
978 uint32_t fSvmVirtVmsaveVmload : 1;
979 /** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
980 uint32_t fSvmVGif : 1;
981 /** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
982 uint32_t fSvmGmet : 1;
983 /** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */
984 uint32_t fSvmSSSCheck : 1;
985 /** SVM: Supports SPEC_CTRL virtualization. */
986 uint32_t fSvmSpecCtrl : 1;
987 /** SVM: Supports HOST_MCE_OVERRIDE. */
988 uint32_t fSvmHostMceOverride : 1;
989 /** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */
990 uint32_t fSvmTlbiCtl : 1;
991 /** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */
992 uint32_t fSvmPadding0 : 14;
993 /** SVM: Maximum supported ASID. */
994 uint32_t uSvmMaxAsid;
995 /** @} */
996
997
998 /** VMX: Maximum physical address width. */
999 uint32_t cVmxMaxPhysAddrWidth : 8;
1000
1001 /** @name VMX basic controls.
1002 * @{ */
1003 /** VMX: Supports INS/OUTS VM-exit instruction info. */
1004 uint32_t fVmxInsOutInfo : 1;
1005 /** @} */
1006
1007 /** @name VMX Pin-based controls.
1008 * @{ */
1009 /** VMX: Supports external interrupt VM-exit. */
1010 uint32_t fVmxExtIntExit : 1;
1011 /** VMX: Supports NMI VM-exit. */
1012 uint32_t fVmxNmiExit : 1;
1013 /** VMX: Supports Virtual NMIs. */
1014 uint32_t fVmxVirtNmi : 1;
1015 /** VMX: Supports preemption timer. */
1016 uint32_t fVmxPreemptTimer : 1;
1017 /** VMX: Supports posted interrupts. */
1018 uint32_t fVmxPostedInt : 1;
1019 /** @} */
1020
1021 /** @name VMX Processor-based controls.
1022 * @{ */
1023 /** VMX: Supports Interrupt-window exiting. */
1024 uint32_t fVmxIntWindowExit : 1;
1025 /** VMX: Supports TSC offsetting. */
1026 uint32_t fVmxTscOffsetting : 1;
1027 /** VMX: Supports HLT exiting. */
1028 uint32_t fVmxHltExit : 1;
1029 /** VMX: Supports INVLPG exiting. */
1030 uint32_t fVmxInvlpgExit : 1;
1031 /** VMX: Supports MWAIT exiting. */
1032 uint32_t fVmxMwaitExit : 1;
1033 /** VMX: Supports RDPMC exiting. */
1034 uint32_t fVmxRdpmcExit : 1;
1035 /** VMX: Supports RDTSC exiting. */
1036 uint32_t fVmxRdtscExit : 1;
1037 /** VMX: Supports CR3-load exiting. */
1038 uint32_t fVmxCr3LoadExit : 1;
1039 /** VMX: Supports CR3-store exiting. */
1040 uint32_t fVmxCr3StoreExit : 1;
1041 /** VMX: Supports tertiary processor-based VM-execution controls. */
1042 uint32_t fVmxTertiaryExecCtls : 1;
1043 /** VMX: Supports CR8-load exiting. */
1044 uint32_t fVmxCr8LoadExit : 1;
1045 /** VMX: Supports CR8-store exiting. */
1046 uint32_t fVmxCr8StoreExit : 1;
1047 /** VMX: Supports TPR shadow. */
1048 uint32_t fVmxUseTprShadow : 1;
1049 /** VMX: Supports NMI-window exiting. */
1050 uint32_t fVmxNmiWindowExit : 1;
1051 /** VMX: Supports Mov-DRx exiting. */
1052 uint32_t fVmxMovDRxExit : 1;
1053 /** VMX: Supports Unconditional I/O exiting. */
1054 uint32_t fVmxUncondIoExit : 1;
1055 /** VMX: Supportgs I/O bitmaps. */
1056 uint32_t fVmxUseIoBitmaps : 1;
1057 /** VMX: Supports Monitor Trap Flag. */
1058 uint32_t fVmxMonitorTrapFlag : 1;
1059 /** VMX: Supports MSR bitmap. */
1060 uint32_t fVmxUseMsrBitmaps : 1;
1061 /** VMX: Supports MONITOR exiting. */
1062 uint32_t fVmxMonitorExit : 1;
1063 /** VMX: Supports PAUSE exiting. */
1064 uint32_t fVmxPauseExit : 1;
1065 /** VMX: Supports secondary processor-based VM-execution controls. */
1066 uint32_t fVmxSecondaryExecCtls : 1;
1067 /** @} */
1068
1069 /** @name VMX Secondary processor-based controls.
1070 * @{ */
1071 /** VMX: Supports virtualize-APIC access. */
1072 uint32_t fVmxVirtApicAccess : 1;
1073 /** VMX: Supports EPT (Extended Page Tables). */
1074 uint32_t fVmxEpt : 1;
1075 /** VMX: Supports descriptor-table exiting. */
1076 uint32_t fVmxDescTableExit : 1;
1077 /** VMX: Supports RDTSCP. */
1078 uint32_t fVmxRdtscp : 1;
1079 /** VMX: Supports virtualize-x2APIC mode. */
1080 uint32_t fVmxVirtX2ApicMode : 1;
1081 /** VMX: Supports VPID. */
1082 uint32_t fVmxVpid : 1;
1083 /** VMX: Supports WBIND exiting. */
1084 uint32_t fVmxWbinvdExit : 1;
1085 /** VMX: Supports Unrestricted guest. */
1086 uint32_t fVmxUnrestrictedGuest : 1;
1087 /** VMX: Supports APIC-register virtualization. */
1088 uint32_t fVmxApicRegVirt : 1;
1089 /** VMX: Supports virtual-interrupt delivery. */
1090 uint32_t fVmxVirtIntDelivery : 1;
1091 /** VMX: Supports Pause-loop exiting. */
1092 uint32_t fVmxPauseLoopExit : 1;
1093 /** VMX: Supports RDRAND exiting. */
1094 uint32_t fVmxRdrandExit : 1;
1095 /** VMX: Supports INVPCID. */
1096 uint32_t fVmxInvpcid : 1;
1097 /** VMX: Supports VM functions. */
1098 uint32_t fVmxVmFunc : 1;
1099 /** VMX: Supports VMCS shadowing. */
1100 uint32_t fVmxVmcsShadowing : 1;
1101 /** VMX: Supports RDSEED exiting. */
1102 uint32_t fVmxRdseedExit : 1;
1103 /** VMX: Supports PML. */
1104 uint32_t fVmxPml : 1;
1105 /** VMX: Supports EPT-violations \#VE. */
1106 uint32_t fVmxEptXcptVe : 1;
1107 /** VMX: Supports conceal VMX from PT. */
1108 uint32_t fVmxConcealVmxFromPt : 1;
1109 /** VMX: Supports XSAVES/XRSTORS. */
1110 uint32_t fVmxXsavesXrstors : 1;
1111 /** VMX: Supports mode-based execute control for EPT. */
1112 uint32_t fVmxModeBasedExecuteEpt : 1;
1113 /** VMX: Supports sub-page write permissions for EPT. */
1114 uint32_t fVmxSppEpt : 1;
1115 /** VMX: Supports Intel PT to output guest-physical addresses for EPT. */
1116 uint32_t fVmxPtEpt : 1;
1117 /** VMX: Supports TSC scaling. */
1118 uint32_t fVmxUseTscScaling : 1;
1119 /** VMX: Supports TPAUSE, UMONITOR, or UMWAIT. */
1120 uint32_t fVmxUserWaitPause : 1;
1121 /** VMX: Supports enclave (ENCLV) exiting. */
1122 uint32_t fVmxEnclvExit : 1;
1123 /** @} */
1124
1125 /** @name VMX Tertiary processor-based controls.
1126 * @{ */
1127 /** VMX: Supports LOADIWKEY exiting. */
1128 uint32_t fVmxLoadIwKeyExit : 1;
1129 /** @} */
1130
1131 /** @name VMX VM-entry controls.
1132 * @{ */
1133 /** VMX: Supports load-debug controls on VM-entry. */
1134 uint32_t fVmxEntryLoadDebugCtls : 1;
1135 /** VMX: Supports IA32e mode guest. */
1136 uint32_t fVmxIa32eModeGuest : 1;
1137 /** VMX: Supports load guest EFER MSR on VM-entry. */
1138 uint32_t fVmxEntryLoadEferMsr : 1;
1139 /** VMX: Supports load guest PAT MSR on VM-entry. */
1140 uint32_t fVmxEntryLoadPatMsr : 1;
1141 /** @} */
1142
1143 /** @name VMX VM-exit controls.
1144 * @{ */
1145 /** VMX: Supports save debug controls on VM-exit. */
1146 uint32_t fVmxExitSaveDebugCtls : 1;
1147 /** VMX: Supports host-address space size. */
1148 uint32_t fVmxHostAddrSpaceSize : 1;
1149 /** VMX: Supports acknowledge external interrupt on VM-exit. */
1150 uint32_t fVmxExitAckExtInt : 1;
1151 /** VMX: Supports save guest PAT MSR on VM-exit. */
1152 uint32_t fVmxExitSavePatMsr : 1;
1153 /** VMX: Supports load hsot PAT MSR on VM-exit. */
1154 uint32_t fVmxExitLoadPatMsr : 1;
1155 /** VMX: Supports save guest EFER MSR on VM-exit. */
1156 uint32_t fVmxExitSaveEferMsr : 1;
1157 /** VMX: Supports load host EFER MSR on VM-exit. */
1158 uint32_t fVmxExitLoadEferMsr : 1;
1159 /** VMX: Supports save VMX preemption timer on VM-exit. */
1160 uint32_t fVmxSavePreemptTimer : 1;
1161 /** VMX: Supports secondary VM-exit controls. */
1162 uint32_t fVmxSecondaryExitCtls : 1;
1163 /** @} */
1164
1165 /** @name VMX Miscellaneous data.
1166 * @{ */
1167 /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
1168 uint32_t fVmxExitSaveEferLma : 1;
1169 /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
1170 uint32_t fVmxPt : 1;
1171 /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1172 * VMWRITE cannot modify read-only VM-exit information fields. */
1173 uint32_t fVmxVmwriteAll : 1;
1174 /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
1175 * length instructions. */
1176 uint32_t fVmxEntryInjectSoftInt : 1;
1177 /** @} */
1178
1179 /** VMX: Padding / reserved for future features. */
1180 uint32_t fVmxPadding0 : 16;
1181 /** VMX: Padding / reserved for future, making it a total of 128 bits. */
1182 uint32_t fVmxPadding1;
1183} CPUMFEATURES;
1184#ifndef VBOX_FOR_DTRACE_LIB
1185AssertCompileSize(CPUMFEATURES, 48);
1186#endif
1187/** Pointer to a CPU feature structure. */
1188typedef CPUMFEATURES *PCPUMFEATURES;
1189/** Pointer to a const CPU feature structure. */
1190typedef CPUMFEATURES const *PCCPUMFEATURES;
1191
1192/**
1193 * Chameleon wrapper structure for the host CPU features.
1194 *
1195 * This is used for the globally readable g_CpumHostFeatures variable, which is
1196 * initialized once during VMMR0 load for ring-0 and during CPUMR3Init in
1197 * ring-3. To reflect this immutability after load/init, we use this wrapper
1198 * structure to switch it between const and non-const depending on the context.
1199 * Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).
1200 */
1201typedef struct CPUHOSTFEATURES
1202{
1203 CPUMFEATURES
1204#ifndef CPUM_WITH_NONCONST_HOST_FEATURES
1205 const
1206#endif
1207 s;
1208} CPUHOSTFEATURES;
1209/** Pointer to a const host CPU feature structure. */
1210typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
1211
1212/** Host CPU features.
1213 * @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after
1214 * module init. */
1215extern CPUHOSTFEATURES g_CpumHostFeatures;
1216
1217
1218/**
1219 * CPU database entry.
1220 */
1221typedef struct CPUMDBENTRY
1222{
1223 /** The CPU name. */
1224 const char *pszName;
1225 /** The full CPU name. */
1226 const char *pszFullName;
1227 /** The CPU vendor (CPUMCPUVENDOR). */
1228 uint8_t enmVendor;
1229 /** The CPU family. */
1230 uint8_t uFamily;
1231 /** The CPU model. */
1232 uint8_t uModel;
1233 /** The CPU stepping. */
1234 uint8_t uStepping;
1235 /** The microarchitecture. */
1236 CPUMMICROARCH enmMicroarch;
1237 /** Scalable bus frequency used for reporting other frequencies. */
1238 uint64_t uScalableBusFreq;
1239 /** Flags - CPUMDB_F_XXX. */
1240 uint32_t fFlags;
1241 /** The maximum physical address with of the CPU. This should correspond to
1242 * the value in CPUID leaf 0x80000008 when present. */
1243 uint8_t cMaxPhysAddrWidth;
1244 /** The MXCSR mask. */
1245 uint32_t fMxCsrMask;
1246 /** Pointer to an array of CPUID leaves. */
1247 PCCPUMCPUIDLEAF paCpuIdLeaves;
1248 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
1249 uint32_t cCpuIdLeaves;
1250 /** The method used to deal with unknown CPUID leaves. */
1251 CPUMUNKNOWNCPUID enmUnknownCpuId;
1252 /** The default unknown CPUID value. */
1253 CPUMCPUID DefUnknownCpuId;
1254
1255 /** MSR mask. Several microarchitectures ignore the higher bits of ECX in
1256 * the RDMSR and WRMSR instructions. */
1257 uint32_t fMsrMask;
1258
1259 /** The number of ranges in the table pointed to b paMsrRanges. */
1260 uint32_t cMsrRanges;
1261 /** MSR ranges for this CPU. */
1262 PCCPUMMSRRANGE paMsrRanges;
1263} CPUMDBENTRY;
1264/** Pointer to a const CPU database entry. */
1265typedef CPUMDBENTRY const *PCCPUMDBENTRY;
1266
1267/** @name CPUMDB_F_XXX - CPUDBENTRY::fFlags
1268 * @{ */
1269/** Should execute all in IEM.
1270 * @todo Implement this - currently done in Main... */
1271#define CPUMDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
1272/** @} */
1273
1274
1275
1276#ifndef VBOX_FOR_DTRACE_LIB
1277
1278#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
1279VMMDECL(int) CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
1280VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1281#endif
1282
1283VMM_INT_DECL(bool) CPUMAssertGuestRFlagsCookie(PVM pVM, PVMCPU pVCpu);
1284
1285
1286/** @name Guest Register Getters.
1287 * @{ */
1288VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR);
1289VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit);
1290VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden);
1291VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu);
1292VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
1293VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu);
1294VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu);
1295VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu);
1296VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu);
1297VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu);
1298VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue);
1299VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu);
1300VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu);
1301VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu);
1302VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu);
1303VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu);
1304VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu);
1305VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu);
1306VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu);
1307VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu);
1308VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu);
1309VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu);
1310VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu);
1311VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu);
1312VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu);
1313VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu);
1314VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu);
1315VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu);
1316VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu);
1317VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu);
1318VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu);
1319VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu);
1320VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu);
1321VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu);
1322VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1323VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t iLeaf, uint32_t iSubLeaf, int f64BitMode,
1324 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
1325VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu);
1326VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatCtrl(PCVMCPUCC pVCpu);
1327VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu);
1328VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPUCC pVCpu);
1329VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPUCC pVCpu);
1330VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue);
1331VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue);
1332/** @} */
1333
1334/** @name Guest Register Setters.
1335 * @{ */
1336VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1337VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1338VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1339VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1340VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0);
1341VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1342VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1343VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1344VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0);
1345VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1);
1346VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2);
1347VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3);
1348VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1349VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7);
1350VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value);
1351VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue);
1352VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1353VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1354VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1355VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1356VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1357VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1358VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1359VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1360VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1361VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1362VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1363VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1364VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1365VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1366VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1367VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1368VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1369VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1370VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1371VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1372VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
1373VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1374VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue);
1375VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu);
1376VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue);
1377VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu);
1378VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM);
1379VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes);
1380VMM_INT_DECL(void) CPUMGetGuestPaePdpes(PVMCPU pVCpu, PX86PDPE paPaePdpes);
1381/** @} */
1382
1383
1384/** @name Misc Guest Predicate Functions.
1385 * @{ */
1386VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu);
1387VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu);
1388VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu);
1389VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu);
1390VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu);
1391VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu);
1392VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu);
1393VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu);
1394VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu);
1395VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu);
1396/** @} */
1397
1398/** @name Nested Hardware-Virtualization Helpers.
1399 * @{ */
1400VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu);
1401VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu);
1402VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1403VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1404
1405/* SVM helpers. */
1406VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1407VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1408VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx);
1409VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx);
1410VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
1411VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1412 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
1413 PSVMIOIOEXITINFO pIoExitInfo);
1414VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit);
1415
1416/* VMX helpers. */
1417VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField);
1418VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess);
1419VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3);
1420VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc);
1421VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick);
1422VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu);
1423VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr);
1424VMM_INT_DECL(bool) CPUMIsGuestVmxEptPagingEnabled(PCVMCPUCC pVCpu);
1425VMM_INT_DECL(bool) CPUMIsGuestVmxEptPaePagingEnabled(PCVMCPUCC pVCpu);
1426VMM_INT_DECL(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCVMCPUCC pVCpu);
1427/** @} */
1428
1429#if !defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS) || defined(DOXYGEN_RUNNING)
1430/** @name Inlined Guest Getters and predicates Functions.
1431 * @{ */
1432
1433/**
1434 * Gets valid CR0 bits for the guest.
1435 *
1436 * @returns Valid CR0 bits.
1437 */
1438DECLINLINE(uint64_t) CPUMGetGuestCR0ValidMask(void)
1439{
1440 return ( X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
1441 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
1442 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG);
1443}
1444
1445/**
1446 * Tests if the guest is running in real mode or not.
1447 *
1448 * @returns true if in real mode, otherwise false.
1449 * @param pCtx Current CPU context.
1450 */
1451DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCCPUMCTX pCtx)
1452{
1453 return !(pCtx->cr0 & X86_CR0_PE);
1454}
1455
1456/**
1457 * Tests if the guest is running in real or virtual 8086 mode.
1458 *
1459 * @returns @c true if it is, @c false if not.
1460 * @param pCtx Current CPU context.
1461 */
1462DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCCPUMCTX pCtx)
1463{
1464 return !(pCtx->cr0 & X86_CR0_PE)
1465 || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1466}
1467
1468/**
1469 * Tests if the guest is running in virtual 8086 mode.
1470 *
1471 * @returns @c true if it is, @c false if not.
1472 * @param pCtx Current CPU context.
1473 */
1474DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCCPUMCTX pCtx)
1475{
1476 return (pCtx->eflags.Bits.u1VM == 1);
1477}
1478
1479/**
1480 * Tests if the guest is running in paged protected or not.
1481 *
1482 * @returns true if in paged protected mode, otherwise false.
1483 * @param pCtx Current CPU context.
1484 */
1485DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1486{
1487 return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1488}
1489
1490/**
1491 * Tests if the guest is running in long mode or not.
1492 *
1493 * @returns true if in long mode, otherwise false.
1494 * @param pCtx Current CPU context.
1495 */
1496DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCCPUMCTX pCtx)
1497{
1498 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1499}
1500
1501VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1502
1503/**
1504 * Tests if the guest is running in 64 bits mode or not.
1505 *
1506 * @returns true if in 64 bits protected mode, otherwise false.
1507 * @param pCtx Current CPU context.
1508 */
1509DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1510{
1511 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1512 return false;
1513 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1514 return CPUMIsGuestIn64BitCodeSlow(pCtx);
1515 return pCtx->cs.Attr.n.u1Long;
1516}
1517
1518/**
1519 * Tests if the guest has paging enabled or not.
1520 *
1521 * @returns true if paging is enabled, otherwise false.
1522 * @param pCtx Current CPU context.
1523 */
1524DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCCPUMCTX pCtx)
1525{
1526 return !!(pCtx->cr0 & X86_CR0_PG);
1527}
1528
1529/**
1530 * Tests if PAE paging is enabled given the relevant control registers.
1531 *
1532 * @returns @c true if in PAE mode, @c false otherwise.
1533 * @param uCr0 The CR0 value.
1534 * @param uCr4 The CR4 value.
1535 * @param uEferMsr The EFER value.
1536 */
1537DECLINLINE(bool) CPUMIsPaePagingEnabled(uint64_t uCr0, uint64_t uCr4, uint64_t uEferMsr)
1538{
1539 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1540 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1541 return ( (uCr4 & X86_CR4_PAE)
1542 && (uCr0 & X86_CR0_PG)
1543 && !(uEferMsr & MSR_K6_EFER_LMA));
1544}
1545
1546/**
1547 * Tests if the guest is running in PAE mode or not.
1548 *
1549 * @returns @c true if in PAE mode, @c false otherwise.
1550 * @param pCtx Current CPU context.
1551 */
1552DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCCPUMCTX pCtx)
1553{
1554 return CPUMIsPaePagingEnabled(pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
1555}
1556
1557/**
1558 * Tests if the guest has AMD SVM enabled or not.
1559 *
1560 * @returns true if SMV is enabled, otherwise false.
1561 * @param pCtx Current CPU context.
1562 */
1563DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1564{
1565 return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1566}
1567
1568/**
1569 * Tests if the guest has Intel VT-x enabled or not.
1570 *
1571 * @returns true if VMX is enabled, otherwise false.
1572 * @param pCtx Current CPU context.
1573 */
1574DECLINLINE(bool) CPUMIsGuestVmxEnabled(PCCPUMCTX pCtx)
1575{
1576 return RT_BOOL(pCtx->cr4 & X86_CR4_VMXE);
1577}
1578
1579/**
1580 * Returns the guest's global-interrupt (GIF) flag.
1581 *
1582 * @returns true when global-interrupts are enabled, otherwise false.
1583 * @param pCtx Current CPU context.
1584 */
1585DECLINLINE(bool) CPUMGetGuestGif(PCCPUMCTX pCtx)
1586{
1587 return pCtx->hwvirt.fGif;
1588}
1589
1590/**
1591 * Sets the guest's global-interrupt flag (GIF).
1592 *
1593 * @param pCtx Current CPU context.
1594 * @param fGif The value to set.
1595 */
1596DECLINLINE(void) CPUMSetGuestGif(PCPUMCTX pCtx, bool fGif)
1597{
1598 pCtx->hwvirt.fGif = fGif;
1599}
1600
1601/**
1602 * Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS.
1603 *
1604 * This also inhibit NMIs, except perhaps for nested guests.
1605 *
1606 * @returns true if interrupts are inhibited by interrupt shadow, false if not.
1607 * @param pCtx Current guest CPU context.
1608 * @note Requires pCtx->rip to be up to date.
1609 * @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1610 * differs from CPUMCTX::rip.
1611 */
1612DECLINLINE(bool) CPUMIsInInterruptShadow(PCCPUMCTX pCtx)
1613{
1614 if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW))
1615 return false;
1616
1617 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1618 return pCtx->uRipInhibitInt == pCtx->rip;
1619}
1620
1621/**
1622 * Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS,
1623 * updating the state if stale.
1624 *
1625 * This also inhibit NMIs, except perhaps for nested guests.
1626 *
1627 * @retval true if interrupts are inhibited by interrupt shadow.
1628 * @retval false if not.
1629 * @param pCtx Current guest CPU context.
1630 * @note Requires pCtx->rip to be up to date.
1631 */
1632DECLINLINE(bool) CPUMIsInInterruptShadowWithUpdate(PCPUMCTX pCtx)
1633{
1634 if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW))
1635 return false;
1636
1637 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1638 if (pCtx->uRipInhibitInt == pCtx->rip)
1639 return true;
1640
1641 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1642 return false;
1643}
1644
1645/**
1646 * Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS,
1647 * updating the state if stale while also returning the reason for the interrupt
1648 * inhibition.
1649 *
1650 * This also inhibit NMIs, except perhaps for nested guests.
1651 *
1652 * @retval true if interrupts are inhibited by interrupt shadow.
1653 * @retval false if not.
1654 * @param pCtx Current guest CPU context.
1655 * @param pfInhibitShw Where to store which type of interrupt inhibition was
1656 * active (see CPUMCTX_INHIBIT_XXX).
1657 * @note Requires pCtx->rip to be up to date.
1658 */
1659DECLINLINE(bool) CPUMIsInInterruptShadowWithUpdateEx(PCPUMCTX pCtx, uint32_t *pfInhibitShw)
1660{
1661 Assert(pfInhibitShw);
1662 *pfInhibitShw = pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW;
1663 return CPUMIsInInterruptShadowWithUpdate(pCtx);
1664}
1665
1666/**
1667 * Checks if we're in an "interrupt shadow" due to a POP SS or MOV SS
1668 * instruction.
1669 *
1670 * This also inhibit NMIs, except perhaps for nested guests.
1671 *
1672 * @retval true if interrupts are inhibited due to POP/MOV SS.
1673 * @retval false if not.
1674 * @param pCtx Current guest CPU context.
1675 * @note Requires pCtx->rip to be up to date.
1676 * @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1677 * differs from CPUMCTX::rip.
1678 * @note Both CPUMIsInInterruptShadowAfterSti() and this function may return
1679 * true depending on the execution engine being used.
1680 */
1681DECLINLINE(bool) CPUMIsInInterruptShadowAfterSs(PCCPUMCTX pCtx)
1682{
1683 if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW_SS))
1684 return false;
1685
1686 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1687 return pCtx->uRipInhibitInt == pCtx->rip;
1688}
1689
1690/**
1691 * Checks if we're in an "interrupt shadow" due to an STI instruction.
1692 *
1693 * This also inhibit NMIs, except perhaps for nested guests.
1694 *
1695 * @retval true if interrupts are inhibited due to STI.
1696 * @retval false if not.
1697 * @param pCtx Current guest CPU context.
1698 * @note Requires pCtx->rip to be up to date.
1699 * @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1700 * differs from CPUMCTX::rip.
1701 * @note Both CPUMIsInInterruptShadowAfterSs() and this function may return
1702 * true depending on the execution engine being used.
1703 */
1704DECLINLINE(bool) CPUMIsInInterruptShadowAfterSti(PCCPUMCTX pCtx)
1705{
1706 if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW_STI))
1707 return false;
1708
1709 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1710 return pCtx->uRipInhibitInt == pCtx->rip;
1711}
1712
1713/**
1714 * Sets the "interrupt shadow" flag, after a STI, POP SS or MOV SS instruction.
1715 *
1716 * @param pCtx Current guest CPU context.
1717 * @note Requires pCtx->rip to be up to date.
1718 */
1719DECLINLINE(void) CPUMSetInInterruptShadow(PCPUMCTX pCtx)
1720{
1721 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1722 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW;
1723 pCtx->uRipInhibitInt = pCtx->rip;
1724}
1725
1726/**
1727 * Sets the "interrupt shadow" flag, after a STI, POP SS or MOV SS instruction,
1728 * extended version.
1729 *
1730 * @param pCtx Current guest CPU context.
1731 * @param rip The RIP for which it is inhibited.
1732 */
1733DECLINLINE(void) CPUMSetInInterruptShadowEx(PCPUMCTX pCtx, uint64_t rip)
1734{
1735 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW;
1736 pCtx->uRipInhibitInt = rip;
1737}
1738
1739/**
1740 * Sets the "interrupt shadow" flag after a POP SS or MOV SS instruction.
1741 *
1742 * @param pCtx Current guest CPU context.
1743 * @note Requires pCtx->rip to be up to date.
1744 */
1745DECLINLINE(void) CPUMSetInInterruptShadowSs(PCPUMCTX pCtx)
1746{
1747 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1748 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW_SS;
1749 pCtx->uRipInhibitInt = pCtx->rip;
1750}
1751
1752/**
1753 * Sets the "interrupt shadow" flag after an STI instruction.
1754 *
1755 * @param pCtx Current guest CPU context.
1756 * @note Requires pCtx->rip to be up to date.
1757 */
1758DECLINLINE(void) CPUMSetInInterruptShadowSti(PCPUMCTX pCtx)
1759{
1760 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1761 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW_STI;
1762 pCtx->uRipInhibitInt = pCtx->rip;
1763}
1764
1765/**
1766 * Clears the "interrupt shadow" flag.
1767 *
1768 * @param pCtx Current guest CPU context.
1769 */
1770DECLINLINE(void) CPUMClearInterruptShadow(PCPUMCTX pCtx)
1771{
1772 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1773}
1774
1775/**
1776 * Update the "interrupt shadow" flag.
1777 *
1778 * @param pCtx Current guest CPU context.
1779 * @param fInhibited The new state.
1780 * @note Requires pCtx->rip to be up to date.
1781 */
1782DECLINLINE(void) CPUMUpdateInterruptShadow(PCPUMCTX pCtx, bool fInhibited)
1783{
1784 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1785 if (!fInhibited)
1786 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1787 else
1788 {
1789 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW;
1790 pCtx->uRipInhibitInt = pCtx->rip;
1791 }
1792}
1793
1794/**
1795 * Update the "interrupt shadow" flag, extended version.
1796 *
1797 * @returns fInhibited.
1798 * @param pCtx Current guest CPU context.
1799 * @param fInhibited The new state.
1800 * @param rip The RIP for which it is inhibited.
1801 */
1802DECLINLINE(bool) CPUMUpdateInterruptShadowEx(PCPUMCTX pCtx, bool fInhibited, uint64_t rip)
1803{
1804 if (!fInhibited)
1805 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1806 else
1807 {
1808 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW;
1809 pCtx->uRipInhibitInt = rip;
1810 }
1811 return fInhibited;
1812}
1813
1814/**
1815 * Update the two "interrupt shadow" flags separately, extended version.
1816 *
1817 * @param pCtx Current guest CPU context.
1818 * @param fInhibitedBySs The new state for the MOV SS & POP SS aspect.
1819 * @param fInhibitedBySti The new state for the STI aspect.
1820 * @param rip The RIP for which it is inhibited.
1821 */
1822DECLINLINE(void) CPUMUpdateInterruptShadowSsStiEx(PCPUMCTX pCtx, bool fInhibitedBySs, bool fInhibitedBySti, uint64_t rip)
1823{
1824 if (!(fInhibitedBySs | fInhibitedBySti))
1825 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1826 else
1827 {
1828 pCtx->eflags.uBoth |= (fInhibitedBySs ? CPUMCTX_INHIBIT_SHADOW_SS : UINT32_C(0))
1829 | (fInhibitedBySti ? CPUMCTX_INHIBIT_SHADOW_STI : UINT32_C(0));
1830 pCtx->uRipInhibitInt = rip;
1831 }
1832}
1833
1834/* VMX forward declarations used by extended function versions: */
1835DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx);
1836DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls);
1837DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx);
1838DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking);
1839
1840/**
1841 * Checks whether interrupts, include NMIs, are inhibited by pending NMI
1842 * delivery.
1843 *
1844 * This only checks the inhibit mask.
1845 *
1846 * @retval true if interrupts are inhibited by NMI handling.
1847 * @retval false if interrupts are not inhibited by NMI handling.
1848 * @param pCtx Current guest CPU context.
1849 */
1850DECLINLINE(bool) CPUMAreInterruptsInhibitedByNmi(PCCPUMCTX pCtx)
1851{
1852 return (pCtx->eflags.uBoth & CPUMCTX_INHIBIT_NMI) != 0;
1853}
1854
1855/**
1856 * Extended version of CPUMAreInterruptsInhibitedByNmi() that takes VMX non-root
1857 * mode into account when check whether interrupts are inhibited by NMI.
1858 *
1859 * @retval true if interrupts are inhibited by NMI handling.
1860 * @retval false if interrupts are not inhibited by NMI handling.
1861 * @param pCtx Current guest CPU context.
1862 */
1863DECLINLINE(bool) CPUMAreInterruptsInhibitedByNmiEx(PCCPUMCTX pCtx)
1864{
1865 /* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
1866 if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1867 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1868 return CPUMAreInterruptsInhibitedByNmi(pCtx);
1869 return CPUMIsGuestVmxVirtNmiBlocking(pCtx);
1870}
1871
1872/**
1873 * Marks interrupts, include NMIs, as inhibited by pending NMI delivery.
1874 *
1875 * @param pCtx Current guest CPU context.
1876 */
1877DECLINLINE(void) CPUMSetInterruptInhibitingByNmi(PCPUMCTX pCtx)
1878{
1879 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_NMI;
1880}
1881
1882/**
1883 * Extended version of CPUMSetInterruptInhibitingByNmi() that takes VMX non-root
1884 * mode into account when marking interrupts as inhibited by NMI.
1885 *
1886 * @param pCtx Current guest CPU context.
1887 */
1888DECLINLINE(void) CPUMSetInterruptInhibitingByNmiEx(PCPUMCTX pCtx)
1889{
1890 /* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
1891 if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1892 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1893 CPUMSetInterruptInhibitingByNmi(pCtx);
1894 else
1895 CPUMSetGuestVmxVirtNmiBlocking(pCtx, true);
1896}
1897
1898/**
1899 * Marks interrupts, include NMIs, as no longer inhibited by pending NMI
1900 * delivery.
1901 *
1902 * @param pCtx Current guest CPU context.
1903 */
1904DECLINLINE(void) CPUMClearInterruptInhibitingByNmi(PCPUMCTX pCtx)
1905{
1906 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_NMI;
1907}
1908
1909/**
1910 * Extended version of CPUMClearInterruptInhibitingByNmi() that takes VMX
1911 * non-root mode into account when doing the updating.
1912 *
1913 * @param pCtx Current guest CPU context.
1914 */
1915DECLINLINE(void) CPUMClearInterruptInhibitingByNmiEx(PCPUMCTX pCtx)
1916{
1917 /* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
1918 if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1919 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1920 CPUMClearInterruptInhibitingByNmi(pCtx);
1921 else
1922 CPUMSetGuestVmxVirtNmiBlocking(pCtx, false);
1923}
1924
1925/**
1926 * Update whether interrupts, include NMIs, are inhibited by pending NMI
1927 * delivery.
1928 *
1929 * @param pCtx Current guest CPU context.
1930 * @param fInhibited The new state.
1931 */
1932DECLINLINE(void) CPUMUpdateInterruptInhibitingByNmi(PCPUMCTX pCtx, bool fInhibited)
1933{
1934 if (!fInhibited)
1935 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_NMI;
1936 else
1937 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_NMI;
1938}
1939
1940/**
1941 * Extended version of CPUMUpdateInterruptInhibitingByNmi() that takes VMX
1942 * non-root mode into account when doing the updating.
1943 *
1944 * @param pCtx Current guest CPU context.
1945 * @param fInhibited The new state.
1946 */
1947DECLINLINE(void) CPUMUpdateInterruptInhibitingByNmiEx(PCPUMCTX pCtx, bool fInhibited)
1948{
1949 /*
1950 * Set the state of guest-NMI blocking in any of the following cases:
1951 * - We're not executing a nested-guest.
1952 * - We're executing an SVM nested-guest[1].
1953 * - We're executing a VMX nested-guest without virtual-NMIs enabled.
1954 *
1955 * [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
1956 * SVM hypervisors must track NMI blocking themselves by intercepting
1957 * the IRET instruction after injection of an NMI.
1958 */
1959 if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1960 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1961 CPUMUpdateInterruptInhibitingByNmi(pCtx, fInhibited);
1962 /*
1963 * Set the state of virtual-NMI blocking, if we are executing a
1964 * VMX nested-guest with virtual-NMIs enabled.
1965 */
1966 else
1967 CPUMSetGuestVmxVirtNmiBlocking(pCtx, fInhibited);
1968}
1969
1970
1971/**
1972 * Checks if we are executing inside an SVM nested hardware-virtualized guest.
1973 *
1974 * @returns @c true if in SVM nested-guest mode, @c false otherwise.
1975 * @param pCtx Current CPU context.
1976 */
1977DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
1978{
1979 /*
1980 * With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
1981 * See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
1982 */
1983#ifndef IN_RC
1984 if ( pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM
1985 || !(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN))
1986 return false;
1987 return true;
1988#else
1989 NOREF(pCtx);
1990 return false;
1991#endif
1992}
1993
1994/**
1995 * Checks if the guest is in VMX non-root operation.
1996 *
1997 * @returns @c true if in VMX non-root operation, @c false otherwise.
1998 * @param pCtx Current CPU context.
1999 */
2000DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx)
2001{
2002#ifndef IN_RC
2003 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
2004 return false;
2005 Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
2006 return pCtx->hwvirt.vmx.fInVmxNonRootMode;
2007#else
2008 NOREF(pCtx);
2009 return false;
2010#endif
2011}
2012
2013/**
2014 * Checks if we are executing inside an SVM or VMX nested hardware-virtualized
2015 * guest.
2016 *
2017 * @returns @c true if in nested-guest mode, @c false otherwise.
2018 * @param pCtx Current CPU context.
2019 */
2020DECLINLINE(bool) CPUMIsGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
2021{
2022#if 0
2023 return CPUMIsGuestInVmxNonRootMode(pCtx) || CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
2024#else
2025 if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
2026 return false;
2027 if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
2028 {
2029 Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
2030 return pCtx->hwvirt.vmx.fInVmxNonRootMode;
2031 }
2032 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2033 return RT_BOOL(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN);
2034#endif
2035}
2036
2037/**
2038 * Checks if we are executing inside an SVM or VMX nested hardware-virtualized
2039 * guest.
2040 *
2041 * @retval CPUMHWVIRT_NONE if not in SVM or VMX non-root mode.
2042 * @retval CPUMHWVIRT_VMX if in VMX non-root mode.
2043 * @retval CPUMHWVIRT_SVM if in SVM non-root mode.
2044 * @param pCtx Current CPU context.
2045 */
2046DECLINLINE(CPUMHWVIRT) CPUMGetGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
2047{
2048 if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
2049 return CPUMHWVIRT_NONE;
2050 if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
2051 {
2052 Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
2053 return pCtx->hwvirt.vmx.fInVmxNonRootMode ? CPUMHWVIRT_VMX : CPUMHWVIRT_NONE;
2054 }
2055 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2056 return pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN ? CPUMHWVIRT_SVM : CPUMHWVIRT_NONE;
2057}
2058
2059/**
2060 * Checks if the guest is in VMX root operation.
2061 *
2062 * @returns @c true if in VMX root operation, @c false otherwise.
2063 * @param pCtx Current CPU context.
2064 */
2065DECLINLINE(bool) CPUMIsGuestInVmxRootMode(PCCPUMCTX pCtx)
2066{
2067#ifndef IN_RC
2068 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
2069 return false;
2070 return pCtx->hwvirt.vmx.fInVmxRootMode;
2071#else
2072 NOREF(pCtx);
2073 return false;
2074#endif
2075}
2076
2077# ifndef IN_RC
2078
2079/**
2080 * Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
2081 * active.
2082 *
2083 * @returns @c true if in intercept is set, @c false otherwise.
2084 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2085 * @param pCtx Current CPU context.
2086 * @param fIntercept The SVM control/instruction intercept, see
2087 * SVM_CTRL_INTERCEPT_*.
2088 */
2089DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint64_t fIntercept)
2090{
2091 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2092 return false;
2093 uint64_t u64Intercepts;
2094 if (!HMGetGuestSvmCtrlIntercepts(pVCpu, &u64Intercepts))
2095 u64Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl;
2096 return RT_BOOL(u64Intercepts & fIntercept);
2097}
2098
2099/**
2100 * Checks if the nested-guest VMCB has the specified CR read intercept active.
2101 *
2102 * @returns @c true if in intercept is set, @c false otherwise.
2103 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2104 * @param pCtx Current CPU context.
2105 * @param uCr The CR register number (0 to 15).
2106 */
2107DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
2108{
2109 Assert(uCr < 16);
2110 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2111 return false;
2112 uint16_t u16Intercepts;
2113 if (!HMGetGuestSvmReadCRxIntercepts(pVCpu, &u16Intercepts))
2114 u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdCRx;
2115 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
2116}
2117
2118/**
2119 * Checks if the nested-guest VMCB has the specified CR write intercept active.
2120 *
2121 * @returns @c true if in intercept is set, @c false otherwise.
2122 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2123 * @param pCtx Current CPU context.
2124 * @param uCr The CR register number (0 to 15).
2125 */
2126DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
2127{
2128 Assert(uCr < 16);
2129 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2130 return false;
2131 uint16_t u16Intercepts;
2132 if (!HMGetGuestSvmWriteCRxIntercepts(pVCpu, &u16Intercepts))
2133 u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrCRx;
2134 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
2135}
2136
2137/**
2138 * Checks if the nested-guest VMCB has the specified DR read intercept active.
2139 *
2140 * @returns @c true if in intercept is set, @c false otherwise.
2141 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2142 * @param pCtx Current CPU context.
2143 * @param uDr The DR register number (0 to 15).
2144 */
2145DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
2146{
2147 Assert(uDr < 16);
2148 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2149 return false;
2150 uint16_t u16Intercepts;
2151 if (!HMGetGuestSvmReadDRxIntercepts(pVCpu, &u16Intercepts))
2152 u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdDRx;
2153 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
2154}
2155
2156/**
2157 * Checks if the nested-guest VMCB has the specified DR write intercept active.
2158 *
2159 * @returns @c true if in intercept is set, @c false otherwise.
2160 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2161 * @param pCtx Current CPU context.
2162 * @param uDr The DR register number (0 to 15).
2163 */
2164DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
2165{
2166 Assert(uDr < 16);
2167 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2168 return false;
2169 uint16_t u16Intercepts;
2170 if (!HMGetGuestSvmWriteDRxIntercepts(pVCpu, &u16Intercepts))
2171 u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrDRx;
2172 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
2173}
2174
2175/**
2176 * Checks if the nested-guest VMCB has the specified exception intercept active.
2177 *
2178 * @returns @c true if in intercept is active, @c false otherwise.
2179 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2180 * @param pCtx Current CPU context.
2181 * @param uVector The exception / interrupt vector.
2182 */
2183DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
2184{
2185 Assert(uVector <= X86_XCPT_LAST);
2186 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2187 return false;
2188 uint32_t u32Intercepts;
2189 if (!HMGetGuestSvmXcptIntercepts(pVCpu, &u32Intercepts))
2190 u32Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u32InterceptXcpt;
2191 return RT_BOOL(u32Intercepts & RT_BIT(uVector));
2192}
2193
2194/**
2195 * Checks if the nested-guest VMCB has virtual-interrupt masking enabled.
2196 *
2197 * @returns @c true if virtual-interrupts are masked, @c false otherwise.
2198 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2199 * @param pCtx Current CPU context.
2200 *
2201 * @remarks Should only be called when SVM feature is exposed to the guest.
2202 */
2203DECLINLINE(bool) CPUMIsGuestSvmVirtIntrMasking(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2204{
2205 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2206 return false;
2207 bool fVIntrMasking;
2208 if (!HMGetGuestSvmVirtIntrMasking(pVCpu, &fVIntrMasking))
2209 fVIntrMasking = pCtx->hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u1VIntrMasking;
2210 return fVIntrMasking;
2211}
2212
2213/**
2214 * Checks if the nested-guest VMCB has nested-paging enabled.
2215 *
2216 * @returns @c true if nested-paging is enabled, @c false otherwise.
2217 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2218 * @param pCtx Current CPU context.
2219 *
2220 * @remarks Should only be called when SVM feature is exposed to the guest.
2221 */
2222DECLINLINE(bool) CPUMIsGuestSvmNestedPagingEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2223{
2224 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2225 return false;
2226 bool fNestedPaging;
2227 if (!HMGetGuestSvmNestedPaging(pVCpu, &fNestedPaging))
2228 fNestedPaging = pCtx->hwvirt.svm.Vmcb.ctrl.NestedPagingCtrl.n.u1NestedPaging;
2229 return fNestedPaging;
2230}
2231
2232/**
2233 * Gets the nested-guest VMCB pause-filter count.
2234 *
2235 * @returns The pause-filter count.
2236 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2237 * @param pCtx Current CPU context.
2238 *
2239 * @remarks Should only be called when SVM feature is exposed to the guest.
2240 */
2241DECLINLINE(uint16_t) CPUMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2242{
2243 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2244 return false;
2245 uint16_t u16PauseFilterCount;
2246 if (!HMGetGuestSvmPauseFilterCount(pVCpu, &u16PauseFilterCount))
2247 u16PauseFilterCount = pCtx->hwvirt.svm.Vmcb.ctrl.u16PauseFilterCount;
2248 return u16PauseFilterCount;
2249}
2250
2251/**
2252 * Updates the NextRIP (NRIP) field in the nested-guest VMCB.
2253 *
2254 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2255 * @param pCtx Current CPU context.
2256 * @param cbInstr The length of the current instruction in bytes.
2257 *
2258 * @remarks Should only be called when SVM feature is exposed to the guest.
2259 */
2260DECLINLINE(void) CPUMGuestSvmUpdateNRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbInstr)
2261{
2262 RT_NOREF(pVCpu);
2263 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2264 pCtx->hwvirt.svm.Vmcb.ctrl.u64NextRIP = pCtx->rip + cbInstr;
2265}
2266
2267/**
2268 * Checks whether one of the given Pin-based VM-execution controls are set when
2269 * executing a nested-guest.
2270 *
2271 * @returns @c true if set, @c false otherwise.
2272 * @param pCtx Current CPU context.
2273 * @param uPinCtls The Pin-based VM-execution controls to check.
2274 *
2275 * @remarks This does not check if all given controls are set if more than one
2276 * control is passed in @a uPinCtl.
2277 */
2278DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls)
2279{
2280 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2281 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & uPinCtls);
2282}
2283
2284/**
2285 * Checks whether one of the given Processor-based VM-execution controls are set
2286 * when executing a nested-guest.
2287 *
2288 * @returns @c true if set, @c false otherwise.
2289 * @param pCtx Current CPU context.
2290 * @param uProcCtls The Processor-based VM-execution controls to check.
2291 *
2292 * @remarks This does not check if all given controls are set if more than one
2293 * control is passed in @a uProcCtls.
2294 */
2295DECLINLINE(bool) CPUMIsGuestVmxProcCtlsSet(PCCPUMCTX pCtx, uint32_t uProcCtls)
2296{
2297 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2298 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls & uProcCtls);
2299}
2300
2301/**
2302 * Checks whether one of the given Secondary Processor-based VM-execution controls
2303 * are set when executing a nested-guest.
2304 *
2305 * @returns @c true if set, @c false otherwise.
2306 * @param pCtx Current CPU context.
2307 * @param uProcCtls2 The Secondary Processor-based VM-execution controls to
2308 * check.
2309 *
2310 * @remarks This does not check if all given controls are set if more than one
2311 * control is passed in @a uProcCtls2.
2312 */
2313DECLINLINE(bool) CPUMIsGuestVmxProcCtls2Set(PCCPUMCTX pCtx, uint32_t uProcCtls2)
2314{
2315 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2316 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls2 & uProcCtls2);
2317}
2318
2319/**
2320 * Checks whether one of the given Tertiary Processor-based VM-execution controls
2321 * are set when executing a nested-guest.
2322 *
2323 * @returns @c true if set, @c false otherwise.
2324 * @param pCtx Current CPU context.
2325 * @param uProcCtls3 The Tertiary Processor-based VM-execution controls to
2326 * check.
2327 *
2328 * @remarks This does not check if all given controls are set if more than one
2329 * control is passed in @a uProcCtls3.
2330 */
2331DECLINLINE(bool) CPUMIsGuestVmxProcCtls3Set(PCCPUMCTX pCtx, uint64_t uProcCtls3)
2332{
2333 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2334 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u64ProcCtls3.u & uProcCtls3);
2335}
2336
2337/**
2338 * Checks whether one of the given VM-exit controls are set when executing a
2339 * nested-guest.
2340 *
2341 * @returns @c true if set, @c false otherwise.
2342 * @param pCtx Current CPU context.
2343 * @param uExitCtls The VM-exit controls to check.
2344 *
2345 * @remarks This does not check if all given controls are set if more than one
2346 * control is passed in @a uExitCtls.
2347 */
2348DECLINLINE(bool) CPUMIsGuestVmxExitCtlsSet(PCCPUMCTX pCtx, uint32_t uExitCtls)
2349{
2350 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2351 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ExitCtls & uExitCtls);
2352}
2353
2354/**
2355 * Checks whether one of the given VM-entry controls are set when executing a
2356 * nested-guest.
2357 *
2358 * @returns @c true if set, @c false otherwise.
2359 * @param pCtx Current CPU context.
2360 * @param uEntryCtls The VM-entry controls to check.
2361 *
2362 * @remarks This does not check if all given controls are set if more than one
2363 * control is passed in @a uEntryCtls.
2364 */
2365DECLINLINE(bool) CPUMIsGuestVmxEntryCtlsSet(PCCPUMCTX pCtx, uint32_t uEntryCtls)
2366{
2367 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2368 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32EntryCtls & uEntryCtls);
2369}
2370
2371/**
2372 * Checks whether events injected in the nested-guest are subject to VM-exit checks.
2373 *
2374 * @returns @c true if set, @c false otherwise.
2375 * @param pCtx Current CPU context.
2376 */
2377DECLINLINE(bool) CPUMIsGuestVmxInterceptEvents(PCCPUMCTX pCtx)
2378{
2379 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2380 return pCtx->hwvirt.vmx.fInterceptEvents;
2381}
2382
2383/**
2384 * Sets whether events injected in the nested-guest are subject to VM-exit checks.
2385 *
2386 * @param pCtx Current CPU context.
2387 * @param fIntercept Whether to subject injected events to VM-exits or not.
2388 */
2389DECLINLINE(void) CPUMSetGuestVmxInterceptEvents(PCPUMCTX pCtx, bool fInterceptEvents)
2390{
2391 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2392 pCtx->hwvirt.vmx.fInterceptEvents = fInterceptEvents;
2393}
2394
2395/**
2396 * Checks whether the given exception causes a VM-exit.
2397 *
2398 * The exception type include hardware exceptions, software exceptions (#BP, #OF)
2399 * and privileged software exceptions (#DB generated by INT1/ICEBP).
2400 *
2401 * Software interrupts do -not- cause VM-exits and hence must not be used with this
2402 * function.
2403 *
2404 * @returns @c true if the exception causes a VM-exit, @c false otherwise.
2405 * @param pCtx Current CPU context.
2406 * @param uVector The exception vector.
2407 * @param uErrCode The error code associated with the exception. Pass 0 if not
2408 * applicable.
2409 */
2410DECLINLINE(bool) CPUMIsGuestVmxXcptInterceptSet(PCCPUMCTX pCtx, uint8_t uVector, uint32_t uErrCode)
2411{
2412 Assert(uVector <= X86_XCPT_LAST);
2413
2414 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2415
2416 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
2417 if (uVector == X86_XCPT_NMI)
2418 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
2419
2420 /* Page-faults are subject to masking using its error code. */
2421 uint32_t fXcptBitmap = pCtx->hwvirt.vmx.Vmcs.u32XcptBitmap;
2422 if (uVector == X86_XCPT_PF)
2423 {
2424 uint32_t const fXcptPFMask = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMask;
2425 uint32_t const fXcptPFMatch = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMatch;
2426 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
2427 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
2428 }
2429
2430 /* Consult the exception bitmap for all other exceptions. */
2431 if (fXcptBitmap & RT_BIT(uVector))
2432 return true;
2433 return false;
2434}
2435
2436
2437/**
2438 * Checks whether the guest is in VMX non-root mode and using EPT paging.
2439 *
2440 * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
2441 * @param pCtx Current CPU context.
2442 */
2443DECLINLINE(bool) CPUMIsGuestVmxEptPagingEnabledEx(PCCPUMCTX pCtx)
2444{
2445 return CPUMIsGuestInVmxNonRootMode(pCtx)
2446 && CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_EPT);
2447}
2448
2449
2450/**
2451 * Implements VMSucceed for VMX instruction success.
2452 *
2453 * @param pCtx Current CPU context.
2454 */
2455DECLINLINE(void) CPUMSetGuestVmxVmSucceed(PCPUMCTX pCtx)
2456{
2457 pCtx->eflags.uBoth &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2458}
2459
2460/**
2461 * Implements VMFailInvalid for VMX instruction failure.
2462 *
2463 * @param pCtx Current CPU context.
2464 */
2465DECLINLINE(void) CPUMSetGuestVmxVmFailInvalid(PCPUMCTX pCtx)
2466{
2467 pCtx->eflags.uBoth &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2468 pCtx->eflags.uBoth |= X86_EFL_CF;
2469}
2470
2471/**
2472 * Implements VMFailValid for VMX instruction failure.
2473 *
2474 * @param pCtx Current CPU context.
2475 * @param enmInsErr The VM instruction error.
2476 */
2477DECLINLINE(void) CPUMSetGuestVmxVmFailValid(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2478{
2479 pCtx->eflags.uBoth &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2480 pCtx->eflags.uBoth |= X86_EFL_ZF;
2481 pCtx->hwvirt.vmx.Vmcs.u32RoVmInstrError = enmInsErr;
2482}
2483
2484/**
2485 * Implements VMFail for VMX instruction failure.
2486 *
2487 * @param pCtx Current CPU context.
2488 * @param enmInsErr The VM instruction error.
2489 */
2490DECLINLINE(void) CPUMSetGuestVmxVmFail(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2491{
2492 if (pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS)
2493 CPUMSetGuestVmxVmFailValid(pCtx, enmInsErr);
2494 else
2495 CPUMSetGuestVmxVmFailInvalid(pCtx);
2496}
2497
2498/**
2499 * Returns the guest-physical address of the APIC-access page when executing a
2500 * nested-guest.
2501 *
2502 * @returns The APIC-access page guest-physical address.
2503 * @param pCtx Current CPU context.
2504 */
2505DECLINLINE(uint64_t) CPUMGetGuestVmxApicAccessPageAddrEx(PCCPUMCTX pCtx)
2506{
2507 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2508 return pCtx->hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
2509}
2510
2511/**
2512 * Gets the nested-guest CR0 subject to the guest/host mask and the read-shadow.
2513 *
2514 * @returns The nested-guest CR0.
2515 * @param pCtx Current CPU context.
2516 * @param fGstHostMask The CR0 guest/host mask to use.
2517 */
2518DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr0(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2519{
2520 /*
2521 * For each CR0 bit owned by the host, the corresponding bit from the
2522 * CR0 read shadow is loaded. For each CR0 bit that is not owned by the host,
2523 * the corresponding bit from the guest CR0 is loaded.
2524 *
2525 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2526 */
2527 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2528 uint64_t const uGstCr0 = pCtx->cr0;
2529 uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2530 return (fReadShadow & fGstHostMask) | (uGstCr0 & ~fGstHostMask);
2531}
2532
2533/**
2534 * Gets the nested-guest CR4 subject to the guest/host mask and the read-shadow.
2535 *
2536 * @returns The nested-guest CR4.
2537 * @param pCtx Current CPU context.
2538 * @param fGstHostMask The CR4 guest/host mask to use.
2539 */
2540DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr4(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2541{
2542 /*
2543 * For each CR4 bit owned by the host, the corresponding bit from the
2544 * CR4 read shadow is loaded. For each CR4 bit that is not owned by the host,
2545 * the corresponding bit from the guest CR4 is loaded.
2546 *
2547 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2548 */
2549 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2550 uint64_t const uGstCr4 = pCtx->cr4;
2551 uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2552 return (fReadShadow & fGstHostMask) | (uGstCr4 & ~fGstHostMask);
2553}
2554
2555/**
2556 * Checks whether the LMSW access causes a VM-exit or not.
2557 *
2558 * @returns @c true if the LMSW access causes a VM-exit, @c false otherwise.
2559 * @param pCtx Current CPU context.
2560 * @param uNewMsw The LMSW source operand (the Machine Status Word).
2561 */
2562DECLINLINE(bool) CPUMIsGuestVmxLmswInterceptSet(PCCPUMCTX pCtx, uint16_t uNewMsw)
2563{
2564 /*
2565 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
2566 *
2567 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
2568 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2569 */
2570 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2571
2572 uint32_t const fGstHostMask = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2573 uint32_t const fReadShadow = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2574
2575 /*
2576 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
2577 * CR0.PE case first, before the rest of the bits in the MSW.
2578 *
2579 * If CR0.PE is owned by the host and CR0.PE differs between the
2580 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
2581 */
2582 if ( (fGstHostMask & X86_CR0_PE)
2583 && (uNewMsw & X86_CR0_PE)
2584 && !(fReadShadow & X86_CR0_PE))
2585 return true;
2586
2587 /*
2588 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
2589 * bits differ between the MSW (source operand) and the read-shadow, we must
2590 * cause a VM-exit.
2591 */
2592 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2593 if ((fReadShadow & fGstHostLmswMask) != (uNewMsw & fGstHostLmswMask))
2594 return true;
2595
2596 return false;
2597}
2598
2599/**
2600 * Checks whether the Mov-to-CR0/CR4 access causes a VM-exit or not.
2601 *
2602 * @returns @c true if the Mov CRX access causes a VM-exit, @c false otherwise.
2603 * @param pCtx Current CPU context.
2604 * @param iCrReg The control register number (must be 0 or 4).
2605 * @param uNewCrX The CR0/CR4 value being written.
2606 */
2607DECLINLINE(bool) CPUMIsGuestVmxMovToCr0Cr4InterceptSet(PCCPUMCTX pCtx, uint8_t iCrReg, uint64_t uNewCrX)
2608{
2609 /*
2610 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
2611 * corresponding bits differ between the source operand and the read-shadow,
2612 * we must cause a VM-exit.
2613 *
2614 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2615 */
2616 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2617 Assert(iCrReg == 0 || iCrReg == 4);
2618
2619 uint64_t fGstHostMask;
2620 uint64_t fReadShadow;
2621 if (iCrReg == 0)
2622 {
2623 fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2624 fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2625 }
2626 else
2627 {
2628 fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2629 fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2630 }
2631
2632 if ((fReadShadow & fGstHostMask) != (uNewCrX & fGstHostMask))
2633 {
2634 Assert(fGstHostMask != 0);
2635 return true;
2636 }
2637
2638 return false;
2639}
2640
2641/**
2642 * Returns whether the guest has an active, current VMCS.
2643 *
2644 * @returns @c true if the guest has an active, current VMCS, @c false otherwise.
2645 * @param pCtx Current CPU context.
2646 */
2647DECLINLINE(bool) CPUMIsGuestVmxCurrentVmcsValid(PCCPUMCTX pCtx)
2648{
2649 return pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS;
2650}
2651
2652# endif /* !IN_RC */
2653
2654/**
2655 * Checks whether the VMX nested-guest is in a state to receive physical (APIC)
2656 * interrupts.
2657 *
2658 * @returns @c true if it's ready, @c false otherwise.
2659 * @param pCtx The guest-CPU context.
2660 */
2661DECLINLINE(bool) CPUMIsGuestVmxPhysIntrEnabled(PCCPUMCTX pCtx)
2662{
2663#ifdef IN_RC
2664 AssertReleaseFailedReturn(false);
2665#else
2666 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2667 if (CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_EXT_INT_EXIT))
2668 return true;
2669 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RFLAGS);
2670 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2671#endif
2672}
2673
2674/**
2675 * Checks whether the VMX nested-guest is blocking virtual-NMIs.
2676 *
2677 * @returns @c true if it's blocked, @c false otherwise.
2678 * @param pCtx The guest-CPU context.
2679 */
2680DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx)
2681{
2682#ifdef IN_RC
2683 RT_NOREF(pCtx);
2684 AssertReleaseFailedReturn(false);
2685#else
2686 /*
2687 * Return the state of virtual-NMI blocking, if we are executing a
2688 * VMX nested-guest with virtual-NMIs enabled.
2689 */
2690 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2691 Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2692 return pCtx->hwvirt.vmx.fVirtNmiBlocking;
2693#endif
2694}
2695
2696/**
2697 * Sets or clears VMX nested-guest virtual-NMI blocking.
2698 *
2699 * @param pCtx The guest-CPU context.
2700 * @param fBlocking Whether virtual-NMI blocking is in effect or not.
2701 */
2702DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking)
2703{
2704#ifdef IN_RC
2705 RT_NOREF2(pCtx, fBlocking);
2706 AssertReleaseFailedReturnVoid();
2707#else
2708 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2709 Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2710 pCtx->hwvirt.vmx.fVirtNmiBlocking = fBlocking;
2711#endif
2712}
2713
2714/**
2715 * Checks whether the VMX nested-guest is in a state to receive virtual interrupts
2716 * (those injected with the "virtual-interrupt delivery" feature).
2717 *
2718 * @returns @c true if it's ready, @c false otherwise.
2719 * @param pCtx The guest-CPU context.
2720 */
2721DECLINLINE(bool) CPUMIsGuestVmxVirtIntrEnabled(PCCPUMCTX pCtx)
2722{
2723#ifdef IN_RC
2724 RT_NOREF2(pCtx);
2725 AssertReleaseFailedReturn(false);
2726#else
2727 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2728 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2729#endif
2730}
2731
2732/** @} */
2733#endif /* !IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS || DOXYGEN_RUNNING */
2734
2735
2736
2737/** @name Hypervisor Register Getters.
2738 * @{ */
2739VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
2740VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
2741VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
2742VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
2743VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
2744VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
2745VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
2746/** @} */
2747
2748/** @name Hypervisor Register Setters.
2749 * @{ */
2750VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
2751VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
2752VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
2753VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
2754VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
2755VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
2756VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
2757VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg);
2758/** @} */
2759
2760#ifdef VBOX_INCLUDED_vmm_cpumctx_h
2761VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
2762#endif
2763
2764/** @name Changed flags.
2765 * These flags are used to keep track of which important register that
2766 * have been changed since last they were reset. The only one allowed
2767 * to clear them is REM!
2768 *
2769 * @todo This is obsolete, but remains as it will be refactored for coordinating
2770 * IEM and NEM/HM later. Probably.
2771 * @{
2772 */
2773#define CPUM_CHANGED_FPU_REM RT_BIT(0)
2774#define CPUM_CHANGED_CR0 RT_BIT(1)
2775#define CPUM_CHANGED_CR4 RT_BIT(2)
2776#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
2777#define CPUM_CHANGED_CR3 RT_BIT(4)
2778#define CPUM_CHANGED_GDTR RT_BIT(5)
2779#define CPUM_CHANGED_IDTR RT_BIT(6)
2780#define CPUM_CHANGED_LDTR RT_BIT(7)
2781#define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */
2782#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
2783#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */
2784#define CPUM_CHANGED_CPUID RT_BIT(11)
2785#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
2786 | CPUM_CHANGED_CR0 \
2787 | CPUM_CHANGED_CR4 \
2788 | CPUM_CHANGED_GLOBAL_TLB_FLUSH \
2789 | CPUM_CHANGED_CR3 \
2790 | CPUM_CHANGED_GDTR \
2791 | CPUM_CHANGED_IDTR \
2792 | CPUM_CHANGED_LDTR \
2793 | CPUM_CHANGED_TR \
2794 | CPUM_CHANGED_SYSENTER_MSR \
2795 | CPUM_CHANGED_HIDDEN_SEL_REGS \
2796 | CPUM_CHANGED_CPUID )
2797/** @} */
2798
2799VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
2800VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
2801VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
2802VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
2803VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
2804VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
2805VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
2806VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
2807VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
2808VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
2809VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
2810VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
2811VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM);
2812VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
2813 uint64_t *puValidEfer);
2814VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
2815VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue);
2816
2817
2818/** Guest CPU interruptibility level, see CPUMGetGuestInterruptibility(). */
2819typedef enum CPUMINTERRUPTIBILITY
2820{
2821 CPUMINTERRUPTIBILITY_INVALID = 0,
2822 CPUMINTERRUPTIBILITY_UNRESTRAINED,
2823 CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED,
2824 CPUMINTERRUPTIBILITY_INT_DISABLED,
2825 CPUMINTERRUPTIBILITY_INT_INHIBITED, /**< @todo rename as it inhibits NMIs too. */
2826 CPUMINTERRUPTIBILITY_NMI_INHIBIT,
2827 CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT,
2828 CPUMINTERRUPTIBILITY_END,
2829 CPUMINTERRUPTIBILITY_32BIT_HACK = 0x7fffffff
2830} CPUMINTERRUPTIBILITY;
2831
2832VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu);
2833
2834/** @name Typical scalable bus frequency values.
2835 * @{ */
2836/** Special internal value indicating that we don't know the frequency.
2837 * @internal */
2838#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
2839#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
2840#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
2841#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
2842#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
2843#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
2844#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
2845#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
2846/** @} */
2847
2848
2849#ifdef IN_RING3
2850/** @defgroup grp_cpum_r3 The CPUM ring-3 API
2851 * @{
2852 */
2853
2854VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
2855
2856VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
2857VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
2858VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves);
2859VMMDECL(CPUMMICROARCH) CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
2860 uint8_t bModel, uint8_t bStepping);
2861VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
2862VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
2863VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
2864#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2865VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
2866#endif
2867
2868VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
2869
2870VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu);
2871VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu);
2872/** @} */
2873#endif /* IN_RING3 */
2874
2875#ifdef IN_RING0
2876/** @defgroup grp_cpum_r0 The CPUM ring-0 API
2877 * @{
2878 */
2879VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
2880VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
2881VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM);
2882VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM);
2883DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPUCC pVCpu);
2884DECLASM(void) CPUMR0TouchHostFpu(void);
2885VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu);
2886VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu);
2887VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu);
2888VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVMCC pVM, PVMCPUCC pVCpu);
2889VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6);
2890VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6);
2891
2892VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6);
2893VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6);
2894/** @} */
2895#endif /* IN_RING0 */
2896
2897/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
2898 * @{
2899 */
2900VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPUCC pVCpu);
2901VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPUCC pVCpu);
2902VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPUCC pVCpu);
2903VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPUCC pVCpu);
2904VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPUCC pVCpu);
2905/** @} */
2906
2907
2908#endif /* !VBOX_FOR_DTRACE_LIB */
2909/** @} */
2910RT_C_DECLS_END
2911
2912
2913#endif /* !VBOX_INCLUDED_vmm_cpum_x86_amd64_h */
2914
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