cpum-x86-amd64.h@ 99260

Last change on this file since 99260 was 99260, checked in by vboxsync, 20 months ago
VMM/CPUM: Nested VMX: bugref:10318 Added CPUMIsInInterruptShadowWithUpdateEx for upcoming change.
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpum_x86_amd64_h
37	#define VBOX_INCLUDED_vmm_cpum_x86_amd64_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <iprt/x86.h>
43	#include <VBox/vmm/hm_svm.h>
44	#include <VBox/vmm/hm_vmx.h>
45
46	RT_C_DECLS_BEGIN
47
48	/** @defgroup grp_cpum The CPU Monitor / Manager API
49	* @ingroup grp_vmm
50	* @{
51	*/
52
53	/**
54	* CPUID feature to set or clear.
55	*/
56	typedef enum CPUMCPUIDFEATURE
57	{
58	CPUMCPUIDFEATURE_INVALID = 0,
59	/** The APIC feature bit. (Std+Ext)
60	* Note! There is a per-cpu flag for masking this CPUID feature bit when the
61	* APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
62	* at VM construction time like all the others. This didn't used to be
63	* that way, this is new with 5.1. */
64	CPUMCPUIDFEATURE_APIC,
65	/** The sysenter/sysexit feature bit. (Std) */
66	CPUMCPUIDFEATURE_SEP,
67	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
68	CPUMCPUIDFEATURE_SYSCALL,
69	/** The PAE feature bit. (Std+Ext) */
70	CPUMCPUIDFEATURE_PAE,
71	/** The NX feature bit. (Ext) */
72	CPUMCPUIDFEATURE_NX,
73	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
74	CPUMCPUIDFEATURE_LAHF,
75	/** The LONG MODE feature bit. (Ext) */
76	CPUMCPUIDFEATURE_LONG_MODE,
77	/** The x2APIC feature bit. (Std) */
78	CPUMCPUIDFEATURE_X2APIC,
79	/** The RDTSCP feature bit. (Ext) */
80	CPUMCPUIDFEATURE_RDTSCP,
81	/** The Hypervisor Present bit. (Std) */
82	CPUMCPUIDFEATURE_HVP,
83	/** The speculation control feature bits. (StExt) */
84	CPUMCPUIDFEATURE_SPEC_CTRL,
85	/** 32bit hackishness. */
86	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
87	} CPUMCPUIDFEATURE;
88
89
90	/**
91	* CPUID leaf.
92	*
93	* @remarks This structure is used by the patch manager and is therefore
94	* more or less set in stone.
95	*/
96	typedef struct CPUMCPUIDLEAF
97	{
98	/** The leaf number. */
99	uint32_t uLeaf;
100	/** The sub-leaf number. */
101	uint32_t uSubLeaf;
102	/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
103	uint32_t fSubLeafMask;
104
105	/** The EAX value. */
106	uint32_t uEax;
107	/** The EBX value. */
108	uint32_t uEbx;
109	/** The ECX value. */
110	uint32_t uEcx;
111	/** The EDX value. */
112	uint32_t uEdx;
113
114	/** Flags. */
115	uint32_t fFlags;
116	} CPUMCPUIDLEAF;
117	#ifndef VBOX_FOR_DTRACE_LIB
118	AssertCompileSize(CPUMCPUIDLEAF, 32);
119	#endif
120	/** Pointer to a CPUID leaf. */
121	typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
122	/** Pointer to a const CPUID leaf. */
123	typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
124
125	/** @name CPUMCPUIDLEAF::fFlags
126	* @{ */
127	/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
128	* and EDX containing the extended APIC ID. */
129	#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
130	/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
131	#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
132	/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
133	#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
134	/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
135	#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
136	/** Mask of the valid flags. */
137	#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
138	/** @} */
139
140	/**
141	* Method used to deal with unknown CPUID leaves.
142	* @remarks Used in patch code.
143	*/
144	typedef enum CPUMUNKNOWNCPUID
145	{
146	/** Invalid zero value. */
147	CPUMUNKNOWNCPUID_INVALID = 0,
148	/** Use given default values (DefCpuId). */
149	CPUMUNKNOWNCPUID_DEFAULTS,
150	/** Return the last standard leaf.
151	* Intel Sandy Bridge has been observed doing this. */
152	CPUMUNKNOWNCPUID_LAST_STD_LEAF,
153	/** Return the last standard leaf, with ecx observed.
154	* Intel Sandy Bridge has been observed doing this. */
155	CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
156	/** The register values are passed thru unmodified. */
157	CPUMUNKNOWNCPUID_PASSTHRU,
158	/** End of valid value. */
159	CPUMUNKNOWNCPUID_END,
160	/** Ensure 32-bit type. */
161	CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
162	} CPUMUNKNOWNCPUID;
163	/** Pointer to unknown CPUID leaf method. */
164	typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
165
166
167	/**
168	* The register set returned by a CPUID operation.
169	*/
170	typedef struct CPUMCPUID
171	{
172	uint32_t uEax;
173	uint32_t uEbx;
174	uint32_t uEcx;
175	uint32_t uEdx;
176	} CPUMCPUID;
177	/** Pointer to a CPUID leaf. */
178	typedef CPUMCPUID *PCPUMCPUID;
179	/** Pointer to a const CPUID leaf. */
180	typedef const CPUMCPUID *PCCPUMCPUID;
181
182
183	/**
184	* MSR read functions.
185	*/
186	typedef enum CPUMMSRRDFN
187	{
188	/** Invalid zero value. */
189	kCpumMsrRdFn_Invalid = 0,
190	/** Return the CPUMMSRRANGE::uValue. */
191	kCpumMsrRdFn_FixedValue,
192	/** Alias to the MSR range starting at the MSR given by
193	* CPUMMSRRANGE::uValue. Must be used in pair with
194	* kCpumMsrWrFn_MsrAlias. */
195	kCpumMsrRdFn_MsrAlias,
196	/** Write only register, GP all read attempts. */
197	kCpumMsrRdFn_WriteOnly,
198
199	kCpumMsrRdFn_Ia32P5McAddr,
200	kCpumMsrRdFn_Ia32P5McType,
201	kCpumMsrRdFn_Ia32TimestampCounter,
202	kCpumMsrRdFn_Ia32PlatformId, /*< Takes real CPU value for reference. /
203	kCpumMsrRdFn_Ia32ApicBase,
204	kCpumMsrRdFn_Ia32FeatureControl,
205	kCpumMsrRdFn_Ia32BiosSignId, /*< Range value returned. /
206	kCpumMsrRdFn_Ia32SmmMonitorCtl,
207	kCpumMsrRdFn_Ia32PmcN,
208	kCpumMsrRdFn_Ia32MonitorFilterLineSize,
209	kCpumMsrRdFn_Ia32MPerf,
210	kCpumMsrRdFn_Ia32APerf,
211	kCpumMsrRdFn_Ia32MtrrCap, /*< Takes real CPU value for reference. /
212	kCpumMsrRdFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
213	kCpumMsrRdFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
214	kCpumMsrRdFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
215	kCpumMsrRdFn_Ia32MtrrDefType,
216	kCpumMsrRdFn_Ia32Pat,
217	kCpumMsrRdFn_Ia32SysEnterCs,
218	kCpumMsrRdFn_Ia32SysEnterEsp,
219	kCpumMsrRdFn_Ia32SysEnterEip,
220	kCpumMsrRdFn_Ia32McgCap,
221	kCpumMsrRdFn_Ia32McgStatus,
222	kCpumMsrRdFn_Ia32McgCtl,
223	kCpumMsrRdFn_Ia32DebugCtl,
224	kCpumMsrRdFn_Ia32SmrrPhysBase,
225	kCpumMsrRdFn_Ia32SmrrPhysMask,
226	kCpumMsrRdFn_Ia32PlatformDcaCap,
227	kCpumMsrRdFn_Ia32CpuDcaCap,
228	kCpumMsrRdFn_Ia32Dca0Cap,
229	kCpumMsrRdFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
230	kCpumMsrRdFn_Ia32PerfStatus, /*< Range value returned. /
231	kCpumMsrRdFn_Ia32PerfCtl, /*< Range value returned. /
232	kCpumMsrRdFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
233	kCpumMsrRdFn_Ia32PerfCapabilities, /*< Takes reference value. /
234	kCpumMsrRdFn_Ia32FixedCtrCtrl,
235	kCpumMsrRdFn_Ia32PerfGlobalStatus, /*< Takes reference value. /
236	kCpumMsrRdFn_Ia32PerfGlobalCtrl,
237	kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
238	kCpumMsrRdFn_Ia32PebsEnable,
239	kCpumMsrRdFn_Ia32ClockModulation, /*< Range value returned. /
240	kCpumMsrRdFn_Ia32ThermInterrupt, /*< Range value returned. /
241	kCpumMsrRdFn_Ia32ThermStatus, /*< Range value returned. /
242	kCpumMsrRdFn_Ia32Therm2Ctl, /*< Range value returned. /
243	kCpumMsrRdFn_Ia32MiscEnable, /*< Range value returned. /
244	kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
245	kCpumMsrRdFn_Ia32McNCtl2, /*< Takes register number of start of range. /
246	kCpumMsrRdFn_Ia32DsArea,
247	kCpumMsrRdFn_Ia32TscDeadline,
248	kCpumMsrRdFn_Ia32X2ApicN,
249	kCpumMsrRdFn_Ia32DebugInterface,
250	kCpumMsrRdFn_Ia32VmxBasic, /*< Takes real value as reference. /
251	kCpumMsrRdFn_Ia32VmxPinbasedCtls, /*< Takes real value as reference. /
252	kCpumMsrRdFn_Ia32VmxProcbasedCtls, /*< Takes real value as reference. /
253	kCpumMsrRdFn_Ia32VmxExitCtls, /*< Takes real value as reference. /
254	kCpumMsrRdFn_Ia32VmxEntryCtls, /*< Takes real value as reference. /
255	kCpumMsrRdFn_Ia32VmxMisc, /*< Takes real value as reference. /
256	kCpumMsrRdFn_Ia32VmxCr0Fixed0, /*< Takes real value as reference. /
257	kCpumMsrRdFn_Ia32VmxCr0Fixed1, /*< Takes real value as reference. /
258	kCpumMsrRdFn_Ia32VmxCr4Fixed0, /*< Takes real value as reference. /
259	kCpumMsrRdFn_Ia32VmxCr4Fixed1, /*< Takes real value as reference. /
260	kCpumMsrRdFn_Ia32VmxVmcsEnum, /*< Takes real value as reference. /
261	kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /*< Takes real value as reference. /
262	kCpumMsrRdFn_Ia32VmxEptVpidCap, /*< Takes real value as reference. /
263	kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /*< Takes real value as reference. /
264	kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /*< Takes real value as reference. /
265	kCpumMsrRdFn_Ia32VmxTrueExitCtls, /*< Takes real value as reference. /
266	kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /*< Takes real value as reference. /
267	kCpumMsrRdFn_Ia32VmxVmFunc, /*< Takes real value as reference. /
268	kCpumMsrRdFn_Ia32SpecCtrl,
269	kCpumMsrRdFn_Ia32ArchCapabilities,
270
271	kCpumMsrRdFn_Amd64Efer,
272	kCpumMsrRdFn_Amd64SyscallTarget,
273	kCpumMsrRdFn_Amd64LongSyscallTarget,
274	kCpumMsrRdFn_Amd64CompSyscallTarget,
275	kCpumMsrRdFn_Amd64SyscallFlagMask,
276	kCpumMsrRdFn_Amd64FsBase,
277	kCpumMsrRdFn_Amd64GsBase,
278	kCpumMsrRdFn_Amd64KernelGsBase,
279	kCpumMsrRdFn_Amd64TscAux,
280
281	kCpumMsrRdFn_IntelEblCrPowerOn,
282	kCpumMsrRdFn_IntelI7CoreThreadCount,
283	kCpumMsrRdFn_IntelP4EbcHardPowerOn,
284	kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
285	kCpumMsrRdFn_IntelP4EbcFrequencyId,
286	kCpumMsrRdFn_IntelP6FsbFrequency, /*< Takes real value as reference. /
287	kCpumMsrRdFn_IntelPlatformInfo,
288	kCpumMsrRdFn_IntelFlexRatio, /*< Takes real value as reference. /
289	kCpumMsrRdFn_IntelPkgCStConfigControl,
290	kCpumMsrRdFn_IntelPmgIoCaptureBase,
291	kCpumMsrRdFn_IntelLastBranchFromToN,
292	kCpumMsrRdFn_IntelLastBranchFromN,
293	kCpumMsrRdFn_IntelLastBranchToN,
294	kCpumMsrRdFn_IntelLastBranchTos,
295	kCpumMsrRdFn_IntelBblCrCtl,
296	kCpumMsrRdFn_IntelBblCrCtl3,
297	kCpumMsrRdFn_IntelI7TemperatureTarget, /*< Range value returned. /
298	kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/*< Takes register number. /
299	kCpumMsrRdFn_IntelI7MiscPwrMgmt,
300	kCpumMsrRdFn_IntelP6CrN,
301	kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
302	kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
303	kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
304	kCpumMsrRdFn_IntelI7SandyAesNiCtl,
305	kCpumMsrRdFn_IntelI7TurboRatioLimit, /*< Returns range value. /
306	kCpumMsrRdFn_IntelI7LbrSelect,
307	kCpumMsrRdFn_IntelI7SandyErrorControl,
308	kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/*< Returns range value. /
309	kCpumMsrRdFn_IntelI7PowerCtl,
310	kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
311	kCpumMsrRdFn_IntelI7PebsLdLat,
312	kCpumMsrRdFn_IntelI7PkgCnResidencyN, /*< Takes C-state number. /
313	kCpumMsrRdFn_IntelI7CoreCnResidencyN, /*< Takes C-state number. /
314	kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/*< Takes real value as reference. /
315	kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /*< Takes real value as reference. /
316	kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /*< Takes real value as reference. /
317	kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /*< Takes real value as reference. /
318	kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /*< Takes real value as reference. /
319	kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /*< Takes real value as reference. /
320	kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /*< Takes real value as reference. /
321	kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /*< Takes real value as reference. /
322	kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /*< Takes real value as reference. /
323	kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /*< Takes real value as reference. /
324	kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/*< Takes real value as reference. /
325	kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /*< Takes real value as reference. /
326	kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /*< Takes real value as reference. /
327	kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /*< Takes real value as reference. /
328	kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /*< Takes real value as reference. /
329	kCpumMsrRdFn_IntelI7RaplPp0Policy, /*< Takes real value as reference. /
330	kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /*< Takes real value as reference. /
331	kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /*< Takes real value as reference. /
332	kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /*< Takes real value as reference. /
333	kCpumMsrRdFn_IntelI7RaplPp1Policy, /*< Takes real value as reference. /
334	kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /*< Takes real value as reference. /
335	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /*< Takes real value as reference. /
336	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /*< Takes real value as reference. /
337	kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
338	kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
339	kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
340	kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
341	kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
342	kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
343	kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
344	kCpumMsrRdFn_IntelI7UncCBoxConfig,
345	kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
346	kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
347	kCpumMsrRdFn_IntelI7SmiCount,
348	kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /*< Range value returned. /
349	kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
350	kCpumMsrRdFn_IntelCore1ExtConfig,
351	kCpumMsrRdFn_IntelCore1DtsCalControl,
352	kCpumMsrRdFn_IntelCore2PeciControl,
353	kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
354
355	kCpumMsrRdFn_P6LastBranchFromIp,
356	kCpumMsrRdFn_P6LastBranchToIp,
357	kCpumMsrRdFn_P6LastIntFromIp,
358	kCpumMsrRdFn_P6LastIntToIp,
359
360	kCpumMsrRdFn_AmdFam15hTscRate,
361	kCpumMsrRdFn_AmdFam15hLwpCfg,
362	kCpumMsrRdFn_AmdFam15hLwpCbAddr,
363	kCpumMsrRdFn_AmdFam10hMc4MiscN,
364	kCpumMsrRdFn_AmdK8PerfCtlN,
365	kCpumMsrRdFn_AmdK8PerfCtrN,
366	kCpumMsrRdFn_AmdK8SysCfg, /*< Range value returned. /
367	kCpumMsrRdFn_AmdK8HwCr,
368	kCpumMsrRdFn_AmdK8IorrBaseN,
369	kCpumMsrRdFn_AmdK8IorrMaskN,
370	kCpumMsrRdFn_AmdK8TopOfMemN,
371	kCpumMsrRdFn_AmdK8NbCfg1,
372	kCpumMsrRdFn_AmdK8McXcptRedir,
373	kCpumMsrRdFn_AmdK8CpuNameN,
374	kCpumMsrRdFn_AmdK8HwThermalCtrl, /*< Range value returned. /
375	kCpumMsrRdFn_AmdK8SwThermalCtrl,
376	kCpumMsrRdFn_AmdK8FidVidControl, /*< Range value returned. /
377	kCpumMsrRdFn_AmdK8FidVidStatus, /*< Range value returned. /
378	kCpumMsrRdFn_AmdK8McCtlMaskN,
379	kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
380	kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
381	kCpumMsrRdFn_AmdK8IntPendingMessage,
382	kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
383	kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
384	kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
385	kCpumMsrRdFn_AmdFam10hPStateCurLimit, /*< Returns range value. /
386	kCpumMsrRdFn_AmdFam10hPStateControl, /*< Returns range value. /
387	kCpumMsrRdFn_AmdFam10hPStateStatus, /*< Returns range value. /
388	kCpumMsrRdFn_AmdFam10hPStateN, /*< Returns range value. This isn't an register index! /
389	kCpumMsrRdFn_AmdFam10hCofVidControl, /*< Returns range value. /
390	kCpumMsrRdFn_AmdFam10hCofVidStatus, /*< Returns range value. /
391	kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
392	kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
393	kCpumMsrRdFn_AmdK8SmmBase,
394	kCpumMsrRdFn_AmdK8SmmAddr,
395	kCpumMsrRdFn_AmdK8SmmMask,
396	kCpumMsrRdFn_AmdK8VmCr,
397	kCpumMsrRdFn_AmdK8IgnNe,
398	kCpumMsrRdFn_AmdK8SmmCtl,
399	kCpumMsrRdFn_AmdK8VmHSavePa,
400	kCpumMsrRdFn_AmdFam10hVmLockKey,
401	kCpumMsrRdFn_AmdFam10hSmmLockKey,
402	kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
403	kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
404	kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
405	kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
406	kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
407	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
408	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
409	kCpumMsrRdFn_AmdK7MicrocodeCtl, /*< Returns range value. /
410	kCpumMsrRdFn_AmdK7ClusterIdMaybe, /*< Returns range value. /
411	kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
412	kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
413	kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
414	kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
415	kCpumMsrRdFn_AmdK8PatchLevel, /*< Returns range value. /
416	kCpumMsrRdFn_AmdK7DebugStatusMaybe,
417	kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
418	kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
419	kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
420	kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
421	kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
422	kCpumMsrRdFn_AmdK7NodeId,
423	kCpumMsrRdFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
424	kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
425	kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
426	kCpumMsrRdFn_AmdK7LoadStoreCfg,
427	kCpumMsrRdFn_AmdK7InstrCacheCfg,
428	kCpumMsrRdFn_AmdK7DataCacheCfg,
429	kCpumMsrRdFn_AmdK7BusUnitCfg,
430	kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
431	kCpumMsrRdFn_AmdFam15hFpuCfg,
432	kCpumMsrRdFn_AmdFam15hDecoderCfg,
433	kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
434	kCpumMsrRdFn_AmdFam15hCombUnitCfg,
435	kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
436	kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
437	kCpumMsrRdFn_AmdFam15hExecUnitCfg,
438	kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
439	kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
440	kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
441	kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
442	kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
443	kCpumMsrRdFn_AmdFam10hIbsOpRip,
444	kCpumMsrRdFn_AmdFam10hIbsOpData,
445	kCpumMsrRdFn_AmdFam10hIbsOpData2,
446	kCpumMsrRdFn_AmdFam10hIbsOpData3,
447	kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
448	kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
449	kCpumMsrRdFn_AmdFam10hIbsCtl,
450	kCpumMsrRdFn_AmdFam14hIbsBrTarget,
451
452	kCpumMsrRdFn_Gim,
453
454	/** End of valid MSR read function indexes. */
455	kCpumMsrRdFn_End
456	} CPUMMSRRDFN;
457
458	/**
459	* MSR write functions.
460	*/
461	typedef enum CPUMMSRWRFN
462	{
463	/** Invalid zero value. */
464	kCpumMsrWrFn_Invalid = 0,
465	/** Writes are ignored, the fWrGpMask is observed though. */
466	kCpumMsrWrFn_IgnoreWrite,
467	/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
468	kCpumMsrWrFn_ReadOnly,
469	/** Alias to the MSR range starting at the MSR given by
470	* CPUMMSRRANGE::uValue. Must be used in pair with
471	* kCpumMsrRdFn_MsrAlias. */
472	kCpumMsrWrFn_MsrAlias,
473
474	kCpumMsrWrFn_Ia32P5McAddr,
475	kCpumMsrWrFn_Ia32P5McType,
476	kCpumMsrWrFn_Ia32TimestampCounter,
477	kCpumMsrWrFn_Ia32ApicBase,
478	kCpumMsrWrFn_Ia32FeatureControl,
479	kCpumMsrWrFn_Ia32BiosSignId,
480	kCpumMsrWrFn_Ia32BiosUpdateTrigger,
481	kCpumMsrWrFn_Ia32SmmMonitorCtl,
482	kCpumMsrWrFn_Ia32PmcN,
483	kCpumMsrWrFn_Ia32MonitorFilterLineSize,
484	kCpumMsrWrFn_Ia32MPerf,
485	kCpumMsrWrFn_Ia32APerf,
486	kCpumMsrWrFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
487	kCpumMsrWrFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
488	kCpumMsrWrFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
489	kCpumMsrWrFn_Ia32MtrrDefType,
490	kCpumMsrWrFn_Ia32Pat,
491	kCpumMsrWrFn_Ia32SysEnterCs,
492	kCpumMsrWrFn_Ia32SysEnterEsp,
493	kCpumMsrWrFn_Ia32SysEnterEip,
494	kCpumMsrWrFn_Ia32McgStatus,
495	kCpumMsrWrFn_Ia32McgCtl,
496	kCpumMsrWrFn_Ia32DebugCtl,
497	kCpumMsrWrFn_Ia32SmrrPhysBase,
498	kCpumMsrWrFn_Ia32SmrrPhysMask,
499	kCpumMsrWrFn_Ia32PlatformDcaCap,
500	kCpumMsrWrFn_Ia32Dca0Cap,
501	kCpumMsrWrFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
502	kCpumMsrWrFn_Ia32PerfStatus,
503	kCpumMsrWrFn_Ia32PerfCtl,
504	kCpumMsrWrFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
505	kCpumMsrWrFn_Ia32PerfCapabilities,
506	kCpumMsrWrFn_Ia32FixedCtrCtrl,
507	kCpumMsrWrFn_Ia32PerfGlobalStatus,
508	kCpumMsrWrFn_Ia32PerfGlobalCtrl,
509	kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
510	kCpumMsrWrFn_Ia32PebsEnable,
511	kCpumMsrWrFn_Ia32ClockModulation,
512	kCpumMsrWrFn_Ia32ThermInterrupt,
513	kCpumMsrWrFn_Ia32ThermStatus,
514	kCpumMsrWrFn_Ia32Therm2Ctl,
515	kCpumMsrWrFn_Ia32MiscEnable,
516	kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
517	kCpumMsrWrFn_Ia32McNCtl2, /*< Takes register number of start of range. /
518	kCpumMsrWrFn_Ia32DsArea,
519	kCpumMsrWrFn_Ia32TscDeadline,
520	kCpumMsrWrFn_Ia32X2ApicN,
521	kCpumMsrWrFn_Ia32DebugInterface,
522	kCpumMsrWrFn_Ia32SpecCtrl,
523	kCpumMsrWrFn_Ia32PredCmd,
524	kCpumMsrWrFn_Ia32FlushCmd,
525
526	kCpumMsrWrFn_Amd64Efer,
527	kCpumMsrWrFn_Amd64SyscallTarget,
528	kCpumMsrWrFn_Amd64LongSyscallTarget,
529	kCpumMsrWrFn_Amd64CompSyscallTarget,
530	kCpumMsrWrFn_Amd64SyscallFlagMask,
531	kCpumMsrWrFn_Amd64FsBase,
532	kCpumMsrWrFn_Amd64GsBase,
533	kCpumMsrWrFn_Amd64KernelGsBase,
534	kCpumMsrWrFn_Amd64TscAux,
535	kCpumMsrWrFn_IntelEblCrPowerOn,
536	kCpumMsrWrFn_IntelP4EbcHardPowerOn,
537	kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
538	kCpumMsrWrFn_IntelP4EbcFrequencyId,
539	kCpumMsrWrFn_IntelFlexRatio,
540	kCpumMsrWrFn_IntelPkgCStConfigControl,
541	kCpumMsrWrFn_IntelPmgIoCaptureBase,
542	kCpumMsrWrFn_IntelLastBranchFromToN,
543	kCpumMsrWrFn_IntelLastBranchFromN,
544	kCpumMsrWrFn_IntelLastBranchToN,
545	kCpumMsrWrFn_IntelLastBranchTos,
546	kCpumMsrWrFn_IntelBblCrCtl,
547	kCpumMsrWrFn_IntelBblCrCtl3,
548	kCpumMsrWrFn_IntelI7TemperatureTarget,
549	kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /*< Takes register number. /
550	kCpumMsrWrFn_IntelI7MiscPwrMgmt,
551	kCpumMsrWrFn_IntelP6CrN,
552	kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
553	kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
554	kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
555	kCpumMsrWrFn_IntelI7SandyAesNiCtl,
556	kCpumMsrWrFn_IntelI7TurboRatioLimit,
557	kCpumMsrWrFn_IntelI7LbrSelect,
558	kCpumMsrWrFn_IntelI7SandyErrorControl,
559	kCpumMsrWrFn_IntelI7PowerCtl,
560	kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
561	kCpumMsrWrFn_IntelI7PebsLdLat,
562	kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
563	kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
564	kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /*< R/O but found writable bits on a Silvermont CPU here. /
565	kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
566	kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /*< R/O but found writable bits on a Silvermont CPU here. /
567	kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
568	kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
569	kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
570	kCpumMsrWrFn_IntelI7RaplPp0Policy,
571	kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
572	kCpumMsrWrFn_IntelI7RaplPp1Policy,
573	kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
574	kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
575	kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
576	kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
577	kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
578	kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
579	kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
580	kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
581	kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
582	kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
583	kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
584	kCpumMsrWrFn_IntelCore1ExtConfig,
585	kCpumMsrWrFn_IntelCore1DtsCalControl,
586	kCpumMsrWrFn_IntelCore2PeciControl,
587
588	kCpumMsrWrFn_P6LastIntFromIp,
589	kCpumMsrWrFn_P6LastIntToIp,
590
591	kCpumMsrWrFn_AmdFam15hTscRate,
592	kCpumMsrWrFn_AmdFam15hLwpCfg,
593	kCpumMsrWrFn_AmdFam15hLwpCbAddr,
594	kCpumMsrWrFn_AmdFam10hMc4MiscN,
595	kCpumMsrWrFn_AmdK8PerfCtlN,
596	kCpumMsrWrFn_AmdK8PerfCtrN,
597	kCpumMsrWrFn_AmdK8SysCfg,
598	kCpumMsrWrFn_AmdK8HwCr,
599	kCpumMsrWrFn_AmdK8IorrBaseN,
600	kCpumMsrWrFn_AmdK8IorrMaskN,
601	kCpumMsrWrFn_AmdK8TopOfMemN,
602	kCpumMsrWrFn_AmdK8NbCfg1,
603	kCpumMsrWrFn_AmdK8McXcptRedir,
604	kCpumMsrWrFn_AmdK8CpuNameN,
605	kCpumMsrWrFn_AmdK8HwThermalCtrl,
606	kCpumMsrWrFn_AmdK8SwThermalCtrl,
607	kCpumMsrWrFn_AmdK8FidVidControl,
608	kCpumMsrWrFn_AmdK8McCtlMaskN,
609	kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
610	kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
611	kCpumMsrWrFn_AmdK8IntPendingMessage,
612	kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
613	kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
614	kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
615	kCpumMsrWrFn_AmdFam10hPStateControl,
616	kCpumMsrWrFn_AmdFam10hPStateStatus,
617	kCpumMsrWrFn_AmdFam10hPStateN,
618	kCpumMsrWrFn_AmdFam10hCofVidControl,
619	kCpumMsrWrFn_AmdFam10hCofVidStatus,
620	kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
621	kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
622	kCpumMsrWrFn_AmdK8SmmBase,
623	kCpumMsrWrFn_AmdK8SmmAddr,
624	kCpumMsrWrFn_AmdK8SmmMask,
625	kCpumMsrWrFn_AmdK8VmCr,
626	kCpumMsrWrFn_AmdK8IgnNe,
627	kCpumMsrWrFn_AmdK8SmmCtl,
628	kCpumMsrWrFn_AmdK8VmHSavePa,
629	kCpumMsrWrFn_AmdFam10hVmLockKey,
630	kCpumMsrWrFn_AmdFam10hSmmLockKey,
631	kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
632	kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
633	kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
634	kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
635	kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
636	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
637	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
638	kCpumMsrWrFn_AmdK7MicrocodeCtl,
639	kCpumMsrWrFn_AmdK7ClusterIdMaybe,
640	kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
641	kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
642	kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
643	kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
644	kCpumMsrWrFn_AmdK8PatchLoader,
645	kCpumMsrWrFn_AmdK7DebugStatusMaybe,
646	kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
647	kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
648	kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
649	kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
650	kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
651	kCpumMsrWrFn_AmdK7NodeId,
652	kCpumMsrWrFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
653	kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
654	kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
655	kCpumMsrWrFn_AmdK7LoadStoreCfg,
656	kCpumMsrWrFn_AmdK7InstrCacheCfg,
657	kCpumMsrWrFn_AmdK7DataCacheCfg,
658	kCpumMsrWrFn_AmdK7BusUnitCfg,
659	kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
660	kCpumMsrWrFn_AmdFam15hFpuCfg,
661	kCpumMsrWrFn_AmdFam15hDecoderCfg,
662	kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
663	kCpumMsrWrFn_AmdFam15hCombUnitCfg,
664	kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
665	kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
666	kCpumMsrWrFn_AmdFam15hExecUnitCfg,
667	kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
668	kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
669	kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
670	kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
671	kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
672	kCpumMsrWrFn_AmdFam10hIbsOpRip,
673	kCpumMsrWrFn_AmdFam10hIbsOpData,
674	kCpumMsrWrFn_AmdFam10hIbsOpData2,
675	kCpumMsrWrFn_AmdFam10hIbsOpData3,
676	kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
677	kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
678	kCpumMsrWrFn_AmdFam10hIbsCtl,
679	kCpumMsrWrFn_AmdFam14hIbsBrTarget,
680
681	kCpumMsrWrFn_Gim,
682
683	/** End of valid MSR write function indexes. */
684	kCpumMsrWrFn_End
685	} CPUMMSRWRFN;
686
687	/**
688	* MSR range.
689	*/
690	typedef struct CPUMMSRRANGE
691	{
692	/** The first MSR. [0] */
693	uint32_t uFirst;
694	/** The last MSR. [4] */
695	uint32_t uLast;
696	/** The read function (CPUMMSRRDFN). [8] */
697	uint16_t enmRdFn;
698	/** The write function (CPUMMSRWRFN). [10] */
699	uint16_t enmWrFn;
700	/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
701	* UINT16_MAX if not used by the read and write functions. [12] */
702	uint32_t offCpumCpu : 24;
703	/** Reserved for future hacks. [15] */
704	uint32_t fReserved : 8;
705	/** The init/read value. [16]
706	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
707	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
708	* offset into CPUM. */
709	uint64_t uValue;
710	/** The bits to ignore when writing. [24] */
711	uint64_t fWrIgnMask;
712	/** The bits that will cause a GP(0) when writing. [32]
713	* This is always checked prior to calling the write function. Using
714	* UINT64_MAX effectively marks the MSR as read-only. */
715	uint64_t fWrGpMask;
716	/** The register name, if applicable. [40] */
717	char szName[56];
718
719	/** The number of reads. */
720	STAMCOUNTER cReads;
721	/** The number of writes. */
722	STAMCOUNTER cWrites;
723	/** The number of times ignored bits were written. */
724	STAMCOUNTER cIgnoredBits;
725	/** The number of GPs generated. */
726	STAMCOUNTER cGps;
727	} CPUMMSRRANGE;
728	#ifndef VBOX_FOR_DTRACE_LIB
729	AssertCompileSize(CPUMMSRRANGE, 128);
730	#endif
731	/** Pointer to an MSR range. */
732	typedef CPUMMSRRANGE *PCPUMMSRRANGE;
733	/** Pointer to a const MSR range. */
734	typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
735
736
737	/**
738	* MSRs which are required while exploding features.
739	*/
740	typedef struct CPUMMSRS
741	{
742	union
743	{
744	VMXMSRS vmx;
745	SVMMSRS svm;
746	} hwvirt;
747	} CPUMMSRS;
748	/** Pointer to an CPUMMSRS struct. */
749	typedef CPUMMSRS *PCPUMMSRS;
750	/** Pointer to a const CPUMMSRS struct. */
751	typedef CPUMMSRS const *PCCPUMMSRS;
752
753
754	/**
755	* CPU features and quirks.
756	* This is mostly exploded CPUID info.
757	*/
758	typedef struct CPUMFEATURES
759	{
760	/** The CPU vendor (CPUMCPUVENDOR). */
761	uint8_t enmCpuVendor;
762	/** The CPU family. */
763	uint8_t uFamily;
764	/** The CPU model. */
765	uint8_t uModel;
766	/** The CPU stepping. */
767	uint8_t uStepping;
768	/** The microarchitecture. */
769	#ifndef VBOX_FOR_DTRACE_LIB
770	CPUMMICROARCH enmMicroarch;
771	#else
772	uint32_t enmMicroarch;
773	#endif
774	/** The maximum physical address width of the CPU. */
775	uint8_t cMaxPhysAddrWidth;
776	/** The maximum linear address width of the CPU. */
777	uint8_t cMaxLinearAddrWidth;
778	/** Max size of the extended state (or FPU state if no XSAVE). */
779	uint16_t cbMaxExtendedState;
780
781	/** Supports MSRs. */
782	uint32_t fMsr : 1;
783	/** Supports the page size extension (4/2 MB pages). */
784	uint32_t fPse : 1;
785	/** Supports 36-bit page size extension (4 MB pages can map memory above
786	* 4GB). */
787	uint32_t fPse36 : 1;
788	/** Supports physical address extension (PAE). */
789	uint32_t fPae : 1;
790	/** Supports page-global extension (PGE). */
791	uint32_t fPge : 1;
792	/** Page attribute table (PAT) support (page level cache control). */
793	uint32_t fPat : 1;
794	/** Supports the FXSAVE and FXRSTOR instructions. */
795	uint32_t fFxSaveRstor : 1;
796	/** Supports the XSAVE and XRSTOR instructions. */
797	uint32_t fXSaveRstor : 1;
798	/** Supports the XSAVEOPT instruction. */
799	uint32_t fXSaveOpt : 1;
800	/** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
801	uint32_t fOpSysXSaveRstor : 1;
802	/** Supports MMX. */
803	uint32_t fMmx : 1;
804	/** Supports AMD extensions to MMX instructions. */
805	uint32_t fAmdMmxExts : 1;
806	/** Supports SSE. */
807	uint32_t fSse : 1;
808	/** Supports SSE2. */
809	uint32_t fSse2 : 1;
810	/** Supports SSE3. */
811	uint32_t fSse3 : 1;
812	/** Supports SSSE3. */
813	uint32_t fSsse3 : 1;
814	/** Supports SSE4.1. */
815	uint32_t fSse41 : 1;
816	/** Supports SSE4.2. */
817	uint32_t fSse42 : 1;
818	/** Supports AVX. */
819	uint32_t fAvx : 1;
820	/** Supports AVX2. */
821	uint32_t fAvx2 : 1;
822	/** Supports AVX512 foundation. */
823	uint32_t fAvx512Foundation : 1;
824	/** Supports RDTSC. */
825	uint32_t fTsc : 1;
826	/** Intel SYSENTER/SYSEXIT support */
827	uint32_t fSysEnter : 1;
828	/** First generation APIC. */
829	uint32_t fApic : 1;
830	/** Second generation APIC. */
831	uint32_t fX2Apic : 1;
832	/** Hypervisor present. */
833	uint32_t fHypervisorPresent : 1;
834	/** MWAIT & MONITOR instructions supported. */
835	uint32_t fMonitorMWait : 1;
836	/** MWAIT Extensions present. */
837	uint32_t fMWaitExtensions : 1;
838	/** Supports CMPXCHG16B in 64-bit mode. */
839	uint32_t fMovCmpXchg16b : 1;
840	/** Supports CLFLUSH. */
841	uint32_t fClFlush : 1;
842	/** Supports CLFLUSHOPT. */
843	uint32_t fClFlushOpt : 1;
844	/** Supports IA32_PRED_CMD.IBPB. */
845	uint32_t fIbpb : 1;
846	/** Supports IA32_SPEC_CTRL.IBRS. */
847	uint32_t fIbrs : 1;
848	/** Supports IA32_SPEC_CTRL.STIBP. */
849	uint32_t fStibp : 1;
850	/** Supports IA32_FLUSH_CMD. */
851	uint32_t fFlushCmd : 1;
852	/** Supports IA32_ARCH_CAP. */
853	uint32_t fArchCap : 1;
854	/** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
855	uint32_t fMdsClear : 1;
856	/** Supports PCID. */
857	uint32_t fPcid : 1;
858	/** Supports INVPCID. */
859	uint32_t fInvpcid : 1;
860	/** Supports read/write FSGSBASE instructions. */
861	uint32_t fFsGsBase : 1;
862	/** Supports BMI1 instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, and TZCNT). */
863	uint32_t fBmi1 : 1;
864	/** Supports BMI2 instructions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX,
865	* and SHLX). */
866	uint32_t fBmi2 : 1;
867	/** Supports POPCNT instruction. */
868	uint32_t fPopCnt : 1;
869	/** Supports RDRAND instruction. */
870	uint32_t fRdRand : 1;
871	/** Supports RDSEED instruction. */
872	uint32_t fRdSeed : 1;
873	/** Supports Hardware Lock Elision (HLE). */
874	uint32_t fHle : 1;
875	/** Supports Restricted Transactional Memory (RTM - XBEGIN, XEND, XABORT). */
876	uint32_t fRtm : 1;
877	/** Supports PCLMULQDQ instruction. */
878	uint32_t fPclMul : 1;
879	/** Supports AES-NI (six AESxxx instructions). */
880	uint32_t fAesNi : 1;
881	/** Support MOVBE instruction. */
882	uint32_t fMovBe : 1;
883	/** Support SHA instructions. */
884	uint32_t fSha : 1;
885	/** Support ADX instructions. */
886	uint32_t fAdx : 1;
887
888	/** Supports AMD 3DNow instructions. */
889	uint32_t f3DNow : 1;
890	/** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
891	uint32_t f3DNowPrefetch : 1;
892
893	/** AMD64: Supports long mode. */
894	uint32_t fLongMode : 1;
895	/** AMD64: SYSCALL/SYSRET support. */
896	uint32_t fSysCall : 1;
897	/** AMD64: No-execute page table bit. */
898	uint32_t fNoExecute : 1;
899	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
900	uint32_t fLahfSahf : 1;
901	/** AMD64: Supports RDTSCP. */
902	uint32_t fRdTscP : 1;
903	/** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
904	uint32_t fMovCr8In32Bit : 1;
905	/** AMD64: Supports XOP (similar to VEX3/AVX). */
906	uint32_t fXop : 1;
907	/** AMD64: Supports ABM, i.e. the LZCNT instruction. */
908	uint32_t fAbm : 1;
909	/** AMD64: Supports TBM (BEXTR, BLCFILL, BLCI, BLCIC, BLCMSK, BLCS,
910	* BLSFILL, BLSIC, T1MSKC, and TZMSK). */
911	uint32_t fTbm : 1;
912
913	/** Indicates that FPU instruction and data pointers may leak.
914	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
915	* is only saved and restored if an exception is pending. */
916	uint32_t fLeakyFxSR : 1;
917
918	/** AMD64: Supports AMD SVM. */
919	uint32_t fSvm : 1;
920
921	/** Support for Intel VMX. */
922	uint32_t fVmx : 1;
923
924	/** Indicates that speculative execution control CPUID bits and MSRs are exposed.
925	* The details are different for Intel and AMD but both have similar
926	* functionality. */
927	uint32_t fSpeculationControl : 1;
928
929	/** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
930	* @remarks Only safe use after CPUM ring-0 init! */
931	uint32_t fArchRdclNo : 1;
932	/** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
933	* @remarks Only safe use after CPUM ring-0 init! */
934	uint32_t fArchIbrsAll : 1;
935	/** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
936	* @remarks Only safe use after CPUM ring-0 init! */
937	uint32_t fArchRsbOverride : 1;
938	/** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
939	* @remarks Only safe use after CPUM ring-0 init! */
940	uint32_t fArchVmmNeedNotFlushL1d : 1;
941	/** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4).
942	* @remarks Only safe use after CPUM ring-0 init! */
943	uint32_t fArchMdsNo : 1;
944
945	/** Alignment padding / reserved for future use (96 bits total, plus 12 bytes
946	* prior to the bit fields -> total of 24 bytes) */
947	uint32_t fPadding0 : 24;
948
949
950	/** @name SVM
951	* @{ */
952	/** SVM: Supports Nested-paging. */
953	uint32_t fSvmNestedPaging : 1;
954	/** SVM: Support LBR (Last Branch Record) virtualization. */
955	uint32_t fSvmLbrVirt : 1;
956	/** SVM: Supports SVM lock. */
957	uint32_t fSvmSvmLock : 1;
958	/** SVM: Supports Next RIP save. */
959	uint32_t fSvmNextRipSave : 1;
960	/** SVM: Supports TSC rate MSR. */
961	uint32_t fSvmTscRateMsr : 1;
962	/** SVM: Supports VMCB clean bits. */
963	uint32_t fSvmVmcbClean : 1;
964	/** SVM: Supports Flush-by-ASID. */
965	uint32_t fSvmFlusbByAsid : 1;
966	/** SVM: Supports decode assist. */
967	uint32_t fSvmDecodeAssists : 1;
968	/** SVM: Supports Pause filter. */
969	uint32_t fSvmPauseFilter : 1;
970	/** SVM: Supports Pause filter threshold. */
971	uint32_t fSvmPauseFilterThreshold : 1;
972	/** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
973	uint32_t fSvmAvic : 1;
974	/** SVM: Supports Virtualized VMSAVE/VMLOAD. */
975	uint32_t fSvmVirtVmsaveVmload : 1;
976	/** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
977	uint32_t fSvmVGif : 1;
978	/** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
979	uint32_t fSvmGmet : 1;
980	/** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */
981	uint32_t fSvmSSSCheck : 1;
982	/** SVM: Supports SPEC_CTRL virtualization. */
983	uint32_t fSvmSpecCtrl : 1;
984	/** SVM: Supports HOST_MCE_OVERRIDE. */
985	uint32_t fSvmHostMceOverride : 1;
986	/** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */
987	uint32_t fSvmTlbiCtl : 1;
988	/** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */
989	uint32_t fSvmPadding0 : 14;
990	/** SVM: Maximum supported ASID. */
991	uint32_t uSvmMaxAsid;
992	/** @} */
993
994
995	/** VMX: Maximum physical address width. */
996	uint32_t cVmxMaxPhysAddrWidth : 8;
997
998	/** @name VMX basic controls.
999	* @{ */
1000	/** VMX: Supports INS/OUTS VM-exit instruction info. */
1001	uint32_t fVmxInsOutInfo : 1;
1002	/** @} */
1003
1004	/** @name VMX Pin-based controls.
1005	* @{ */
1006	/** VMX: Supports external interrupt VM-exit. */
1007	uint32_t fVmxExtIntExit : 1;
1008	/** VMX: Supports NMI VM-exit. */
1009	uint32_t fVmxNmiExit : 1;
1010	/** VMX: Supports Virtual NMIs. */
1011	uint32_t fVmxVirtNmi : 1;
1012	/** VMX: Supports preemption timer. */
1013	uint32_t fVmxPreemptTimer : 1;
1014	/** VMX: Supports posted interrupts. */
1015	uint32_t fVmxPostedInt : 1;
1016	/** @} */
1017
1018	/** @name VMX Processor-based controls.
1019	* @{ */
1020	/** VMX: Supports Interrupt-window exiting. */
1021	uint32_t fVmxIntWindowExit : 1;
1022	/** VMX: Supports TSC offsetting. */
1023	uint32_t fVmxTscOffsetting : 1;
1024	/** VMX: Supports HLT exiting. */
1025	uint32_t fVmxHltExit : 1;
1026	/** VMX: Supports INVLPG exiting. */
1027	uint32_t fVmxInvlpgExit : 1;
1028	/** VMX: Supports MWAIT exiting. */
1029	uint32_t fVmxMwaitExit : 1;
1030	/** VMX: Supports RDPMC exiting. */
1031	uint32_t fVmxRdpmcExit : 1;
1032	/** VMX: Supports RDTSC exiting. */
1033	uint32_t fVmxRdtscExit : 1;
1034	/** VMX: Supports CR3-load exiting. */
1035	uint32_t fVmxCr3LoadExit : 1;
1036	/** VMX: Supports CR3-store exiting. */
1037	uint32_t fVmxCr3StoreExit : 1;
1038	/** VMX: Supports tertiary processor-based VM-execution controls. */
1039	uint32_t fVmxTertiaryExecCtls : 1;
1040	/** VMX: Supports CR8-load exiting. */
1041	uint32_t fVmxCr8LoadExit : 1;
1042	/** VMX: Supports CR8-store exiting. */
1043	uint32_t fVmxCr8StoreExit : 1;
1044	/** VMX: Supports TPR shadow. */
1045	uint32_t fVmxUseTprShadow : 1;
1046	/** VMX: Supports NMI-window exiting. */
1047	uint32_t fVmxNmiWindowExit : 1;
1048	/** VMX: Supports Mov-DRx exiting. */
1049	uint32_t fVmxMovDRxExit : 1;
1050	/** VMX: Supports Unconditional I/O exiting. */
1051	uint32_t fVmxUncondIoExit : 1;
1052	/** VMX: Supportgs I/O bitmaps. */
1053	uint32_t fVmxUseIoBitmaps : 1;
1054	/** VMX: Supports Monitor Trap Flag. */
1055	uint32_t fVmxMonitorTrapFlag : 1;
1056	/** VMX: Supports MSR bitmap. */
1057	uint32_t fVmxUseMsrBitmaps : 1;
1058	/** VMX: Supports MONITOR exiting. */
1059	uint32_t fVmxMonitorExit : 1;
1060	/** VMX: Supports PAUSE exiting. */
1061	uint32_t fVmxPauseExit : 1;
1062	/** VMX: Supports secondary processor-based VM-execution controls. */
1063	uint32_t fVmxSecondaryExecCtls : 1;
1064	/** @} */
1065
1066	/** @name VMX Secondary processor-based controls.
1067	* @{ */
1068	/** VMX: Supports virtualize-APIC access. */
1069	uint32_t fVmxVirtApicAccess : 1;
1070	/** VMX: Supports EPT (Extended Page Tables). */
1071	uint32_t fVmxEpt : 1;
1072	/** VMX: Supports descriptor-table exiting. */
1073	uint32_t fVmxDescTableExit : 1;
1074	/** VMX: Supports RDTSCP. */
1075	uint32_t fVmxRdtscp : 1;
1076	/** VMX: Supports virtualize-x2APIC mode. */
1077	uint32_t fVmxVirtX2ApicMode : 1;
1078	/** VMX: Supports VPID. */
1079	uint32_t fVmxVpid : 1;
1080	/** VMX: Supports WBIND exiting. */
1081	uint32_t fVmxWbinvdExit : 1;
1082	/** VMX: Supports Unrestricted guest. */
1083	uint32_t fVmxUnrestrictedGuest : 1;
1084	/** VMX: Supports APIC-register virtualization. */
1085	uint32_t fVmxApicRegVirt : 1;
1086	/** VMX: Supports virtual-interrupt delivery. */
1087	uint32_t fVmxVirtIntDelivery : 1;
1088	/** VMX: Supports Pause-loop exiting. */
1089	uint32_t fVmxPauseLoopExit : 1;
1090	/** VMX: Supports RDRAND exiting. */
1091	uint32_t fVmxRdrandExit : 1;
1092	/** VMX: Supports INVPCID. */
1093	uint32_t fVmxInvpcid : 1;
1094	/** VMX: Supports VM functions. */
1095	uint32_t fVmxVmFunc : 1;
1096	/** VMX: Supports VMCS shadowing. */
1097	uint32_t fVmxVmcsShadowing : 1;
1098	/** VMX: Supports RDSEED exiting. */
1099	uint32_t fVmxRdseedExit : 1;
1100	/** VMX: Supports PML. */
1101	uint32_t fVmxPml : 1;
1102	/** VMX: Supports EPT-violations \#VE. */
1103	uint32_t fVmxEptXcptVe : 1;
1104	/** VMX: Supports conceal VMX from PT. */
1105	uint32_t fVmxConcealVmxFromPt : 1;
1106	/** VMX: Supports XSAVES/XRSTORS. */
1107	uint32_t fVmxXsavesXrstors : 1;
1108	/** VMX: Supports mode-based execute control for EPT. */
1109	uint32_t fVmxModeBasedExecuteEpt : 1;
1110	/** VMX: Supports sub-page write permissions for EPT. */
1111	uint32_t fVmxSppEpt : 1;
1112	/** VMX: Supports Intel PT to output guest-physical addresses for EPT. */
1113	uint32_t fVmxPtEpt : 1;
1114	/** VMX: Supports TSC scaling. */
1115	uint32_t fVmxUseTscScaling : 1;
1116	/** VMX: Supports TPAUSE, UMONITOR, or UMWAIT. */
1117	uint32_t fVmxUserWaitPause : 1;
1118	/** VMX: Supports enclave (ENCLV) exiting. */
1119	uint32_t fVmxEnclvExit : 1;
1120	/** @} */
1121
1122	/** @name VMX Tertiary processor-based controls.
1123	* @{ */
1124	/** VMX: Supports LOADIWKEY exiting. */
1125	uint32_t fVmxLoadIwKeyExit : 1;
1126	/** @} */
1127
1128	/** @name VMX VM-entry controls.
1129	* @{ */
1130	/** VMX: Supports load-debug controls on VM-entry. */
1131	uint32_t fVmxEntryLoadDebugCtls : 1;
1132	/** VMX: Supports IA32e mode guest. */
1133	uint32_t fVmxIa32eModeGuest : 1;
1134	/** VMX: Supports load guest EFER MSR on VM-entry. */
1135	uint32_t fVmxEntryLoadEferMsr : 1;
1136	/** VMX: Supports load guest PAT MSR on VM-entry. */
1137	uint32_t fVmxEntryLoadPatMsr : 1;
1138	/** @} */
1139
1140	/** @name VMX VM-exit controls.
1141	* @{ */
1142	/** VMX: Supports save debug controls on VM-exit. */
1143	uint32_t fVmxExitSaveDebugCtls : 1;
1144	/** VMX: Supports host-address space size. */
1145	uint32_t fVmxHostAddrSpaceSize : 1;
1146	/** VMX: Supports acknowledge external interrupt on VM-exit. */
1147	uint32_t fVmxExitAckExtInt : 1;
1148	/** VMX: Supports save guest PAT MSR on VM-exit. */
1149	uint32_t fVmxExitSavePatMsr : 1;
1150	/** VMX: Supports load hsot PAT MSR on VM-exit. */
1151	uint32_t fVmxExitLoadPatMsr : 1;
1152	/** VMX: Supports save guest EFER MSR on VM-exit. */
1153	uint32_t fVmxExitSaveEferMsr : 1;
1154	/** VMX: Supports load host EFER MSR on VM-exit. */
1155	uint32_t fVmxExitLoadEferMsr : 1;
1156	/** VMX: Supports save VMX preemption timer on VM-exit. */
1157	uint32_t fVmxSavePreemptTimer : 1;
1158	/** VMX: Supports secondary VM-exit controls. */
1159	uint32_t fVmxSecondaryExitCtls : 1;
1160	/** @} */
1161
1162	/** @name VMX Miscellaneous data.
1163	* @{ */
1164	/** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
1165	uint32_t fVmxExitSaveEferLma : 1;
1166	/** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
1167	uint32_t fVmxPt : 1;
1168	/** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1169	* VMWRITE cannot modify read-only VM-exit information fields. */
1170	uint32_t fVmxVmwriteAll : 1;
1171	/** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
1172	* length instructions. */
1173	uint32_t fVmxEntryInjectSoftInt : 1;
1174	/** @} */
1175
1176	/** VMX: Padding / reserved for future features. */
1177	uint32_t fVmxPadding0 : 16;
1178	/** VMX: Padding / reserved for future, making it a total of 128 bits. */
1179	uint32_t fVmxPadding1;
1180	} CPUMFEATURES;
1181	#ifndef VBOX_FOR_DTRACE_LIB
1182	AssertCompileSize(CPUMFEATURES, 48);
1183	#endif
1184	/** Pointer to a CPU feature structure. */
1185	typedef CPUMFEATURES *PCPUMFEATURES;
1186	/** Pointer to a const CPU feature structure. */
1187	typedef CPUMFEATURES const *PCCPUMFEATURES;
1188
1189	/**
1190	* Chameleon wrapper structure for the host CPU features.
1191	*
1192	* This is used for the globally readable g_CpumHostFeatures variable, which is
1193	* initialized once during VMMR0 load for ring-0 and during CPUMR3Init in
1194	* ring-3. To reflect this immutability after load/init, we use this wrapper
1195	* structure to switch it between const and non-const depending on the context.
1196	* Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).
1197	*/
1198	typedef struct CPUHOSTFEATURES
1199	{
1200	CPUMFEATURES
1201	#ifndef CPUM_WITH_NONCONST_HOST_FEATURES
1202	const
1203	#endif
1204	s;
1205	} CPUHOSTFEATURES;
1206	/** Pointer to a const host CPU feature structure. */
1207	typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
1208
1209	/** Host CPU features.
1210	* @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after
1211	* module init. */
1212	extern CPUHOSTFEATURES g_CpumHostFeatures;
1213
1214
1215	/**
1216	* CPU database entry.
1217	*/
1218	typedef struct CPUMDBENTRY
1219	{
1220	/** The CPU name. */
1221	const char *pszName;
1222	/** The full CPU name. */
1223	const char *pszFullName;
1224	/** The CPU vendor (CPUMCPUVENDOR). */
1225	uint8_t enmVendor;
1226	/** The CPU family. */
1227	uint8_t uFamily;
1228	/** The CPU model. */
1229	uint8_t uModel;
1230	/** The CPU stepping. */
1231	uint8_t uStepping;
1232	/** The microarchitecture. */
1233	CPUMMICROARCH enmMicroarch;
1234	/** Scalable bus frequency used for reporting other frequencies. */
1235	uint64_t uScalableBusFreq;
1236	/** Flags - CPUMDB_F_XXX. */
1237	uint32_t fFlags;
1238	/** The maximum physical address with of the CPU. This should correspond to
1239	* the value in CPUID leaf 0x80000008 when present. */
1240	uint8_t cMaxPhysAddrWidth;
1241	/** The MXCSR mask. */
1242	uint32_t fMxCsrMask;
1243	/** Pointer to an array of CPUID leaves. */
1244	PCCPUMCPUIDLEAF paCpuIdLeaves;
1245	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
1246	uint32_t cCpuIdLeaves;
1247	/** The method used to deal with unknown CPUID leaves. */
1248	CPUMUNKNOWNCPUID enmUnknownCpuId;
1249	/** The default unknown CPUID value. */
1250	CPUMCPUID DefUnknownCpuId;
1251
1252	/** MSR mask. Several microarchitectures ignore the higher bits of ECX in
1253	* the RDMSR and WRMSR instructions. */
1254	uint32_t fMsrMask;
1255
1256	/** The number of ranges in the table pointed to b paMsrRanges. */
1257	uint32_t cMsrRanges;
1258	/** MSR ranges for this CPU. */
1259	PCCPUMMSRRANGE paMsrRanges;
1260	} CPUMDBENTRY;
1261	/** Pointer to a const CPU database entry. */
1262	typedef CPUMDBENTRY const *PCCPUMDBENTRY;
1263
1264	/** @name CPUMDB_F_XXX - CPUDBENTRY::fFlags
1265	* @{ */
1266	/** Should execute all in IEM.
1267	* @todo Implement this - currently done in Main... */
1268	#define CPUMDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
1269	/** @} */
1270
1271
1272
1273	#ifndef VBOX_FOR_DTRACE_LIB
1274
1275	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1276	VMMDECL(int) CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves);
1277	VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1278	#endif
1279
1280	VMM_INT_DECL(bool) CPUMAssertGuestRFlagsCookie(PVM pVM, PVMCPU pVCpu);
1281
1282
1283	/** @name Guest Register Getters.
1284	* @{ */
1285	VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR);
1286	VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit);
1287	VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden);
1288	VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu);
1289	VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t pGCPtrBase, uint32_t pcbLimit);
1290	VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu);
1291	VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu);
1292	VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu);
1293	VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu);
1294	VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu);
1295	VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue);
1296	VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu);
1297	VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu);
1298	VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu);
1299	VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu);
1300	VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu);
1301	VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu);
1302	VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu);
1303	VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu);
1304	VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu);
1305	VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu);
1306	VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu);
1307	VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu);
1308	VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu);
1309	VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu);
1310	VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu);
1311	VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu);
1312	VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu);
1313	VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu);
1314	VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu);
1315	VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu);
1316	VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu);
1317	VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu);
1318	VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu);
1319	VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1320	VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t iLeaf, uint32_t iSubLeaf, int f64BitMode,
1321	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
1322	VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu);
1323	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatCtrl(PCVMCPUCC pVCpu);
1324	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu);
1325	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPUCC pVCpu);
1326	VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPUCC pVCpu);
1327	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue);
1328	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue);
1329	/** @} */
1330
1331	/** @name Guest Register Setters.
1332	* @{ */
1333	VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1334	VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1335	VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1336	VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1337	VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0);
1338	VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1339	VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1340	VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1341	VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0);
1342	VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1);
1343	VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2);
1344	VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3);
1345	VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1346	VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7);
1347	VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value);
1348	VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue);
1349	VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1350	VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1351	VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1352	VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1353	VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1354	VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1355	VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1356	VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1357	VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1358	VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1359	VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1360	VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1361	VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1362	VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1363	VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1364	VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1365	VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1366	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1367	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1368	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1369	VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
1370	VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1371	VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue);
1372	VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu);
1373	VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue);
1374	VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu);
1375	VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM);
1376	VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes);
1377	VMM_INT_DECL(void) CPUMGetGuestPaePdpes(PVMCPU pVCpu, PX86PDPE paPaePdpes);
1378	/** @} */
1379
1380
1381	/** @name Misc Guest Predicate Functions.
1382	* @{ */
1383	VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu);
1384	VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu);
1385	VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu);
1386	VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu);
1387	VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu);
1388	VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu);
1389	VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu);
1390	VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu);
1391	VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu);
1392	VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu);
1393	/** @} */
1394
1395	/** @name Nested Hardware-Virtualization Helpers.
1396	* @{ */
1397	VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu);
1398	VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu);
1399	VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1400	VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1401
1402	/* SVM helpers. */
1403	VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1404	VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1405	VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx);
1406	VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx);
1407	VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
1408	VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1409	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
1410	PSVMIOIOEXITINFO pIoExitInfo);
1411	VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint8_t puMsrpmBit);
1412
1413	/* VMX helpers. */
1414	VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField);
1415	VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess);
1416	VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3);
1417	VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc);
1418	VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick);
1419	VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu);
1420	VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr);
1421	VMM_INT_DECL(bool) CPUMIsGuestVmxEptPagingEnabled(PCVMCPUCC pVCpu);
1422	VMM_INT_DECL(bool) CPUMIsGuestVmxEptPaePagingEnabled(PCVMCPUCC pVCpu);
1423	VMM_INT_DECL(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCVMCPUCC pVCpu);
1424	/** @} */
1425
1426	#if !defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS) \|\| defined(DOXYGEN_RUNNING)
1427	/** @name Inlined Guest Getters and predicates Functions.
1428	* @{ */
1429
1430	/**
1431	* Gets valid CR0 bits for the guest.
1432	*
1433	* @returns Valid CR0 bits.
1434	*/
1435	DECLINLINE(uint64_t) CPUMGetGuestCR0ValidMask(void)
1436	{
1437	return ( X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS
1438	\| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_WP \| X86_CR0_AM
1439	\| X86_CR0_NW \| X86_CR0_CD \| X86_CR0_PG);
1440	}
1441
1442	/**
1443	* Tests if the guest is running in real mode or not.
1444	*
1445	* @returns true if in real mode, otherwise false.
1446	* @param pCtx Current CPU context.
1447	*/
1448	DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCCPUMCTX pCtx)
1449	{
1450	return !(pCtx->cr0 & X86_CR0_PE);
1451	}
1452
1453	/**
1454	* Tests if the guest is running in real or virtual 8086 mode.
1455	*
1456	* @returns @c true if it is, @c false if not.
1457	* @param pCtx Current CPU context.
1458	*/
1459	DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCCPUMCTX pCtx)
1460	{
1461	return !(pCtx->cr0 & X86_CR0_PE)
1462	\|\| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1463	}
1464
1465	/**
1466	* Tests if the guest is running in virtual 8086 mode.
1467	*
1468	* @returns @c true if it is, @c false if not.
1469	* @param pCtx Current CPU context.
1470	*/
1471	DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCCPUMCTX pCtx)
1472	{
1473	return (pCtx->eflags.Bits.u1VM == 1);
1474	}
1475
1476	/**
1477	* Tests if the guest is running in paged protected or not.
1478	*
1479	* @returns true if in paged protected mode, otherwise false.
1480	* @param pCtx Current CPU context.
1481	*/
1482	DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1483	{
1484	return (pCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
1485	}
1486
1487	/**
1488	* Tests if the guest is running in long mode or not.
1489	*
1490	* @returns true if in long mode, otherwise false.
1491	* @param pCtx Current CPU context.
1492	*/
1493	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCCPUMCTX pCtx)
1494	{
1495	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1496	}
1497
1498	VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1499
1500	/**
1501	* Tests if the guest is running in 64 bits mode or not.
1502	*
1503	* @returns true if in 64 bits protected mode, otherwise false.
1504	* @param pCtx Current CPU context.
1505	*/
1506	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1507	{
1508	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1509	return false;
1510	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1511	return CPUMIsGuestIn64BitCodeSlow(pCtx);
1512	return pCtx->cs.Attr.n.u1Long;
1513	}
1514
1515	/**
1516	* Tests if the guest has paging enabled or not.
1517	*
1518	* @returns true if paging is enabled, otherwise false.
1519	* @param pCtx Current CPU context.
1520	*/
1521	DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCCPUMCTX pCtx)
1522	{
1523	return !!(pCtx->cr0 & X86_CR0_PG);
1524	}
1525
1526	/**
1527	* Tests if PAE paging is enabled given the relevant control registers.
1528	*
1529	* @returns @c true if in PAE mode, @c false otherwise.
1530	* @param uCr0 The CR0 value.
1531	* @param uCr4 The CR4 value.
1532	* @param uEferMsr The EFER value.
1533	*/
1534	DECLINLINE(bool) CPUMIsPaePagingEnabled(uint64_t uCr0, uint64_t uCr4, uint64_t uEferMsr)
1535	{
1536	/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1537	than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1538	return ( (uCr4 & X86_CR4_PAE)
1539	&& (uCr0 & X86_CR0_PG)
1540	&& !(uEferMsr & MSR_K6_EFER_LMA));
1541	}
1542
1543	/**
1544	* Tests if the guest is running in PAE mode or not.
1545	*
1546	* @returns @c true if in PAE mode, @c false otherwise.
1547	* @param pCtx Current CPU context.
1548	*/
1549	DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCCPUMCTX pCtx)
1550	{
1551	return CPUMIsPaePagingEnabled(pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
1552	}
1553
1554	/**
1555	* Tests if the guest has AMD SVM enabled or not.
1556	*
1557	* @returns true if SMV is enabled, otherwise false.
1558	* @param pCtx Current CPU context.
1559	*/
1560	DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1561	{
1562	return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1563	}
1564
1565	/**
1566	* Tests if the guest has Intel VT-x enabled or not.
1567	*
1568	* @returns true if VMX is enabled, otherwise false.
1569	* @param pCtx Current CPU context.
1570	*/
1571	DECLINLINE(bool) CPUMIsGuestVmxEnabled(PCCPUMCTX pCtx)
1572	{
1573	return RT_BOOL(pCtx->cr4 & X86_CR4_VMXE);
1574	}
1575
1576	/**
1577	* Returns the guest's global-interrupt (GIF) flag.
1578	*
1579	* @returns true when global-interrupts are enabled, otherwise false.
1580	* @param pCtx Current CPU context.
1581	*/
1582	DECLINLINE(bool) CPUMGetGuestGif(PCCPUMCTX pCtx)
1583	{
1584	return pCtx->hwvirt.fGif;
1585	}
1586
1587	/**
1588	* Sets the guest's global-interrupt flag (GIF).
1589	*
1590	* @param pCtx Current CPU context.
1591	* @param fGif The value to set.
1592	*/
1593	DECLINLINE(void) CPUMSetGuestGif(PCPUMCTX pCtx, bool fGif)
1594	{
1595	pCtx->hwvirt.fGif = fGif;
1596	}
1597
1598	/**
1599	* Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS.
1600	*
1601	* This also inhibit NMIs, except perhaps for nested guests.
1602	*
1603	* @returns true if interrupts are inhibited by interrupt shadow, false if not.
1604	* @param pCtx Current guest CPU context.
1605	* @note Requires pCtx->rip to be up to date.
1606	* @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1607	* differs from CPUMCTX::rip.
1608	*/
1609	DECLINLINE(bool) CPUMIsInInterruptShadow(PCCPUMCTX pCtx)
1610	{
1611	if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW))
1612	return false;
1613
1614	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1615	return pCtx->uRipInhibitInt == pCtx->rip;
1616	}
1617
1618	/**
1619	* Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS,
1620	* updating the state if stale.
1621	*
1622	* This also inhibit NMIs, except perhaps for nested guests.
1623	*
1624	* @retval true if interrupts are inhibited by interrupt shadow.
1625	* @retval false if not.
1626	* @param pCtx Current guest CPU context.
1627	* @note Requires pCtx->rip to be up to date.
1628	*/
1629	DECLINLINE(bool) CPUMIsInInterruptShadowWithUpdate(PCPUMCTX pCtx)
1630	{
1631	if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW))
1632	return false;
1633
1634	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1635	if (pCtx->uRipInhibitInt == pCtx->rip)
1636	return true;
1637
1638	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1639	return false;
1640	}
1641
1642	/**
1643	* Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS,
1644	* updating the state if stale while also returning the reason for the interrupt
1645	* inhibition.
1646	*
1647	* This also inhibit NMIs, except perhaps for nested guests.
1648	*
1649	* @retval true if interrupts are inhibited by interrupt shadow.
1650	* @retval false if not.
1651	* @param pCtx Current guest CPU context.
1652	* @param pfInhibitShw Where to store which type of interrupt inhibition was
1653	* active (see CPUMCTX_INHIBIT_XXX).
1654	* @note Requires pCtx->rip to be up to date.
1655	*/
1656	DECLINLINE(bool) CPUMIsInInterruptShadowWithUpdateEx(PCPUMCTX pCtx, uint32_t *pfInhibitShw)
1657	{
1658	Assert(pfInhibitShw);
1659	*pfInhibitShw = pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW;
1660	return CPUMIsInInterruptShadowWithUpdate(pCtx);
1661	}
1662
1663	/**
1664	* Checks if we're in an "interrupt shadow" due to a POP SS or MOV SS
1665	* instruction.
1666	*
1667	* This also inhibit NMIs, except perhaps for nested guests.
1668	*
1669	* @retval true if interrupts are inhibited due to POP/MOV SS.
1670	* @retval false if not.
1671	* @param pCtx Current guest CPU context.
1672	* @note Requires pCtx->rip to be up to date.
1673	* @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1674	* differs from CPUMCTX::rip.
1675	* @note Both CPUMIsInInterruptShadowAfterSti() and this function may return
1676	* true depending on the execution engine being used.
1677	*/
1678	DECLINLINE(bool) CPUMIsInInterruptShadowAfterSs(PCCPUMCTX pCtx)
1679	{
1680	if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW_SS))
1681	return false;
1682
1683	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1684	return pCtx->uRipInhibitInt == pCtx->rip;
1685	}
1686
1687	/**
1688	* Checks if we're in an "interrupt shadow" due to an STI instruction.
1689	*
1690	* This also inhibit NMIs, except perhaps for nested guests.
1691	*
1692	* @retval true if interrupts are inhibited due to STI.
1693	* @retval false if not.
1694	* @param pCtx Current guest CPU context.
1695	* @note Requires pCtx->rip to be up to date.
1696	* @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1697	* differs from CPUMCTX::rip.
1698	* @note Both CPUMIsInInterruptShadowAfterSs() and this function may return
1699	* true depending on the execution engine being used.
1700	*/
1701	DECLINLINE(bool) CPUMIsInInterruptShadowAfterSti(PCCPUMCTX pCtx)
1702	{
1703	if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW_STI))
1704	return false;
1705
1706	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1707	return pCtx->uRipInhibitInt == pCtx->rip;
1708	}
1709
1710	/**
1711	* Sets the "interrupt shadow" flag, after a STI, POP SS or MOV SS instruction.
1712	*
1713	* @param pCtx Current guest CPU context.
1714	* @note Requires pCtx->rip to be up to date.
1715	*/
1716	DECLINLINE(void) CPUMSetInInterruptShadow(PCPUMCTX pCtx)
1717	{
1718	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1719	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW;
1720	pCtx->uRipInhibitInt = pCtx->rip;
1721	}
1722
1723	/**
1724	* Sets the "interrupt shadow" flag, after a STI, POP SS or MOV SS instruction,
1725	* extended version.
1726	*
1727	* @param pCtx Current guest CPU context.
1728	* @param rip The RIP for which it is inhibited.
1729	*/
1730	DECLINLINE(void) CPUMSetInInterruptShadowEx(PCPUMCTX pCtx, uint64_t rip)
1731	{
1732	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW;
1733	pCtx->uRipInhibitInt = rip;
1734	}
1735
1736	/**
1737	* Sets the "interrupt shadow" flag after a POP SS or MOV SS instruction.
1738	*
1739	* @param pCtx Current guest CPU context.
1740	* @note Requires pCtx->rip to be up to date.
1741	*/
1742	DECLINLINE(void) CPUMSetInInterruptShadowSs(PCPUMCTX pCtx)
1743	{
1744	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1745	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW_SS;
1746	pCtx->uRipInhibitInt = pCtx->rip;
1747	}
1748
1749	/**
1750	* Sets the "interrupt shadow" flag after an STI instruction.
1751	*
1752	* @param pCtx Current guest CPU context.
1753	* @note Requires pCtx->rip to be up to date.
1754	*/
1755	DECLINLINE(void) CPUMSetInInterruptShadowSti(PCPUMCTX pCtx)
1756	{
1757	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1758	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW_STI;
1759	pCtx->uRipInhibitInt = pCtx->rip;
1760	}
1761
1762	/**
1763	* Clears the "interrupt shadow" flag.
1764	*
1765	* @param pCtx Current guest CPU context.
1766	*/
1767	DECLINLINE(void) CPUMClearInterruptShadow(PCPUMCTX pCtx)
1768	{
1769	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1770	}
1771
1772	/**
1773	* Update the "interrupt shadow" flag.
1774	*
1775	* @param pCtx Current guest CPU context.
1776	* @param fInhibited The new state.
1777	* @note Requires pCtx->rip to be up to date.
1778	*/
1779	DECLINLINE(void) CPUMUpdateInterruptShadow(PCPUMCTX pCtx, bool fInhibited)
1780	{
1781	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1782	if (!fInhibited)
1783	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1784	else
1785	{
1786	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW;
1787	pCtx->uRipInhibitInt = pCtx->rip;
1788	}
1789	}
1790
1791	/**
1792	* Update the "interrupt shadow" flag, extended version.
1793	*
1794	* @returns fInhibited.
1795	* @param pCtx Current guest CPU context.
1796	* @param fInhibited The new state.
1797	* @param rip The RIP for which it is inhibited.
1798	*/
1799	DECLINLINE(bool) CPUMUpdateInterruptShadowEx(PCPUMCTX pCtx, bool fInhibited, uint64_t rip)
1800	{
1801	if (!fInhibited)
1802	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1803	else
1804	{
1805	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_SHADOW;
1806	pCtx->uRipInhibitInt = rip;
1807	}
1808	return fInhibited;
1809	}
1810
1811	/**
1812	* Update the two "interrupt shadow" flags separately, extended version.
1813	*
1814	* @param pCtx Current guest CPU context.
1815	* @param fInhibitedBySs The new state for the MOV SS & POP SS aspect.
1816	* @param fInhibitedBySti The new state for the STI aspect.
1817	* @param rip The RIP for which it is inhibited.
1818	*/
1819	DECLINLINE(void) CPUMUpdateInterruptShadowSsStiEx(PCPUMCTX pCtx, bool fInhibitedBySs, bool fInhibitedBySti, uint64_t rip)
1820	{
1821	if (!(fInhibitedBySs \| fInhibitedBySti))
1822	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1823	else
1824	{
1825	pCtx->eflags.uBoth \|= (fInhibitedBySs ? CPUMCTX_INHIBIT_SHADOW_SS : UINT32_C(0))
1826	\| (fInhibitedBySti ? CPUMCTX_INHIBIT_SHADOW_STI : UINT32_C(0));
1827	pCtx->uRipInhibitInt = rip;
1828	}
1829	}
1830
1831	/* VMX forward declarations used by extended function versions: */
1832	DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx);
1833	DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls);
1834	DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx);
1835	DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking);
1836
1837	/**
1838	* Checks whether interrupts, include NMIs, are inhibited by pending NMI
1839	* delivery.
1840	*
1841	* This only checks the inhibit mask.
1842	*
1843	* @retval true if interrupts are inhibited by NMI handling.
1844	* @retval false if interrupts are not inhibited by NMI handling.
1845	* @param pCtx Current guest CPU context.
1846	*/
1847	DECLINLINE(bool) CPUMAreInterruptsInhibitedByNmi(PCCPUMCTX pCtx)
1848	{
1849	return (pCtx->eflags.uBoth & CPUMCTX_INHIBIT_NMI) != 0;
1850	}
1851
1852	/**
1853	* Extended version of CPUMAreInterruptsInhibitedByNmi() that takes VMX non-root
1854	* mode into account when check whether interrupts are inhibited by NMI.
1855	*
1856	* @retval true if interrupts are inhibited by NMI handling.
1857	* @retval false if interrupts are not inhibited by NMI handling.
1858	* @param pCtx Current guest CPU context.
1859	*/
1860	DECLINLINE(bool) CPUMAreInterruptsInhibitedByNmiEx(PCCPUMCTX pCtx)
1861	{
1862	/* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
1863	if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1864	\|\| !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1865	return CPUMAreInterruptsInhibitedByNmi(pCtx);
1866	return CPUMIsGuestVmxVirtNmiBlocking(pCtx);
1867	}
1868
1869	/**
1870	* Marks interrupts, include NMIs, as inhibited by pending NMI delivery.
1871	*
1872	* @param pCtx Current guest CPU context.
1873	*/
1874	DECLINLINE(void) CPUMSetInterruptInhibitingByNmi(PCPUMCTX pCtx)
1875	{
1876	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_NMI;
1877	}
1878
1879	/**
1880	* Extended version of CPUMSetInterruptInhibitingByNmi() that takes VMX non-root
1881	* mode into account when marking interrupts as inhibited by NMI.
1882	*
1883	* @param pCtx Current guest CPU context.
1884	*/
1885	DECLINLINE(void) CPUMSetInterruptInhibitingByNmiEx(PCPUMCTX pCtx)
1886	{
1887	/* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
1888	if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1889	\|\| !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1890	CPUMSetInterruptInhibitingByNmi(pCtx);
1891	else
1892	CPUMSetGuestVmxVirtNmiBlocking(pCtx, true);
1893	}
1894
1895	/**
1896	* Marks interrupts, include NMIs, as no longer inhibited by pending NMI
1897	* delivery.
1898	*
1899	* @param pCtx Current guest CPU context.
1900	*/
1901	DECLINLINE(void) CPUMClearInterruptInhibitingByNmi(PCPUMCTX pCtx)
1902	{
1903	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_NMI;
1904	}
1905
1906	/**
1907	* Extended version of CPUMClearInterruptInhibitingByNmi() that takes VMX
1908	* non-root mode into account when doing the updating.
1909	*
1910	* @param pCtx Current guest CPU context.
1911	*/
1912	DECLINLINE(void) CPUMClearInterruptInhibitingByNmiEx(PCPUMCTX pCtx)
1913	{
1914	/* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
1915	if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1916	\|\| !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1917	CPUMClearInterruptInhibitingByNmi(pCtx);
1918	else
1919	CPUMSetGuestVmxVirtNmiBlocking(pCtx, false);
1920	}
1921
1922	/**
1923	* Update whether interrupts, include NMIs, are inhibited by pending NMI
1924	* delivery.
1925	*
1926	* @param pCtx Current guest CPU context.
1927	* @param fInhibited The new state.
1928	*/
1929	DECLINLINE(void) CPUMUpdateInterruptInhibitingByNmi(PCPUMCTX pCtx, bool fInhibited)
1930	{
1931	if (!fInhibited)
1932	pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_NMI;
1933	else
1934	pCtx->eflags.uBoth \|= CPUMCTX_INHIBIT_NMI;
1935	}
1936
1937	/**
1938	* Extended version of CPUMUpdateInterruptInhibitingByNmi() that takes VMX
1939	* non-root mode into account when doing the updating.
1940	*
1941	* @param pCtx Current guest CPU context.
1942	* @param fInhibited The new state.
1943	*/
1944	DECLINLINE(void) CPUMUpdateInterruptInhibitingByNmiEx(PCPUMCTX pCtx, bool fInhibited)
1945	{
1946	/*
1947	* Set the state of guest-NMI blocking in any of the following cases:
1948	* - We're not executing a nested-guest.
1949	* - We're executing an SVM nested-guest[1].
1950	* - We're executing a VMX nested-guest without virtual-NMIs enabled.
1951	*
1952	* [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
1953	* SVM hypervisors must track NMI blocking themselves by intercepting
1954	* the IRET instruction after injection of an NMI.
1955	*/
1956	if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
1957	\|\| !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
1958	CPUMUpdateInterruptInhibitingByNmi(pCtx, fInhibited);
1959	/*
1960	* Set the state of virtual-NMI blocking, if we are executing a
1961	* VMX nested-guest with virtual-NMIs enabled.
1962	*/
1963	else
1964	CPUMSetGuestVmxVirtNmiBlocking(pCtx, fInhibited);
1965	}
1966
1967
1968	/**
1969	* Checks if we are executing inside an SVM nested hardware-virtualized guest.
1970	*
1971	* @returns @c true if in SVM nested-guest mode, @c false otherwise.
1972	* @param pCtx Current CPU context.
1973	*/
1974	DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
1975	{
1976	/*
1977	* With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
1978	* See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
1979	*/
1980	#ifndef IN_RC
1981	if ( pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM
1982	\|\| !(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN))
1983	return false;
1984	return true;
1985	#else
1986	NOREF(pCtx);
1987	return false;
1988	#endif
1989	}
1990
1991	/**
1992	* Checks if the guest is in VMX non-root operation.
1993	*
1994	* @returns @c true if in VMX non-root operation, @c false otherwise.
1995	* @param pCtx Current CPU context.
1996	*/
1997	DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx)
1998	{
1999	#ifndef IN_RC
2000	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
2001	return false;
2002	Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode \|\| pCtx->hwvirt.vmx.fInVmxRootMode);
2003	return pCtx->hwvirt.vmx.fInVmxNonRootMode;
2004	#else
2005	NOREF(pCtx);
2006	return false;
2007	#endif
2008	}
2009
2010	/**
2011	* Checks if we are executing inside an SVM or VMX nested hardware-virtualized
2012	* guest.
2013	*
2014	* @returns @c true if in nested-guest mode, @c false otherwise.
2015	* @param pCtx Current CPU context.
2016	*/
2017	DECLINLINE(bool) CPUMIsGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
2018	{
2019	#if 0
2020	return CPUMIsGuestInVmxNonRootMode(pCtx) \|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
2021	#else
2022	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
2023	return false;
2024	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
2025	{
2026	Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode \|\| pCtx->hwvirt.vmx.fInVmxRootMode);
2027	return pCtx->hwvirt.vmx.fInVmxNonRootMode;
2028	}
2029	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2030	return RT_BOOL(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN);
2031	#endif
2032	}
2033
2034	/**
2035	* Checks if we are executing inside an SVM or VMX nested hardware-virtualized
2036	* guest.
2037	*
2038	* @retval CPUMHWVIRT_NONE if not in SVM or VMX non-root mode.
2039	* @retval CPUMHWVIRT_VMX if in VMX non-root mode.
2040	* @retval CPUMHWVIRT_SVM if in SVM non-root mode.
2041	* @param pCtx Current CPU context.
2042	*/
2043	DECLINLINE(CPUMHWVIRT) CPUMGetGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
2044	{
2045	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
2046	return CPUMHWVIRT_NONE;
2047	if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
2048	{
2049	Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode \|\| pCtx->hwvirt.vmx.fInVmxRootMode);
2050	return pCtx->hwvirt.vmx.fInVmxNonRootMode ? CPUMHWVIRT_VMX : CPUMHWVIRT_NONE;
2051	}
2052	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2053	return pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN ? CPUMHWVIRT_SVM : CPUMHWVIRT_NONE;
2054	}
2055
2056	/**
2057	* Checks if the guest is in VMX root operation.
2058	*
2059	* @returns @c true if in VMX root operation, @c false otherwise.
2060	* @param pCtx Current CPU context.
2061	*/
2062	DECLINLINE(bool) CPUMIsGuestInVmxRootMode(PCCPUMCTX pCtx)
2063	{
2064	#ifndef IN_RC
2065	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
2066	return false;
2067	return pCtx->hwvirt.vmx.fInVmxRootMode;
2068	#else
2069	NOREF(pCtx);
2070	return false;
2071	#endif
2072	}
2073
2074	# ifndef IN_RC
2075
2076	/**
2077	* Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
2078	* active.
2079	*
2080	* @returns @c true if in intercept is set, @c false otherwise.
2081	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2082	* @param pCtx Current CPU context.
2083	* @param fIntercept The SVM control/instruction intercept, see
2084	* SVM_CTRL_INTERCEPT_*.
2085	*/
2086	DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint64_t fIntercept)
2087	{
2088	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2089	return false;
2090	uint64_t u64Intercepts;
2091	if (!HMGetGuestSvmCtrlIntercepts(pVCpu, &u64Intercepts))
2092	u64Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl;
2093	return RT_BOOL(u64Intercepts & fIntercept);
2094	}
2095
2096	/**
2097	* Checks if the nested-guest VMCB has the specified CR read intercept active.
2098	*
2099	* @returns @c true if in intercept is set, @c false otherwise.
2100	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2101	* @param pCtx Current CPU context.
2102	* @param uCr The CR register number (0 to 15).
2103	*/
2104	DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
2105	{
2106	Assert(uCr < 16);
2107	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2108	return false;
2109	uint16_t u16Intercepts;
2110	if (!HMGetGuestSvmReadCRxIntercepts(pVCpu, &u16Intercepts))
2111	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdCRx;
2112	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
2113	}
2114
2115	/**
2116	* Checks if the nested-guest VMCB has the specified CR write intercept active.
2117	*
2118	* @returns @c true if in intercept is set, @c false otherwise.
2119	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2120	* @param pCtx Current CPU context.
2121	* @param uCr The CR register number (0 to 15).
2122	*/
2123	DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
2124	{
2125	Assert(uCr < 16);
2126	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2127	return false;
2128	uint16_t u16Intercepts;
2129	if (!HMGetGuestSvmWriteCRxIntercepts(pVCpu, &u16Intercepts))
2130	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrCRx;
2131	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
2132	}
2133
2134	/**
2135	* Checks if the nested-guest VMCB has the specified DR read intercept active.
2136	*
2137	* @returns @c true if in intercept is set, @c false otherwise.
2138	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2139	* @param pCtx Current CPU context.
2140	* @param uDr The DR register number (0 to 15).
2141	*/
2142	DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
2143	{
2144	Assert(uDr < 16);
2145	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2146	return false;
2147	uint16_t u16Intercepts;
2148	if (!HMGetGuestSvmReadDRxIntercepts(pVCpu, &u16Intercepts))
2149	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdDRx;
2150	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
2151	}
2152
2153	/**
2154	* Checks if the nested-guest VMCB has the specified DR write intercept active.
2155	*
2156	* @returns @c true if in intercept is set, @c false otherwise.
2157	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2158	* @param pCtx Current CPU context.
2159	* @param uDr The DR register number (0 to 15).
2160	*/
2161	DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
2162	{
2163	Assert(uDr < 16);
2164	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2165	return false;
2166	uint16_t u16Intercepts;
2167	if (!HMGetGuestSvmWriteDRxIntercepts(pVCpu, &u16Intercepts))
2168	u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrDRx;
2169	return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
2170	}
2171
2172	/**
2173	* Checks if the nested-guest VMCB has the specified exception intercept active.
2174	*
2175	* @returns @c true if in intercept is active, @c false otherwise.
2176	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2177	* @param pCtx Current CPU context.
2178	* @param uVector The exception / interrupt vector.
2179	*/
2180	DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
2181	{
2182	Assert(uVector <= X86_XCPT_LAST);
2183	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2184	return false;
2185	uint32_t u32Intercepts;
2186	if (!HMGetGuestSvmXcptIntercepts(pVCpu, &u32Intercepts))
2187	u32Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u32InterceptXcpt;
2188	return RT_BOOL(u32Intercepts & RT_BIT(uVector));
2189	}
2190
2191	/**
2192	* Checks if the nested-guest VMCB has virtual-interrupt masking enabled.
2193	*
2194	* @returns @c true if virtual-interrupts are masked, @c false otherwise.
2195	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2196	* @param pCtx Current CPU context.
2197	*
2198	* @remarks Should only be called when SVM feature is exposed to the guest.
2199	*/
2200	DECLINLINE(bool) CPUMIsGuestSvmVirtIntrMasking(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2201	{
2202	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2203	return false;
2204	bool fVIntrMasking;
2205	if (!HMGetGuestSvmVirtIntrMasking(pVCpu, &fVIntrMasking))
2206	fVIntrMasking = pCtx->hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u1VIntrMasking;
2207	return fVIntrMasking;
2208	}
2209
2210	/**
2211	* Checks if the nested-guest VMCB has nested-paging enabled.
2212	*
2213	* @returns @c true if nested-paging is enabled, @c false otherwise.
2214	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2215	* @param pCtx Current CPU context.
2216	*
2217	* @remarks Should only be called when SVM feature is exposed to the guest.
2218	*/
2219	DECLINLINE(bool) CPUMIsGuestSvmNestedPagingEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2220	{
2221	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2222	return false;
2223	bool fNestedPaging;
2224	if (!HMGetGuestSvmNestedPaging(pVCpu, &fNestedPaging))
2225	fNestedPaging = pCtx->hwvirt.svm.Vmcb.ctrl.NestedPagingCtrl.n.u1NestedPaging;
2226	return fNestedPaging;
2227	}
2228
2229	/**
2230	* Gets the nested-guest VMCB pause-filter count.
2231	*
2232	* @returns The pause-filter count.
2233	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2234	* @param pCtx Current CPU context.
2235	*
2236	* @remarks Should only be called when SVM feature is exposed to the guest.
2237	*/
2238	DECLINLINE(uint16_t) CPUMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2239	{
2240	if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2241	return false;
2242	uint16_t u16PauseFilterCount;
2243	if (!HMGetGuestSvmPauseFilterCount(pVCpu, &u16PauseFilterCount))
2244	u16PauseFilterCount = pCtx->hwvirt.svm.Vmcb.ctrl.u16PauseFilterCount;
2245	return u16PauseFilterCount;
2246	}
2247
2248	/**
2249	* Updates the NextRIP (NRIP) field in the nested-guest VMCB.
2250	*
2251	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2252	* @param pCtx Current CPU context.
2253	* @param cbInstr The length of the current instruction in bytes.
2254	*
2255	* @remarks Should only be called when SVM feature is exposed to the guest.
2256	*/
2257	DECLINLINE(void) CPUMGuestSvmUpdateNRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbInstr)
2258	{
2259	RT_NOREF(pVCpu);
2260	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2261	pCtx->hwvirt.svm.Vmcb.ctrl.u64NextRIP = pCtx->rip + cbInstr;
2262	}
2263
2264	/**
2265	* Checks whether one of the given Pin-based VM-execution controls are set when
2266	* executing a nested-guest.
2267	*
2268	* @returns @c true if set, @c false otherwise.
2269	* @param pCtx Current CPU context.
2270	* @param uPinCtls The Pin-based VM-execution controls to check.
2271	*
2272	* @remarks This does not check if all given controls are set if more than one
2273	* control is passed in @a uPinCtl.
2274	*/
2275	DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls)
2276	{
2277	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2278	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & uPinCtls);
2279	}
2280
2281	/**
2282	* Checks whether one of the given Processor-based VM-execution controls are set
2283	* when executing a nested-guest.
2284	*
2285	* @returns @c true if set, @c false otherwise.
2286	* @param pCtx Current CPU context.
2287	* @param uProcCtls The Processor-based VM-execution controls to check.
2288	*
2289	* @remarks This does not check if all given controls are set if more than one
2290	* control is passed in @a uProcCtls.
2291	*/
2292	DECLINLINE(bool) CPUMIsGuestVmxProcCtlsSet(PCCPUMCTX pCtx, uint32_t uProcCtls)
2293	{
2294	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2295	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls & uProcCtls);
2296	}
2297
2298	/**
2299	* Checks whether one of the given Secondary Processor-based VM-execution controls
2300	* are set when executing a nested-guest.
2301	*
2302	* @returns @c true if set, @c false otherwise.
2303	* @param pCtx Current CPU context.
2304	* @param uProcCtls2 The Secondary Processor-based VM-execution controls to
2305	* check.
2306	*
2307	* @remarks This does not check if all given controls are set if more than one
2308	* control is passed in @a uProcCtls2.
2309	*/
2310	DECLINLINE(bool) CPUMIsGuestVmxProcCtls2Set(PCCPUMCTX pCtx, uint32_t uProcCtls2)
2311	{
2312	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2313	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls2 & uProcCtls2);
2314	}
2315
2316	/**
2317	* Checks whether one of the given Tertiary Processor-based VM-execution controls
2318	* are set when executing a nested-guest.
2319	*
2320	* @returns @c true if set, @c false otherwise.
2321	* @param pCtx Current CPU context.
2322	* @param uProcCtls3 The Tertiary Processor-based VM-execution controls to
2323	* check.
2324	*
2325	* @remarks This does not check if all given controls are set if more than one
2326	* control is passed in @a uProcCtls3.
2327	*/
2328	DECLINLINE(bool) CPUMIsGuestVmxProcCtls3Set(PCCPUMCTX pCtx, uint64_t uProcCtls3)
2329	{
2330	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2331	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u64ProcCtls3.u & uProcCtls3);
2332	}
2333
2334	/**
2335	* Checks whether one of the given VM-exit controls are set when executing a
2336	* nested-guest.
2337	*
2338	* @returns @c true if set, @c false otherwise.
2339	* @param pCtx Current CPU context.
2340	* @param uExitCtls The VM-exit controls to check.
2341	*
2342	* @remarks This does not check if all given controls are set if more than one
2343	* control is passed in @a uExitCtls.
2344	*/
2345	DECLINLINE(bool) CPUMIsGuestVmxExitCtlsSet(PCCPUMCTX pCtx, uint32_t uExitCtls)
2346	{
2347	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2348	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ExitCtls & uExitCtls);
2349	}
2350
2351	/**
2352	* Checks whether one of the given VM-entry controls are set when executing a
2353	* nested-guest.
2354	*
2355	* @returns @c true if set, @c false otherwise.
2356	* @param pCtx Current CPU context.
2357	* @param uEntryCtls The VM-entry controls to check.
2358	*
2359	* @remarks This does not check if all given controls are set if more than one
2360	* control is passed in @a uEntryCtls.
2361	*/
2362	DECLINLINE(bool) CPUMIsGuestVmxEntryCtlsSet(PCCPUMCTX pCtx, uint32_t uEntryCtls)
2363	{
2364	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2365	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32EntryCtls & uEntryCtls);
2366	}
2367
2368	/**
2369	* Checks whether events injected in the nested-guest are subject to VM-exit checks.
2370	*
2371	* @returns @c true if set, @c false otherwise.
2372	* @param pCtx Current CPU context.
2373	*/
2374	DECLINLINE(bool) CPUMIsGuestVmxInterceptEvents(PCCPUMCTX pCtx)
2375	{
2376	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2377	return pCtx->hwvirt.vmx.fInterceptEvents;
2378	}
2379
2380	/**
2381	* Sets whether events injected in the nested-guest are subject to VM-exit checks.
2382	*
2383	* @param pCtx Current CPU context.
2384	* @param fIntercept Whether to subject injected events to VM-exits or not.
2385	*/
2386	DECLINLINE(void) CPUMSetGuestVmxInterceptEvents(PCPUMCTX pCtx, bool fInterceptEvents)
2387	{
2388	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2389	pCtx->hwvirt.vmx.fInterceptEvents = fInterceptEvents;
2390	}
2391
2392	/**
2393	* Checks whether the given exception causes a VM-exit.
2394	*
2395	* The exception type include hardware exceptions, software exceptions (#BP, #OF)
2396	* and privileged software exceptions (#DB generated by INT1/ICEBP).
2397	*
2398	* Software interrupts do -not- cause VM-exits and hence must not be used with this
2399	* function.
2400	*
2401	* @returns @c true if the exception causes a VM-exit, @c false otherwise.
2402	* @param pCtx Current CPU context.
2403	* @param uVector The exception vector.
2404	* @param uErrCode The error code associated with the exception. Pass 0 if not
2405	* applicable.
2406	*/
2407	DECLINLINE(bool) CPUMIsGuestVmxXcptInterceptSet(PCCPUMCTX pCtx, uint8_t uVector, uint32_t uErrCode)
2408	{
2409	Assert(uVector <= X86_XCPT_LAST);
2410
2411	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2412
2413	/* NMIs have a dedicated VM-execution control for causing VM-exits. */
2414	if (uVector == X86_XCPT_NMI)
2415	return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
2416
2417	/* Page-faults are subject to masking using its error code. */
2418	uint32_t fXcptBitmap = pCtx->hwvirt.vmx.Vmcs.u32XcptBitmap;
2419	if (uVector == X86_XCPT_PF)
2420	{
2421	uint32_t const fXcptPFMask = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMask;
2422	uint32_t const fXcptPFMatch = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMatch;
2423	if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
2424	fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
2425	}
2426
2427	/* Consult the exception bitmap for all other exceptions. */
2428	if (fXcptBitmap & RT_BIT(uVector))
2429	return true;
2430	return false;
2431	}
2432
2433
2434	/**
2435	* Checks whether the guest is in VMX non-root mode and using EPT paging.
2436	*
2437	* @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
2438	* @param pCtx Current CPU context.
2439	*/
2440	DECLINLINE(bool) CPUMIsGuestVmxEptPagingEnabledEx(PCCPUMCTX pCtx)
2441	{
2442	return CPUMIsGuestInVmxNonRootMode(pCtx)
2443	&& CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_EPT);
2444	}
2445
2446
2447	/**
2448	* Implements VMSucceed for VMX instruction success.
2449	*
2450	* @param pCtx Current CPU context.
2451	*/
2452	DECLINLINE(void) CPUMSetGuestVmxVmSucceed(PCPUMCTX pCtx)
2453	{
2454	pCtx->eflags.uBoth &= ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF);
2455	}
2456
2457	/**
2458	* Implements VMFailInvalid for VMX instruction failure.
2459	*
2460	* @param pCtx Current CPU context.
2461	*/
2462	DECLINLINE(void) CPUMSetGuestVmxVmFailInvalid(PCPUMCTX pCtx)
2463	{
2464	pCtx->eflags.uBoth &= ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF);
2465	pCtx->eflags.uBoth \|= X86_EFL_CF;
2466	}
2467
2468	/**
2469	* Implements VMFailValid for VMX instruction failure.
2470	*
2471	* @param pCtx Current CPU context.
2472	* @param enmInsErr The VM instruction error.
2473	*/
2474	DECLINLINE(void) CPUMSetGuestVmxVmFailValid(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2475	{
2476	pCtx->eflags.uBoth &= ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF);
2477	pCtx->eflags.uBoth \|= X86_EFL_ZF;
2478	pCtx->hwvirt.vmx.Vmcs.u32RoVmInstrError = enmInsErr;
2479	}
2480
2481	/**
2482	* Implements VMFail for VMX instruction failure.
2483	*
2484	* @param pCtx Current CPU context.
2485	* @param enmInsErr The VM instruction error.
2486	*/
2487	DECLINLINE(void) CPUMSetGuestVmxVmFail(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2488	{
2489	if (pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS)
2490	CPUMSetGuestVmxVmFailValid(pCtx, enmInsErr);
2491	else
2492	CPUMSetGuestVmxVmFailInvalid(pCtx);
2493	}
2494
2495	/**
2496	* Returns the guest-physical address of the APIC-access page when executing a
2497	* nested-guest.
2498	*
2499	* @returns The APIC-access page guest-physical address.
2500	* @param pCtx Current CPU context.
2501	*/
2502	DECLINLINE(uint64_t) CPUMGetGuestVmxApicAccessPageAddrEx(PCCPUMCTX pCtx)
2503	{
2504	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2505	return pCtx->hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
2506	}
2507
2508	/**
2509	* Gets the nested-guest CR0 subject to the guest/host mask and the read-shadow.
2510	*
2511	* @returns The nested-guest CR0.
2512	* @param pCtx Current CPU context.
2513	* @param fGstHostMask The CR0 guest/host mask to use.
2514	*/
2515	DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr0(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2516	{
2517	/*
2518	* For each CR0 bit owned by the host, the corresponding bit from the
2519	* CR0 read shadow is loaded. For each CR0 bit that is not owned by the host,
2520	* the corresponding bit from the guest CR0 is loaded.
2521	*
2522	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2523	*/
2524	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2525	uint64_t const uGstCr0 = pCtx->cr0;
2526	uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2527	return (fReadShadow & fGstHostMask) \| (uGstCr0 & ~fGstHostMask);
2528	}
2529
2530	/**
2531	* Gets the nested-guest CR4 subject to the guest/host mask and the read-shadow.
2532	*
2533	* @returns The nested-guest CR4.
2534	* @param pCtx Current CPU context.
2535	* @param fGstHostMask The CR4 guest/host mask to use.
2536	*/
2537	DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr4(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2538	{
2539	/*
2540	* For each CR4 bit owned by the host, the corresponding bit from the
2541	* CR4 read shadow is loaded. For each CR4 bit that is not owned by the host,
2542	* the corresponding bit from the guest CR4 is loaded.
2543	*
2544	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2545	*/
2546	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2547	uint64_t const uGstCr4 = pCtx->cr4;
2548	uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2549	return (fReadShadow & fGstHostMask) \| (uGstCr4 & ~fGstHostMask);
2550	}
2551
2552	/**
2553	* Checks whether the LMSW access causes a VM-exit or not.
2554	*
2555	* @returns @c true if the LMSW access causes a VM-exit, @c false otherwise.
2556	* @param pCtx Current CPU context.
2557	* @param uNewMsw The LMSW source operand (the Machine Status Word).
2558	*/
2559	DECLINLINE(bool) CPUMIsGuestVmxLmswInterceptSet(PCCPUMCTX pCtx, uint16_t uNewMsw)
2560	{
2561	/*
2562	* LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
2563	*
2564	* See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
2565	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2566	*/
2567	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2568
2569	uint32_t const fGstHostMask = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2570	uint32_t const fReadShadow = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2571
2572	/*
2573	* LMSW can never clear CR0.PE but it may set it. Hence, we handle the
2574	* CR0.PE case first, before the rest of the bits in the MSW.
2575	*
2576	* If CR0.PE is owned by the host and CR0.PE differs between the
2577	* MSW (source operand) and the read-shadow, we must cause a VM-exit.
2578	*/
2579	if ( (fGstHostMask & X86_CR0_PE)
2580	&& (uNewMsw & X86_CR0_PE)
2581	&& !(fReadShadow & X86_CR0_PE))
2582	return true;
2583
2584	/*
2585	* If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
2586	* bits differ between the MSW (source operand) and the read-shadow, we must
2587	* cause a VM-exit.
2588	*/
2589	uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS);
2590	if ((fReadShadow & fGstHostLmswMask) != (uNewMsw & fGstHostLmswMask))
2591	return true;
2592
2593	return false;
2594	}
2595
2596	/**
2597	* Checks whether the Mov-to-CR0/CR4 access causes a VM-exit or not.
2598	*
2599	* @returns @c true if the Mov CRX access causes a VM-exit, @c false otherwise.
2600	* @param pCtx Current CPU context.
2601	* @param iCrReg The control register number (must be 0 or 4).
2602	* @param uNewCrX The CR0/CR4 value being written.
2603	*/
2604	DECLINLINE(bool) CPUMIsGuestVmxMovToCr0Cr4InterceptSet(PCCPUMCTX pCtx, uint8_t iCrReg, uint64_t uNewCrX)
2605	{
2606	/*
2607	* For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
2608	* corresponding bits differ between the source operand and the read-shadow,
2609	* we must cause a VM-exit.
2610	*
2611	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2612	*/
2613	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2614	Assert(iCrReg == 0 \|\| iCrReg == 4);
2615
2616	uint64_t fGstHostMask;
2617	uint64_t fReadShadow;
2618	if (iCrReg == 0)
2619	{
2620	fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2621	fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2622	}
2623	else
2624	{
2625	fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2626	fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2627	}
2628
2629	if ((fReadShadow & fGstHostMask) != (uNewCrX & fGstHostMask))
2630	{
2631	Assert(fGstHostMask != 0);
2632	return true;
2633	}
2634
2635	return false;
2636	}
2637
2638	/**
2639	* Returns whether the guest has an active, current VMCS.
2640	*
2641	* @returns @c true if the guest has an active, current VMCS, @c false otherwise.
2642	* @param pCtx Current CPU context.
2643	*/
2644	DECLINLINE(bool) CPUMIsGuestVmxCurrentVmcsValid(PCCPUMCTX pCtx)
2645	{
2646	return pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS;
2647	}
2648
2649	# endif /* !IN_RC */
2650
2651	/**
2652	* Checks whether the VMX nested-guest is in a state to receive physical (APIC)
2653	* interrupts.
2654	*
2655	* @returns @c true if it's ready, @c false otherwise.
2656	* @param pCtx The guest-CPU context.
2657	*/
2658	DECLINLINE(bool) CPUMIsGuestVmxPhysIntrEnabled(PCCPUMCTX pCtx)
2659	{
2660	#ifdef IN_RC
2661	AssertReleaseFailedReturn(false);
2662	#else
2663	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2664	if (CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_EXT_INT_EXIT))
2665	return true;
2666	return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2667	#endif
2668	}
2669
2670	/**
2671	* Checks whether the VMX nested-guest is blocking virtual-NMIs.
2672	*
2673	* @returns @c true if it's blocked, @c false otherwise.
2674	* @param pCtx The guest-CPU context.
2675	*/
2676	DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx)
2677	{
2678	#ifdef IN_RC
2679	RT_NOREF(pCtx);
2680	AssertReleaseFailedReturn(false);
2681	#else
2682	/*
2683	* Return the state of virtual-NMI blocking, if we are executing a
2684	* VMX nested-guest with virtual-NMIs enabled.
2685	*/
2686	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2687	Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2688	return pCtx->hwvirt.vmx.fVirtNmiBlocking;
2689	#endif
2690	}
2691
2692	/**
2693	* Sets or clears VMX nested-guest virtual-NMI blocking.
2694	*
2695	* @param pCtx The guest-CPU context.
2696	* @param fBlocking Whether virtual-NMI blocking is in effect or not.
2697	*/
2698	DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking)
2699	{
2700	#ifdef IN_RC
2701	RT_NOREF2(pCtx, fBlocking);
2702	AssertReleaseFailedReturnVoid();
2703	#else
2704	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2705	Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
2706	pCtx->hwvirt.vmx.fVirtNmiBlocking = fBlocking;
2707	#endif
2708	}
2709
2710	/**
2711	* Checks whether the VMX nested-guest is in a state to receive virtual interrupts
2712	* (those injected with the "virtual-interrupt delivery" feature).
2713	*
2714	* @returns @c true if it's ready, @c false otherwise.
2715	* @param pCtx The guest-CPU context.
2716	*/
2717	DECLINLINE(bool) CPUMIsGuestVmxVirtIntrEnabled(PCCPUMCTX pCtx)
2718	{
2719	#ifdef IN_RC
2720	RT_NOREF2(pCtx);
2721	AssertReleaseFailedReturn(false);
2722	#else
2723	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2724	return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2725	#endif
2726	}
2727
2728	/** @} */
2729	#endif /* !IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS \|\| DOXYGEN_RUNNING */
2730
2731
2732
2733	/** @name Hypervisor Register Getters.
2734	* @{ */
2735	VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
2736	VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
2737	VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
2738	VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
2739	VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
2740	VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
2741	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
2742	/** @} */
2743
2744	/** @name Hypervisor Register Setters.
2745	* @{ */
2746	VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
2747	VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
2748	VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
2749	VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
2750	VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
2751	VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
2752	VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
2753	VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg);
2754	/** @} */
2755
2756	#ifdef VBOX_INCLUDED_vmm_cpumctx_h
2757	VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
2758	#endif
2759
2760	/** @name Changed flags.
2761	* These flags are used to keep track of which important register that
2762	* have been changed since last they were reset. The only one allowed
2763	* to clear them is REM!
2764	*
2765	* @todo This is obsolete, but remains as it will be refactored for coordinating
2766	* IEM and NEM/HM later. Probably.
2767	* @{
2768	*/
2769	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
2770	#define CPUM_CHANGED_CR0 RT_BIT(1)
2771	#define CPUM_CHANGED_CR4 RT_BIT(2)
2772	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
2773	#define CPUM_CHANGED_CR3 RT_BIT(4)
2774	#define CPUM_CHANGED_GDTR RT_BIT(5)
2775	#define CPUM_CHANGED_IDTR RT_BIT(6)
2776	#define CPUM_CHANGED_LDTR RT_BIT(7)
2777	#define CPUM_CHANGED_TR RT_BIT(8) /*@< Currently unused. /
2778	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
2779	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /*@< Currently unused. /
2780	#define CPUM_CHANGED_CPUID RT_BIT(11)
2781	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
2782	\| CPUM_CHANGED_CR0 \
2783	\| CPUM_CHANGED_CR4 \
2784	\| CPUM_CHANGED_GLOBAL_TLB_FLUSH \
2785	\| CPUM_CHANGED_CR3 \
2786	\| CPUM_CHANGED_GDTR \
2787	\| CPUM_CHANGED_IDTR \
2788	\| CPUM_CHANGED_LDTR \
2789	\| CPUM_CHANGED_TR \
2790	\| CPUM_CHANGED_SYSENTER_MSR \
2791	\| CPUM_CHANGED_HIDDEN_SEL_REGS \
2792	\| CPUM_CHANGED_CPUID )
2793	/** @} */
2794
2795	VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
2796	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
2797	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
2798	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
2799	VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
2800	VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
2801	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
2802	VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
2803	VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
2804	VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
2805	VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
2806	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
2807	VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM);
2808	VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
2809	uint64_t *puValidEfer);
2810	VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
2811	VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue);
2812
2813
2814	/** Guest CPU interruptibility level, see CPUMGetGuestInterruptibility(). */
2815	typedef enum CPUMINTERRUPTIBILITY
2816	{
2817	CPUMINTERRUPTIBILITY_INVALID = 0,
2818	CPUMINTERRUPTIBILITY_UNRESTRAINED,
2819	CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED,
2820	CPUMINTERRUPTIBILITY_INT_DISABLED,
2821	CPUMINTERRUPTIBILITY_INT_INHIBITED, /*< @todo rename as it inhibits NMIs too. /
2822	CPUMINTERRUPTIBILITY_NMI_INHIBIT,
2823	CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT,
2824	CPUMINTERRUPTIBILITY_END,
2825	CPUMINTERRUPTIBILITY_32BIT_HACK = 0x7fffffff
2826	} CPUMINTERRUPTIBILITY;
2827
2828	VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu);
2829
2830	/** @name Typical scalable bus frequency values.
2831	* @{ */
2832	/** Special internal value indicating that we don't know the frequency.
2833	* @internal */
2834	#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
2835	#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
2836	#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
2837	#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
2838	#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
2839	#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
2840	#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
2841	#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
2842	/** @} */
2843
2844
2845	#ifdef IN_RING3
2846	/** @defgroup grp_cpum_r3 The CPUM ring-3 API
2847	* @{
2848	*/
2849
2850	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
2851
2852	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
2853	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
2854	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves);
2855	VMMDECL(CPUMMICROARCH) CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
2856	uint8_t bModel, uint8_t bStepping);
2857	VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
2858	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
2859	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
2860	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2861	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
2862	#endif
2863
2864	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
2865
2866	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu);
2867	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu);
2868	/** @} */
2869	#endif /* IN_RING3 */
2870
2871	#ifdef IN_RING0
2872	/** @defgroup grp_cpum_r0 The CPUM ring-0 API
2873	* @{
2874	*/
2875	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
2876	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
2877	VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM);
2878	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM);
2879	DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPUCC pVCpu);
2880	DECLASM(void) CPUMR0TouchHostFpu(void);
2881	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu);
2882	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu);
2883	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu);
2884	VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVMCC pVM, PVMCPUCC pVCpu);
2885	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6);
2886	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6);
2887
2888	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6);
2889	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6);
2890	/** @} */
2891	#endif /* IN_RING0 */
2892
2893	/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
2894	* @{
2895	*/
2896	VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPUCC pVCpu);
2897	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPUCC pVCpu);
2898	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPUCC pVCpu);
2899	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPUCC pVCpu);
2900	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPUCC pVCpu);
2901	/** @} */
2902
2903
2904	#endif /* !VBOX_FOR_DTRACE_LIB */
2905	/** @} */
2906	RT_C_DECLS_END
2907
2908
2909	#endif /* !VBOX_INCLUDED_vmm_cpum_x86_amd64_h */
2910

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source: vbox/trunk/include/VBox/vmm/cpum-x86-amd64.h@ 99260

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