VirtualBox

source: vbox/trunk/include/VBox/vmm/apic.h@ 64622

Last change on this file since 64622 was 63634, checked in by vboxsync, 8 years ago

VMM/APIC: doxygen fix.
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File size: 8.0 KB
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1/** @file
2 * APIC - Advanced Programmable Interrupt Controller.
3 */
4
5/*
6 * Copyright (C) 2006-2016 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_apic_h
27#define ___VBox_vmm_apic_h
28
29#include <VBox/vmm/pdmins.h>
30#include <VBox/vmm/pdmdev.h>
31
32/** @defgroup grp_apic The local APIC VMM API
33 * @ingroup grp_vmm
34 * @{
35 */
36
37/** Offset of APIC ID Register. */
38#define XAPIC_OFF_ID 0x020
39/** Offset of APIC Version Register. */
40#define XAPIC_OFF_VERSION 0x030
41/** Offset of Task Priority Register. */
42#define XAPIC_OFF_TPR 0x080
43/** Offset of Arbitrartion Priority register. */
44#define XAPIC_OFF_APR 0x090
45/** Offset of Processor Priority register. */
46#define XAPIC_OFF_PPR 0x0A0
47/** Offset of End Of Interrupt register. */
48#define XAPIC_OFF_EOI 0x0B0
49/** Offset of Remote Read Register. */
50#define XAPIC_OFF_RRD 0x0C0
51/** Offset of Logical Destination Register. */
52#define XAPIC_OFF_LDR 0x0D0
53/** Offset of Destination Format Register. */
54#define XAPIC_OFF_DFR 0x0E0
55/** Offset of Spurious Interrupt Vector Register. */
56#define XAPIC_OFF_SVR 0x0F0
57/** Offset of In-service Register (bits 31:0). */
58#define XAPIC_OFF_ISR0 0x100
59/** Offset of In-service Register (bits 63:32). */
60#define XAPIC_OFF_ISR1 0x110
61/** Offset of In-service Register (bits 95:64). */
62#define XAPIC_OFF_ISR2 0x120
63/** Offset of In-service Register (bits 127:96). */
64#define XAPIC_OFF_ISR3 0x130
65/** Offset of In-service Register (bits 159:128). */
66#define XAPIC_OFF_ISR4 0x140
67/** Offset of In-service Register (bits 191:160). */
68#define XAPIC_OFF_ISR5 0x150
69/** Offset of In-service Register (bits 223:192). */
70#define XAPIC_OFF_ISR6 0x160
71/** Offset of In-service Register (bits 255:224). */
72#define XAPIC_OFF_ISR7 0x170
73/** Offset of Trigger Mode Register (bits 31:0). */
74#define XAPIC_OFF_TMR0 0x180
75/** Offset of Trigger Mode Register (bits 63:32). */
76#define XAPIC_OFF_TMR1 0x190
77/** Offset of Trigger Mode Register (bits 95:64). */
78#define XAPIC_OFF_TMR2 0x1A0
79/** Offset of Trigger Mode Register (bits 127:96). */
80#define XAPIC_OFF_TMR3 0x1B0
81/** Offset of Trigger Mode Register (bits 159:128). */
82#define XAPIC_OFF_TMR4 0x1C0
83/** Offset of Trigger Mode Register (bits 191:160). */
84#define XAPIC_OFF_TMR5 0x1D0
85/** Offset of Trigger Mode Register (bits 223:192). */
86#define XAPIC_OFF_TMR6 0x1E0
87/** Offset of Trigger Mode Register (bits 255:224). */
88#define XAPIC_OFF_TMR7 0x1F0
89/** Offset of Interrupt Request Register (bits 31:0). */
90#define XAPIC_OFF_IRR0 0x200
91/** Offset of Interrupt Request Register (bits 63:32). */
92#define XAPIC_OFF_IRR1 0x210
93/** Offset of Interrupt Request Register (bits 95:64). */
94#define XAPIC_OFF_IRR2 0x220
95/** Offset of Interrupt Request Register (bits 127:96). */
96#define XAPIC_OFF_IRR3 0x230
97/** Offset of Interrupt Request Register (bits 159:128). */
98#define XAPIC_OFF_IRR4 0x240
99/** Offset of Interrupt Request Register (bits 191:160). */
100#define XAPIC_OFF_IRR5 0x250
101/** Offset of Interrupt Request Register (bits 223:192). */
102#define XAPIC_OFF_IRR6 0x260
103/** Offset of Interrupt Request Register (bits 255:224). */
104#define XAPIC_OFF_IRR7 0x270
105/** Offset of Error Status Register. */
106#define XAPIC_OFF_ESR 0x280
107/** Offset of LVT CMCI Register. */
108#define XAPIC_OFF_LVT_CMCI 0x2F0
109/** Offset of Interrupt Command Register - Lo. */
110#define XAPIC_OFF_ICR_LO 0x300
111/** Offset of Interrupt Command Register - Hi. */
112#define XAPIC_OFF_ICR_HI 0x310
113/** Offset of LVT Timer Register. */
114#define XAPIC_OFF_LVT_TIMER 0x320
115/** Offset of LVT Thermal Sensor Register. */
116#define XAPIC_OFF_LVT_THERMAL 0x330
117/** Offset of LVT Performance Counter Register. */
118#define XAPIC_OFF_LVT_PERF 0x340
119/** Offset of LVT LINT0 Register. */
120#define XAPIC_OFF_LVT_LINT0 0x350
121/** Offset of LVT LINT1 Register. */
122#define XAPIC_OFF_LVT_LINT1 0x360
123/** Offset of LVT Error Register . */
124#define XAPIC_OFF_LVT_ERROR 0x370
125/** Offset of Timer Initial Count Register. */
126#define XAPIC_OFF_TIMER_ICR 0x380
127/** Offset of Timer Current Count Register. */
128#define XAPIC_OFF_TIMER_CCR 0x390
129/** Offset of Timer Divide Configuration Register. */
130#define XAPIC_OFF_TIMER_DCR 0x3E0
131/** Offset of Self-IPI Register (x2APIC only). */
132#define X2APIC_OFF_SELF_IPI 0x3F0
133
134/** Offset of LVT range start. */
135#define XAPIC_OFF_LVT_START XAPIC_OFF_LVT_TIMER
136/** Offset of LVT range end (inclusive). */
137#define XAPIC_OFF_LVT_END XAPIC_OFF_LVT_ERROR
138/** Offset of LVT extended range start. */
139#define XAPIC_OFF_LVT_EXT_START XAPIC_OFF_LVT_CMCI
140/** Offset of LVT extended range end (inclusive). */
141#define XAPIC_OFF_LVT_EXT_END XAPIC_OFF_LVT_CMCI
142
143/**
144 * xAPIC trigger mode.
145 */
146typedef enum XAPICTRIGGERMODE
147{
148 XAPICTRIGGERMODE_EDGE = 0,
149 XAPICTRIGGERMODE_LEVEL
150} XAPICTRIGGERMODE;
151
152RT_C_DECLS_BEGIN
153
154#ifdef IN_RING3
155/** @defgroup grp_apic_r3 The APIC Host Context Ring-3 API
156 * @{
157 */
158VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu);
159VMMR3_INT_DECL(void) APICR3HvEnable(PVM pVM);
160/** @} */
161#endif /* IN_RING3 */
162
163#ifdef IN_RING0
164/** @defgroup grp_apic_r0 The APIC Host Context Ring-0 API
165 * @{
166 */
167VMMR0_INT_DECL(int) APICR0InitVM(PVM pVM);
168VMMR0_INT_DECL(int) APICR0TermVM(PVM pVM);
169/** @} */
170#endif /* IN_RING0 */
171
172VMMDECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr);
173VMMDECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr);
174VMMDECL(void) APICUpdatePendingInterrupts(PVMCPU pVCpu);
175VMMDECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr);
176
177/** @name Hyper-V interface (Ring-3 and all-context API).
178 * @{ */
179#ifdef IN_RING3
180VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode);
181#endif
182VMM_INT_DECL(void) APICHvSendInterrupt(PVMCPU pVCpu, uint8_t uVector, bool fAutoEoi, XAPICTRIGGERMODE enmTriggerMode);
183VMM_INT_DECL(VBOXSTRICTRC) APICHvSetTpr(PVMCPU pVCpu, uint8_t uTpr);
184VMM_INT_DECL(uint8_t) APICHvGetTpr(PVMCPU pVCpu);
185VMM_INT_DECL(VBOXSTRICTRC) APICHvSetIcr(PVMCPU pVCpu, uint64_t uIcr);
186VMM_INT_DECL(uint64_t) APICHvGetIcr(PVMCPU pVCpu);
187VMM_INT_DECL(VBOXSTRICTRC) APICHvSetEoi(PVMCPU pVCpu, uint32_t uEoi);
188/** @} */
189
190RT_C_DECLS_END
191
192extern const PDMDEVREG g_DeviceAPIC;
193/** @} */
194
195#endif
196
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