rawpci.h@ 36564

Last change on this file since 36564 was 36552, checked in by vboxsync, 14 years ago
PCI: device reset logic, cleanups, read MSI regs from the device
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 18.0 KB

Line
1	/** @file
2	* Raw PCI Devices (aka PCI pass-through). (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2010-2011 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_rawpci_h
27	#define ___VBox_rawpci_h
28
29	#include <VBox/types.h>
30	#include <VBox/sup.h>
31
32	RT_C_DECLS_BEGIN
33
34	/**
35	* Handle for the raw PCI device.
36	*/
37	typedef uint32_t PCIRAWDEVHANDLE;
38
39	/**
40	* Handle for the ISR.
41	*/
42	typedef uint32_t PCIRAWISRHANDLE;
43
44	/**
45	* Physical memory action enumeration.
46	*/
47	typedef enum PCIRAWMEMINFOACTION
48	{
49	/** Pages mapped. */
50	PCIRAW_MEMINFO_MAP,
51	/** Pages unmapped. */
52	PCIRAW_MEMINFO_UNMAP,
53	/** The usual 32-bit type blow up. */
54	PCIRAW_MEMINFO_32BIT_HACK = 0x7fffffff
55	} PCIRAWMEMINFOACTION;
56
57	/**
58	* Per-VM capability flag bits.
59	*/
60	typedef enum PCIRAWVMFLAGS
61	{
62	/** If we can use IOMMU in this VM. */
63	PCIRAW_VMFLAGS_HAS_IOMMU = (1 << 0),
64	PCIRAW_VMFLAGS_32BIT_HACK = 0x7fffffff
65	} PCIRAWVMFLAGS;
66
67	/* Forward declaration. */
68	struct RAWPCIPERVM;
69
70	/**
71	* Callback to notify raw PCI subsystem about mapping/unmapping of
72	* host pages to the guest. Typical usecase is to register physical
73	* RAM pages with IOMMU, so that it could allow DMA for PCI devices
74	* directly from the guest RAM.
75	* Region shall be one or more contigous (both host and guest) pages
76	* of physical memory.
77	*
78	* @returns VBox status code.
79	*
80	* @param pVM VM pointer.
81	* @param HostStart Physical address of region start on the host.
82	* @param GuestStart Physical address of region start on the guest.
83	* @param cMemSize Region size in bytes.
84	* @param Action Action performed (i.e. if page was mapped or unmapped).
85	*/
86	typedef DECLCALLBACK(int) FNRAWPCICONTIGPHYSMEMINFO(struct RAWPCIPERVM* pVmData, RTHCPHYS HostStart, RTGCPHYS GuestStart, uint64_t cMemSize, PCIRAWMEMINFOACTION Action);
87	typedef FNRAWPCICONTIGPHYSMEMINFO *PFNRAWPCICONTIGPHYSMEMINFO;
88
89	/** Data being part of the VM structure. */
90	typedef struct RAWPCIPERVM
91	{
92	/** Shall only be interpreted by the host PCI driver. */
93	RTR0PTR pDriverData;
94	/** Callback called when mapping of host pages to the guest changes. */
95	PFNRAWPCICONTIGPHYSMEMINFO pfnContigMemInfo;
96	/** Flags describing VM capabilities (such as IOMMU presence). */
97	uint32_t fVmCaps;
98	} RAWPCIPERVM;
99	typedef RAWPCIPERVM *PRAWPCIPERVM;
100
101	/** Parameters buffer for PCIRAWR0_DO_OPEN_DEVICE call */
102	typedef struct
103	{
104	/* in */
105	uint32_t PciAddress;
106	uint32_t fFlags;
107	/* out */
108	PCIRAWDEVHANDLE Device;
109	uint32_t fDevFlags;
110	} PCIRAWREQOPENDEVICE;
111
112	/** Parameters buffer for PCIRAWR0_DO_CLOSE_DEVICE call */
113	typedef struct
114	{
115	/* in */
116	uint32_t fFlags;
117	} PCIRAWREQCLOSEDEVICE;
118
119	/** Parameters buffer for PCIRAWR0_DO_GET_REGION_INFO call */
120	typedef struct
121	{
122	/* in */
123	int32_t iRegion;
124	/* out */
125	RTGCPHYS RegionStart;
126	uint64_t u64RegionSize;
127	bool fPresent;
128	uint32_t fFlags;
129	} PCIRAWREQGETREGIONINFO;
130
131	/** Parameters buffer for PCIRAWR0_DO_MAP_REGION call. */
132	typedef struct
133	{
134	/* in */
135	RTGCPHYS StartAddress;
136	uint64_t iRegionSize;
137	int32_t iRegion;
138	uint32_t fFlags;
139	/* out */
140	RTR3PTR pvAddressR3;
141	RTR0PTR pvAddressR0;
142	} PCIRAWREQMAPREGION;
143
144	/** Parameters buffer for PCIRAWR0_DO_UNMAP_REGION call. */
145	typedef struct
146	{
147	/* in */
148	RTGCPHYS StartAddress;
149	uint64_t iRegionSize;
150	RTR3PTR pvAddressR3;
151	RTR0PTR pvAddressR0;
152	int32_t iRegion;
153	} PCIRAWREQUNMAPREGION;
154
155	/** Parameters buffer for PCIRAWR0_DO_PIO_WRITE call. */
156	typedef struct
157	{
158	/* in */
159	uint16_t iPort;
160	uint16_t cb;
161	uint32_t iValue;
162	} PCIRAWREQPIOWRITE;
163
164	/** Parameters buffer for PCIRAWR0_DO_PIO_READ call. */
165	typedef struct
166	{
167	/* in */
168	uint16_t iPort;
169	uint16_t cb;
170	/* out */
171	uint32_t iValue;
172	} PCIRAWREQPIOREAD;
173
174	/** Memory operand. */
175	typedef struct
176	{
177	union
178	{
179	uint8_t u8;
180	uint16_t u16;
181	uint32_t u32;
182	uint64_t u64;
183	} u;
184	uint8_t cb;
185	} PCIRAWMEMLOC;
186
187	/** Parameters buffer for PCIRAWR0_DO_MMIO_WRITE call. */
188	typedef struct
189	{
190	/* in */
191	RTR0PTR Address;
192	PCIRAWMEMLOC Value;
193	} PCIRAWREQMMIOWRITE;
194
195	/** Parameters buffer for PCIRAWR0_DO_MMIO_READ call. */
196	typedef struct
197	{
198	/* in */
199	RTR0PTR Address;
200	/* inout (Value.cb is in) */
201	PCIRAWMEMLOC Value;
202	} PCIRAWREQMMIOREAD;
203
204	/* Parameters buffer for PCIRAWR0_DO_PCICFG_WRITE call. */
205	typedef struct
206	{
207	/* in */
208	uint32_t iOffset;
209	PCIRAWMEMLOC Value;
210	} PCIRAWREQPCICFGWRITE;
211
212	/** Parameters buffer for PCIRAWR0_DO_PCICFG_READ call. */
213	typedef struct
214	{
215	/* in */
216	uint32_t iOffset;
217	/* inout (Value.cb is in) */
218	PCIRAWMEMLOC Value;
219	} PCIRAWREQPCICFGREAD;
220
221	/** Parameters buffer for PCIRAWR0_DO_GET_IRQ call. */
222	typedef struct PCIRAWREQGETIRQ
223	{
224	/* in */
225	int64_t iTimeout;
226	/* out */
227	int32_t iIrq;
228	} PCIRAWREQGETIRQ;
229
230	/** Parameters buffer for PCIRAWR0_DO_POWER_STATE_CHANGE call. */
231	typedef struct PCIRAWREQPOWERSTATECHANGE
232	{
233	/* in */
234	uint32_t iState;
235	/* in/out */
236	uint64_t u64Param;
237	} PCIRAWREQPOWERSTATECHANGE;
238
239	/**
240	* Request buffer use for communication with the driver.
241	*/
242	typedef struct PCIRAWSENDREQ
243	{
244	/** The request header. */
245	SUPVMMR0REQHDR Hdr;
246	/** Alternative to passing the taking the session from the VM handle.
247	* Either use this member or use the VM handle, don't do both.
248	*/
249	PSUPDRVSESSION pSession;
250	/** Request type. */
251	int32_t iRequest;
252	/** Host device request targetted to. */
253	PCIRAWDEVHANDLE TargetDevice;
254	/** Call parameters. */
255	union
256	{
257	PCIRAWREQOPENDEVICE aOpenDevice;
258	PCIRAWREQCLOSEDEVICE aCloseDevice;
259	PCIRAWREQGETREGIONINFO aGetRegionInfo;
260	PCIRAWREQMAPREGION aMapRegion;
261	PCIRAWREQUNMAPREGION aUnmapRegion;
262	PCIRAWREQPIOWRITE aPioWrite;
263	PCIRAWREQPIOREAD aPioRead;
264	PCIRAWREQMMIOWRITE aMmioWrite;
265	PCIRAWREQMMIOREAD aMmioRead;
266	PCIRAWREQPCICFGWRITE aPciCfgWrite;
267	PCIRAWREQPCICFGREAD aPciCfgRead;
268	PCIRAWREQGETIRQ aGetIrq;
269	PCIRAWREQPOWERSTATECHANGE aPowerStateChange;
270	} u;
271	} PCIRAWSENDREQ;
272	typedef PCIRAWSENDREQ *PPCIRAWSENDREQ;
273
274	/**
275	* Operations performed by the driver.
276	*/
277	typedef enum PCIRAWR0OPERATION
278	{
279	/* Open device. */
280	PCIRAWR0_DO_OPEN_DEVICE,
281	/* Close device. */
282	PCIRAWR0_DO_CLOSE_DEVICE,
283	/* Get PCI region info. */
284	PCIRAWR0_DO_GET_REGION_INFO,
285	/* Map PCI region into VM address space. */
286	PCIRAWR0_DO_MAP_REGION,
287	/* Unmap PCI region from VM address space. */
288	PCIRAWR0_DO_UNMAP_REGION,
289	/* Perform PIO write. */
290	PCIRAWR0_DO_PIO_WRITE,
291	/* Perform PIO read. */
292	PCIRAWR0_DO_PIO_READ,
293	/* Perform MMIO write. */
294	PCIRAWR0_DO_MMIO_WRITE,
295	/* Perform MMIO read. */
296	PCIRAWR0_DO_MMIO_READ,
297	/* Perform PCI config write. */
298	PCIRAWR0_DO_PCICFG_WRITE,
299	/* Perform PCI config read. */
300	PCIRAWR0_DO_PCICFG_READ,
301	/* Get next IRQ for the device. */
302	PCIRAWR0_DO_GET_IRQ,
303	/* Enable getting IRQs for the device. */
304	PCIRAWR0_DO_ENABLE_IRQ,
305	/* Disable getting IRQs for the device. */
306	PCIRAWR0_DO_DISABLE_IRQ,
307	/* Notify driver about guest power state change. */
308	PCIRAWR0_DO_POWER_STATE_CHANGE,
309	/** The usual 32-bit type blow up. */
310	PCIRAWR0_DO_32BIT_HACK = 0x7fffffff
311	} PCIRAWR0OPERATION;
312
313	/**
314	* Power state enumeration.
315	*/
316	typedef enum PCIRAWPOWERSTATE
317	{
318	/* Power on. */
319	PCIRAW_POWER_ON,
320	/* Power off. */
321	PCIRAW_POWER_OFF,
322	/* Suspend. */
323	PCIRAW_POWER_SUSPEND,
324	/* Resume. */
325	PCIRAW_POWER_RESUME,
326	/* Reset. */
327	PCIRAW_POWER_RESET,
328	/** The usual 32-bit type blow up. */
329	PCIRAW_POWER_32BIT_HACK = 0x7fffffff
330	} PCIRAWPOWERSTATE;
331
332
333	/** Forward declarations. */
334	typedef struct RAWPCIFACTORY *PRAWPCIFACTORY;
335	typedef struct RAWPCIDEVPORT *PRAWPCIDEVPORT;
336
337	/**
338	* Interrupt service routine callback.
339	*
340	* @param pvContext Opaque user data passed to the handler.
341	* @param iIrq Interrupt number.
342	*/
343	typedef DECLCALLBACK(void) FNRAWPCIISR(void *pvContext, int32_t iIrq);
344	typedef FNRAWPCIISR *PFNRAWPCIISR;
345
346	/**
347	* This is the port on the device interface, i.e. the driver side which the
348	* host device is connected to.
349	*
350	* This is only used for the in-kernel PCI device connections.
351	*/
352	typedef struct RAWPCIDEVPORT
353	{
354	/** Structure version number. (RAWPCIDEVPORT_VERSION) */
355	uint32_t u32Version;
356
357	/**
358	* Init device.
359	*
360	* @param pPort Pointer to this structure.
361	* @param fFlags Initialization flags.
362	*/
363	DECLR0CALLBACKMEMBER(int, pfnInit,(PRAWPCIDEVPORT pPort,
364	uint32_t fFlags));
365
366
367	/**
368	* Deinit device.
369	*
370	* @param pPort Pointer to this structure.
371	* @param fFlags Initialization flags.
372	*/
373	DECLR0CALLBACKMEMBER(int, pfnDeinit,(PRAWPCIDEVPORT pPort,
374	uint32_t fFlags));
375
376
377	/**
378	* Destroy device.
379	*
380	* @param pPort Pointer to this structure.
381	*/
382	DECLR0CALLBACKMEMBER(int, pfnDestroy,(PRAWPCIDEVPORT pPort));
383
384	/**
385	* Get PCI region info.
386	*
387	* @param pPort Pointer to this structure.
388	*/
389	DECLR0CALLBACKMEMBER(int, pfnGetRegionInfo,(PRAWPCIDEVPORT pPort,
390	int32_t iRegion,
391	RTHCPHYS *pRegionStart,
392	uint64_t *pu64RegionSize,
393	bool *pfPresent,
394	uint32_t *pfFlags));
395
396
397	/**
398	* Map PCI region.
399	*
400	* @param pPort Pointer to this structure.
401	*/
402	DECLR0CALLBACKMEMBER(int, pfnMapRegion,(PRAWPCIDEVPORT pPort,
403	int32_t iRegion,
404	RTHCPHYS RegionStart,
405	uint64_t u64RegionSize,
406	int32_t fFlags,
407	RTR0PTR *pRegionBaseR0));
408
409	/**
410	* Unmap PCI region.
411	*
412	* @param pPort Pointer to this structure.
413	*/
414	DECLR0CALLBACKMEMBER(int, pfnUnmapRegion,(PRAWPCIDEVPORT pPort,
415	int32_t iRegion,
416	RTHCPHYS RegionStart,
417	uint64_t u64RegionSize,
418	RTR0PTR RegionBase));
419
420	/**
421	* Read device PCI register.
422	*
423	* @param pPort Pointer to this structure.
424	* @param Register PCI register.
425	* @param pValue Read value (with desired read width).
426	*/
427	DECLR0CALLBACKMEMBER(int, pfnPciCfgRead,(PRAWPCIDEVPORT pPort,
428	uint32_t Register,
429	PCIRAWMEMLOC *pValue));
430
431
432	/**
433	* Write device PCI register.
434	*
435	* @param pPort Pointer to this structure.
436	* @param Register PCI register.
437	* @param pValue Write value (with desired write width).
438	*/
439	DECLR0CALLBACKMEMBER(int, pfnPciCfgWrite,(PRAWPCIDEVPORT pPort,
440	uint32_t Register,
441	PCIRAWMEMLOC *pValue));
442
443	/**
444	* Request to register interrupt handler.
445	*
446	* @param pPort Pointer to this structure.
447	* @param pfnHandler Pointer to the handler.
448	* @param pIrqContext Context passed to the handler.
449	* @param phIsr Handle for the ISR, .
450	*/
451	DECLR0CALLBACKMEMBER(int, pfnRegisterIrqHandler,(PRAWPCIDEVPORT pPort,
452	PFNRAWPCIISR pfnHandler,
453	void* pIrqContext,
454	PCIRAWISRHANDLE *phIsr));
455
456	/**
457	* Request to unregister interrupt handler.
458	*
459	* @param pPort Pointer to this structure.
460	* @param hIsr Handle of ISR to unregister (retured by earlier pfnRegisterIrqHandler).
461	*/
462	DECLR0CALLBACKMEMBER(int, pfnUnregisterIrqHandler,(PRAWPCIDEVPORT pPort,
463	PCIRAWISRHANDLE hIsr));
464
465	/**
466	* Power state change notification.
467	*
468	* @param pPort Pointer to this structure.
469	* @param aState New power state.
470	* @param pu64Param State-specific in/out parameter.
471	*/
472	DECLR0CALLBACKMEMBER(int, pfnPowerStateChange,(PRAWPCIDEVPORT pPort,
473	PCIRAWPOWERSTATE aState,
474	uint64_t *pu64Param));
475
476	/** Structure version number. (RAWPCIDEVPORT_VERSION) */
477	uint32_t u32VersionEnd;
478	} RAWPCIDEVPORT;
479	/** Version number for the RAWPCIDEVPORT::u32Version and RAWPCIIFPORT::u32VersionEnd fields. */
480	#define RAWPCIDEVPORT_VERSION UINT32_C(0xAFBDCC02)
481
482	/**
483	* The component factory interface for create a raw PCI interfaces.
484	*/
485	typedef struct RAWPCIFACTORY
486	{
487	/**
488	* Release this factory.
489	*
490	* SUPR0ComponentQueryFactory (SUPDRVFACTORY::pfnQueryFactoryInterface to be precise)
491	* will retain a reference to the factory and the caller has to call this method to
492	* release it once the pfnCreateAndConnect call(s) has been done.
493	*
494	* @param pIfFactory Pointer to this structure.
495	*/
496	DECLR0CALLBACKMEMBER(void, pfnRelease,(PRAWPCIFACTORY pFactory));
497
498	/**
499	* Create an instance for the specfied host PCI card and connects it
500	* to the driver.
501	*
502	*
503	* @returns VBox status code.
504	*
505	* @param pIfFactory Pointer to this structure.
506	* @param u32HostAddress Address of PCI device on the host.
507	* @param fFlags Creation flags.
508	* @param pVmCtx Context of VM where device is created.
509	* @param ppDevPort Where to store the pointer to the device port
510	* on success.
511	*
512	*/
513	DECLR0CALLBACKMEMBER(int, pfnCreateAndConnect,(PRAWPCIFACTORY pFactory,
514	uint32_t u32HostAddress,
515	uint32_t fFlags,
516	PRAWPCIPERVM pVmCtx,
517	PRAWPCIDEVPORT *ppDevPort,
518	uint32_t *pfDevFlags));
519
520
521	/**
522	* Initialize per-VM data related to PCI passthrough.
523	*
524	* @returns VBox status code.
525	*
526	* @param pIfFactory Pointer to this structure.
527	* @param pVM Pointer to VM structure to initialize.
528	* @param pPciData Pointer to PCI data.
529	*/
530	DECLR0CALLBACKMEMBER(int, pfnInitVm,(PRAWPCIFACTORY pFactory,
531	PVM pVM,
532	PRAWPCIPERVM pPciData));
533
534	/**
535	* Deinitialize per-VM data related to PCI passthrough.
536	*
537	* @returns VBox status code.
538	*
539	* @param pIfFactory Pointer to this structure.
540	* @param pVM Pointer to VM structure to deinitialize.
541	* @param pPciData Pointer to PCI data.
542	*/
543	DECLR0CALLBACKMEMBER(void, pfnDeinitVm,(PRAWPCIFACTORY pFactory,
544	PVM pVM,
545	PRAWPCIPERVM pPciData));
546	} RAWPCIFACTORY;
547
548	#define RAWPCIFACTORY_UUID_STR "ea089839-4171-476f-adfb-9e7ab1cbd0fb"
549
550	/**
551	* Flags passed to pfnPciDeviceConstructStart(), to notify driver
552	* about options to be used to open device.
553	*/
554	typedef enum PCIRAWDRIVERFLAGS
555	{
556	/** If runtime shall try to detach host driver. */
557	PCIRAWDRIVERRFLAG_DETACH_HOST_DRIVER = (1 << 0),
558	/** The usual 32-bit type blow up. */
559	PCIRAWDRIVERRFLAG_32BIT_HACK = 0x7fffffff
560	} PCIRAWDRIVERFLAGS;
561
562	/**
563	* Flags used to describe PCI region, matches to PCIADDRESSSPACE
564	* in pci.h.
565	*/
566	typedef enum PCIRAWADDRESSSPACE
567	{
568	/** Memory. */
569	PCIRAW_ADDRESS_SPACE_MEM = 0x00,
570	/** I/O space. */
571	PCIRAW_ADDRESS_SPACE_IO = 0x01,
572	/** 32-bit BAR. */
573	PCIRAW_ADDRESS_SPACE_BAR32 = 0x00,
574	/** 64-bit BAR. */
575	PCIRAW_ADDRESS_SPACE_BAR64 = 0x04,
576	/** Prefetch memory. */
577	PCIRAW_ADDRESS_SPACE_MEM_PREFETCH = 0x08,
578	/** The usual 32-bit type blow up. */
579	PCIRAW_ADDRESS_SPACE_32BIT_HACK = 0x7fffffff
580	} PCIRAWADDRESSSPACE;
581
582	RT_C_DECLS_END
583
584	#endif

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