VirtualBox

source: vbox/trunk/include/VBox/pgm.h@ 8112

Last change on this file since 8112 was 8112, checked in by vboxsync, 17 years ago

Another attempt at a proper check. (init order messed up the previous one)

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File size: 25.3 KB
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1/** @file
2 * PGM - Page Monitor/Monitor.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_pgm_h
27#define ___VBox_pgm_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/sup.h>
32#include <VBox/vmapi.h>
33#include <VBox/x86.h>
34
35__BEGIN_DECLS
36
37/** @defgroup grp_pgm The Page Monitor/Manager API
38 * @{
39 */
40
41/* remove after fixing the switcher */
42#define PGM_WITH_BROKEN_32PAE_SWITCHER
43
44/** Chunk size for dynamically allocated physical memory. */
45#define PGM_DYNAMIC_CHUNK_SIZE (1*1024*1024)
46/** Shift GC physical address by 20 bits to get the offset into the pvHCChunkHC array. */
47#define PGM_DYNAMIC_CHUNK_SHIFT 20
48/** Dynamic chunk offset mask. */
49#define PGM_DYNAMIC_CHUNK_OFFSET_MASK 0xfffff
50/** Dynamic chunk base mask. */
51#define PGM_DYNAMIC_CHUNK_BASE_MASK (~(RTGCPHYS)PGM_DYNAMIC_CHUNK_OFFSET_MASK)
52
53
54/** Page flags used for PGMHyperSetPageFlags
55 * @deprecated
56 * @{ */
57#define PGMPAGE_READ 1
58#define PGMPAGE_WRITE 2
59#define PGMPAGE_USER 4
60#define PGMPAGE_SYSTEM 8
61#define PGMPAGE_NOTPRESENT 16
62/** @} */
63
64
65/**
66 * FNPGMRELOCATE callback mode.
67 */
68typedef enum PGMRELOCATECALL
69{
70 /** The callback is for checking if the suggested address is suitable. */
71 PGMRELOCATECALL_SUGGEST = 1,
72 /** The callback is for executing the relocation. */
73 PGMRELOCATECALL_RELOCATE
74} PGMRELOCATECALL;
75
76
77/**
78 * Callback function which will be called when PGM is trying to find
79 * a new location for the mapping.
80 *
81 * The callback is called in two modes, 1) the check mode and 2) the relocate mode.
82 * In 1) the callback should say if it objects to a suggested new location. If it
83 * accepts the new location, it is called again for doing it's relocation.
84 *
85 *
86 * @returns true if the location is ok.
87 * @returns false if another location should be found.
88 * @param GCPtrOld The old virtual address.
89 * @param GCPtrNew The new virtual address.
90 * @param enmMode Used to indicate the callback mode.
91 * @param pvUser User argument.
92 * @remark The return value is no a failure indicator, it's an acceptance
93 * indicator. Relocation can not fail!
94 */
95typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
96/** Pointer to a relocation callback function. */
97typedef FNPGMRELOCATE *PFNPGMRELOCATE;
98
99
100/**
101 * Physical page access handler type.
102 */
103typedef enum PGMPHYSHANDLERTYPE
104{
105 /** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
106 PGMPHYSHANDLERTYPE_MMIO = 1,
107 /** Handler all write access to a physical page range. */
108 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
109 /** Handler all access to a physical page range. */
110 PGMPHYSHANDLERTYPE_PHYSICAL_ALL
111
112} PGMPHYSHANDLERTYPE;
113
114/**
115 * \#PF Handler callback for physical access handler ranges (MMIO among others) in GC.
116 *
117 * @returns VBox status code (appropriate for GC return).
118 * @param pVM VM Handle.
119 * @param uErrorCode CPU Error code.
120 * @param pRegFrame Trap register frame.
121 * NULL on DMA and other non CPU access.
122 * @param pvFault The fault address (cr2).
123 * @param GCPhysFault The GC physical address corresponding to pvFault.
124 * @param pvUser User argument.
125 */
126typedef DECLCALLBACK(int) FNPGMGCPHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
127/** Pointer to PGM access callback. */
128typedef FNPGMGCPHYSHANDLER *PFNPGMGCPHYSHANDLER;
129
130/**
131 * \#PF Handler callback for physical access handler ranges (MMIO among others) in R0.
132 *
133 * @returns VBox status code (appropriate for GC return).
134 * @param pVM VM Handle.
135 * @param uErrorCode CPU Error code.
136 * @param pRegFrame Trap register frame.
137 * NULL on DMA and other non CPU access.
138 * @param pvFault The fault address (cr2).
139 * @param GCPhysFault The GC physical address corresponding to pvFault.
140 * @param pvUser User argument.
141 */
142typedef DECLCALLBACK(int) FNPGMR0PHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
143/** Pointer to PGM access callback. */
144typedef FNPGMR0PHYSHANDLER *PFNPGMR0PHYSHANDLER;
145
146/**
147 * Guest Access type
148 */
149typedef enum PGMACCESSTYPE
150{
151 /** Read access. */
152 PGMACCESSTYPE_READ = 1,
153 /** Write access. */
154 PGMACCESSTYPE_WRITE
155} PGMACCESSTYPE;
156
157/**
158 * \#PF Handler callback for physical access handler ranges (MMIO among others) in HC.
159 *
160 * The handler can not raise any faults, it's mainly for monitoring write access
161 * to certain pages.
162 *
163 * @returns VINF_SUCCESS if the handler have carried out the operation.
164 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
165 * @param pVM VM Handle.
166 * @param GCPhys The physical address the guest is writing to.
167 * @param pvPhys The HC mapping of that address.
168 * @param pvBuf What the guest is reading/writing.
169 * @param cbBuf How much it's reading/writing.
170 * @param enmAccessType The access type.
171 * @param pvUser User argument.
172 */
173typedef DECLCALLBACK(int) FNPGMR3PHYSHANDLER(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
174/** Pointer to PGM access callback. */
175typedef FNPGMR3PHYSHANDLER *PFNPGMR3PHYSHANDLER;
176
177
178/**
179 * Virtual access handler type.
180 */
181typedef enum PGMVIRTHANDLERTYPE
182{
183 /** Write access handled. */
184 PGMVIRTHANDLERTYPE_WRITE = 1,
185 /** All access handled. */
186 PGMVIRTHANDLERTYPE_ALL,
187 /** Hypervisor write access handled.
188 * This is used to catch the guest trying to write to LDT, TSS and any other
189 * system structure which the brain dead intel guys let unprivilegde code find. */
190 PGMVIRTHANDLERTYPE_HYPERVISOR
191} PGMVIRTHANDLERTYPE;
192
193/**
194 * \#PF Handler callback for virtual access handler ranges.
195 *
196 * Important to realize that a physical page in a range can have aliases, and
197 * for ALL and WRITE handlers these will also trigger.
198 *
199 * @returns VBox status code (appropriate for GC return).
200 * @param pVM VM Handle.
201 * @param uErrorCode CPU Error code.
202 * @param pRegFrame Trap register frame.
203 * @param pvFault The fault address (cr2).
204 * @param pvRange The base address of the handled virtual range.
205 * @param offRange The offset of the access into this range.
206 * (If it's a EIP range this's the EIP, if not it's pvFault.)
207 */
208typedef DECLCALLBACK(int) FNPGMGCVIRTHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
209/** Pointer to PGM access callback. */
210typedef FNPGMGCVIRTHANDLER *PFNPGMGCVIRTHANDLER;
211
212/**
213 * \#PF Handler callback for virtual access handler ranges.
214 *
215 * Important to realize that a physical page in a range can have aliases, and
216 * for ALL and WRITE handlers these will also trigger.
217 *
218 * @returns VINF_SUCCESS if the handler have carried out the operation.
219 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
220 * @param pVM VM Handle.
221 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
222 * @param pvPtr The HC mapping of that address.
223 * @param pvBuf What the guest is reading/writing.
224 * @param cbBuf How much it's reading/writing.
225 * @param enmAccessType The access type.
226 * @param pvUser User argument.
227 */
228typedef DECLCALLBACK(int) FNPGMHCVIRTHANDLER(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
229/** Pointer to PGM access callback. */
230typedef FNPGMHCVIRTHANDLER *PFNPGMHCVIRTHANDLER;
231
232
233/**
234 * \#PF Handler callback for invalidation of virtual access handler ranges.
235 *
236 * @param pVM VM Handle.
237 * @param GCPtr The virtual address the guest has changed.
238 */
239typedef DECLCALLBACK(int) FNPGMHCVIRTINVALIDATE(PVM pVM, RTGCPTR GCPtr);
240/** Pointer to PGM invalidation callback. */
241typedef FNPGMHCVIRTINVALIDATE *PFNPGMHCVIRTINVALIDATE;
242
243/**
244 * Paging mode.
245 */
246typedef enum PGMMODE
247{
248 /** The usual invalid value. */
249 PGMMODE_INVALID = 0,
250 /** Real mode. */
251 PGMMODE_REAL,
252 /** Protected mode, no paging. */
253 PGMMODE_PROTECTED,
254 /** 32-bit paging. */
255 PGMMODE_32_BIT,
256 /** PAE paging. */
257 PGMMODE_PAE,
258 /** PAE paging with NX enabled. */
259 PGMMODE_PAE_NX,
260 /** 64-bit AMD paging (long mode). */
261 PGMMODE_AMD64,
262 /** 64-bit AMD paging (long mode) with NX enabled. */
263 PGMMODE_AMD64_NX,
264 /** The max number of modes */
265 PGMMODE_MAX,
266 /** 32bit hackishness. */
267 PGMMODE_32BIT_HACK = 0x7fffffff
268} PGMMODE;
269
270/**
271 * The current ROM page protection.
272 */
273typedef enum PGMROMPROT
274{
275 /** The customary invalid value. */
276 PGMROMPROT_INVALID = 0,
277 /** Read from the virgin ROM page, ignore writes.
278 * Map the virgin page, use write access handler to ignore writes. */
279 PGMROMPROT_READ_ROM_WRITE_IGNORE,
280 /** Read from the virgin ROM page, write to the shadow RAM.
281 * Map the virgin page, use write access handler change the RAM. */
282 PGMROMPROT_READ_ROM_WRITE_RAM,
283 /** Read from the shadow ROM page, ignore writes.
284 * Map the shadow page read-only, use write access handler to ignore writes. */
285 PGMROMPROT_READ_RAM_WRITE_IGNORE,
286 /** Read from the shadow ROM page, ignore writes.
287 * Map the shadow page read-write, disabled write access handler. */
288 PGMROMPROT_READ_RAM_WRITE_RAM,
289 /** The end of valid values. */
290 PGMROMPROT_END,
291 /** The usual 32-bit type size hack. */
292 PGMROMPROT_32BIT_HACK = 0x7fffffff
293} PGMROMPROT;
294
295/**
296 * Is the ROM mapped (true) or is the shadow RAM mapped (false).
297 *
298 * @returns boolean.
299 * @param enmProt The PGMROMPROT value, must be valid.
300 */
301#define PGMROMPROT_IS_ROM(enmProt) \
302 ( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
303 || (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
304
305
306PGMDECL(uint32_t) PGMGetHyperCR3(PVM pVM);
307PGMDECL(uint32_t) PGMGetHyper32BitCR3(PVM pVM);
308PGMDECL(uint32_t) PGMGetHyperPaeCR3(PVM pVM);
309PGMDECL(uint32_t) PGMGetHyperAmd64CR3(PVM pVM);
310PGMDECL(uint32_t) PGMGetInterHCCR3(PVM pVM);
311PGMDECL(uint32_t) PGMGetInterGCCR3(PVM pVM);
312PGMDECL(uint32_t) PGMGetInter32BitCR3(PVM pVM);
313PGMDECL(uint32_t) PGMGetInterPaeCR3(PVM pVM);
314PGMDECL(uint32_t) PGMGetInterAmd64CR3(PVM pVM);
315PGMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
316PGMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage);
317PGMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess);
318PGMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess);
319PGMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
320PGMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
321PGMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
322PGMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
323PGMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
324PGMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
325PGMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
326PGMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
327PGMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr);
328PGMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
329PGMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
330PGMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal);
331PGMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
332PGMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer);
333PGMDECL(PGMMODE) PGMGetGuestMode(PVM pVM);
334PGMDECL(PGMMODE) PGMGetShadowMode(PVM pVM);
335PGMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
336PGMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
337PGMDECL(int) PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
338 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
339 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
340 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC, RTGCPTR pvUserGC,
341 R3PTRTYPE(const char *) pszDesc);
342PGMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
343PGMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
344PGMDECL(int) PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
345 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
346 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
347 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC, RTGCPTR pvUserGC,
348 R3PTRTYPE(const char *) pszDesc);
349PGMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
350PGMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
351PGMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
352PGMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
353PGMDECL(int) PGMHandlerPhysicalPageReset(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
354PGMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
355PGMDECL(bool) PGMPhysIsA20Enabled(PVM pVM);
356PGMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
357PGMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
358PGMDECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
359PGMDECL(int) PGMPhysGCPtr2GCPhys(PVM pVM, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
360PGMDECL(int) PGMPhysGCPtr2HCPhys(PVM pVM, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
361PDMDECL(void) PGMPhysInvalidatePageGCMapTLB(PVM pVM);
362PDMDECL(void) PGMPhysInvalidatePageR0MapTLB(PVM pVM);
363PDMDECL(void) PGMPhysInvalidatePageR3MapTLB(PVM pVM);
364
365/**
366 * Page mapping lock.
367 *
368 * @remarks This doesn't work in structures shared between
369 * ring-3, ring-0 and/or GC.
370 */
371typedef struct PGMPAGEMAPLOCK
372{
373 /** @todo see PGMPhysIsPageMappingLockValid for possibly incorrect assumptions */
374#ifdef IN_GC
375 /** Just a dummy for the time being. */
376 uint32_t u32Dummy;
377#else
378 /** Pointer to the PGMPAGE. */
379 void *pvPage;
380 /** Pointer to the PGMCHUNKR3MAP. */
381 void *pvMap;
382#endif
383} PGMPAGEMAPLOCK;
384/** Pointer to a page mapping lock. */
385typedef PGMPAGEMAPLOCK *PPGMPAGEMAPLOCK;
386
387PGMDECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
388PGMDECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
389PGMDECL(int) PGMPhysGCPtr2CCPtr(PVM pVM, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
390PGMDECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVM pVM, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
391PGMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
392
393/**
394 * Checks if the lock structure is valid
395 *
396 * @param pVM The VM handle.
397 * @param pLock The lock structure initialized by the mapping function.
398 */
399DECLINLINE(bool) PGMPhysIsPageMappingLockValid(PVM pVM, PPGMPAGEMAPLOCK pLock)
400{
401 /** @todo -> complete/change this */
402#ifdef IN_GC
403 return !!(pLock->u32Dummy);
404#else
405 return !!(pLock->pvPage);
406#endif
407}
408
409PGMDECL(int) PGMPhysGCPhys2HCPtr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTHCPTR pHCPtr);
410PGMDECL(int) PGMPhysGCPtr2HCPtr(PVM pVM, RTGCPTR GCPtr, PRTHCPTR pHCPtr);
411PGMDECL(int) PGMPhysGCPtr2HCPtrByGstCR3(PVM pVM, RTGCPTR GCPtr, uint64_t cr3, unsigned fFlags, PRTHCPTR pHCPtr);
412PGMDECL(void) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
413PGMDECL(void) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
414#ifndef IN_GC /* Only ring 0 & 3. */
415PGMDECL(int) PGMPhysReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
416PGMDECL(int) PGMPhysWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
417PGMDECL(int) PGMPhysReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
418PGMDECL(int) PGMPhysWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
419PGMDECL(int) PGMPhysReadGCPtrSafe(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
420PGMDECL(int) PGMPhysWriteGCPtrSafe(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
421PGMDECL(int) PGMPhysWriteGCPtrDirty(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
422PGMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
423#endif /* !IN_GC */
424PGMDECL(int) PGMPhysInterpretedRead(PVM pVM, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb);
425#ifdef VBOX_STRICT
426PGMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
427PGMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
428PGMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4);
429#endif /* VBOX_STRICT */
430
431
432#ifdef IN_GC
433/** @defgroup grp_pgm_gc The PGM Guest Context API
434 * @ingroup grp_pgm
435 * @{
436 */
437PGMGCDECL(int) PGMGCDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv);
438PGMGCDECL(int) PGMGCDynMapGCPageEx(PVM pVM, RTGCPHYS GCPhys, void **ppv);
439PGMGCDECL(int) PGMGCDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv);
440PGMGCDECL(int) PGMGCInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
441/** @} */
442#endif /* IN_GC */
443
444
445#ifdef IN_RING0
446/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
447 * @ingroup grp_pgm
448 * @{
449 */
450PGMR0DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM);
451/** @} */
452#endif /* IN_RING0 */
453
454
455
456#ifdef IN_RING3
457/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
458 * @ingroup grp_pgm
459 * @{
460 */
461PGMR3DECL(int) PGMR3Init(PVM pVM);
462PGMR3DECL(int) PGMR3InitDynMap(PVM pVM);
463PGMR3DECL(int) PGMR3InitFinalize(PVM pVM);
464PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
465PGMR3DECL(void) PGMR3Reset(PVM pVM);
466PGMR3DECL(int) PGMR3Term(PVM pVM);
467PDMR3DECL(int) PGMR3LockCall(PVM pVM);
468PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable);
469#ifndef VBOX_WITH_NEW_PHYS_CODE
470PGMR3DECL(int) PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS GCPhys);
471#endif /* !VBOX_WITH_NEW_PHYS_CODE */
472PGMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
473PDMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
474 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
475 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
476 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC, RTGCPTR pvUserGC,
477 R3PTRTYPE(const char *) pszDesc);
478PDMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
479PDMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc);
480PDMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
481PDMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
482PDMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
483PDMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
484PDMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
485
486/** @group PGMR3PhysRegisterRom flags.
487 * @{ */
488/** Inidicates that ROM shadowing should be enabled. */
489#define PGMPHYS_ROM_FLAG_SHADOWED RT_BIT_32(0)
490/** Indicates that what pvBinary points to won't go away
491 * and can be used for strictness checks. */
492#define PGMPHYS_ROM_FLAG_PERMANENT_BINARY RT_BIT_32(1)
493/** @} */
494
495PGMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
496 const void *pvBinary, uint32_t fFlags, const char *pszDesc);
497PGMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
498PGMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
499#ifndef VBOX_WITH_NEW_PHYS_CODE
500PGMR3DECL(int) PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
501#endif /* !VBOX_WITH_NEW_PHYS_CODE */
502PGMR3DECL(int) PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask);
503PGMDECL(void) PGMR3PhysSetA20(PVM pVM, bool fEnable);
504PGMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc);
505PGMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
506PGMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
507PGMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
508PGMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
509PGMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
510PGMR3DECL(bool) PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0);
511PGMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
512PGMR3DECL(int) PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
513 PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
514 const char *pszModR0, const char *pszHandlerR0, RTR0PTR pvUserR0,
515 const char *pszModGC, const char *pszHandlerGC, RTGCPTR pvUserGC, const char *pszDesc);
516PGMDECL(int) PGMHandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
517 PFNPGMHCVIRTINVALIDATE pfnInvalidateHC,
518 PFNPGMHCVIRTHANDLER pfnHandlerHC, RTGCPTR pfnHandlerGC,
519 R3PTRTYPE(const char *) pszDesc);
520PGMR3DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
521 PFNPGMHCVIRTINVALIDATE pfnInvalidateHC,
522 PFNPGMHCVIRTHANDLER pfnHandlerHC,
523 const char *pszHandlerGC, const char *pszModGC, const char *pszDesc);
524PGMDECL(int) PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, PFNPGMHCVIRTINVALIDATE pfnInvalidateHC);
525PGMDECL(int) PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
526PDMR3DECL(int) PGMR3PoolGrow(PVM pVM);
527#ifdef ___VBox_dbgf_h /** @todo fix this! */
528PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
529#endif
530PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch);
531
532/** @todo r=bird: s/Byte/U8/ s/Word/U16/ s/Dword/U32/ to match other functions names and returned types. */
533PGMR3DECL(uint8_t) PGMR3PhysReadByte(PVM pVM, RTGCPHYS GCPhys);
534PGMR3DECL(uint16_t) PGMR3PhysReadWord(PVM pVM, RTGCPHYS GCPhys);
535PGMR3DECL(uint32_t) PGMR3PhysReadDword(PVM pVM, RTGCPHYS GCPhys);
536PGMR3DECL(void) PGMR3PhysWriteByte(PVM pVM, RTGCPHYS GCPhys, uint8_t val);
537PGMR3DECL(void) PGMR3PhysWriteWord(PVM pVM, RTGCPHYS GCPhys, uint16_t val);
538PGMR3DECL(void) PGMR3PhysWriteDword(PVM pVM, RTGCPHYS GCPhys, uint32_t val);
539PDMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
540PGMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
541PDMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
542
543PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
544
545PGMR3DECL(int) PGMR3DbgHCPtr2GCPhys(PVM pVM, RTHCPTR HCPtr, PRTGCPHYS pGCPhys);
546PGMR3DECL(int) PGMR3DbgHCPtr2HCPhys(PVM pVM, RTHCPTR HCPtr, PRTHCPHYS pHCPhys);
547PGMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
548PDMR3DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
549PDMR3DECL(int) PGMR3DbgScanVirtual(PVM pVM, RTGCUINTPTR GCPtr, RTGCUINTPTR cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
550/** @} */
551#endif /* IN_RING3 */
552
553__END_DECLS
554
555/** @} */
556#endif
557
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