| 1 | /** @file
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| 2 | * PGM - Page Monitor / Monitor.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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| 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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| 24 | *
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| 25 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 26 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 27 | * additional information or have any questions.
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| 28 | */
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| 29 |
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| 30 | #ifndef ___VBox_pgm_h
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| 31 | #define ___VBox_pgm_h
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| 32 |
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| 33 | #include <VBox/cdefs.h>
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| 34 | #include <VBox/types.h>
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| 35 | #include <VBox/sup.h>
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| 36 | #include <VBox/vmapi.h>
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| 37 | #include <VBox/x86.h>
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| 38 | #include <VBox/hwacc_vmx.h>
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| 39 |
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| 40 | __BEGIN_DECLS
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| 41 |
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| 42 | /** @defgroup grp_pgm The Page Monitor / Manager API
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| 43 | * @{
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| 44 | */
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| 45 |
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| 46 | /** Chunk size for dynamically allocated physical memory. */
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| 47 | #define PGM_DYNAMIC_CHUNK_SIZE (1*1024*1024)
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| 48 | /** Shift GC physical address by 20 bits to get the offset into the pvHCChunkHC array. */
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| 49 | #define PGM_DYNAMIC_CHUNK_SHIFT 20
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| 50 | /** Dynamic chunk offset mask. */
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| 51 | #define PGM_DYNAMIC_CHUNK_OFFSET_MASK 0xfffff
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| 52 | /** Dynamic chunk base mask. */
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| 53 | #define PGM_DYNAMIC_CHUNK_BASE_MASK (~(RTGCPHYS)PGM_DYNAMIC_CHUNK_OFFSET_MASK)
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| 54 |
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| 55 |
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| 56 | /**
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| 57 | * FNPGMRELOCATE callback mode.
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| 58 | */
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| 59 | typedef enum PGMRELOCATECALL
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| 60 | {
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| 61 | /** The callback is for checking if the suggested address is suitable. */
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| 62 | PGMRELOCATECALL_SUGGEST = 1,
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| 63 | /** The callback is for executing the relocation. */
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| 64 | PGMRELOCATECALL_RELOCATE
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| 65 | } PGMRELOCATECALL;
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| 66 |
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| 67 |
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| 68 | /**
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| 69 | * Callback function which will be called when PGM is trying to find
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| 70 | * a new location for the mapping.
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| 71 | *
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| 72 | * The callback is called in two modes, 1) the check mode and 2) the relocate mode.
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| 73 | * In 1) the callback should say if it objects to a suggested new location. If it
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| 74 | * accepts the new location, it is called again for doing it's relocation.
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| 75 | *
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| 76 | *
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| 77 | * @returns true if the location is ok.
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| 78 | * @returns false if another location should be found.
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| 79 | * @param GCPtrOld The old virtual address.
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| 80 | * @param GCPtrNew The new virtual address.
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| 81 | * @param enmMode Used to indicate the callback mode.
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| 82 | * @param pvUser User argument.
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| 83 | * @remark The return value is no a failure indicator, it's an acceptance
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| 84 | * indicator. Relocation can not fail!
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| 85 | */
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| 86 | typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
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| 87 | /** Pointer to a relocation callback function. */
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| 88 | typedef FNPGMRELOCATE *PFNPGMRELOCATE;
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| 89 |
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| 90 |
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| 91 | /**
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| 92 | * Physical page access handler type.
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| 93 | */
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| 94 | typedef enum PGMPHYSHANDLERTYPE
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| 95 | {
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| 96 | /** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
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| 97 | PGMPHYSHANDLERTYPE_MMIO = 1,
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| 98 | /** Handler all write access to a physical page range. */
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| 99 | PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
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| 100 | /** Handler all access to a physical page range. */
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| 101 | PGMPHYSHANDLERTYPE_PHYSICAL_ALL
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| 102 |
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| 103 | } PGMPHYSHANDLERTYPE;
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| 104 |
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| 105 | /**
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| 106 | * \#PF Handler callback for physical access handler ranges in RC.
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| 107 | *
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| 108 | * @returns VBox status code (appropriate for RC return).
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| 109 | * @param pVM VM Handle.
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| 110 | * @param uErrorCode CPU Error code.
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| 111 | * @param pRegFrame Trap register frame.
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| 112 | * NULL on DMA and other non CPU access.
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| 113 | * @param pvFault The fault address (cr2).
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| 114 | * @param GCPhysFault The GC physical address corresponding to pvFault.
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| 115 | * @param pvUser User argument.
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| 116 | */
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| 117 | typedef DECLCALLBACK(int) FNPGMRCPHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
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| 118 | /** Pointer to PGM access callback. */
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| 119 | typedef FNPGMRCPHYSHANDLER *PFNPGMRCPHYSHANDLER;
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| 120 |
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| 121 | /**
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| 122 | * \#PF Handler callback for physical access handler ranges in R0.
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| 123 | *
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| 124 | * @returns VBox status code (appropriate for R0 return).
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| 125 | * @param pVM VM Handle.
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| 126 | * @param uErrorCode CPU Error code.
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| 127 | * @param pRegFrame Trap register frame.
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| 128 | * NULL on DMA and other non CPU access.
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| 129 | * @param pvFault The fault address (cr2).
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| 130 | * @param GCPhysFault The GC physical address corresponding to pvFault.
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| 131 | * @param pvUser User argument.
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| 132 | */
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| 133 | typedef DECLCALLBACK(int) FNPGMR0PHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
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| 134 | /** Pointer to PGM access callback. */
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| 135 | typedef FNPGMR0PHYSHANDLER *PFNPGMR0PHYSHANDLER;
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| 136 |
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| 137 | /**
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| 138 | * Guest Access type
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| 139 | */
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| 140 | typedef enum PGMACCESSTYPE
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| 141 | {
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| 142 | /** Read access. */
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| 143 | PGMACCESSTYPE_READ = 1,
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| 144 | /** Write access. */
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| 145 | PGMACCESSTYPE_WRITE
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| 146 | } PGMACCESSTYPE;
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| 147 |
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| 148 | /**
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| 149 | * \#PF Handler callback for physical access handler ranges (MMIO among others) in HC.
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| 150 | *
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| 151 | * The handler can not raise any faults, it's mainly for monitoring write access
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| 152 | * to certain pages.
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| 153 | *
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| 154 | * @returns VINF_SUCCESS if the handler have carried out the operation.
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| 155 | * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
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| 156 | * @param pVM VM Handle.
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| 157 | * @param GCPhys The physical address the guest is writing to.
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| 158 | * @param pvPhys The HC mapping of that address.
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| 159 | * @param pvBuf What the guest is reading/writing.
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| 160 | * @param cbBuf How much it's reading/writing.
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| 161 | * @param enmAccessType The access type.
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| 162 | * @param pvUser User argument.
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| 163 | */
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| 164 | typedef DECLCALLBACK(int) FNPGMR3PHYSHANDLER(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
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| 165 | /** Pointer to PGM access callback. */
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| 166 | typedef FNPGMR3PHYSHANDLER *PFNPGMR3PHYSHANDLER;
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| 167 |
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| 168 |
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| 169 | /**
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| 170 | * Virtual access handler type.
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| 171 | */
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| 172 | typedef enum PGMVIRTHANDLERTYPE
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| 173 | {
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| 174 | /** Write access handled. */
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| 175 | PGMVIRTHANDLERTYPE_WRITE = 1,
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| 176 | /** All access handled. */
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| 177 | PGMVIRTHANDLERTYPE_ALL,
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| 178 | /** Hypervisor write access handled.
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| 179 | * This is used to catch the guest trying to write to LDT, TSS and any other
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| 180 | * system structure which the brain dead intel guys let unprivilegde code find. */
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| 181 | PGMVIRTHANDLERTYPE_HYPERVISOR
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| 182 | } PGMVIRTHANDLERTYPE;
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| 183 |
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| 184 | /**
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| 185 | * \#PF Handler callback for virtual access handler ranges, RC.
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| 186 | *
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| 187 | * Important to realize that a physical page in a range can have aliases, and
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| 188 | * for ALL and WRITE handlers these will also trigger.
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| 189 | *
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| 190 | * @returns VBox status code (appropriate for GC return).
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| 191 | * @param pVM VM Handle.
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| 192 | * @param uErrorCode CPU Error code.
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| 193 | * @param pRegFrame Trap register frame.
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| 194 | * @param pvFault The fault address (cr2).
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| 195 | * @param pvRange The base address of the handled virtual range.
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| 196 | * @param offRange The offset of the access into this range.
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| 197 | * (If it's a EIP range this's the EIP, if not it's pvFault.)
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| 198 | */
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| 199 | typedef DECLCALLBACK(int) FNPGMRCVIRTHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
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| 200 | /** Pointer to PGM access callback. */
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| 201 | typedef FNPGMRCVIRTHANDLER *PFNPGMRCVIRTHANDLER;
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| 202 |
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| 203 | /**
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| 204 | * \#PF Handler callback for virtual access handler ranges, R3.
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| 205 | *
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| 206 | * Important to realize that a physical page in a range can have aliases, and
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| 207 | * for ALL and WRITE handlers these will also trigger.
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| 208 | *
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| 209 | * @returns VINF_SUCCESS if the handler have carried out the operation.
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| 210 | * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
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| 211 | * @param pVM VM Handle.
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| 212 | * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
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| 213 | * @param pvPtr The HC mapping of that address.
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| 214 | * @param pvBuf What the guest is reading/writing.
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| 215 | * @param cbBuf How much it's reading/writing.
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| 216 | * @param enmAccessType The access type.
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| 217 | * @param pvUser User argument.
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| 218 | */
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| 219 | typedef DECLCALLBACK(int) FNPGMR3VIRTHANDLER(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
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| 220 | /** Pointer to PGM access callback. */
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| 221 | typedef FNPGMR3VIRTHANDLER *PFNPGMR3VIRTHANDLER;
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| 222 |
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| 223 |
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| 224 | /**
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| 225 | * \#PF Handler callback for invalidation of virtual access handler ranges.
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| 226 | *
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| 227 | * @param pVM VM Handle.
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| 228 | * @param GCPtr The virtual address the guest has changed.
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| 229 | */
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| 230 | typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, RTGCPTR GCPtr);
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| 231 | /** Pointer to PGM invalidation callback. */
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| 232 | typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
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| 233 |
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| 234 | /**
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| 235 | * Paging mode.
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| 236 | */
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| 237 | typedef enum PGMMODE
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| 238 | {
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| 239 | /** The usual invalid value. */
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| 240 | PGMMODE_INVALID = 0,
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| 241 | /** Real mode. */
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| 242 | PGMMODE_REAL,
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| 243 | /** Protected mode, no paging. */
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| 244 | PGMMODE_PROTECTED,
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| 245 | /** 32-bit paging. */
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| 246 | PGMMODE_32_BIT,
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| 247 | /** PAE paging. */
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| 248 | PGMMODE_PAE,
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| 249 | /** PAE paging with NX enabled. */
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| 250 | PGMMODE_PAE_NX,
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| 251 | /** 64-bit AMD paging (long mode). */
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| 252 | PGMMODE_AMD64,
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| 253 | /** 64-bit AMD paging (long mode) with NX enabled. */
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| 254 | PGMMODE_AMD64_NX,
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| 255 | /** Nested paging mode (shadow only; guest physical to host physical). */
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| 256 | PGMMODE_NESTED,
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| 257 | /** Extended paging (Intel) mode. */
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| 258 | PGMMODE_EPT,
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| 259 | /** The max number of modes */
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| 260 | PGMMODE_MAX,
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| 261 | /** 32bit hackishness. */
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| 262 | PGMMODE_32BIT_HACK = 0x7fffffff
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| 263 | } PGMMODE;
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| 264 |
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| 265 | /** Macro for checking if the guest is using paging.
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| 266 | * @param enmMode PGMMODE_*.
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| 267 | * @remark ASSUMES certain order of the PGMMODE_* values.
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| 268 | */
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| 269 | #define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
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| 270 |
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| 271 | /** Macro for checking if it's one of the long mode modes.
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| 272 | * @param enmMode PGMMODE_*.
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| 273 | */
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| 274 | #define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX || (enmMode) == PGMMODE_AMD64)
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| 275 |
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| 276 | /**
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| 277 | * Is the ROM mapped (true) or is the shadow RAM mapped (false).
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| 278 | *
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| 279 | * @returns boolean.
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| 280 | * @param enmProt The PGMROMPROT value, must be valid.
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| 281 | */
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| 282 | #define PGMROMPROT_IS_ROM(enmProt) \
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| 283 | ( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
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| 284 | || (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
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| 285 |
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| 286 | VMMDECL(int) PGMRegisterStringFormatTypes(void);
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| 287 | VMMDECL(void) PGMDeregisterStringFormatTypes(void);
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| 288 | VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
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| 289 | VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
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| 290 | VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
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| 291 | VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
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| 292 | VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
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| 293 | VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
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| 294 | VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
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| 295 | VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
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| 296 | VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
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| 297 | VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
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| 298 | VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
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| 299 | VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
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| 300 | VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
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| 301 | VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
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| 302 | VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
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| 303 | #ifndef IN_RING0
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| 304 | VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
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| 305 | VMMDECL(int) PGMMapResolveConflicts(PVM pVM);
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| 306 | #endif
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| 307 | #ifdef VBOX_STRICT
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| 308 | VMMDECL(void) PGMMapCheck(PVM pVM);
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| 309 | #endif
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| 310 | VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
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| 311 | VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
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| 312 | VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
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| 313 | VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
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| 314 | VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
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| 315 | VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
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| 316 | VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
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| 317 | VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdPt);
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| 318 |
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| 319 | VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
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| 320 | VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
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| 321 | VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
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| 322 | VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
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| 323 | VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
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| 324 | VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
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| 325 | VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
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| 326 | VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
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| 327 | VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
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| 328 | VMMDECL(int) PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
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| 329 | R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
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| 330 | R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
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| 331 | RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
|
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| 332 | R3PTRTYPE(const char *) pszDesc);
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| 333 | VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
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| 334 | VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
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| 335 | VMMDECL(int) PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
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| 336 | R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
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| 337 | R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
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| 338 | RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
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| 339 | R3PTRTYPE(const char *) pszDesc);
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| 340 | VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
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| 341 | VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
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| 342 | VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
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| 343 | VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
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| 344 | VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
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| 345 | VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
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|---|
| 346 | VMMDECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
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| 347 | VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
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| 348 | VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
|
|---|
| 349 | VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
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| 350 | VMMDECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
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| 351 | VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
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| 352 | VMMDECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
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| 353 | VMMDECL(void) PGMPhysInvalidatePageGCMapTLB(PVM pVM);
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| 354 | VMMDECL(void) PGMPhysInvalidatePageR0MapTLB(PVM pVM);
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| 355 | VMMDECL(void) PGMPhysInvalidatePageR3MapTLB(PVM pVM);
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| 356 |
|
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| 357 | VMMDECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
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|---|
| 358 | VMMDECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
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|---|
| 359 | VMMDECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
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|---|
| 360 | VMMDECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
|
|---|
| 361 | VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
|
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| 362 |
|
|---|
| 363 | /**
|
|---|
| 364 | * Checks if the lock structure is valid
|
|---|
| 365 | *
|
|---|
| 366 | * @param pVM The VM handle.
|
|---|
| 367 | * @param pLock The lock structure initialized by the mapping function.
|
|---|
| 368 | */
|
|---|
| 369 | DECLINLINE(bool) PGMPhysIsPageMappingLockValid(PVM pVM, PPGMPAGEMAPLOCK pLock)
|
|---|
| 370 | {
|
|---|
| 371 | /** @todo -> complete/change this */
|
|---|
| 372 | #if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
|
|---|
| 373 | return !!(pLock->u32Dummy);
|
|---|
| 374 | #else
|
|---|
| 375 | return !!(pLock->pvPage);
|
|---|
| 376 | #endif
|
|---|
| 377 | }
|
|---|
| 378 |
|
|---|
| 379 | VMMDECL(int) PGMPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTR3PTR pR3Ptr);
|
|---|
| 380 | #ifdef VBOX_STRICT
|
|---|
| 381 | VMMDECL(RTR3PTR) PGMPhysGCPhys2R3PtrAssert(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange);
|
|---|
| 382 | #endif
|
|---|
| 383 | VMMDECL(int) PGMPhysGCPtr2R3Ptr(PVMCPU pVCpu, RTGCPTR GCPtr, PRTR3PTR pR3Ptr);
|
|---|
| 384 | VMMDECL(int) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
|
|---|
| 385 | VMMDECL(int) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
|
|---|
| 386 | VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
|
|---|
| 387 | #ifndef IN_RC /* Only ring 0 & 3. */
|
|---|
| 388 | VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
|
|---|
| 389 | VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
|
|---|
| 390 | VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
|
|---|
| 391 | VMMDECL(int) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
|
|---|
| 392 | VMMDECL(int) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
|
|---|
| 393 | VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
|
|---|
| 394 | #endif /* !IN_RC */
|
|---|
| 395 | VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
|
|---|
| 396 | VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
|
|---|
| 397 | VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
|
|---|
| 398 | #ifdef VBOX_STRICT
|
|---|
| 399 | VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
|
|---|
| 400 | VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
|
|---|
| 401 | VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
|
|---|
| 402 | #endif /* VBOX_STRICT */
|
|---|
| 403 |
|
|---|
| 404 | #if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
|
|---|
| 405 | VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv);
|
|---|
| 406 | VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv);
|
|---|
| 407 | # ifdef IN_RC
|
|---|
| 408 | VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv);
|
|---|
| 409 | VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage);
|
|---|
| 410 | VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage);
|
|---|
| 411 | # ifdef VBOX_STRICT
|
|---|
| 412 | VMMDECL(void) PGMDynCheckLocks(PVM pVM);
|
|---|
| 413 | # endif
|
|---|
| 414 | # endif
|
|---|
| 415 | VMMDECL(void) PGMDynMapStartAutoSet(PVMCPU pVCpu);
|
|---|
| 416 | VMMDECL(void) PGMDynMapReleaseAutoSet(PVMCPU pVCpu);
|
|---|
| 417 | VMMDECL(void) PGMDynMapFlushAutoSet(PVMCPU pVCpu);
|
|---|
| 418 | VMMDECL(void) PGMDynMapMigrateAutoSet(PVMCPU pVCpu);
|
|---|
| 419 | VMMDECL(uint32_t) PGMDynMapPushAutoSubset(PVMCPU pVCpu);
|
|---|
| 420 | VMMDECL(void) PGMDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
|
|---|
| 421 | #endif
|
|---|
| 422 |
|
|---|
| 423 |
|
|---|
| 424 | #ifdef IN_RC
|
|---|
| 425 | /** @defgroup grp_pgm_gc The PGM Guest Context API
|
|---|
| 426 | * @ingroup grp_pgm
|
|---|
| 427 | * @{
|
|---|
| 428 | */
|
|---|
| 429 | /** @} */
|
|---|
| 430 | #endif /* IN_RC */
|
|---|
| 431 |
|
|---|
| 432 |
|
|---|
| 433 | #ifdef IN_RING0
|
|---|
| 434 | /** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
|
|---|
| 435 | * @ingroup grp_pgm
|
|---|
| 436 | * @{
|
|---|
| 437 | */
|
|---|
| 438 | VMMR0DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM, PVMCPU pVCpu);
|
|---|
| 439 | VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
|
|---|
| 440 | # ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
|
|---|
| 441 | VMMR0DECL(int) PGMR0DynMapInit(void);
|
|---|
| 442 | VMMR0DECL(void) PGMR0DynMapTerm(void);
|
|---|
| 443 | VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
|
|---|
| 444 | VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
|
|---|
| 445 | VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
|
|---|
| 446 | # endif
|
|---|
| 447 | /** @} */
|
|---|
| 448 | #endif /* IN_RING0 */
|
|---|
| 449 |
|
|---|
| 450 |
|
|---|
| 451 |
|
|---|
| 452 | #ifdef IN_RING3
|
|---|
| 453 | /** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
|
|---|
| 454 | * @ingroup grp_pgm
|
|---|
| 455 | * @{
|
|---|
| 456 | */
|
|---|
| 457 | VMMR3DECL(int) PGMR3Init(PVM pVM);
|
|---|
| 458 | VMMR3DECL(int) PGMR3InitCPU(PVM pVM);
|
|---|
| 459 | VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
|
|---|
| 460 | VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
|
|---|
| 461 | VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
|
|---|
| 462 | VMMR3DECL(void) PGMR3Reset(PVM pVM);
|
|---|
| 463 | VMMR3DECL(int) PGMR3Term(PVM pVM);
|
|---|
| 464 | VMMR3DECL(int) PGMR3TermCPU(PVM pVM);
|
|---|
| 465 | VMMR3DECL(int) PGMR3LockCall(PVM pVM);
|
|---|
| 466 | VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
|
|---|
| 467 |
|
|---|
| 468 | VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
|
|---|
| 469 | VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
|
|---|
| 470 | R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
|
|---|
| 471 | R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
|
|---|
| 472 | RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
|
|---|
| 473 | R3PTRTYPE(const char *) pszDesc);
|
|---|
| 474 | VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
|
|---|
| 475 | VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc);
|
|---|
| 476 | VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
|
|---|
| 477 | VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
|
|---|
| 478 | VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
|
|---|
| 479 | VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
|
|---|
| 480 | VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
|
|---|
| 481 | VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
|
|---|
| 482 |
|
|---|
| 483 | /** @group PGMR3PhysRegisterRom flags.
|
|---|
| 484 | * @{ */
|
|---|
| 485 | /** Inidicates that ROM shadowing should be enabled. */
|
|---|
| 486 | #define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
|
|---|
| 487 | /** Indicates that what pvBinary points to won't go away
|
|---|
| 488 | * and can be used for strictness checks. */
|
|---|
| 489 | #define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
|
|---|
| 490 | /** @} */
|
|---|
| 491 |
|
|---|
| 492 | VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
|
|---|
| 493 | const void *pvBinary, uint32_t fFlags, const char *pszDesc);
|
|---|
| 494 | VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
|
|---|
| 495 | VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
|
|---|
| 496 | VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
|
|---|
| 497 | /** @name PGMR3MapPT flags.
|
|---|
| 498 | * @{ */
|
|---|
| 499 | /** The mapping may be unmapped later. The default is permanent mappings. */
|
|---|
| 500 | #define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
|
|---|
| 501 | /** @} */
|
|---|
| 502 | VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc);
|
|---|
| 503 | VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
|
|---|
| 504 | VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
|
|---|
| 505 | VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
|
|---|
| 506 | VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
|
|---|
| 507 | VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
|
|---|
| 508 | VMMR3DECL(int) PGMR3MappingsDisable(PVM pVM);
|
|---|
| 509 | VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
|
|---|
| 510 | VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
|
|---|
| 511 |
|
|---|
| 512 | VMMR3DECL(int) PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
|
|---|
| 513 | PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
|
|---|
| 514 | const char *pszModR0, const char *pszHandlerR0, RTR0PTR pvUserR0,
|
|---|
| 515 | const char *pszModRC, const char *pszHandlerRC, RTRCPTR pvUserRC, const char *pszDesc);
|
|---|
| 516 | VMMDECL(int) PGMR3HandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
|
|---|
| 517 | R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3,
|
|---|
| 518 | R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3,
|
|---|
| 519 | RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC,
|
|---|
| 520 | R3PTRTYPE(const char *) pszDesc);
|
|---|
| 521 | VMMR3DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
|
|---|
| 522 | PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
|
|---|
| 523 | PFNPGMR3VIRTHANDLER pfnHandlerR3,
|
|---|
| 524 | const char *pszHandlerRC, const char *pszModRC, const char *pszDesc);
|
|---|
| 525 | VMMDECL(int) PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3);
|
|---|
| 526 | VMMDECL(int) PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
|
|---|
| 527 | VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
|
|---|
| 528 | #ifdef ___VBox_dbgf_h /** @todo fix this! */
|
|---|
| 529 | VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
|
|---|
| 530 | #endif
|
|---|
| 531 | VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch);
|
|---|
| 532 |
|
|---|
| 533 | VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
|
|---|
| 534 | VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys);
|
|---|
| 535 | VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys);
|
|---|
| 536 | VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys);
|
|---|
| 537 | VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys);
|
|---|
| 538 | VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value);
|
|---|
| 539 | VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value);
|
|---|
| 540 | VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value);
|
|---|
| 541 | VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value);
|
|---|
| 542 | VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
|
|---|
| 543 | VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
|
|---|
| 544 | VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
|
|---|
| 545 | VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
|
|---|
| 546 | VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
|
|---|
| 547 | VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
|
|---|
| 548 | VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
|
|---|
| 549 |
|
|---|
| 550 | VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
|
|---|
| 551 |
|
|---|
| 552 | VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PVM pVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
|
|---|
| 553 | VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PVM pVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
|
|---|
| 554 | VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
|
|---|
| 555 | VMMR3DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
|
|---|
| 556 | VMMR3DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
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| 557 | VMMR3DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
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| 558 | VMMR3DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
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| 559 | VMMR3DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
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| 560 | VMMR3DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
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| 561 | /** @} */
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| 562 | #endif /* IN_RING3 */
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| 563 |
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| 564 | __END_DECLS
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| 565 |
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| 566 | /** @} */
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| 567 | #endif
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| 568 |
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