VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 64373

Last change on this file since 64373 was 64373, checked in by vboxsync, 8 years ago

PDM,Devices: Support for multiple PCI devices/function in a single PDM device.
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1/** @file
2 * PCI - The PCI Controller And Devices Constants. (DEV)
3 */
4
5/*
6 * Copyright (C) 2006-2016 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_pci_h
27#define ___VBox_pci_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <iprt/assert.h>
32
33/** @defgroup grp_pci PCI - The PCI Controller.
34 * @ingroup grp_devdrv
35 * @{
36 */
37
38
39/**
40 * PCI configuration word 4 (command) and word 6 (status).
41 */
42typedef enum PCICONFIGCOMMAND
43{
44 /** Supports/uses memory accesses. */
45 PCI_COMMAND_IOACCESS = 0x0001,
46 PCI_COMMAND_MEMACCESS = 0x0002,
47 PCI_COMMAND_BUSMASTER = 0x0004
48} PCICONFIGCOMMAND;
49
50
51/**
52 * PCI Address space specification.
53 * This is used when registering a I/O region.
54 */
55/**
56 * Defined by the PCI specification.
57 */
58typedef enum PCIADDRESSSPACE
59{
60 /** Memory. */
61 PCI_ADDRESS_SPACE_MEM = 0x00,
62 /** I/O space. */
63 PCI_ADDRESS_SPACE_IO = 0x01,
64 /** 32-bit BAR. */
65 PCI_ADDRESS_SPACE_BAR32 = 0x00,
66 /** 64-bit BAR. */
67 PCI_ADDRESS_SPACE_BAR64 = 0x04,
68 /** Prefetch memory. */
69 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
70} PCIADDRESSSPACE;
71
72
73
74/** @name PCI Configuration Space Registers
75 * @{ */
76/* Commented out values common for different header types */
77/* Common part of the header */
78#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
79#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
80#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
81#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
82#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
83#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
84#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
85#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
86#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
87#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
88#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
89#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
90#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
91#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
92#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
93#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
94
95/* Type 0 header, device */
96#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
97#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
98#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
99#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
100#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
101#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
102#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
103#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
104#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
105#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
106/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
107#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
108#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
109#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
110#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
111/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
112/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
113#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
114#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
115
116/* Type 1 header, PCI-to-PCI bridge */
117/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
118/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
119#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
120#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
121#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
122#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
123#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
124#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
125#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
126#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
127#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
128#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
129#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
130#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
131#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
132#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
133#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
134/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
135/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
136/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
137/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
138#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
139#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
140
141/* Type 2 header, PCI-to-CardBus bridge */
142#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
143#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
144#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
145#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
146#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
147#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
148/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
149/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
150#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
151#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
152#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
153#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
154#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
155#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
156#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
157#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
158/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
159/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
160/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
161/** @} */
162
163
164/* Possible values in status bitmask */
165#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
166#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
167#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
168#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
169#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
170#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
171#define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
172#define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
173#define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
174#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
175#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
176#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
177#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
178#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
179
180
181/* Command bitmask */
182#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
183#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
184#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
185#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
186#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
187#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
188#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
189#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
190#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
191#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
192#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
193
194
195/* Capability list values (capability offset 0) */
196/* Next value pointer in offset 1, or 0 if none */
197#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
198#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
199#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
200#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
201#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
202#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
203#define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
204#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
205#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
206#define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
207#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
208#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
209#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
210#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
211#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
212#define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
213#define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
214#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
215#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
216
217/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
218#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
219#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
220#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
221#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
222#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
223#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
224#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
225#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
226#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
227#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
228#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
229#define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
230#define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
231#define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
232
233
234/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
235#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
236#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
237#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
238/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
239 someone very similar to log_2().
240 000 1
241 001 2
242 010 4
243 011 8
244 100 16
245 101 32
246 110 Reserved
247 111 Reserved */
248#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
249#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
250
251/* MSI-X flags (2 bytes, capability offset 2) */
252#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
253#define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
254
255/* Power management flags (2 bytes, capability offset 2) */
256#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
257#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
258#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
259#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
260#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
261#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
262#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
263#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
264#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
265#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
266#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
267#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
268#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
269#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
270
271/* Power management control flags (2 bytes, capability offset 4) */
272#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
273#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
274#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
275#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
276#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
277#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
278
279/* PCI-X config flags (2 bytes, capability offset 2) */
280#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
281#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
282#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
283#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
284#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
285#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
286#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
287#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
288
289/* PCI-X config flags (4 bytes, capability offset 4) */
290#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
291#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
292#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
293#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
294#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
295#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
296#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
297#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
298#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
299#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
300#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
301#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
302#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
303
304/* PCI Express config flags (2 bytes, capability offset 2) */
305#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
306#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
307#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
308#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
309#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
310#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
311#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
312#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
313#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
314#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
315#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
316#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
317#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
318
319/* PCI Express device capabilities (4 bytes, capability offset 4) */
320#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
321#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
322#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
323#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
324#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
325#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
326#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
327#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
328#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
329#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
330#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
331#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
332
333/* PCI Express device control (2 bytes, capability offset 8) */
334#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
335#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
336#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
337#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
338#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
339#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
340#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
341#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
342#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
343#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
344#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
345#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
346#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
347
348/* PCI Express device status (2 bytes, capability offset 10) */
349#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
350#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
351#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
352#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
353#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
354#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
355
356/* PCI Express link capabilities (4 bytes, capability offset 12) */
357#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
358#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
359#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
360#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
361#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
362#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
363#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
364#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
365#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
366#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
367
368/* PCI Express link control (2 bytes, capability offset 16) */
369#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
370#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
371#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
372#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
373#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
374#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
375#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
376#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
377#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
378#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
379
380/* PCI Express link status (2 bytes, capability offset 18) */
381#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
382#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
383#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
384#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
385#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
386#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
387#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
388#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
389
390/* PCI Express slot capabilities (4 bytes, capability offset 20) */
391#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
392#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
393#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
394#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
395#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
396#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
397#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
398#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
399#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
400#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
401#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
402#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
403
404/* PCI Express slot control (2 bytes, capability offset 24) */
405#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
406#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
407#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
408#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
409#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
410#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
411#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
412#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
413#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
414#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
415#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
416
417/* PCI Express slot status (2 bytes, capability offset 26) */
418#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
419#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
420#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
421#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
422#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
423#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
424#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
425#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
426#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
427
428/* PCI Express root control (2 bytes, capability offset 28) */
429#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
430#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
431#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
432#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
433#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
434
435/* PCI Express root capabilities (2 bytes, capability offset 30) */
436#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
437
438/* PCI Express root status (4 bytes, capability offset 32) */
439#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
440#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
441#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
442
443
444/** Fixed I/O region number for ROM. */
445#define VBOX_PCI_ROM_SLOT 6
446/** Max number of I/O regions. */
447#define VBOX_PCI_NUM_REGIONS 7
448
449#define PCI_ROM_SLOT VBOX_PCI_ROM_SLOT /**< deprecated */
450#define PCI_NUM_REGIONS VBOX_PCI_NUM_REGIONS /**< deprecated */
451
452/** Number of functions per device. */
453#define VBOX_PCI_MAX_FUNCTIONS 8
454/** Number of devices per bus. */
455#define VBOX_PCI_MAX_DEVICES 32
456/** The device number shift count for a device+function number. */
457#define VBOX_PCI_DEVFN_DEV_SHIFT 3
458/** The device number shift count for a device+function number. */
459#define VBOX_PCI_DEVFN_FUN_MASK 0x7
460/** Make a device+function number. */
461#define VBOX_PCI_DEVFN_MAKE(a_uPciDevNo, a_uPciFunNo) (((a_uPciDevNo) << VBOX_PCI_DEVFN_DEV_SHIFT) | (a_uPciFunNo))
462
463
464#if defined(__cplusplus) && defined(IN_RING3)
465/* For RTStrPrintf(). */
466# include <iprt/string.h>
467
468/**
469 * Class representing PCI address. PCI device consist of
470 * bus, device and function numbers. Generally device PCI
471 * address could be changed during runtime, but only by
472 * an OS PCI driver.
473 *
474 * @remarks C++ classes (structs included) are not generally accepted in
475 * VMM devices or drivers. An exception may be granted for this class
476 * if it's contained to ring-3 and that this is a one time exception
477 * which sets no precedent.
478 */
479struct PCIBusAddress
480{
481 /** @todo: think if we'll need domain, which is higher
482 * word of the address. */
483 int miBus;
484 int miDevice;
485 int miFn;
486
487 PCIBusAddress()
488 {
489 clear();
490 }
491
492 PCIBusAddress(int iBus, int iDevice, int iFn)
493 {
494 init(iBus, iDevice, iFn);
495 }
496
497 PCIBusAddress(int32_t iAddr)
498 {
499 clear();
500 fromLong(iAddr);
501 }
502
503 PCIBusAddress& clear()
504 {
505 miBus = miDevice = miFn = -1;
506 return *this;
507 }
508
509 void init(int iBus, int iDevice, int iFn)
510 {
511 miBus = iBus;
512 miDevice = iDevice;
513 miFn = iFn;
514 }
515
516 void init(const PCIBusAddress &a)
517 {
518 miBus = a.miBus;
519 miDevice = a.miDevice;
520 miFn = a.miFn;
521 }
522
523 bool operator<(const PCIBusAddress &a) const
524 {
525 if (miBus < a.miBus)
526 return true;
527
528 if (miBus > a.miBus)
529 return false;
530
531 if (miDevice < a.miDevice)
532 return true;
533
534 if (miDevice > a.miDevice)
535 return false;
536
537 if (miFn < a.miFn)
538 return true;
539
540 if (miFn > a.miFn)
541 return false;
542
543 return false;
544 }
545
546 bool operator==(const PCIBusAddress &a) const
547 {
548 return (miBus == a.miBus)
549 && (miDevice == a.miDevice)
550 && (miFn == a.miFn);
551 }
552
553 bool operator!=(const PCIBusAddress &a) const
554 {
555 return (miBus != a.miBus)
556 || (miDevice != a.miDevice)
557 || (miFn != a.miFn);
558 }
559
560 bool valid() const
561 {
562 return (miBus != -1)
563 && (miDevice != -1)
564 && (miFn != -1);
565 }
566
567 int32_t asLong() const
568 {
569 Assert(valid());
570 return (miBus << 8) | (miDevice << 3) | miFn;
571 }
572
573 PCIBusAddress& fromLong(int32_t value)
574 {
575 miBus = (value >> 8) & 0xff;
576 miDevice = (value & 0xff) >> 3;
577 miFn = (value & 7);
578 return *this;
579 }
580
581 /** Create string representation of this PCI address. */
582 bool format(char* szBuf, int32_t cBufSize)
583 {
584 if (cBufSize < (/* bus */ 2 + /* : */ 1 + /* device */ 2 + /* . */ 1 + /* function*/ 1 + /* \0 */1))
585 return false;
586
587 if (valid())
588 RTStrPrintf(szBuf, cBufSize, "%02x:%02x.%01x", miBus, miDevice, miFn);
589 else
590 RTStrPrintf(szBuf, cBufSize, "%s", "<bad>");
591
592 return true;
593 }
594
595 static const size_t cMaxAddrSize = 10;
596};
597
598#endif /* __cplusplus && IN_RING3 */
599
600/** @} */
601
602#endif
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