1 | /** @file
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2 | * PCI - The PCI Controller And Devices. (DEV)
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3 | */
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4 |
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5 | /*
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6 | * Copyright (C) 2006-2015 Oracle Corporation
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7 | *
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8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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9 | * available from http://www.virtualbox.org. This file is free software;
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10 | * you can redistribute it and/or modify it under the terms of the GNU
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11 | * General Public License (GPL) as published by the Free Software
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12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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15 | *
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16 | * The contents of this file may alternatively be used under the terms
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17 | * of the Common Development and Distribution License Version 1.0
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18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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19 | * VirtualBox OSE distribution, in which case the provisions of the
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20 | * CDDL are applicable instead of those of the GPL.
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21 | *
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22 | * You may elect to license modified versions of this file under the
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23 | * terms and conditions of either the GPL or the CDDL or both.
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24 | */
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25 |
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26 | #ifndef ___VBox_pci_h
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27 | #define ___VBox_pci_h
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28 |
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29 | #include <VBox/cdefs.h>
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30 | #include <VBox/types.h>
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31 | #include <iprt/assert.h>
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32 |
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33 | /** @defgroup grp_pci PCI - The PCI Controller.
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34 | * @{
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35 | */
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36 |
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37 | /** Pointer to a PCI device. */
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38 | typedef struct PCIDevice *PPCIDEVICE;
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39 |
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40 |
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41 | /**
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42 | * PCI configuration word 4 (command) and word 6 (status).
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43 | */
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44 | typedef enum PCICONFIGCOMMAND
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45 | {
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46 | /** Supports/uses memory accesses. */
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47 | PCI_COMMAND_IOACCESS = 0x0001,
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48 | PCI_COMMAND_MEMACCESS = 0x0002,
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49 | PCI_COMMAND_BUSMASTER = 0x0004
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50 | } PCICONFIGCOMMAND;
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51 |
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52 |
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53 | /**
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54 | * PCI Address space specification.
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55 | * This is used when registering a I/O region.
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56 | */
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57 | /**
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58 | * Defined by the PCI specification.
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59 | */
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60 | typedef enum PCIADDRESSSPACE
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61 | {
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62 | /** Memory. */
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63 | PCI_ADDRESS_SPACE_MEM = 0x00,
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64 | /** I/O space. */
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65 | PCI_ADDRESS_SPACE_IO = 0x01,
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66 | /** 32-bit BAR. */
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67 | PCI_ADDRESS_SPACE_BAR32 = 0x00,
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68 | /** 64-bit BAR. */
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69 | PCI_ADDRESS_SPACE_BAR64 = 0x04,
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70 | /** Prefetch memory. */
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71 | PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
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72 | } PCIADDRESSSPACE;
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73 |
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74 |
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75 | /**
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76 | * Callback function for mapping an PCI I/O region.
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77 | *
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78 | * @return VBox status code.
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79 | * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
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80 | * @param iRegion The region number.
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81 | * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
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82 | * is an I/O port, otherwise it's a physical address.
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83 | *
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84 | * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
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85 | * that the device deregister access handlers for it and update its internal
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86 | * state to reflect this.
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87 | *
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88 | * @param enmType One of the PCI_ADDRESS_SPACE_* values.
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89 | *
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90 | * @remarks Called with the PDM lock held. The device lock is NOT take because
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91 | * that is very likely be a lock order violation.
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92 | */
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93 | typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
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94 | /** Pointer to a FNPCIIOREGIONMAP() function. */
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95 | typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
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96 |
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97 |
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98 | /** @name PCI Configuration Space Registers
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99 | * @{ */
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100 | /* Commented out values common for different header types */
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101 | /* Common part of the header */
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102 | #define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
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103 | #define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
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104 | #define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
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105 | #define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
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106 | #define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
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107 | #define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
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108 | #define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
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109 | #define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
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110 | #define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
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111 | #define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
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112 | #define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
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113 | #define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
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114 | #define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
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115 | #define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
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116 | #define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
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117 | #define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
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118 |
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119 | /* Type 0 header, device */
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120 | #define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
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121 | #define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
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122 | #define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
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123 | #define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
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124 | #define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
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125 | #define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
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126 | #define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
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127 | #define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
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128 | #define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
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129 | #define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
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130 | /* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
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131 | #define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
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132 | #define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
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133 | #define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
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134 | #define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
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135 | /* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
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136 | /* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
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137 | #define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
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138 | #define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
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139 |
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140 | /* Type 1 header, PCI-to-PCI bridge */
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141 | /* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
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142 | /* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
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143 | #define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
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144 | #define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
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145 | #define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
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146 | #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
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147 | #define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
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148 | #define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
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149 | #define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
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150 | #define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
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151 | #define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
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152 | #define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
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153 | #define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
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154 | #define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
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155 | #define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
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156 | #define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
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157 | #define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
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158 | /* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
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159 | /* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
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160 | /* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
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161 | /* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
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162 | #define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
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163 | #define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
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164 |
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165 | /* Type 2 header, PCI-to-CardBus bridge */
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166 | #define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
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167 | #define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
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168 | #define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
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169 | #define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
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170 | #define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
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171 | #define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
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172 | /* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
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173 | /* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
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174 | #define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
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175 | #define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
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176 | #define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
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177 | #define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
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178 | #define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
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179 | #define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
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180 | #define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
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181 | #define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
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182 | /* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
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183 | /* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
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184 | /* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
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185 | /** @} */
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186 |
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187 |
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188 | /* Possible values in status bitmask */
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189 | #define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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190 | #define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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191 | #define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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192 | #define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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193 | #define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
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194 | #define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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195 | #define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
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196 | #define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
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197 | #define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
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198 | #define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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199 | #define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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200 | #define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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201 | #define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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202 | #define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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203 |
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204 |
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205 | /* Command bitmask */
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206 | #define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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207 | #define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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208 | #define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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209 | #define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
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210 | #define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
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211 | #define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
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212 | #define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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213 | #define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
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214 | #define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
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215 | #define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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216 | #define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
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217 |
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218 |
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219 | /* Capability list values (capability offset 0) */
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220 | /* Next value pointer in offset 1, or 0 if none */
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221 | #define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
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222 | #define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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223 | #define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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224 | #define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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225 | #define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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226 | #define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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227 | #define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
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228 | #define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
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229 | #define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
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230 | #define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
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231 | #define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
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232 | #define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
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233 | #define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
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234 | #define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
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235 | #define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
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236 | #define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
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237 | #define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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238 | #define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
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239 | #define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
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240 |
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241 | /* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
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242 | #define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
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243 | #define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
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244 | #define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
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245 | #define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
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246 | #define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
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247 | #define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
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248 | #define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
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249 | #define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
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250 | #define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
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251 | #define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
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252 | #define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
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253 | #define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
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254 | #define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
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255 | #define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
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256 |
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257 |
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258 | /* MSI flags, aka Message Control (2 bytes, capability offset 2) */
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259 | #define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
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260 | #define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
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261 | #define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
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262 | /* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
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263 | someone very similar to log_2().
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264 | 000 1
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265 | 001 2
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266 | 010 4
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267 | 011 8
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268 | 100 16
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269 | 101 32
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270 | 110 Reserved
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271 | 111 Reserved */
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272 | #define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
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273 | #define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
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274 |
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275 | /* MSI-X flags (2 bytes, capability offset 2) */
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276 | #define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
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277 | #define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
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278 |
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279 | /* Power management flags (2 bytes, capability offset 2) */
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280 | #define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
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281 | #define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
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282 | #define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
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283 | #define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
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284 | #define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
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285 | #define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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286 | #define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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287 | #define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
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288 | #define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
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289 | #define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
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290 | #define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
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291 | #define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
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292 | #define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
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293 | #define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
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294 |
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295 | /* Power management control flags (2 bytes, capability offset 4) */
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296 | #define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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297 | #define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
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298 | #define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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299 | #define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
|
---|
300 | #define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
|
---|
301 | #define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
|
---|
302 |
|
---|
303 | /* PCI-X config flags (2 bytes, capability offset 2) */
|
---|
304 | #define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
|
---|
305 | #define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
|
---|
306 | #define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
|
---|
307 | #define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
|
---|
308 | #define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
|
---|
309 | #define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
|
---|
310 | #define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
|
---|
311 | #define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
|
---|
312 |
|
---|
313 | /* PCI-X config flags (4 bytes, capability offset 4) */
|
---|
314 | #define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
|
---|
315 | #define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
|
---|
316 | #define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
|
---|
317 | #define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
|
---|
318 | #define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
|
---|
319 | #define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
|
---|
320 | #define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
|
---|
321 | #define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
|
---|
322 | #define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
|
---|
323 | #define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
|
---|
324 | #define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
|
---|
325 | #define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
|
---|
326 | #define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
|
---|
327 |
|
---|
328 | /* PCI Express config flags (2 bytes, capability offset 2) */
|
---|
329 | #define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
|
---|
330 | #define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
|
---|
331 | #define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
|
---|
332 | #define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
|
---|
333 | #define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
|
---|
334 | #define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
|
---|
335 | #define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
|
---|
336 | #define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
|
---|
337 | #define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
|
---|
338 | #define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
|
---|
339 | #define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
|
---|
340 | #define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
|
---|
341 | #define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
|
---|
342 |
|
---|
343 | /* PCI Express device capabilities (4 bytes, capability offset 4) */
|
---|
344 | #define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
|
---|
345 | #define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
|
---|
346 | #define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
|
---|
347 | #define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
|
---|
348 | #define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
|
---|
349 | #define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
|
---|
350 | #define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
|
---|
351 | #define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
|
---|
352 | #define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
|
---|
353 | #define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
|
---|
354 | #define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
|
---|
355 | #define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
|
---|
356 |
|
---|
357 | /* PCI Express device control (2 bytes, capability offset 8) */
|
---|
358 | #define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
|
---|
359 | #define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
|
---|
360 | #define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
|
---|
361 | #define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
|
---|
362 | #define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
|
---|
363 | #define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
|
---|
364 | #define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
|
---|
365 | #define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
|
---|
366 | #define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
|
---|
367 | #define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
|
---|
368 | #define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
|
---|
369 | #define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
|
---|
370 | #define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
|
---|
371 |
|
---|
372 | /* PCI Express device status (2 bytes, capability offset 10) */
|
---|
373 | #define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
|
---|
374 | #define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
|
---|
375 | #define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
|
---|
376 | #define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
|
---|
377 | #define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
|
---|
378 | #define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
|
---|
379 |
|
---|
380 | /* PCI Express link capabilities (4 bytes, capability offset 12) */
|
---|
381 | #define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
|
---|
382 | #define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
|
---|
383 | #define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
|
---|
384 | #define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
|
---|
385 | #define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
|
---|
386 | #define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
|
---|
387 | #define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
|
---|
388 | #define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
|
---|
389 | #define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
|
---|
390 | #define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
|
---|
391 |
|
---|
392 | /* PCI Express link control (2 bytes, capability offset 16) */
|
---|
393 | #define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
|
---|
394 | #define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
|
---|
395 | #define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
|
---|
396 | #define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
|
---|
397 | #define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
|
---|
398 | #define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
|
---|
399 | #define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
|
---|
400 | #define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
|
---|
401 | #define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
|
---|
402 | #define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
|
---|
403 |
|
---|
404 | /* PCI Express link status (2 bytes, capability offset 18) */
|
---|
405 | #define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
|
---|
406 | #define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
|
---|
407 | #define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
|
---|
408 | #define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
|
---|
409 | #define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
|
---|
410 | #define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
|
---|
411 | #define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
|
---|
412 | #define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
|
---|
413 |
|
---|
414 | /* PCI Express slot capabilities (4 bytes, capability offset 20) */
|
---|
415 | #define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
|
---|
416 | #define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
|
---|
417 | #define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
|
---|
418 | #define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
|
---|
419 | #define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
|
---|
420 | #define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
|
---|
421 | #define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
|
---|
422 | #define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
|
---|
423 | #define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
|
---|
424 | #define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
|
---|
425 | #define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
|
---|
426 | #define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
|
---|
427 |
|
---|
428 | /* PCI Express slot control (2 bytes, capability offset 24) */
|
---|
429 | #define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
|
---|
430 | #define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
|
---|
431 | #define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
|
---|
432 | #define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
|
---|
433 | #define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
|
---|
434 | #define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
|
---|
435 | #define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
|
---|
436 | #define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
|
---|
437 | #define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
|
---|
438 | #define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
|
---|
439 | #define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
|
---|
440 |
|
---|
441 | /* PCI Express slot status (2 bytes, capability offset 26) */
|
---|
442 | #define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
|
---|
443 | #define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
|
---|
444 | #define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
|
---|
445 | #define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
|
---|
446 | #define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
|
---|
447 | #define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
|
---|
448 | #define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
|
---|
449 | #define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
|
---|
450 | #define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
|
---|
451 |
|
---|
452 | /* PCI Express root control (2 bytes, capability offset 28) */
|
---|
453 | #define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
|
---|
454 | #define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
|
---|
455 | #define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
|
---|
456 | #define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
|
---|
457 | #define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
|
---|
458 |
|
---|
459 | /* PCI Express root capabilities (2 bytes, capability offset 30) */
|
---|
460 | #define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
|
---|
461 |
|
---|
462 | /* PCI Express root status (4 bytes, capability offset 32) */
|
---|
463 | #define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
|
---|
464 | #define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
|
---|
465 | #define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
|
---|
466 |
|
---|
467 |
|
---|
468 | /**
|
---|
469 | * Callback function for reading from the PCI configuration space.
|
---|
470 | *
|
---|
471 | * @returns The register value.
|
---|
472 | * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
|
---|
473 | * @param Address The configuration space register address. [0..4096]
|
---|
474 | * @param cb The register size. [1,2,4]
|
---|
475 | *
|
---|
476 | * @remarks Called with the PDM lock held. The device lock is NOT take because
|
---|
477 | * that is very likely be a lock order violation.
|
---|
478 | */
|
---|
479 | typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
|
---|
480 | /** Pointer to a FNPCICONFIGREAD() function. */
|
---|
481 | typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
|
---|
482 | /** Pointer to a PFNPCICONFIGREAD. */
|
---|
483 | typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
|
---|
484 |
|
---|
485 | /**
|
---|
486 | * Callback function for writing to the PCI configuration space.
|
---|
487 | *
|
---|
488 | * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
|
---|
489 | * @param Address The configuration space register address. [0..4096]
|
---|
490 | * @param u32Value The value that's being written. The number of bits actually used from
|
---|
491 | * this value is determined by the cb parameter.
|
---|
492 | * @param cb The register size. [1,2,4]
|
---|
493 | *
|
---|
494 | * @remarks Called with the PDM lock held. The device lock is NOT take because
|
---|
495 | * that is very likely be a lock order violation.
|
---|
496 | */
|
---|
497 | typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
|
---|
498 | /** Pointer to a FNPCICONFIGWRITE() function. */
|
---|
499 | typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
|
---|
500 | /** Pointer to a PFNPCICONFIGWRITE. */
|
---|
501 | typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
|
---|
502 |
|
---|
503 | /** Fixed I/O region number for ROM. */
|
---|
504 | #define PCI_ROM_SLOT 6
|
---|
505 | #define VBOX_PCI_ROM_SLOT 6
|
---|
506 | /** Max number of I/O regions. */
|
---|
507 | #define PCI_NUM_REGIONS 7
|
---|
508 | #define VBOX_PCI_NUM_REGIONS 7
|
---|
509 |
|
---|
510 | /*
|
---|
511 | * Hack to include the PCIDEVICEINT structure at the right place
|
---|
512 | * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
|
---|
513 | */
|
---|
514 | #ifdef PCI_INCLUDE_PRIVATE
|
---|
515 | # include "PCIInternal.h"
|
---|
516 | #endif
|
---|
517 |
|
---|
518 | /**
|
---|
519 | * PCI Device structure.
|
---|
520 | */
|
---|
521 | typedef struct PCIDevice
|
---|
522 | {
|
---|
523 | /** PCI config space. */
|
---|
524 | uint8_t config[256];
|
---|
525 |
|
---|
526 | /** Internal data. */
|
---|
527 | union
|
---|
528 | {
|
---|
529 | #ifdef PCIDEVICEINT_DECLARED
|
---|
530 | PCIDEVICEINT s;
|
---|
531 | #endif
|
---|
532 | char padding[328];
|
---|
533 | } Int;
|
---|
534 |
|
---|
535 | /** Read only data.
|
---|
536 | * @{
|
---|
537 | */
|
---|
538 | /** PCI device number on the pci bus. */
|
---|
539 | int32_t devfn;
|
---|
540 | uint32_t Alignment0; /**< Alignment. */
|
---|
541 | /** Device name. */
|
---|
542 | R3PTRTYPE(const char *) name;
|
---|
543 | /** Pointer to the device instance which registered the device. */
|
---|
544 | PPDMDEVINSR3 pDevIns;
|
---|
545 | /** @} */
|
---|
546 | } PCIDEVICE;
|
---|
547 |
|
---|
548 | /** @todo handle extended space access. */
|
---|
549 |
|
---|
550 | DECLINLINE(void) PCIDevSetByte(PPCIDEVICE pPciDev, uint32_t offReg, uint8_t u8Value)
|
---|
551 | {
|
---|
552 | pPciDev->config[offReg] = u8Value;
|
---|
553 | }
|
---|
554 |
|
---|
555 | DECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t offReg)
|
---|
556 | {
|
---|
557 | return pPciDev->config[offReg];
|
---|
558 | }
|
---|
559 |
|
---|
560 | DECLINLINE(void) PCIDevSetWord(PPCIDEVICE pPciDev, uint32_t offReg, uint16_t u16Value)
|
---|
561 | {
|
---|
562 | *(uint16_t*)&pPciDev->config[offReg] = RT_H2LE_U16(u16Value);
|
---|
563 | }
|
---|
564 |
|
---|
565 | DECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t offReg)
|
---|
566 | {
|
---|
567 | uint16_t u16Value = *(uint16_t*)&pPciDev->config[offReg];
|
---|
568 | return RT_H2LE_U16(u16Value);
|
---|
569 | }
|
---|
570 |
|
---|
571 | DECLINLINE(void) PCIDevSetDWord(PPCIDEVICE pPciDev, uint32_t offReg, uint32_t u32Value)
|
---|
572 | {
|
---|
573 | *(uint32_t*)&pPciDev->config[offReg] = RT_H2LE_U32(u32Value);
|
---|
574 | }
|
---|
575 |
|
---|
576 | DECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t offReg)
|
---|
577 | {
|
---|
578 | uint32_t u32Value = *(uint32_t*)&pPciDev->config[offReg];
|
---|
579 | return RT_H2LE_U32(u32Value);
|
---|
580 | }
|
---|
581 |
|
---|
582 | DECLINLINE(void) PCIDevSetQWord(PPCIDEVICE pPciDev, uint32_t offReg, uint64_t u64Value)
|
---|
583 | {
|
---|
584 | *(uint64_t*)&pPciDev->config[offReg] = RT_H2LE_U64(u64Value);
|
---|
585 | }
|
---|
586 |
|
---|
587 | DECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t offReg)
|
---|
588 | {
|
---|
589 | uint64_t u64Value = *(uint64_t*)&pPciDev->config[offReg];
|
---|
590 | return RT_H2LE_U64(u64Value);
|
---|
591 | }
|
---|
592 |
|
---|
593 | /**
|
---|
594 | * Sets the vendor id config register.
|
---|
595 | * @param pPciDev The PCI device.
|
---|
596 | * @param u16VendorId The vendor id.
|
---|
597 | */
|
---|
598 | DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
|
---|
599 | {
|
---|
600 | PCIDevSetWord(pPciDev, VBOX_PCI_VENDOR_ID, u16VendorId);
|
---|
601 | }
|
---|
602 |
|
---|
603 | /**
|
---|
604 | * Gets the vendor id config register.
|
---|
605 | * @returns the vendor id.
|
---|
606 | * @param pPciDev The PCI device.
|
---|
607 | */
|
---|
608 | DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
|
---|
609 | {
|
---|
610 | return PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID);
|
---|
611 | }
|
---|
612 |
|
---|
613 |
|
---|
614 | /**
|
---|
615 | * Sets the device id config register.
|
---|
616 | * @param pPciDev The PCI device.
|
---|
617 | * @param u16DeviceId The device id.
|
---|
618 | */
|
---|
619 | DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
|
---|
620 | {
|
---|
621 | PCIDevSetWord(pPciDev, VBOX_PCI_DEVICE_ID, u16DeviceId);
|
---|
622 | }
|
---|
623 |
|
---|
624 | /**
|
---|
625 | * Gets the device id config register.
|
---|
626 | * @returns the device id.
|
---|
627 | * @param pPciDev The PCI device.
|
---|
628 | */
|
---|
629 | DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
|
---|
630 | {
|
---|
631 | return PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID);
|
---|
632 | }
|
---|
633 |
|
---|
634 | /**
|
---|
635 | * Sets the command config register.
|
---|
636 | *
|
---|
637 | * @param pPciDev The PCI device.
|
---|
638 | * @param u16Command The command register value.
|
---|
639 | */
|
---|
640 | DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
|
---|
641 | {
|
---|
642 | PCIDevSetWord(pPciDev, VBOX_PCI_COMMAND, u16Command);
|
---|
643 | }
|
---|
644 |
|
---|
645 |
|
---|
646 | /**
|
---|
647 | * Gets the command config register.
|
---|
648 | * @returns The command register value.
|
---|
649 | * @param pPciDev The PCI device.
|
---|
650 | */
|
---|
651 | DECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
|
---|
652 | {
|
---|
653 | return PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
|
---|
654 | }
|
---|
655 |
|
---|
656 | /**
|
---|
657 | * Checks if the given PCI device is a bus master.
|
---|
658 | * @returns true if the device is a bus master, false if not.
|
---|
659 | * @param pPciDev The PCI device.
|
---|
660 | */
|
---|
661 | DECLINLINE(bool) PCIDevIsBusmaster(PPCIDEVICE pPciDev)
|
---|
662 | {
|
---|
663 | return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_MASTER) != 0;
|
---|
664 | }
|
---|
665 |
|
---|
666 | /**
|
---|
667 | * Checks if INTx interrupts disabled in the command config register.
|
---|
668 | * @returns true if disabled.
|
---|
669 | * @param pPciDev The PCI device.
|
---|
670 | */
|
---|
671 | DECLINLINE(bool) PCIDevIsIntxDisabled(PPCIDEVICE pPciDev)
|
---|
672 | {
|
---|
673 | return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_INTX_DISABLE) != 0;
|
---|
674 | }
|
---|
675 |
|
---|
676 | /**
|
---|
677 | * Gets the status config register.
|
---|
678 | *
|
---|
679 | * @returns status config register.
|
---|
680 | * @param pPciDev The PCI device.
|
---|
681 | */
|
---|
682 | DECLINLINE(uint16_t) PCIDevGetStatus(PPCIDEVICE pPciDev)
|
---|
683 | {
|
---|
684 | return PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
|
---|
685 | }
|
---|
686 |
|
---|
687 | /**
|
---|
688 | * Sets the status config register.
|
---|
689 | *
|
---|
690 | * @param pPciDev The PCI device.
|
---|
691 | * @param u16Status The status register value.
|
---|
692 | */
|
---|
693 | DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
|
---|
694 | {
|
---|
695 | PCIDevSetWord(pPciDev, VBOX_PCI_STATUS, u16Status);
|
---|
696 | }
|
---|
697 |
|
---|
698 |
|
---|
699 | /**
|
---|
700 | * Sets the revision id config register.
|
---|
701 | *
|
---|
702 | * @param pPciDev The PCI device.
|
---|
703 | * @param u8RevisionId The revision id.
|
---|
704 | */
|
---|
705 | DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
|
---|
706 | {
|
---|
707 | PCIDevSetByte(pPciDev, VBOX_PCI_REVISION_ID, u8RevisionId);
|
---|
708 | }
|
---|
709 |
|
---|
710 |
|
---|
711 | /**
|
---|
712 | * Sets the register level programming class config register.
|
---|
713 | *
|
---|
714 | * @param pPciDev The PCI device.
|
---|
715 | * @param u8ClassProg The new value.
|
---|
716 | */
|
---|
717 | DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
|
---|
718 | {
|
---|
719 | PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_PROG, u8ClassProg);
|
---|
720 | }
|
---|
721 |
|
---|
722 |
|
---|
723 | /**
|
---|
724 | * Sets the sub-class (aka device class) config register.
|
---|
725 | *
|
---|
726 | * @param pPciDev The PCI device.
|
---|
727 | * @param u8SubClass The sub-class.
|
---|
728 | */
|
---|
729 | DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
|
---|
730 | {
|
---|
731 | PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_SUB, u8SubClass);
|
---|
732 | }
|
---|
733 |
|
---|
734 |
|
---|
735 | /**
|
---|
736 | * Sets the base class config register.
|
---|
737 | *
|
---|
738 | * @param pPciDev The PCI device.
|
---|
739 | * @param u8BaseClass The base class.
|
---|
740 | */
|
---|
741 | DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
|
---|
742 | {
|
---|
743 | PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_BASE, u8BaseClass);
|
---|
744 | }
|
---|
745 |
|
---|
746 | /**
|
---|
747 | * Sets the header type config register.
|
---|
748 | *
|
---|
749 | * @param pPciDev The PCI device.
|
---|
750 | * @param u8HdrType The header type.
|
---|
751 | */
|
---|
752 | DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
|
---|
753 | {
|
---|
754 | PCIDevSetByte(pPciDev, VBOX_PCI_HEADER_TYPE, u8HdrType);
|
---|
755 | }
|
---|
756 |
|
---|
757 | /**
|
---|
758 | * Gets the header type config register.
|
---|
759 | *
|
---|
760 | * @param pPciDev The PCI device.
|
---|
761 | * @returns u8HdrType The header type.
|
---|
762 | */
|
---|
763 | DECLINLINE(uint8_t) PCIDevGetHeaderType(PPCIDEVICE pPciDev)
|
---|
764 | {
|
---|
765 | return PCIDevGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
|
---|
766 | }
|
---|
767 |
|
---|
768 | /**
|
---|
769 | * Sets the BIST (built-in self-test) config register.
|
---|
770 | *
|
---|
771 | * @param pPciDev The PCI device.
|
---|
772 | * @param u8Bist The BIST value.
|
---|
773 | */
|
---|
774 | DECLINLINE(void) PCIDevSetBIST(PPCIDEVICE pPciDev, uint8_t u8Bist)
|
---|
775 | {
|
---|
776 | PCIDevSetByte(pPciDev, VBOX_PCI_BIST, u8Bist);
|
---|
777 | }
|
---|
778 |
|
---|
779 | /**
|
---|
780 | * Gets the BIST (built-in self-test) config register.
|
---|
781 | *
|
---|
782 | * @param pPciDev The PCI device.
|
---|
783 | * @returns u8Bist The BIST.
|
---|
784 | */
|
---|
785 | DECLINLINE(uint8_t) PCIDevGetBIST(PPCIDEVICE pPciDev)
|
---|
786 | {
|
---|
787 | return PCIDevGetByte(pPciDev, VBOX_PCI_BIST);
|
---|
788 | }
|
---|
789 |
|
---|
790 |
|
---|
791 | /**
|
---|
792 | * Sets a base address config register.
|
---|
793 | *
|
---|
794 | * @param pPciDev The PCI device.
|
---|
795 | * @param iReg Base address register number (0..5).
|
---|
796 | * @param fIOSpace Whether it's I/O (true) or memory (false) space.
|
---|
797 | * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
|
---|
798 | * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
|
---|
799 | * @param u32Addr The address value.
|
---|
800 | */
|
---|
801 | DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit,
|
---|
802 | uint32_t u32Addr)
|
---|
803 | {
|
---|
804 | if (fIOSpace)
|
---|
805 | {
|
---|
806 | Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
|
---|
807 | u32Addr |= RT_BIT_32(0);
|
---|
808 | }
|
---|
809 | else
|
---|
810 | {
|
---|
811 | Assert(!(u32Addr & 0xf));
|
---|
812 | if (fPrefetchable)
|
---|
813 | u32Addr |= RT_BIT_32(3);
|
---|
814 | if (f64Bit)
|
---|
815 | u32Addr |= 0x2 << 1;
|
---|
816 | }
|
---|
817 | switch (iReg)
|
---|
818 | {
|
---|
819 | case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
|
---|
820 | case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
|
---|
821 | case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
|
---|
822 | case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
|
---|
823 | case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
|
---|
824 | case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
|
---|
825 | default: AssertFailedReturnVoid();
|
---|
826 | }
|
---|
827 |
|
---|
828 | PCIDevSetDWord(pPciDev, iReg, u32Addr);
|
---|
829 | }
|
---|
830 |
|
---|
831 | /**
|
---|
832 | * Please document me. I don't seem to be getting as much as calculating
|
---|
833 | * the address of some PCI region.
|
---|
834 | */
|
---|
835 | DECLINLINE(uint32_t) PCIDevGetRegionReg(uint32_t iRegion)
|
---|
836 | {
|
---|
837 | return iRegion == VBOX_PCI_ROM_SLOT
|
---|
838 | ? VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
|
---|
839 | }
|
---|
840 |
|
---|
841 | /**
|
---|
842 | * Sets the sub-system vendor id config register.
|
---|
843 | *
|
---|
844 | * @param pPciDev The PCI device.
|
---|
845 | * @param u16SubSysVendorId The sub-system vendor id.
|
---|
846 | */
|
---|
847 | DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
|
---|
848 | {
|
---|
849 | PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, u16SubSysVendorId);
|
---|
850 | }
|
---|
851 |
|
---|
852 | /**
|
---|
853 | * Gets the sub-system vendor id config register.
|
---|
854 | * @returns the sub-system vendor id.
|
---|
855 | * @param pPciDev The PCI device.
|
---|
856 | */
|
---|
857 | DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
|
---|
858 | {
|
---|
859 | return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID);
|
---|
860 | }
|
---|
861 |
|
---|
862 |
|
---|
863 | /**
|
---|
864 | * Sets the sub-system id config register.
|
---|
865 | *
|
---|
866 | * @param pPciDev The PCI device.
|
---|
867 | * @param u16SubSystemId The sub-system id.
|
---|
868 | */
|
---|
869 | DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
|
---|
870 | {
|
---|
871 | PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID, u16SubSystemId);
|
---|
872 | }
|
---|
873 |
|
---|
874 | /**
|
---|
875 | * Gets the sub-system id config register.
|
---|
876 | * @returns the sub-system id.
|
---|
877 | * @param pPciDev The PCI device.
|
---|
878 | */
|
---|
879 | DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
|
---|
880 | {
|
---|
881 | return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID);
|
---|
882 | }
|
---|
883 |
|
---|
884 | /**
|
---|
885 | * Sets offset to capability list.
|
---|
886 | *
|
---|
887 | * @param pPciDev The PCI device.
|
---|
888 | * @param u8Offset The offset to capability list.
|
---|
889 | */
|
---|
890 | DECLINLINE(void) PCIDevSetCapabilityList(PPCIDEVICE pPciDev, uint8_t u8Offset)
|
---|
891 | {
|
---|
892 | PCIDevSetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST, u8Offset);
|
---|
893 | }
|
---|
894 |
|
---|
895 | /**
|
---|
896 | * Returns offset to capability list.
|
---|
897 | *
|
---|
898 | * @returns offset to capability list.
|
---|
899 | * @param pPciDev The PCI device.
|
---|
900 | */
|
---|
901 | DECLINLINE(uint8_t) PCIDevGetCapabilityList(PPCIDEVICE pPciDev)
|
---|
902 | {
|
---|
903 | return PCIDevGetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST);
|
---|
904 | }
|
---|
905 |
|
---|
906 | /**
|
---|
907 | * Sets the interrupt line config register.
|
---|
908 | *
|
---|
909 | * @param pPciDev The PCI device.
|
---|
910 | * @param u8Line The interrupt line.
|
---|
911 | */
|
---|
912 | DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
|
---|
913 | {
|
---|
914 | PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, u8Line);
|
---|
915 | }
|
---|
916 |
|
---|
917 | /**
|
---|
918 | * Gets the interrupt line config register.
|
---|
919 | *
|
---|
920 | * @returns The interrupt line.
|
---|
921 | * @param pPciDev The PCI device.
|
---|
922 | */
|
---|
923 | DECLINLINE(uint8_t) PCIDevGetInterruptLine(PPCIDEVICE pPciDev)
|
---|
924 | {
|
---|
925 | return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE);
|
---|
926 | }
|
---|
927 |
|
---|
928 | /**
|
---|
929 | * Sets the interrupt pin config register.
|
---|
930 | *
|
---|
931 | * @param pPciDev The PCI device.
|
---|
932 | * @param u8Pin The interrupt pin.
|
---|
933 | */
|
---|
934 | DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
|
---|
935 | {
|
---|
936 | PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN, u8Pin);
|
---|
937 | }
|
---|
938 |
|
---|
939 | /**
|
---|
940 | * Gets the interrupt pin config register.
|
---|
941 | *
|
---|
942 | * @returns The interrupt pin.
|
---|
943 | * @param pPciDev The PCI device.
|
---|
944 | */
|
---|
945 | DECLINLINE(uint8_t) PCIDevGetInterruptPin(PPCIDEVICE pPciDev)
|
---|
946 | {
|
---|
947 | return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
|
---|
948 | }
|
---|
949 |
|
---|
950 | #ifdef PCIDEVICEINT_DECLARED
|
---|
951 | DECLINLINE(void) pciDevSetRequestedDevfunc(PPCIDEVICE pDev)
|
---|
952 | {
|
---|
953 | pDev->Int.s.fFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC;
|
---|
954 | }
|
---|
955 |
|
---|
956 | DECLINLINE(void) pciDevClearRequestedDevfunc(PPCIDEVICE pDev)
|
---|
957 | {
|
---|
958 | pDev->Int.s.fFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC;
|
---|
959 | }
|
---|
960 |
|
---|
961 | DECLINLINE(bool) pciDevIsRequestedDevfunc(PPCIDEVICE pDev)
|
---|
962 | {
|
---|
963 | return (pDev->Int.s.fFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0;
|
---|
964 | }
|
---|
965 |
|
---|
966 | DECLINLINE(void) pciDevSetPci2PciBridge(PPCIDEVICE pDev)
|
---|
967 | {
|
---|
968 | pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE;
|
---|
969 | }
|
---|
970 |
|
---|
971 | DECLINLINE(bool) pciDevIsPci2PciBridge(PPCIDEVICE pDev)
|
---|
972 | {
|
---|
973 | return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0;
|
---|
974 | }
|
---|
975 |
|
---|
976 | DECLINLINE(void) pciDevSetPciExpress(PPCIDEVICE pDev)
|
---|
977 | {
|
---|
978 | pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE;
|
---|
979 | }
|
---|
980 |
|
---|
981 | DECLINLINE(bool) pciDevIsPciExpress(PPCIDEVICE pDev)
|
---|
982 | {
|
---|
983 | return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0;
|
---|
984 | }
|
---|
985 |
|
---|
986 | DECLINLINE(void) pciDevSetMsiCapable(PPCIDEVICE pDev)
|
---|
987 | {
|
---|
988 | pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI_CAPABLE;
|
---|
989 | }
|
---|
990 |
|
---|
991 | DECLINLINE(void) pciDevClearMsiCapable(PPCIDEVICE pDev)
|
---|
992 | {
|
---|
993 | pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI_CAPABLE;
|
---|
994 | }
|
---|
995 |
|
---|
996 | DECLINLINE(bool) pciDevIsMsiCapable(PPCIDEVICE pDev)
|
---|
997 | {
|
---|
998 | return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0;
|
---|
999 | }
|
---|
1000 |
|
---|
1001 | DECLINLINE(void) pciDevSetMsi64Capable(PPCIDEVICE pDev)
|
---|
1002 | {
|
---|
1003 | pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI64_CAPABLE;
|
---|
1004 | }
|
---|
1005 |
|
---|
1006 | DECLINLINE(void) pciDevClearMsi64Capable(PPCIDEVICE pDev)
|
---|
1007 | {
|
---|
1008 | pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI64_CAPABLE;
|
---|
1009 | }
|
---|
1010 |
|
---|
1011 | DECLINLINE(bool) pciDevIsMsi64Capable(PPCIDEVICE pDev)
|
---|
1012 | {
|
---|
1013 | return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI64_CAPABLE) != 0;
|
---|
1014 | }
|
---|
1015 |
|
---|
1016 | DECLINLINE(void) pciDevSetMsixCapable(PPCIDEVICE pDev)
|
---|
1017 | {
|
---|
1018 | pDev->Int.s.fFlags |= PCIDEV_FLAG_MSIX_CAPABLE;
|
---|
1019 | }
|
---|
1020 |
|
---|
1021 | DECLINLINE(void) pciDevClearMsixCapable(PPCIDEVICE pDev)
|
---|
1022 | {
|
---|
1023 | pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSIX_CAPABLE;
|
---|
1024 | }
|
---|
1025 |
|
---|
1026 | DECLINLINE(bool) pciDevIsMsixCapable(PPCIDEVICE pDev)
|
---|
1027 | {
|
---|
1028 | return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0;
|
---|
1029 | }
|
---|
1030 |
|
---|
1031 | DECLINLINE(void) pciDevSetPassthrough(PPCIDEVICE pDev)
|
---|
1032 | {
|
---|
1033 | pDev->Int.s.fFlags |= PCIDEV_FLAG_PASSTHROUGH;
|
---|
1034 | }
|
---|
1035 |
|
---|
1036 | DECLINLINE(void) pciDevClearPassthrough(PPCIDEVICE pDev)
|
---|
1037 | {
|
---|
1038 | pDev->Int.s.fFlags &= ~PCIDEV_FLAG_PASSTHROUGH;
|
---|
1039 | }
|
---|
1040 |
|
---|
1041 | DECLINLINE(bool) pciDevIsPassthrough(PPCIDEVICE pDev)
|
---|
1042 | {
|
---|
1043 | return (pDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) != 0;
|
---|
1044 | }
|
---|
1045 |
|
---|
1046 | #endif /* PCIDEVICEINT_DECLARED */
|
---|
1047 |
|
---|
1048 | #if defined(__cplusplus) && defined(IN_RING3)
|
---|
1049 | /* For RTStrPrintf(). */
|
---|
1050 | #include <iprt/string.h>
|
---|
1051 |
|
---|
1052 | /**
|
---|
1053 | * Class representing PCI address. PCI device consist of
|
---|
1054 | * bus, device and function numbers. Generally device PCI
|
---|
1055 | * address could be changed during runtime, but only by
|
---|
1056 | * an OS PCI driver.
|
---|
1057 | *
|
---|
1058 | * @remarks C++ classes (structs included) are not generally accepted in
|
---|
1059 | * VMM devices or drivers. An exception may be granted for this class
|
---|
1060 | * if it's contained to ring-3 and that this is a one time exception
|
---|
1061 | * which sets no precedent.
|
---|
1062 | */
|
---|
1063 | struct PCIBusAddress
|
---|
1064 | {
|
---|
1065 | /** @todo: think if we'll need domain, which is higher
|
---|
1066 | * word of the address. */
|
---|
1067 | int miBus;
|
---|
1068 | int miDevice;
|
---|
1069 | int miFn;
|
---|
1070 |
|
---|
1071 | PCIBusAddress()
|
---|
1072 | {
|
---|
1073 | clear();
|
---|
1074 | }
|
---|
1075 |
|
---|
1076 | PCIBusAddress(int iBus, int iDevice, int iFn)
|
---|
1077 | {
|
---|
1078 | init(iBus, iDevice, iFn);
|
---|
1079 | }
|
---|
1080 |
|
---|
1081 | PCIBusAddress(int32_t iAddr)
|
---|
1082 | {
|
---|
1083 | clear();
|
---|
1084 | fromLong(iAddr);
|
---|
1085 | }
|
---|
1086 |
|
---|
1087 | PCIBusAddress& clear()
|
---|
1088 | {
|
---|
1089 | miBus = miDevice = miFn = -1;
|
---|
1090 | return *this;
|
---|
1091 | }
|
---|
1092 |
|
---|
1093 | void init(int iBus, int iDevice, int iFn)
|
---|
1094 | {
|
---|
1095 | miBus = iBus;
|
---|
1096 | miDevice = iDevice;
|
---|
1097 | miFn = iFn;
|
---|
1098 | }
|
---|
1099 |
|
---|
1100 | void init(const PCIBusAddress &a)
|
---|
1101 | {
|
---|
1102 | miBus = a.miBus;
|
---|
1103 | miDevice = a.miDevice;
|
---|
1104 | miFn = a.miFn;
|
---|
1105 | }
|
---|
1106 |
|
---|
1107 | bool operator<(const PCIBusAddress &a) const
|
---|
1108 | {
|
---|
1109 | if (miBus < a.miBus)
|
---|
1110 | return true;
|
---|
1111 |
|
---|
1112 | if (miBus > a.miBus)
|
---|
1113 | return false;
|
---|
1114 |
|
---|
1115 | if (miDevice < a.miDevice)
|
---|
1116 | return true;
|
---|
1117 |
|
---|
1118 | if (miDevice > a.miDevice)
|
---|
1119 | return false;
|
---|
1120 |
|
---|
1121 | if (miFn < a.miFn)
|
---|
1122 | return true;
|
---|
1123 |
|
---|
1124 | if (miFn > a.miFn)
|
---|
1125 | return false;
|
---|
1126 |
|
---|
1127 | return false;
|
---|
1128 | }
|
---|
1129 |
|
---|
1130 | bool operator==(const PCIBusAddress &a) const
|
---|
1131 | {
|
---|
1132 | return (miBus == a.miBus)
|
---|
1133 | && (miDevice == a.miDevice)
|
---|
1134 | && (miFn == a.miFn);
|
---|
1135 | }
|
---|
1136 |
|
---|
1137 | bool operator!=(const PCIBusAddress &a) const
|
---|
1138 | {
|
---|
1139 | return (miBus != a.miBus)
|
---|
1140 | || (miDevice != a.miDevice)
|
---|
1141 | || (miFn != a.miFn);
|
---|
1142 | }
|
---|
1143 |
|
---|
1144 | bool valid() const
|
---|
1145 | {
|
---|
1146 | return (miBus != -1)
|
---|
1147 | && (miDevice != -1)
|
---|
1148 | && (miFn != -1);
|
---|
1149 | }
|
---|
1150 |
|
---|
1151 | int32_t asLong() const
|
---|
1152 | {
|
---|
1153 | Assert(valid());
|
---|
1154 | return (miBus << 8) | (miDevice << 3) | miFn;
|
---|
1155 | }
|
---|
1156 |
|
---|
1157 | PCIBusAddress& fromLong(int32_t value)
|
---|
1158 | {
|
---|
1159 | miBus = (value >> 8) & 0xff;
|
---|
1160 | miDevice = (value & 0xff) >> 3;
|
---|
1161 | miFn = (value & 7);
|
---|
1162 | return *this;
|
---|
1163 | }
|
---|
1164 |
|
---|
1165 | /** Create string representation of this PCI address. */
|
---|
1166 | bool format(char* szBuf, int32_t cBufSize)
|
---|
1167 | {
|
---|
1168 | if (cBufSize < (/* bus */ 2 + /* : */ 1 + /* device */ 2 + /* . */ 1 + /* function*/ 1 + /* \0 */1))
|
---|
1169 | return false;
|
---|
1170 |
|
---|
1171 | if (valid())
|
---|
1172 | RTStrPrintf(szBuf, cBufSize, "%02x:%02x.%01x", miBus, miDevice, miFn);
|
---|
1173 | else
|
---|
1174 | RTStrPrintf(szBuf, cBufSize, "%s", "<bad>");
|
---|
1175 |
|
---|
1176 | return true;
|
---|
1177 | }
|
---|
1178 |
|
---|
1179 | static const size_t cMaxAddrSize = 10;
|
---|
1180 | };
|
---|
1181 | #endif /* __cplusplus */
|
---|
1182 |
|
---|
1183 | /** @} */
|
---|
1184 |
|
---|
1185 | #endif
|
---|