VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 55027

Last change on this file since 55027 was 44543, checked in by vboxsync, 12 years ago

VBox/pci.h: uOffset -> offReg.
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File size: 47.0 KB
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1/** @file
2 * PCI - The PCI Controller And Devices. (DEV)
3 */
4
5/*
6 * Copyright (C) 2006-2013 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_pci_h
27#define ___VBox_pci_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <iprt/assert.h>
32
33/** @defgroup grp_pci PCI - The PCI Controller.
34 * @{
35 */
36
37/** Pointer to a PCI device. */
38typedef struct PCIDevice *PPCIDEVICE;
39
40
41/**
42 * PCI configuration word 4 (command) and word 6 (status).
43 */
44typedef enum PCICONFIGCOMMAND
45{
46 /** Supports/uses memory accesses. */
47 PCI_COMMAND_IOACCESS = 0x0001,
48 PCI_COMMAND_MEMACCESS = 0x0002,
49 PCI_COMMAND_BUSMASTER = 0x0004
50} PCICONFIGCOMMAND;
51
52
53/**
54 * PCI Address space specification.
55 * This is used when registering a I/O region.
56 */
57/**
58 * Defined by the PCI specification.
59 */
60typedef enum PCIADDRESSSPACE
61{
62 /** Memory. */
63 PCI_ADDRESS_SPACE_MEM = 0x00,
64 /** I/O space. */
65 PCI_ADDRESS_SPACE_IO = 0x01,
66 /** 32-bit BAR. */
67 PCI_ADDRESS_SPACE_BAR32 = 0x00,
68 /** 64-bit BAR. */
69 PCI_ADDRESS_SPACE_BAR64 = 0x04,
70 /** Prefetch memory. */
71 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
72} PCIADDRESSSPACE;
73
74
75/**
76 * Callback function for mapping an PCI I/O region.
77 *
78 * @return VBox status code.
79 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
80 * @param iRegion The region number.
81 * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
82 * is an I/O port, otherwise it's a physical address.
83 *
84 * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
85 * that the device deregister access handlers for it and update its internal
86 * state to reflect this.
87 *
88 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
89 *
90 * @remarks Called with the PDM lock held. The device lock is NOT take because
91 * that is very likely be a lock order violation.
92 */
93typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
94/** Pointer to a FNPCIIOREGIONMAP() function. */
95typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
96
97
98/** @name PCI Configuration Space Registers
99 * @{ */
100/* Commented out values common for different header types */
101/* Common part of the header */
102#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
103#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
104#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
105#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
106#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
107#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
108#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
109#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
110#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
111#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
112#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
113#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
114#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
115#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
116#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
117#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
118
119/* Type 0 header, device */
120#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
121#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
122#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
123#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
124#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
125#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
126#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
127#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
128#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
129#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
130/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
131#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
132#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
133#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
134#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
135/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
136/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
137#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
138#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
139
140/* Type 1 header, PCI-to-PCI bridge */
141/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
142/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
143#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
144#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
145#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
146#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
147#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
148#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
149#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
150#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
151#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
152#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
153#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
154#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
155#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
156#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
157#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
158/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
159/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
160/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
161/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
162#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
163#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
164
165/* Type 2 header, PCI-to-CardBus bridge */
166#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
167#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
168#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
169#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
170#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
171#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
172/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
173/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
174#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
175#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
176#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
177#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
178#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
179#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
180#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
181#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
182/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
183/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
184/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
185/** @} */
186
187
188/* Possible values in status bitmask */
189#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
190#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
191#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
192#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
193#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
194#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
195#define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
196#define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
197#define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
198#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
199#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
200#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
201#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
202#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
203
204
205/* Command bitmask */
206#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
207#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
208#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
209#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
210#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
211#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
212#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
213#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
214#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
215#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
216#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
217
218
219/* Capability list values (capability offset 0) */
220/* Next value pointer in offset 1, or 0 if none */
221#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
222#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
223#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
224#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
225#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
226#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
227#define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
228#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
229#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
230#define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
231#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
232#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
233#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
234#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
235#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
236#define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
237#define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
238#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
239#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
240
241/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
242#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
243#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
244#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
245#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
246#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
247#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
248#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
249#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
250#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
251#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
252#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
253#define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
254#define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
255#define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
256
257
258/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
259#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
260#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
261#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
262/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
263 someone very similar to log_2().
264 000 1
265 001 2
266 010 4
267 011 8
268 100 16
269 101 32
270 110 Reserved
271 111 Reserved */
272#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
273#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
274
275/* MSI-X flags (2 bytes, capability offset 2) */
276#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
277#define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
278
279/* Power management flags (2 bytes, capability offset 2) */
280#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
281#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
282#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
283#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
284#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
285#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
286#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
287#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
288#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
289#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
290#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
291#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
292#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
293#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
294
295/* Power management control flags (2 bytes, capability offset 4) */
296#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
297#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
298#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
299#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
300#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
301#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
302
303/* PCI-X config flags (2 bytes, capability offset 2) */
304#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
305#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
306#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
307#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
308#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
309#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
310#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
311#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
312
313/* PCI-X config flags (4 bytes, capability offset 4) */
314#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
315#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
316#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
317#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
318#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
319#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
320#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
321#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
322#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
323#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
324#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
325#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
326#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
327
328/* PCI Express config flags (2 bytes, capability offset 2) */
329#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
330#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
331#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
332#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
333#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
334#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
335#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
336#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
337#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
338#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
339#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
340#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
341#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
342
343/* PCI Express device capabilities (4 bytes, capability offset 4) */
344#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
345#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
346#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
347#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
348#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
349#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
350#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
351#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
352#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
353#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
354#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
355#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
356
357/* PCI Express device control (2 bytes, capability offset 8) */
358#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
359#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
360#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
361#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
362#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
363#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
364#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
365#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
366#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
367#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
368#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
369#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
370#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
371
372/* PCI Express device status (2 bytes, capability offset 10) */
373#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
374#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
375#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
376#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
377#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
378#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
379
380/* PCI Express link capabilities (4 bytes, capability offset 12) */
381#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
382#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
383#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
384#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
385#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
386#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
387#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
388#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
389#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
390#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
391
392/* PCI Express link control (2 bytes, capability offset 16) */
393#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
394#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
395#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
396#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
397#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
398#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
399#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
400#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
401#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
402#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
403
404/* PCI Express link status (2 bytes, capability offset 18) */
405#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
406#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
407#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
408#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
409#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
410#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
411#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
412#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
413
414/* PCI Express slot capabilities (4 bytes, capability offset 20) */
415#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
416#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
417#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
418#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
419#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
420#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
421#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
422#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
423#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
424#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
425#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
426#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
427
428/* PCI Express slot control (2 bytes, capability offset 24) */
429#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
430#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
431#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
432#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
433#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
434#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
435#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
436#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
437#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
438#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
439#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
440
441/* PCI Express slot status (2 bytes, capability offset 26) */
442#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
443#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
444#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
445#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
446#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
447#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
448#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
449#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
450#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
451
452/* PCI Express root control (2 bytes, capability offset 28) */
453#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
454#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
455#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
456#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
457#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
458
459/* PCI Express root capabilities (2 bytes, capability offset 30) */
460#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
461
462/* PCI Express root status (4 bytes, capability offset 32) */
463#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
464#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
465#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
466
467
468/**
469 * Callback function for reading from the PCI configuration space.
470 *
471 * @returns The register value.
472 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
473 * @param Address The configuration space register address. [0..4096]
474 * @param cb The register size. [1,2,4]
475 *
476 * @remarks Called with the PDM lock held. The device lock is NOT take because
477 * that is very likely be a lock order violation.
478 */
479typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
480/** Pointer to a FNPCICONFIGREAD() function. */
481typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
482/** Pointer to a PFNPCICONFIGREAD. */
483typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
484
485/**
486 * Callback function for writing to the PCI configuration space.
487 *
488 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
489 * @param Address The configuration space register address. [0..4096]
490 * @param u32Value The value that's being written. The number of bits actually used from
491 * this value is determined by the cb parameter.
492 * @param cb The register size. [1,2,4]
493 *
494 * @remarks Called with the PDM lock held. The device lock is NOT take because
495 * that is very likely be a lock order violation.
496 */
497typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
498/** Pointer to a FNPCICONFIGWRITE() function. */
499typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
500/** Pointer to a PFNPCICONFIGWRITE. */
501typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
502
503/** Fixed I/O region number for ROM. */
504#define PCI_ROM_SLOT 6
505#define VBOX_PCI_ROM_SLOT 6
506/** Max number of I/O regions. */
507#define PCI_NUM_REGIONS 7
508#define VBOX_PCI_NUM_REGIONS 7
509
510/*
511 * Hack to include the PCIDEVICEINT structure at the right place
512 * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
513 */
514#ifdef PCI_INCLUDE_PRIVATE
515# include "PCIInternal.h"
516#endif
517
518/**
519 * PCI Device structure.
520 */
521typedef struct PCIDevice
522{
523 /** PCI config space. */
524 uint8_t config[256];
525
526 /** Internal data. */
527 union
528 {
529#ifdef PCIDEVICEINT_DECLARED
530 PCIDEVICEINT s;
531#endif
532 char padding[328];
533 } Int;
534
535 /** Read only data.
536 * @{
537 */
538 /** PCI device number on the pci bus. */
539 int32_t devfn;
540 uint32_t Alignment0; /**< Alignment. */
541 /** Device name. */
542 R3PTRTYPE(const char *) name;
543 /** Pointer to the device instance which registered the device. */
544 PPDMDEVINSR3 pDevIns;
545 /** @} */
546} PCIDEVICE;
547
548/** @todo handle extended space access. */
549
550DECLINLINE(void) PCIDevSetByte(PPCIDEVICE pPciDev, uint32_t offReg, uint8_t u8Value)
551{
552 pPciDev->config[offReg] = u8Value;
553}
554
555DECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t offReg)
556{
557 return pPciDev->config[offReg];
558}
559
560DECLINLINE(void) PCIDevSetWord(PPCIDEVICE pPciDev, uint32_t offReg, uint16_t u16Value)
561{
562 *(uint16_t*)&pPciDev->config[offReg] = RT_H2LE_U16(u16Value);
563}
564
565DECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t offReg)
566{
567 uint16_t u16Value = *(uint16_t*)&pPciDev->config[offReg];
568 return RT_H2LE_U16(u16Value);
569}
570
571DECLINLINE(void) PCIDevSetDWord(PPCIDEVICE pPciDev, uint32_t offReg, uint32_t u32Value)
572{
573 *(uint32_t*)&pPciDev->config[offReg] = RT_H2LE_U32(u32Value);
574}
575
576DECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t offReg)
577{
578 uint32_t u32Value = *(uint32_t*)&pPciDev->config[offReg];
579 return RT_H2LE_U32(u32Value);
580}
581
582DECLINLINE(void) PCIDevSetQWord(PPCIDEVICE pPciDev, uint32_t offReg, uint64_t u64Value)
583{
584 *(uint64_t*)&pPciDev->config[offReg] = RT_H2LE_U64(u64Value);
585}
586
587DECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t offReg)
588{
589 uint64_t u64Value = *(uint64_t*)&pPciDev->config[offReg];
590 return RT_H2LE_U64(u64Value);
591}
592
593/**
594 * Sets the vendor id config register.
595 * @param pPciDev The PCI device.
596 * @param u16VendorId The vendor id.
597 */
598DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
599{
600 PCIDevSetWord(pPciDev, VBOX_PCI_VENDOR_ID, u16VendorId);
601}
602
603/**
604 * Gets the vendor id config register.
605 * @returns the vendor id.
606 * @param pPciDev The PCI device.
607 */
608DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
609{
610 return PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID);
611}
612
613
614/**
615 * Sets the device id config register.
616 * @param pPciDev The PCI device.
617 * @param u16DeviceId The device id.
618 */
619DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
620{
621 PCIDevSetWord(pPciDev, VBOX_PCI_DEVICE_ID, u16DeviceId);
622}
623
624/**
625 * Gets the device id config register.
626 * @returns the device id.
627 * @param pPciDev The PCI device.
628 */
629DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
630{
631 return PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID);
632}
633
634/**
635 * Sets the command config register.
636 *
637 * @param pPciDev The PCI device.
638 * @param u16Command The command register value.
639 */
640DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
641{
642 PCIDevSetWord(pPciDev, VBOX_PCI_COMMAND, u16Command);
643}
644
645
646/**
647 * Gets the command config register.
648 * @returns The command register value.
649 * @param pPciDev The PCI device.
650 */
651DECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
652{
653 return PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
654}
655
656/**
657 * Checks if the given PCI device is a bus master.
658 * @returns true if the device is a bus master, false if not.
659 * @param pPciDev The PCI device.
660 */
661DECLINLINE(bool) PCIDevIsBusmaster(PPCIDEVICE pPciDev)
662{
663 return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_MASTER) != 0;
664}
665
666/**
667 * Checks if INTx interrupts disabled in the command config register.
668 * @returns true if disabled.
669 * @param pPciDev The PCI device.
670 */
671DECLINLINE(bool) PCIDevIsIntxDisabled(PPCIDEVICE pPciDev)
672{
673 return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_INTX_DISABLE) != 0;
674}
675
676/**
677 * Gets the status config register.
678 *
679 * @returns status config register.
680 * @param pPciDev The PCI device.
681 */
682DECLINLINE(uint16_t) PCIDevGetStatus(PPCIDEVICE pPciDev)
683{
684 return PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
685}
686
687/**
688 * Sets the status config register.
689 *
690 * @param pPciDev The PCI device.
691 * @param u16Status The status register value.
692 */
693DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
694{
695 PCIDevSetWord(pPciDev, VBOX_PCI_STATUS, u16Status);
696}
697
698
699/**
700 * Sets the revision id config register.
701 *
702 * @param pPciDev The PCI device.
703 * @param u8RevisionId The revision id.
704 */
705DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
706{
707 PCIDevSetByte(pPciDev, VBOX_PCI_REVISION_ID, u8RevisionId);
708}
709
710
711/**
712 * Sets the register level programming class config register.
713 *
714 * @param pPciDev The PCI device.
715 * @param u8ClassProg The new value.
716 */
717DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
718{
719 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_PROG, u8ClassProg);
720}
721
722
723/**
724 * Sets the sub-class (aka device class) config register.
725 *
726 * @param pPciDev The PCI device.
727 * @param u8SubClass The sub-class.
728 */
729DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
730{
731 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_SUB, u8SubClass);
732}
733
734
735/**
736 * Sets the base class config register.
737 *
738 * @param pPciDev The PCI device.
739 * @param u8BaseClass The base class.
740 */
741DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
742{
743 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_BASE, u8BaseClass);
744}
745
746/**
747 * Sets the header type config register.
748 *
749 * @param pPciDev The PCI device.
750 * @param u8HdrType The header type.
751 */
752DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
753{
754 PCIDevSetByte(pPciDev, VBOX_PCI_HEADER_TYPE, u8HdrType);
755}
756
757/**
758 * Gets the header type config register.
759 *
760 * @param pPciDev The PCI device.
761 * @returns u8HdrType The header type.
762 */
763DECLINLINE(uint8_t) PCIDevGetHeaderType(PPCIDEVICE pPciDev)
764{
765 return PCIDevGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
766}
767
768/**
769 * Sets the BIST (built-in self-test) config register.
770 *
771 * @param pPciDev The PCI device.
772 * @param u8Bist The BIST value.
773 */
774DECLINLINE(void) PCIDevSetBIST(PPCIDEVICE pPciDev, uint8_t u8Bist)
775{
776 PCIDevSetByte(pPciDev, VBOX_PCI_BIST, u8Bist);
777}
778
779/**
780 * Gets the BIST (built-in self-test) config register.
781 *
782 * @param pPciDev The PCI device.
783 * @returns u8Bist The BIST.
784 */
785DECLINLINE(uint8_t) PCIDevGetBIST(PPCIDEVICE pPciDev)
786{
787 return PCIDevGetByte(pPciDev, VBOX_PCI_BIST);
788}
789
790
791/**
792 * Sets a base address config register.
793 *
794 * @param pPciDev The PCI device.
795 * @param fIOSpace Whether it's I/O (true) or memory (false) space.
796 * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
797 * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
798 * @param u32Addr The address value.
799 */
800DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit, uint32_t u32Addr)
801{
802 if (fIOSpace)
803 {
804 Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
805 u32Addr |= RT_BIT_32(0);
806 }
807 else
808 {
809 Assert(!(u32Addr & 0xf));
810 if (fPrefetchable)
811 u32Addr |= RT_BIT_32(3);
812 if (f64Bit)
813 u32Addr |= 0x2 << 1;
814 }
815 switch (iReg)
816 {
817 case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
818 case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
819 case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
820 case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
821 case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
822 case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
823 default: AssertFailedReturnVoid();
824 }
825
826 PCIDevSetDWord(pPciDev, iReg, u32Addr);
827}
828
829/**
830 * Please document me. I don't seem to be getting as much as calculating
831 * the address of some PCI region.
832 */
833DECLINLINE(uint32_t) PCIDevGetRegionReg(uint32_t iRegion)
834{
835 return iRegion == VBOX_PCI_ROM_SLOT
836 ? VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
837}
838
839/**
840 * Sets the sub-system vendor id config register.
841 *
842 * @param pPciDev The PCI device.
843 * @param u16SubSysVendorId The sub-system vendor id.
844 */
845DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
846{
847 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, u16SubSysVendorId);
848}
849
850/**
851 * Gets the sub-system vendor id config register.
852 * @returns the sub-system vendor id.
853 * @param pPciDev The PCI device.
854 */
855DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
856{
857 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID);
858}
859
860
861/**
862 * Sets the sub-system id config register.
863 *
864 * @param pPciDev The PCI device.
865 * @param u16SubSystemId The sub-system id.
866 */
867DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
868{
869 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID, u16SubSystemId);
870}
871
872/**
873 * Gets the sub-system id config register.
874 * @returns the sub-system id.
875 * @param pPciDev The PCI device.
876 */
877DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
878{
879 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID);
880}
881
882/**
883 * Sets offset to capability list.
884 *
885 * @param pPciDev The PCI device.
886 * @param u8Offset The offset to capability list.
887 */
888DECLINLINE(void) PCIDevSetCapabilityList(PPCIDEVICE pPciDev, uint8_t u8Offset)
889{
890 PCIDevSetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST, u8Offset);
891}
892
893/**
894 * Returns offset to capability list.
895 *
896 * @returns offset to capability list.
897 * @param pPciDev The PCI device.
898 */
899DECLINLINE(uint8_t) PCIDevGetCapabilityList(PPCIDEVICE pPciDev)
900{
901 return PCIDevGetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST);
902}
903
904/**
905 * Sets the interrupt line config register.
906 *
907 * @param pPciDev The PCI device.
908 * @param u8Line The interrupt line.
909 */
910DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
911{
912 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, u8Line);
913}
914
915/**
916 * Gets the interrupt line config register.
917 *
918 * @returns The interrupt line.
919 * @param pPciDev The PCI device.
920 */
921DECLINLINE(uint8_t) PCIDevGetInterruptLine(PPCIDEVICE pPciDev)
922{
923 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE);
924}
925
926/**
927 * Sets the interrupt pin config register.
928 *
929 * @param pPciDev The PCI device.
930 * @param u8Pin The interrupt pin.
931 */
932DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
933{
934 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN, u8Pin);
935}
936
937/**
938 * Gets the interrupt pin config register.
939 *
940 * @returns The interrupt pin.
941 * @param pPciDev The PCI device.
942 */
943DECLINLINE(uint8_t) PCIDevGetInterruptPin(PPCIDEVICE pPciDev)
944{
945 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
946}
947
948#ifdef PCIDEVICEINT_DECLARED
949DECLINLINE(void) pciDevSetRequestedDevfunc(PPCIDEVICE pDev)
950{
951 pDev->Int.s.fFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC;
952}
953
954DECLINLINE(void) pciDevClearRequestedDevfunc(PPCIDEVICE pDev)
955{
956 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC;
957}
958
959DECLINLINE(bool) pciDevIsRequestedDevfunc(PPCIDEVICE pDev)
960{
961 return (pDev->Int.s.fFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0;
962}
963
964DECLINLINE(void) pciDevSetPci2PciBridge(PPCIDEVICE pDev)
965{
966 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE;
967}
968
969DECLINLINE(bool) pciDevIsPci2PciBridge(PPCIDEVICE pDev)
970{
971 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0;
972}
973
974DECLINLINE(void) pciDevSetPciExpress(PPCIDEVICE pDev)
975{
976 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE;
977}
978
979DECLINLINE(bool) pciDevIsPciExpress(PPCIDEVICE pDev)
980{
981 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0;
982}
983
984DECLINLINE(void) pciDevSetMsiCapable(PPCIDEVICE pDev)
985{
986 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI_CAPABLE;
987}
988
989DECLINLINE(void) pciDevClearMsiCapable(PPCIDEVICE pDev)
990{
991 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI_CAPABLE;
992}
993
994DECLINLINE(bool) pciDevIsMsiCapable(PPCIDEVICE pDev)
995{
996 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0;
997}
998
999DECLINLINE(void) pciDevSetMsi64Capable(PPCIDEVICE pDev)
1000{
1001 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI64_CAPABLE;
1002}
1003
1004DECLINLINE(void) pciDevClearMsi64Capable(PPCIDEVICE pDev)
1005{
1006 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI64_CAPABLE;
1007}
1008
1009DECLINLINE(bool) pciDevIsMsi64Capable(PPCIDEVICE pDev)
1010{
1011 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI64_CAPABLE) != 0;
1012}
1013
1014DECLINLINE(void) pciDevSetMsixCapable(PPCIDEVICE pDev)
1015{
1016 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSIX_CAPABLE;
1017}
1018
1019DECLINLINE(void) pciDevClearMsixCapable(PPCIDEVICE pDev)
1020{
1021 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSIX_CAPABLE;
1022}
1023
1024DECLINLINE(bool) pciDevIsMsixCapable(PPCIDEVICE pDev)
1025{
1026 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0;
1027}
1028
1029DECLINLINE(void) pciDevSetPassthrough(PPCIDEVICE pDev)
1030{
1031 pDev->Int.s.fFlags |= PCIDEV_FLAG_PASSTHROUGH;
1032}
1033
1034DECLINLINE(void) pciDevClearPassthrough(PPCIDEVICE pDev)
1035{
1036 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_PASSTHROUGH;
1037}
1038
1039DECLINLINE(bool) pciDevIsPassthrough(PPCIDEVICE pDev)
1040{
1041 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) != 0;
1042}
1043
1044#endif /* PCIDEVICEINT_DECLARED */
1045
1046#if defined(__cplusplus) && defined(IN_RING3)
1047/* For RTStrPrintf(). */
1048#include <iprt/string.h>
1049
1050/**
1051 * Class representing PCI address. PCI device consist of
1052 * bus, device and function numbers. Generally device PCI
1053 * address could be changed during runtime, but only by
1054 * an OS PCI driver.
1055 *
1056 * @remarks C++ classes (structs included) are not generally accepted in
1057 * VMM devices or drivers. An exception may be granted for this class
1058 * if it's contained to ring-3 and that this is a one time exception
1059 * which sets no precedent.
1060 */
1061struct PCIBusAddress
1062{
1063 /** @todo: think if we'll need domain, which is higher
1064 * word of the address. */
1065 int miBus;
1066 int miDevice;
1067 int miFn;
1068
1069 PCIBusAddress()
1070 {
1071 clear();
1072 }
1073
1074 PCIBusAddress(int iBus, int iDevice, int iFn)
1075 {
1076 init(iBus, iDevice, iFn);
1077 }
1078
1079 PCIBusAddress(int32_t iAddr)
1080 {
1081 clear();
1082 fromLong(iAddr);
1083 }
1084
1085 PCIBusAddress& clear()
1086 {
1087 miBus = miDevice = miFn = -1;
1088 return *this;
1089 }
1090
1091 void init(int iBus, int iDevice, int iFn)
1092 {
1093 miBus = iBus;
1094 miDevice = iDevice;
1095 miFn = iFn;
1096 }
1097
1098 void init(const PCIBusAddress &a)
1099 {
1100 miBus = a.miBus;
1101 miDevice = a.miDevice;
1102 miFn = a.miFn;
1103 }
1104
1105 bool operator<(const PCIBusAddress &a) const
1106 {
1107 if (miBus < a.miBus)
1108 return true;
1109
1110 if (miBus > a.miBus)
1111 return false;
1112
1113 if (miDevice < a.miDevice)
1114 return true;
1115
1116 if (miDevice > a.miDevice)
1117 return false;
1118
1119 if (miFn < a.miFn)
1120 return true;
1121
1122 if (miFn > a.miFn)
1123 return false;
1124
1125 return false;
1126 }
1127
1128 bool operator==(const PCIBusAddress &a) const
1129 {
1130 return (miBus == a.miBus)
1131 && (miDevice == a.miDevice)
1132 && (miFn == a.miFn);
1133 }
1134
1135 bool operator!=(const PCIBusAddress &a) const
1136 {
1137 return (miBus != a.miBus)
1138 || (miDevice != a.miDevice)
1139 || (miFn != a.miFn);
1140 }
1141
1142 bool valid() const
1143 {
1144 return (miBus != -1)
1145 && (miDevice != -1)
1146 && (miFn != -1);
1147 }
1148
1149 int32_t asLong() const
1150 {
1151 Assert(valid());
1152 return (miBus << 8) | (miDevice << 3) | miFn;
1153 }
1154
1155 PCIBusAddress& fromLong(int32_t value)
1156 {
1157 miBus = (value >> 8) & 0xff;
1158 miDevice = (value & 0xff) >> 3;
1159 miFn = (value & 7);
1160 return *this;
1161 }
1162
1163 /** Create string representation of this PCI address. */
1164 bool format(char* szBuf, int32_t cBufSize)
1165 {
1166 if (cBufSize < (/* bus */ 2 + /* : */ 1 + /* device */ 2 + /* . */ 1 + /* function*/ 1 + /* \0 */1))
1167 return false;
1168
1169 if (valid())
1170 RTStrPrintf(szBuf, cBufSize, "%02x:%02x.%01x", miBus, miDevice, miFn);
1171 else
1172 RTStrPrintf(szBuf, cBufSize, "%s", "<bad>");
1173
1174 return true;
1175 }
1176
1177 static const size_t cMaxAddrSize = 10;
1178};
1179#endif /* __cplusplus */
1180
1181/** @} */
1182
1183#endif
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