VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 32820

Last change on this file since 32820 was 32820, checked in by vboxsync, 14 years ago

PCI, PDM: initial drop of MSI support
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File size: 41.7 KB
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1/** @file
2 * PCI - The PCI Controller And Devices. (DEV)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_pci_h
27#define ___VBox_pci_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <iprt/assert.h>
32
33/** @defgroup grp_pci PCI - The PCI Controller.
34 * @{
35 */
36
37/** Pointer to a PCI device. */
38typedef struct PCIDevice *PPCIDEVICE;
39
40
41/**
42 * PCI configuration word 4 (command) and word 6 (status).
43 */
44typedef enum PCICONFIGCOMMAND
45{
46 /** Supports/uses memory accesses. */
47 PCI_COMMAND_IOACCESS = 0x0001,
48 PCI_COMMAND_MEMACCESS = 0x0002,
49 PCI_COMMAND_BUSMASTER = 0x0004
50} PCICONFIGCOMMAND;
51
52
53/**
54 * PCI Address space specification.
55 * This is used when registering a I/O region.
56 */
57/** Note: There are all sorts of dirty dependencies on the values in the
58 * pci device. Be careful when changing this.
59 * @todo we should introduce 32 & 64 bits physical address types
60 */
61typedef enum PCIADDRESSSPACE
62{
63 /** Memory. */
64 PCI_ADDRESS_SPACE_MEM = 0x00,
65 /** I/O space. */
66 PCI_ADDRESS_SPACE_IO = 0x01,
67 /** Prefetch memory. */
68 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
69} PCIADDRESSSPACE;
70
71
72/**
73 * Callback function for mapping an PCI I/O region.
74 *
75 * @return VBox status code.
76 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
77 * @param iRegion The region number.
78 * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
79 * is an I/O port, otherwise it's a physical address.
80 *
81 * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
82 * that the device deregister access handlers for it and update its internal
83 * state to reflect this.
84 *
85 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
86 *
87 * @remarks The address is *NOT* relative to pci_mem_base.
88 */
89typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
90/** Pointer to a FNPCIIOREGIONMAP() function. */
91typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
92
93
94/** @name PCI Configuration Space Registers
95 * @{ */
96/* Commented out values common for different header types */
97/* Common part of the header */
98#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
99#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
100#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
101#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
102#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
103#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
104#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
105#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
106#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
107#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
108#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
109#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
110#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
111#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
112#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
113#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
114
115/* Type 0 header, device */
116#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
117#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
118#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
119#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
120#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
121#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
122#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
123#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
124#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
125#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
126/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
127#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
128#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
129#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
130#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
131/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
132/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
133#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
134#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
135
136/* Type 1 header, PCI-to-PCI bridge */
137/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
138/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
139#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
140#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
141#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
142#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
143#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
144#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
145#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
146#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
147#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
148#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
149#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
150#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
151#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
152#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
153#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
154/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
155/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
156/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
157/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
158#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
159#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
160
161/* Type 2 header, PCI-to-CardBus bridge */
162#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
163#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
164#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
165#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
166#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
167#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
168/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
169/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
170#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
171#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
172#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
173#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
174#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
175#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
176#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
177#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
178/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
179/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
180/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
181/** @} */
182
183
184/* Possible values in status bitmask */
185#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
186#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
187#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
188#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
189#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
190#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
191#define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
192#define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
193#define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
194#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
195#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
196#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
197#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
198#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
199
200
201/* Command bitmask */
202#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
203#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
204#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
205#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
206#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
207#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
208#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
209#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
210#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
211#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
212#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
213
214
215/* Capability list values (capability offset 0) */
216/* Next value pointer in offset 1, or 0 if none */
217#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
218#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
219#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
220#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
221#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
222#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
223#define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
224#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
225#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
226#define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
227#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
228#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
229#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
230#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
231#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
232#define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
233#define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
234#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
235#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
236
237/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
238#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
239#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
240#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
241#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
242#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
243#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
244#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
245#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
246#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
247#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
248#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
249#define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
250#define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
251#define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
252
253
254/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
255#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
256#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
257#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
258/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
259 someone very similar to log_2().
260 000 1
261 001 2
262 010 4
263 011 8
264 100 16
265 101 32
266 110 Reserved
267 111 Reserved */
268#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
269#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
270
271/* MSI-X flags (2 bytes, capability offset 2) */
272#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000
273
274/* Power management flags (2 bytes, capability offset 2) */
275#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
276#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
277#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
278#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
279#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
280#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
281#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
282#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
283#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
284#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
285#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
286#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
287#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
288#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
289
290/* Power management control flags (2 bytes, capability offset 4) */
291#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
292#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
293#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
294#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
295#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
296#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
297
298/* PCI-X config flags (2 bytes, capability offset 2) */
299#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
300#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
301#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
302#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
303#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
304#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
305#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
306#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
307
308/* PCI-X config flags (4 bytes, capability offset 4) */
309#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
310#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
311#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
312#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
313#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
314#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
315#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
316#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
317#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
318#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
319#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
320#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
321#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
322
323/* PCI Express config flags (2 bytes, capability offset 2) */
324#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
325#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
326#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
327#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
328#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
329#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
330#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
331#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
332#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
333#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
334#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
335#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
336#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
337
338/* PCI Express device capabilities (4 bytes, capability offset 4) */
339#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
340#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
341#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
342#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
343#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
344#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
345#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
346#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
347#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
348#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
349#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
350#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
351
352/* PCI Express device control (2 bytes, capability offset 8) */
353#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
354#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
355#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
356#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
357#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
358#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
359#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
360#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
361#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
362#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
363#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
364#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
365#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
366
367/* PCI Express device status (2 bytes, capability offset 10) */
368#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
369#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
370#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
371#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
372#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
373#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
374
375/* PCI Express link capabilities (4 bytes, capability offset 12) */
376#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
377#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
378#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
379#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
380#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
381#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
382#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
383#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
384#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
385#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
386
387/* PCI Express link control (2 bytes, capability offset 16) */
388#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
389#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
390#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
391#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
392#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
393#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
394#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
395#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
396#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
397#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
398
399/* PCI Express link status (2 bytes, capability offset 18) */
400#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
401#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
402#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
403#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
404#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
405#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
406#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
407#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
408
409/* PCI Express slot capabilities (4 bytes, capability offset 20) */
410#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
411#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
412#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
413#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
414#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
415#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
416#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
417#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
418#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
419#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
420#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
421#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
422
423/* PCI Express slot control (2 bytes, capability offset 24) */
424#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
425#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
426#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
427#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
428#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
429#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
430#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
431#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
432#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
433#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
434#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
435
436/* PCI Express slot status (2 bytes, capability offset 26) */
437#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
438#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
439#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
440#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
441#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
442#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
443#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
444#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
445#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
446
447/* PCI Express root control (2 bytes, capability offset 28) */
448#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
449#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
450#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
451#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
452#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
453
454/* PCI Express root capabilities (2 bytes, capability offset 30) */
455#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
456
457/* PCI Express root status (4 bytes, capability offset 32) */
458#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
459#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
460#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
461
462
463/**
464 * Callback function for reading from the PCI configuration space.
465 *
466 * @returns The register value.
467 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
468 * @param Address The configuration space register address. [0..4096]
469 * @param cb The register size. [1,2,4]
470 */
471typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
472/** Pointer to a FNPCICONFIGREAD() function. */
473typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
474/** Pointer to a PFNPCICONFIGREAD. */
475typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
476
477/**
478 * Callback function for writing to the PCI configuration space.
479 *
480 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
481 * @param Address The configuration space register address. [0..4096]
482 * @param u32Value The value that's being written. The number of bits actually used from
483 * this value is determined by the cb parameter.
484 * @param cb The register size. [1,2,4]
485 */
486typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
487/** Pointer to a FNPCICONFIGWRITE() function. */
488typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
489/** Pointer to a PFNPCICONFIGWRITE. */
490typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
491
492/** Fixed I/O region number for ROM. */
493#define PCI_ROM_SLOT 6
494/** Max number of I/O regions. */
495#define PCI_NUM_REGIONS 7
496
497/*
498 * Hack to include the PCIDEVICEINT structure at the right place
499 * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
500 */
501#ifdef PCI_INCLUDE_PRIVATE
502# include "PCIInternal.h"
503#endif
504
505/**
506 * PCI Device structure.
507 */
508typedef struct PCIDevice
509{
510 /** PCI config space. */
511 uint8_t config[256];
512
513 /** Internal data. */
514 union
515 {
516#ifdef PCIDEVICEINT_DECLARED
517 PCIDEVICEINT s;
518#endif
519 char padding[256];
520 } Int;
521
522 /** Read only data.
523 * @{
524 */
525 /** PCI device number on the pci bus. */
526 int32_t devfn;
527 uint32_t Alignment0; /**< Alignment. */
528 /** Device name. */
529 R3PTRTYPE(const char *) name;
530 /** Pointer to the device instance which registered the device. */
531 PPDMDEVINSR3 pDevIns;
532 /** @} */
533} PCIDEVICE;
534
535/* @todo: handle extended space access */
536DECLINLINE(void) PCIDevSetByte(PPCIDEVICE pPciDev, uint32_t uOffset, uint8_t u8Value)
537{
538 pPciDev->config[uOffset] = u8Value;
539}
540
541DECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t uOffset)
542{
543 return pPciDev->config[uOffset];
544}
545
546DECLINLINE(void) PCIDevSetWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint16_t u16Value)
547{
548 *(uint16_t*)&pPciDev->config[uOffset] = RT_H2LE_U16(u16Value);
549}
550
551DECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t uOffset)
552{
553 uint16_t u16Value = *(uint16_t*)&pPciDev->config[uOffset];
554 return RT_H2LE_U16(u16Value);
555}
556
557DECLINLINE(void) PCIDevSetDWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint32_t u32Value)
558{
559 *(uint32_t*)&pPciDev->config[uOffset] = RT_H2LE_U32(u32Value);
560}
561
562DECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t uOffset)
563{
564 uint32_t u32Value = *(uint32_t*)&pPciDev->config[uOffset];
565 return RT_H2LE_U32(u32Value);
566}
567
568DECLINLINE(void) PCIDevSetQWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint64_t u64Value)
569{
570 *(uint64_t*)&pPciDev->config[uOffset] = RT_H2LE_U64(u64Value);
571}
572
573DECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t uOffset)
574{
575 uint64_t u64Value = *(uint64_t*)&pPciDev->config[uOffset];
576 return RT_H2LE_U64(u64Value);
577}
578
579/**
580 * Sets the vendor id config register.
581 * @param pPciDev The PCI device.
582 * @param u16VendorId The vendor id.
583 */
584DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
585{
586 PCIDevSetWord(pPciDev, VBOX_PCI_VENDOR_ID, u16VendorId);
587}
588
589/**
590 * Gets the vendor id config register.
591 * @returns the vendor id.
592 * @param pPciDev The PCI device.
593 */
594DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
595{
596 return PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID);
597}
598
599
600/**
601 * Sets the device id config register.
602 * @param pPciDev The PCI device.
603 * @param u16DeviceId The device id.
604 */
605DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
606{
607 PCIDevSetWord(pPciDev, VBOX_PCI_DEVICE_ID, u16DeviceId);
608}
609
610/**
611 * Gets the device id config register.
612 * @returns the device id.
613 * @param pPciDev The PCI device.
614 */
615DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
616{
617 return PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID);
618}
619
620/**
621 * Sets the command config register.
622 *
623 * @param pPciDev The PCI device.
624 * @param u16Command The command register value.
625 */
626DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
627{
628 PCIDevSetWord(pPciDev, VBOX_PCI_COMMAND, u16Command);
629}
630
631
632/**
633 * Gets the command config register.
634 * @returns The command register value.
635 * @param pPciDev The PCI device.
636 */
637DECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
638{
639 return PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
640}
641
642
643/**
644 * Sets the status config register.
645 *
646 * @param pPciDev The PCI device.
647 * @param u16Status The status register value.
648 */
649DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
650{
651 PCIDevSetWord(pPciDev, VBOX_PCI_STATUS, u16Status);
652}
653
654
655/**
656 * Sets the revision id config register.
657 *
658 * @param pPciDev The PCI device.
659 * @param u8RevisionId The revision id.
660 */
661DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
662{
663 PCIDevSetByte(pPciDev, VBOX_PCI_REVISION_ID, u8RevisionId);
664}
665
666
667/**
668 * Sets the register level programming class config register.
669 *
670 * @param pPciDev The PCI device.
671 * @param u8ClassProg The new value.
672 */
673DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
674{
675 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_PROG, u8ClassProg);
676}
677
678
679/**
680 * Sets the sub-class (aka device class) config register.
681 *
682 * @param pPciDev The PCI device.
683 * @param u8SubClass The sub-class.
684 */
685DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
686{
687 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_SUB, u8SubClass);
688}
689
690
691/**
692 * Sets the base class config register.
693 *
694 * @param pPciDev The PCI device.
695 * @param u8BaseClass The base class.
696 */
697DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
698{
699 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_BASE, u8BaseClass);
700}
701
702/**
703 * Sets the header type config register.
704 *
705 * @param pPciDev The PCI device.
706 * @param u8HdrType The header type.
707 */
708DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
709{
710 PCIDevSetByte(pPciDev, VBOX_PCI_HEADER_TYPE, u8HdrType);
711}
712
713/**
714 * Gets the header type config register.
715 *
716 * @param pPciDev The PCI device.
717 * @returns u8HdrType The header type.
718 */
719DECLINLINE(uint8_t) PCIDevGetHeaderType(PPCIDEVICE pPciDev)
720{
721 return PCIDevGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
722}
723
724/**
725 * Sets the BIST (built-in self-test)config register.
726 *
727 * @param pPciDev The PCI device.
728 * @param u8Bist The BIST value.
729 */
730DECLINLINE(void) PCIDevSetBIST(PPCIDEVICE pPciDev, uint8_t u8Bist)
731{
732 PCIDevSetByte(pPciDev, VBOX_PCI_BIST, u8Bist);
733}
734
735/**
736 * Gets the BIST (built-in self-test)config register.
737 *
738 * @param pPciDev The PCI device.
739 * @returns u8Bist The BIST.
740 */
741DECLINLINE(uint8_t) PCIDevGetBIST(PPCIDEVICE pPciDev)
742{
743 return PCIDevGetByte(pPciDev, VBOX_PCI_BIST);
744}
745
746
747/**
748 * Sets a base address config register.
749 *
750 * @param pPciDev The PCI device.
751 * @param fIOSpace Whether it's I/O (true) or memory (false) space.
752 * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
753 * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
754 * @param u32Addr The address value.
755 */
756DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit, uint32_t u32Addr)
757{
758 if (fIOSpace)
759 {
760 Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
761 u32Addr |= RT_BIT_32(0);
762 }
763 else
764 {
765 Assert(!(u32Addr & 0xf));
766 if (fPrefetchable)
767 u32Addr |= RT_BIT_32(3);
768 if (f64Bit)
769 u32Addr |= 0x2 << 1;
770 }
771 switch (iReg)
772 {
773 case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
774 case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
775 case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
776 case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
777 case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
778 case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
779 default: AssertFailedReturnVoid();
780 }
781
782 PCIDevSetDWord(pPciDev, iReg, u32Addr);
783}
784
785
786/**
787 * Sets the sub-system vendor id config register.
788 *
789 * @param pPciDev The PCI device.
790 * @param u16SubSysVendorId The sub-system vendor id.
791 */
792DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
793{
794 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, u16SubSysVendorId);
795}
796
797/**
798 * Gets the sub-system vendor id config register.
799 * @returns the sub-system vendor id.
800 * @param pPciDev The PCI device.
801 */
802DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
803{
804 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID);
805}
806
807
808/**
809 * Sets the sub-system id config register.
810 *
811 * @param pPciDev The PCI device.
812 * @param u16SubSystemId The sub-system id.
813 */
814DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
815{
816 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID, u16SubSystemId);
817}
818
819/**
820 * Gets the sub-system id config register.
821 * @returns the sub-system id.
822 * @param pPciDev The PCI device.
823 */
824DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
825{
826 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID);
827}
828
829/**
830 * Sets offset to capability list.
831 *
832 * @param pPciDev The PCI device.
833 * @param u8Offset The offset to capability list.
834 */
835DECLINLINE(void) PCIDevSetCapabilityList(PPCIDEVICE pPciDev, uint8_t u8Offset)
836{
837 PCIDevSetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST, u8Offset);
838}
839
840/**
841 * Returns offset to capability list.
842 *
843 * @returns offset to capability list.
844 * @param pPciDev The PCI device.
845 */
846DECLINLINE(uint8_t) PCIDevGetCapabilityList(PPCIDEVICE pPciDev)
847{
848 return PCIDevGetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST);
849}
850
851/**
852 * Sets the interrupt line config register.
853 *
854 * @param pPciDev The PCI device.
855 * @param u8Line The interrupt line.
856 */
857DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
858{
859 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, u8Line);
860}
861
862/**
863 * Gets the interrupt line config register.
864 *
865 * @returns The interrupt line.
866 * @param pPciDev The PCI device.
867 */
868DECLINLINE(uint8_t) PCIDevGetInterruptLine(PPCIDEVICE pPciDev)
869{
870 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE);
871}
872
873/**
874 * Sets the interrupt pin config register.
875 *
876 * @param pPciDev The PCI device.
877 * @param u8Pin The interrupt pin.
878 */
879DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
880{
881 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN, u8Pin);
882}
883
884/**
885 * Gets the interrupt pin config register.
886 *
887 * @returns The interrupt pin.
888 * @param pPciDev The PCI device.
889 */
890DECLINLINE(uint8_t) PCIDevGetInterruptPin(PPCIDEVICE pPciDev)
891{
892 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
893}
894
895#ifdef PCIDEVICEINT_DECLARED
896DECLINLINE(void) PCISetRequestedDevfunc(PPCIDEVICE pDev)
897{
898 pDev->Int.s.uFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC;
899}
900
901DECLINLINE(void) PCIClearRequestedDevfunc(PPCIDEVICE pDev)
902{
903 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC;
904}
905
906DECLINLINE(bool) PCIIsRequestedDevfunc(PPCIDEVICE pDev)
907{
908 return (pDev->Int.s.uFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0;
909}
910
911DECLINLINE(void) PCISetPci2PciBridge(PPCIDEVICE pDev)
912{
913 pDev->Int.s.uFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE;
914}
915
916DECLINLINE(bool) PCIIsPci2PciBridge(PPCIDEVICE pDev)
917{
918 return (pDev->Int.s.uFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0;
919}
920
921DECLINLINE(void) PCISetPciExpress(PPCIDEVICE pDev)
922{
923 pDev->Int.s.uFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE;
924}
925
926DECLINLINE(bool) PCIIsPciExpress(PPCIDEVICE pDev)
927{
928 return (pDev->Int.s.uFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0;
929}
930
931DECLINLINE(void) PCISetMsiCapable(PPCIDEVICE pDev)
932{
933 pDev->Int.s.uFlags |= PCIDEV_FLAG_MSI_CAPABLE;
934}
935
936DECLINLINE(void) PCIClearMsiCapable(PPCIDEVICE pDev)
937{
938 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_MSI_CAPABLE;
939}
940
941DECLINLINE(bool) PCIIsMsiCapable(PPCIDEVICE pDev)
942{
943 return (pDev->Int.s.uFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0;
944}
945
946DECLINLINE(void) PCISetMsixCapable(PPCIDEVICE pDev)
947{
948 pDev->Int.s.uFlags |= PCIDEV_FLAG_MSIX_CAPABLE;
949}
950
951DECLINLINE(void) PCIClearMsixCapable(PPCIDEVICE pDev)
952{
953 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_MSIX_CAPABLE;
954}
955
956DECLINLINE(bool) PCIIsMsixCapable(PPCIDEVICE pDev)
957{
958 return (pDev->Int.s.uFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0;
959}
960#endif
961
962/** @} */
963
964#endif
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