VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 106165

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1/** @file
2 * PCI - The PCI Controller And Devices Constants. (DEV)
3 */
4
5/*
6 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_pci_h
37#define VBOX_INCLUDED_pci_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <VBox/cdefs.h>
43#include <VBox/types.h>
44#include <iprt/assert.h>
45
46/** @defgroup grp_pci PCI - The PCI Controller.
47 * @ingroup grp_devdrv
48 * @{
49 */
50
51/** @name PCI device classes.
52 * @{ */
53#define VBOX_PCI_CLASS_UNCLASSIFIED 0x00
54#define VBOX_PCI_CLASS_MASS_STORAGE 0x01
55#define VBOX_PCI_CLASS_NETWORK 0x02
56#define VBOX_PCI_CLASS_DISPLAY 0x03
57#define VBOX_PCI_CLASS_MULTI_MEDIA 0x04
58#define VBOX_PCI_CLASS_MEMORY 0x05
59#define VBOX_PCI_CLASS_BRIDGE 0x06
60#define VBOX_PCI_CLASS_COMM 0x07
61#define VBOX_PCI_CLASS_SYSTEM 0x08
62#define VBOX_PCI_CLASS_INPUT 0x09
63#define VBOX_PCI_CLASS_DOCKING_STATION 0x0a
64#define VBOX_PCI_CLASS_PROCESSOR 0x0b
65#define VBOX_PCI_CLASS_SERIAL_BUS 0x0c
66#define VBOX_PCI_CLASS_WIRELESS 0x0d
67#define VBOX_PCI_CLASS_INTELLIGENT 0x0e
68#define VBOX_PCI_CLASS_SAT_COMM 0x0f
69#define VBOX_PCI_CLASS_ENCRYPTION 0x10
70#define VBOX_PCI_CLASS_SIG_PROC 0x11
71#define VBOX_PCI_CLASS_PROC_ACCEL 0x12
72#define VBOX_PCI_CLASS_NON_ESS_INSTR 0x13
73#define VBOX_PCI_CLASS_CO_PROCESSOR 0x40
74#define VBOX_PCI_CLASS_UNASSIGNED 0xff
75/** @} */
76
77/** @name PCI device sub-classes.
78 * @{ */
79#define VBOX_PCI_SUB_UNCLASSIFIED_NON_VGA 0x00
80#define VBOX_PCI_SUB_UNCLASSIFIED_VGA 0x01
81
82#define VBOX_PCI_SUB_MASS_STORAGE_SCSI_BUS 0x00
83#define VBOX_PCI_SUB_MASS_STORAGE_IDE 0x01
84#define VBOX_PCI_SUB_MASS_STORAGE_FLOPPY 0x02
85#define VBOX_PCI_SUB_MASS_STORAGE_IPI_BUS 0x03
86#define VBOX_PCI_SUB_MASS_STORAGE_RAID 0x04
87#define VBOX_PCI_SUB_MASS_STORAGE_ATA 0x05
88#define VBOX_PCI_SUB_MASS_STORAGE_SATA 0x06
89#define VBOX_PCI_SUB_MASS_STORAGE_SCSI 0x07
90#define VBOX_PCI_SUB_MASS_STORAGE_NVME 0x08
91#define VBOX_PCI_SUB_MASS_STORAGE_OTHER 0x80
92
93#define VBOX_PCI_SUB_NETWORK_ETHERNET 0x00
94#define VBOX_PCI_SUB_NETWORK_TOKEN_RING 0x01
95#define VBOX_PCI_SUB_NETWORK_FDDI 0x02
96#define VBOX_PCI_SUB_NETWORK_ATM 0x03
97#define VBOX_PCI_SUB_NETWORK_ISDN 0x04
98#define VBOX_PCI_SUB_NETWORK_WORLD_FIP 0x05
99#define VBOX_PCI_SUB_NETWORK_PICMG 0x06
100#define VBOX_PCI_SUB_NETWORK_INFINIBAND 0x07
101#define VBOX_PCI_SUB_NETWORK_FABRIC 0x08
102#define VBOX_PCI_SUB_NETWORK_OTHER 0x80
103
104#define VBOX_PCI_SUB_DISPLAY_VGA 0x00
105#define VBOX_PCI_SUB_DISPLAY_XGA 0x01
106#define VBOX_PCI_SUB_DISPLAY_3D 0x02
107#define VBOX_PCI_SUB_DISPLAY_OTHER 0x80
108
109#define VBOX_PCI_SUB_MULTI_MEDIA_MM_VIDEO 0x00
110#define VBOX_PCI_SUB_MULTI_MEDIA_MM_AUDIO 0x01
111#define VBOX_PCI_SUB_MULTI_MEDIA_TELE 0x02
112#define VBOX_PCI_SUB_MULTI_MEDIA_AUDIO 0x03
113#define VBOX_PCI_SUB_MULTI_MEDIA_OTHER 0x80
114
115#define VBOX_PCI_SUB_MEMORY_RAM 0x00
116#define VBOX_PCI_SUB_MEMORY_FLASH 0x01
117#define VBOX_PCI_SUB_MEMORY_OTHER 0x80
118
119#define VBOX_PCI_SUB_BRIDGE_HOST 0x00
120#define VBOX_PCI_SUB_BRIDGE_ISA 0x01
121#define VBOX_PCI_SUB_BRIDGE_EISA 0x02
122#define VBOX_PCI_SUB_BRIDGE_MCA 0x03
123#define VBOX_PCI_SUB_BRIDGE_PCI 0x04
124#define VBOX_PCI_SUB_BRIDGE_PCMCIA 0x05
125#define VBOX_PCI_SUB_BRIDGE_NUBUS 0x06
126#define VBOX_PCI_SUB_BRIDGE_CARDBUS 0x07
127#define VBOX_PCI_SUB_BRIDGE_RACEWAY 0x08
128#define VBOX_PCI_SUB_BRIDGE_SEMI_PCI 0x09
129#define VBOX_PCI_SUB_BRIDGE_INFINIBAND_PCI 0x0a
130#define VBOX_PCI_SUB_BRIDGE_OTHER 0x80
131
132#define VBOX_PCI_SUB_COMM_SERIAL 0x00
133#define VBOX_PCI_SUB_COMM_PARALLEL 0x01
134#define VBOX_PCI_SUB_COMM_MULTIPORT_SERIAL 0x02
135#define VBOX_PCI_SUB_COMM_MODEM 0x03
136#define VBOX_PCI_SUB_COMM_GBIP 0x04
137#define VBOX_PCI_SUB_COMM_SMART_CARD 0x05
138#define VBOX_PCI_SUB_COMM_OTHER 0x80
139
140#define VBOX_PCI_SUB_SYSTEM_PIC 0x00
141#define VBOX_PCI_SUB_SYSTEM_DMA 0x01
142#define VBOX_PCI_SUB_SYSTEM_TIMER 0x02
143#define VBOX_PCI_SUB_SYSTEM_RTC 0x03
144#define VBOX_PCI_SUB_SYSTEM_PCI_HOTPLUG 0x04
145#define VBOX_PCI_SUB_SYSTEM_SD_HOST 0x05
146#define VBOX_PCI_SUB_SYSTEM_IOMMU 0x06
147#define VBOX_PCI_SUB_SYSTEM_OTHER 0x80
148
149#define VBOX_PCI_SUB_INPUT_KEYBOARD 0x00
150#define VBOX_PCI_SUB_INPUT_PEN 0x01
151#define VBOX_PCI_SUB_INPUT_MOUSE 0x02
152#define VBOX_PCI_SUB_INPUT_SCANNER 0x03
153#define VBOX_PCI_SUB_INPUT_GAMEPORT 0x04
154#define VBOX_PCI_SUB_INPUT_OTHER 0x80
155
156#define VBOX_PCI_SUB_DOCKING_ST_GENERIC 0x00
157#define VBOX_PCI_SUB_DOCKING_ST_OTHER 0x80
158
159#define VBOX_PCI_SUB_PROCESSOR_386 0x00
160#define VBOX_PCI_SUB_PROCESSOR_486 0x01
161#define VBOX_PCI_SUB_PROCESSOR_PENTIUM 0x02
162#define VBOX_PCI_SUB_PROCESSOR_PENTIUM_PRO 0x03
163#define VBOX_PCI_SUB_PROCESSOR_ALPHA 0x10
164#define VBOX_PCI_SUB_PROCESSOR_POWERPC 0x20
165#define VBOX_PCI_SUB_PROCESSOR_MIPS 0x30
166#define VBOX_PCI_SUB_PROCESSOR_CO_PROC 0x40
167#define VBOX_PCI_SUB_PROCESSOR_OTHER 0x80
168
169#define VBOX_PCI_SUB_SERIAL_BUS_FIREWIRE 0x00
170#define VBOX_PCI_SUB_SERIAL_BUS_ACCESS 0x01
171#define VBOX_PCI_SUB_SERIAL_BUS_SSA 0x02
172#define VBOX_PCI_SUB_SERIAL_BUS_USB 0x03
173#define VBOX_PCI_SUB_SERIAL_BUS_FIBRE 0x04
174#define VBOX_PCI_SUB_SERIAL_BUS_SMBUS 0x05
175#define VBOX_PCI_SUB_SERIAL_BUS_INFINIBAND 0x06
176#define VBOX_PCI_SUB_SERIAL_BUS_IPMI 0x07
177#define VBOX_PCI_SUB_SERIAL_BUS_SERCOS 0x08
178#define VBOX_PCI_SUB_SERIAL_BUS_CANBUS 0x09
179#define VBOX_PCI_SUB_SERIAL_BUS_OTHER 0x80
180
181#define VBOX_PCI_SUB_WIRELESS_IRDA 0x00
182#define VBOX_PCI_SUB_WIRELESS_IR 0x01
183#define VBOX_PCI_SUB_WIRELESS_RF 0x10
184#define VBOX_PCI_SUB_WIRELESS_BLUETOOTH 0x11
185#define VBOX_PCI_SUB_WIRELESS_BROADBAND 0x12
186#define VBOX_PCI_SUB_WIRELESS_ETH_8021A 0x20
187#define VBOX_PCI_SUB_WIRELESS_ETH_8021B 0x21
188#define VBOX_PCI_SUB_WIRELESS_OTHER 0x80
189
190#define VBOX_PCI_SUB_INTELLIGENT_I20 0x00
191
192#define VBOX_PCI_SUB_SAT_COMM_TV 0x01
193#define VBOX_PCI_SUB_SAT_COMM_AUDIO 0x02
194#define VBOX_PCI_SUB_SAT_COMM_VOICE 0x03
195#define VBOX_PCI_SUB_SAT_COMM_DATA 0x04
196
197#define VBOX_PCI_SUB_ENCRYPT_NETWORK 0x00
198#define VBOX_PCI_SUB_ENCRYPT_ENTERTAINMENT 0x01
199#define VBOX_PCI_SUB_ENCRYPT_OTHER 0x80
200
201#define VBOX_PCI_SUB_SIG_PROC_DPIO 0x00
202#define VBOX_PCI_SUB_SIG_PROC_PERF_COUNTERS 0x01
203#define VBOX_PCI_SUB_SIG_PROC_COMM_SYNC 0x10
204#define VBOX_PCI_SUB_SIG_PROC_MANAGEMENT 0x20
205#define VBOX_PCI_SUB_SIG_PROC_OTHER 0x80
206/** @} */
207
208/**
209 * PCI configuration word 4 (command) and word 6 (status).
210 */
211typedef enum PCICONFIGCOMMAND
212{
213 /** Supports/uses memory accesses. */
214 PCI_COMMAND_IOACCESS = 0x0001,
215 PCI_COMMAND_MEMACCESS = 0x0002,
216 PCI_COMMAND_BUSMASTER = 0x0004
217} PCICONFIGCOMMAND;
218
219
220/**
221 * PCI Address space specification.
222 * This is used when registering a I/O region.
223 */
224/**
225 * Defined by the PCI specification.
226 */
227typedef enum PCIADDRESSSPACE
228{
229 /** Memory. */
230 PCI_ADDRESS_SPACE_MEM = 0x00,
231 /** I/O space. */
232 PCI_ADDRESS_SPACE_IO = 0x01,
233 /** 32-bit BAR. */
234 PCI_ADDRESS_SPACE_BAR32 = 0x00,
235 /** 64-bit BAR. */
236 PCI_ADDRESS_SPACE_BAR64 = 0x04,
237 /** Prefetch memory. */
238 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
239} PCIADDRESSSPACE;
240
241
242/**
243 * PCI Memory Request with Address Type.
244 * In accordance with the PCI ATS spec.
245 * See PCI ATS spec. 2.1."Memory Requests with Address Type".
246 */
247typedef enum PCIADDRTYPE
248{
249 /** Untranslated request. */
250 PCIADDRTYPE_UNTRANSLATED = 0x0,
251 /** Translation request. */
252 PCIADDRTYPE_TRANSLATION,
253 /** Translated requested. */
254 PCIADDRTYPE_TRANSLATED,
255 /** Reserved. */
256 PCIADDRTYPE_RSVD
257} PCIADDRTYPE;
258
259
260/** @name PCI Configuration Space Registers
261 * @{ */
262/* Commented out values common for different header types */
263/* Common part of the header */
264#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
265#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
266#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
267#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
268#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
269#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
270#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
271#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
272#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
273#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
274#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
275#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
276#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
277#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
278#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
279#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
280
281/* Type 0 header, device */
282#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
283#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
284#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
285#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
286#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
287#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
288#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
289#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
290#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
291#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
292/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
293#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
294#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
295#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
296#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
297/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
298/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
299#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
300#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
301
302/* Type 1 header, PCI-to-PCI bridge */
303/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
304/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
305#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
306#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
307#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
308#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
309#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
310#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
311#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
312#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
313#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
314#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
315#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
316#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
317#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
318#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
319#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
320/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
321/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
322/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
323/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
324#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
325#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
326
327/* Type 2 header, PCI-to-CardBus bridge */
328#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
329#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
330#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
331#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
332#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
333#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
334/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
335/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
336#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
337#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
338#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
339#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
340#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
341#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
342#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
343#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
344/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
345/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
346/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
347/** @} */
348
349
350/* Possible values in status bitmask */
351#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
352#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
353#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
354#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
355#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
356#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
357#define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
358#define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
359#define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
360#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
361#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
362#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
363#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
364#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
365
366
367/* Command bitmask */
368#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
369#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
370#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
371#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
372#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
373#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
374#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
375#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
376#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
377#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
378#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
379
380
381/* Capability list values (capability offset 0) */
382/* Next value pointer in offset 1, or 0 if none */
383#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
384#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
385#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
386#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
387#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
388#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
389#define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
390#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
391#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
392#define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
393#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
394#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
395#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
396#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
397#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
398#define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
399#define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
400#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
401#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
402
403/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
404#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
405#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
406#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
407#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
408#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
409#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
410#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
411#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
412#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
413#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
414#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
415#define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
416#define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
417#define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
418
419
420/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
421#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
422#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
423#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
424/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
425 someone very similar to log_2().
426 000 1
427 001 2
428 010 4
429 011 8
430 100 16
431 101 32
432 110 Reserved
433 111 Reserved */
434#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
435#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
436
437/* MSI-X flags (2 bytes, capability offset 2) */
438#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
439#define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
440
441/* Power management flags (2 bytes, capability offset 2) */
442#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
443#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
444#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
445#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
446#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
447#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
448#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
449#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
450#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
451#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
452#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
453#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
454#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
455#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
456
457/* Power management control flags (2 bytes, capability offset 4) */
458#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
459#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
460#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
461#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
462#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
463#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
464
465/* PCI-X config flags (2 bytes, capability offset 2) */
466#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
467#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
468#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
469#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
470#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
471#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
472#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
473#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
474
475/* PCI-X config flags (4 bytes, capability offset 4) */
476#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
477#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
478#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
479#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
480#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
481#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
482#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
483#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
484#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
485#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
486#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
487#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
488#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
489
490/* PCI Express config flags (2 bytes, capability offset 2) */
491#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
492#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
493#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
494#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
495#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
496#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
497#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
498#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
499#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
500#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
501#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
502#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
503#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
504
505/* PCI Express device capabilities (4 bytes, capability offset 4) */
506#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
507#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
508#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
509#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
510#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
511#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
512#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
513#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
514#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
515#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
516#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
517#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
518
519/* PCI Express device control (2 bytes, capability offset 8) */
520#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
521#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
522#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
523#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
524#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
525#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
526#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
527#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
528#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
529#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
530#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
531#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
532#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
533
534/* PCI Express device status (2 bytes, capability offset 10) */
535#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
536#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
537#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
538#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
539#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
540#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
541
542/* PCI Express link capabilities (4 bytes, capability offset 12) */
543#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
544#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
545#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
546#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
547#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
548#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
549#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
550#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
551#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
552#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
553
554/* PCI Express link control (2 bytes, capability offset 16) */
555#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
556#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
557#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
558#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
559#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
560#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
561#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
562#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
563#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
564#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
565
566/* PCI Express link status (2 bytes, capability offset 18) */
567#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
568#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
569#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
570#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
571#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
572#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
573#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
574#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
575
576/* PCI Express slot capabilities (4 bytes, capability offset 20) */
577#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
578#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
579#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
580#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
581#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
582#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
583#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
584#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
585#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
586#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
587#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
588#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
589
590/* PCI Express slot control (2 bytes, capability offset 24) */
591#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
592#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
593#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
594#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
595#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
596#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
597#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
598#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
599#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
600#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
601#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
602
603/* PCI Express slot status (2 bytes, capability offset 26) */
604#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
605#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
606#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
607#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
608#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
609#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
610#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
611#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
612#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
613
614/* PCI Express root control (2 bytes, capability offset 28) */
615#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
616#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
617#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
618#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
619#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
620
621/* PCI Express root capabilities (2 bytes, capability offset 30) */
622#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
623
624/* PCI Express root status (4 bytes, capability offset 32) */
625#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
626#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
627#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
628
629
630/** Fixed I/O region number for ROM. */
631#define VBOX_PCI_ROM_SLOT 6
632/** Max number of I/O regions. */
633#define VBOX_PCI_NUM_REGIONS 7
634
635#define PCI_ROM_SLOT VBOX_PCI_ROM_SLOT /**< deprecated */
636#define PCI_NUM_REGIONS VBOX_PCI_NUM_REGIONS /**< deprecated */
637
638/** Number of functions per device. */
639#define VBOX_PCI_MAX_FUNCTIONS 8
640/** Number of devices per bus. */
641#define VBOX_PCI_MAX_DEVICES 32
642/** The function number mask for a device+function number. */
643#define VBOX_PCI_DEVFN_FUN_MASK 0x7
644/** The device number shift count for a device+function number. */
645#define VBOX_PCI_DEVFN_DEV_SHIFT 3
646/** The device number mask for a device+function number. */
647#define VBOX_PCI_DEVFN_DEV_MASK 0x1f
648/** The bus number shift count for a bus+device+function number. */
649#define VBOX_PCI_BUS_SHIFT 0x8
650/** The bus number mask a bus+device+function number. */
651#define VBOX_PCI_BUS_MASK 0xff
652/** Make a device+function number. */
653#define VBOX_PCI_DEVFN_MAKE(a_uPciDevNo, a_uPciFunNo) ( ((a_uPciDevNo) << VBOX_PCI_DEVFN_DEV_SHIFT) \
654 | ((a_uPciFunNo) & VBOX_PCI_DEVFN_FUN_MASK))
655
656/** Checks whether the PCIBDF is valid. */
657#define PCIBDF_IS_VALID(a_uBusDevFn) (!((a_uBusDevFn) & PCI_BDF_F_INVALID))
658/** Make a PCIBDF given the bus and device:function. */
659#define PCIBDF_MAKE(a_uBus, a_uDevFn) (((a_uBus) << VBOX_PCI_BUS_SHIFT) | (a_uDevFn))
660
661/** Southbridge I/O APIC (when IOMMU is enabled): Bus. */
662#define VBOX_PCI_BUS_SB_IOAPIC 0
663/** Southbridge I/O APIC (when IOMMU is enabled): Device. */
664#define VBOX_PCI_DEV_SB_IOAPIC 0x14
665/** Southbridge I/O APIC (when IOMMU is enabled): Function. */
666#define VBOX_PCI_FN_SB_IOAPIC 0
667/** PCI BDF (hardcoded by linux guests) reserved for the SB I/O APIC when using VMs
668 * with an AMD IOMMU. */
669#define VBOX_PCI_BDF_SB_IOAPIC PCIBDF_MAKE(VBOX_PCI_BUS_SB_IOAPIC, \
670 VBOX_PCI_DEVFN_MAKE(VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC))
671
672/**
673 * A PCI PASID (Process Address Space ID).
674 *
675 * A PASID is 20 bits wide. We use bit 31 to indicate the PASID is invalid or not
676 * present.
677 */
678typedef uint32_t PCIPASID;
679/** PCIPASID: Valid. */
680#define PCIPASID_F_VALID RT_BIT(31)
681/** Nil PCIPASID value. */
682#define NIL_PCIPASID UINT32_C(0)
683/** Returns whether the PCI PASID is valid. */
684#define PCIPASID_IS_VALID(a) (((a) & PCIPASID_F_VALID) != 0)
685/** Returns the PASID value of a PCI PASID. */
686#define PCIPASID_VAL(a) ((a) & UINT32_C(0xfffff))
687
688
689#if defined(__cplusplus) && defined(IN_RING3)
690/* For RTStrPrintf(). */
691# include <iprt/string.h>
692
693/**
694 * Class representing PCI address. PCI device consist of
695 * bus, device and function numbers. Generally device PCI
696 * address could be changed during runtime, but only by
697 * an OS PCI driver.
698 *
699 * @remarks C++ classes (structs included) are not generally accepted in
700 * VMM devices or drivers. An exception may be granted for this class
701 * if it's contained to ring-3 and that this is a one time exception
702 * which sets no precedent.
703 */
704struct PCIBusAddress
705{
706 /** @todo: think if we'll need domain, which is higher
707 * word of the address. */
708 int miBus;
709 int miDevice;
710 int miFn;
711
712 PCIBusAddress()
713 {
714 clear();
715 }
716
717 PCIBusAddress(int iBus, int iDevice, int iFn)
718 {
719 init(iBus, iDevice, iFn);
720 }
721
722 PCIBusAddress(int32_t iAddr)
723 {
724 clear();
725 fromLong(iAddr);
726 }
727
728 PCIBusAddress& clear()
729 {
730 miBus = miDevice = miFn = -1;
731 return *this;
732 }
733
734 void init(int iBus, int iDevice, int iFn)
735 {
736 miBus = iBus;
737 miDevice = iDevice;
738 miFn = iFn;
739 }
740
741 void init(const PCIBusAddress &a)
742 {
743 miBus = a.miBus;
744 miDevice = a.miDevice;
745 miFn = a.miFn;
746 }
747
748 bool operator<(const PCIBusAddress &a) const
749 {
750 if (miBus < a.miBus)
751 return true;
752
753 if (miBus > a.miBus)
754 return false;
755
756 if (miDevice < a.miDevice)
757 return true;
758
759 if (miDevice > a.miDevice)
760 return false;
761
762 if (miFn < a.miFn)
763 return true;
764
765 if (miFn > a.miFn)
766 return false;
767
768 return false;
769 }
770
771 bool operator==(const PCIBusAddress &a) const
772 {
773 return (miBus == a.miBus)
774 && (miDevice == a.miDevice)
775 && (miFn == a.miFn);
776 }
777
778 bool operator!=(const PCIBusAddress &a) const
779 {
780 return (miBus != a.miBus)
781 || (miDevice != a.miDevice)
782 || (miFn != a.miFn);
783 }
784
785 bool valid() const
786 {
787 return (miBus != -1)
788 && (miDevice != -1)
789 && (miFn != -1);
790 }
791
792 int32_t asLong() const
793 {
794 Assert(valid());
795 return (miBus << 8) | (miDevice << 3) | miFn;
796 }
797
798 PCIBusAddress& fromLong(int32_t value)
799 {
800 miBus = (value >> 8) & 0xff;
801 miDevice = (value & 0xff) >> 3;
802 miFn = (value & 7);
803 return *this;
804 }
805
806 /** Create string representation of this PCI address. */
807 bool format(char* szBuf, size_t cBufSize)
808 {
809 if (cBufSize < (/* bus */ 2 + /* : */ 1 + /* device */ 2 + /* . */ 1 + /* function*/ 1 + /* \0 */1))
810 return false;
811
812 if (valid())
813 RTStrPrintf(szBuf, cBufSize, "%02x:%02x.%01x", miBus, miDevice, miFn);
814 else
815 RTStrPrintf(szBuf, cBufSize, "%s", "<bad>");
816
817 return true;
818 }
819
820 static const size_t cMaxAddrSize = 10;
821};
822
823#endif /* __cplusplus && IN_RING3 */
824
825/** @} */
826
827#endif /* !VBOX_INCLUDED_pci_h */
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