VirtualBox

source: vbox/trunk/include/VBox/iommu-intel.h@ 89363

Last change on this file since 89363 was 89312, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Address translation, WIP.
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File size: 132.7 KB
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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (Intel).
3 */
4
5/*
6 * Copyright (C) 2021 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_iommu_intel_h
27#define VBOX_INCLUDED_iommu_intel_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/assertcompile.h>
33#include <iprt/types.h>
34
35
36/**
37 * @name MMIO register offsets.
38 * In accordance with the Intel spec.
39 * @{
40 */
41#define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */
42#define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
43#define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
44#define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
45#define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
46#define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
47#define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
48
49#define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
50#define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
51#define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
52#define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
53#define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
54
55#define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
56
57#define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
58#define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
59#define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
60#define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
61#define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
62
63#define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
64#define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
65#define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
66#define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
67#define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
68#define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
69#define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
70#define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
71#define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
72
73#define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
74
75#define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
76#define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
77#define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
78#define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
79#define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
80#define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
81#define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
82#define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
83
84#define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
85#define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
86
87#define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
88#define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
89#define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
90#define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
91#define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
92#define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
93#define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
94#define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
95#define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
96#define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
97#define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
98
99#define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
100#define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
101#define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
102#define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
103#define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
104#define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
105#define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
106#define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
107#define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
108#define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
109#define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
110#define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
111#define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
112#define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
113#define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
114#define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
115#define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
116#define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
117#define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
118#define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
119
120#define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */
121#define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
122#define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /**< Reserved for future for Virtual Command. */
123#define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
124#define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /**< Reserved for future for Virtual Command Response. */
125/** @} */
126
127
128/** @name Root Entry.
129 * In accordance with the Intel spec.
130 * @{ */
131/** P: Present. */
132#define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
133#define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
134/** R: Reserved (bits 11:1). */
135#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
136#define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
137/** CTP: Context-Table Pointer. */
138#define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
139#define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
140RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
141 (P, RSVD_11_1, CTP));
142
143/** Root Entry. */
144typedef struct VTD_ROOT_ENTRY_T
145{
146 /** The qwords in the root entry. */
147 uint64_t au64[2];
148} VTD_ROOT_ENTRY_T;
149/** Pointer to a root entry. */
150typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
151/** Pointer to a const root entry. */
152typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
153
154/* Root Entry: Qword 0 valid mask. */
155#define VTD_ROOT_ENTRY_0_VALID_MASK (VTD_BF_0_ROOT_ENTRY_P_MASK | VTD_BF_0_ROOT_ENTRY_CTP_MASK)
156/* Root Entry: Qword 1 valid mask. */
157#define VTD_ROOT_ENTRY_1_VALID_MASK UINT64_C(0)
158/** @} */
159
160
161/** @name Scalable-mode Root Entry.
162 * In accordance with the Intel spec.
163 * @{ */
164/** LP: Lower Present. */
165#define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
166#define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
167/** R: Reserved (bits 11:1). */
168#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
169#define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
170/** LCTP: Lower Context-Table Pointer */
171#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
172#define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
173RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
174 (LP, RSVD_11_1, LCTP));
175
176/** UP: Upper Present. */
177#define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
178#define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
179/** R: Reserved (bits 11:1). */
180#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
181#define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
182/** UCTP: Upper Context-Table Pointer. */
183#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
184#define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
185RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
186 (UP, RSVD_11_1, UCTP));
187
188/** Scalable-mode root entry. */
189typedef struct VTD_SM_ROOT_ENTRY_T
190{
191 /** The lower scalable-mode root entry. */
192 uint64_t uLower;
193 /** The upper scalable-mode root entry. */
194 uint64_t uUpper;
195} VTD_SM_ROOT_ENTRY_T;
196/** Pointer to a scalable-mode root entry. */
197typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
198/** Pointer to a const scalable-mode root entry. */
199typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
200/** @} */
201
202
203/** @name Context Entry.
204 * In accordance with the Intel spec.
205 * @{ */
206/** P: Present. */
207#define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
208#define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
209/** FPD: Fault Processing Disable. */
210#define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
211#define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
212/** TT: Translation Type. */
213#define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
214#define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
215/** R: Reserved (bits 11:4). */
216#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
217#define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
218/** SLPTPTR: Second Level Page Translation Pointer. */
219#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
220#define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
221RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
222 (P, FPD, TT, RSVD_11_4, SLPTPTR));
223
224/** AW: Address Width. */
225#define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
226#define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
227/** IGN: Ignored (bits 6:3). */
228#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
229#define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
230/** R: Reserved (bit 7). */
231#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
232#define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
233/** DID: Domain Identifier. */
234#define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
235#define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
236/** R: Reserved (bits 63:24). */
237#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
238#define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
239RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
240 (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
241
242/** Context Entry. */
243typedef struct VTD_CONTEXT_ENTRY_T
244{
245 /** The qwords in the context entry. */
246 uint64_t au64[2];
247} VTD_CONTEXT_ENTRY_T;
248/** Pointer to a context entry. */
249typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
250/** Pointer to a const context entry. */
251typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
252
253/* Context Entry: Qword 0 valid mask. */
254#define VTD_CONTEXT_ENTRY_0_VALID_MASK ( VTD_BF_0_CONTEXT_ENTRY_P_MASK \
255 | VTD_BF_0_CONTEXT_ENTRY_FPD_MASK \
256 | VTD_BF_0_CONTEXT_ENTRY_TT_MASK \
257 | VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK)
258/* Context Entry: Qword 1 valid mask. */
259#define VTD_CONTEXT_ENTRY_1_VALID_MASK ( VTD_BF_1_CONTEXT_ENTRY_AW_MASK \
260 | VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK \
261 | VTD_BF_1_CONTEXT_ENTRY_DID_MASK)
262/** @} */
263
264
265/** @name Scalable-mode Context Entry.
266 * In accordance with the Intel spec.
267 * @{ */
268/** P: Present. */
269#define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
270#define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
271/** FPD: Fault Processing Disable. */
272#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
273#define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
274/** DTE: Device-TLB Enable. */
275#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
276#define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
277/** PASIDE: PASID Enable. */
278#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
279#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
280/** PRE: Page Request Enable. */
281#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
282#define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
283/** R: Reserved (bits 8:5). */
284#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
285#define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
286/** PDTS: PASID Directory Size. */
287#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
288#define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
289/** PASIDDIRPTR: PASID Directory Pointer. */
290#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
291#define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
292RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
293 (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
294
295/** RID_PASID: Requested Id to PASID assignment. */
296#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
297#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
298/** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
299#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
300#define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
301/** R: Reserved (bits 63:21). */
302#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
303#define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
304RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
305 (RID_PASID, RID_PRIV, RSVD_63_21));
306
307/** Scalable-mode Context Entry. */
308typedef struct VTD_SM_CONTEXT_ENTRY_T
309{
310 /** The qwords in the scalable-mode context entry. */
311 uint64_t au64[4];
312} VTD_SM_CONTEXT_ENTRY_T;
313/** Pointer to a scalable-mode context entry. */
314typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
315/** Pointer to a const scalable-mode context entry. */
316typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
317/** @} */
318
319
320/** @name Scalable-mode PASID Directory Entry.
321 * In accordance with the Intel spec.
322 * @{ */
323/** P: Present. */
324#define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
325#define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
326/** FPD: Fault Processing Disable. */
327#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
328#define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
329/** R: Reserved (bits 11:2). */
330#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
331#define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
332/** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
333#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
334#define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
335RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
336 (P, FPD, RSVD_11_2, SMPTBLPTR));
337
338/** Scalable-mode PASID Directory Entry. */
339typedef struct VTD_SM_PASID_DIR_ENTRY_T
340{
341 /** The scalable-mode PASID directory entry. */
342 uint64_t u;
343} VTD_SM_PASID_DIR_ENTRY_T;
344/** Pointer to a scalable-mode PASID directory entry. */
345typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
346/** Pointer to a const scalable-mode PASID directory entry. */
347typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
348/** @} */
349
350
351/** @name Scalable-mode PASID Table Entry.
352 * In accordance with the Intel spec.
353 * @{ */
354/** P: Present. */
355#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
356#define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
357/** FPD: Fault Processing Disable. */
358#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
359#define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
360/** AW: Address Width. */
361#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
362#define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
363/** SLEE: Second-Level Execute Enable. */
364#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
365#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
366/** PGTT: PASID Granular Translation Type. */
367#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
368#define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
369/** SLADE: Second-Level Address/Dirty Enable. */
370#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
371#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
372/** R: Reserved (bits 11:10). */
373#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
374#define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
375/** SLPTPTR: Second-Level Page Table Pointer. */
376#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
377#define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
378RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
379 (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
380
381/** DID: Domain Identifer. */
382#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
383#define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
384/** R: Reserved (bits 22:16). */
385#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
386#define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
387/** PWSNP: Page-Walk Snoop. */
388#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
389#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
390/** PGSNP: Page Snoop. */
391#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
392#define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
393/** CD: Cache Disable. */
394#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
395#define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
396/** EMTE: Extended Memory Type Enable. */
397#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
398#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
399/** EMT: Extended Memory Type. */
400#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
401#define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
402/** PWT: Page-Level Write Through. */
403#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
404#define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
405/** PCD: Page-Level Cache Disable. */
406#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
407#define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
408/** PAT: Page Attribute Table. */
409#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
410#define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
411RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
412 (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
413
414/** SRE: Supervisor Request Enable. */
415#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
416#define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
417/** ERE: Execute Request Enable. */
418#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
419#define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
420/** FLPM: First Level Paging Mode. */
421#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
422#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
423/** WPE: Write Protect Enable. */
424#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
425#define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
426/** NXE: No-Execute Enable. */
427#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
428#define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
429/** SMEP: Supervisor Mode Execute Prevent. */
430#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
431#define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
432/** EAFE: Extended Accessed Flag Enable. */
433#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
434#define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
435/** R: Reserved (bits 11:8). */
436#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
437#define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
438/** FLPTPTR: First Level Page Table Pointer. */
439#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
440#define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
441RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
442 (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
443
444/** Scalable-mode PASID Table Entry. */
445typedef struct VTD_SM_PASID_TBL_ENTRY_T
446{
447 /** The qwords in the scalable-mode PASID table entry. */
448 uint64_t au64[8];
449} VTD_SM_PASID_TBL_ENTRY_T;
450/** Pointer to a scalable-mode PASID table entry. */
451typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
452/** Pointer to a const scalable-mode PASID table entry. */
453typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
454/** @} */
455
456
457/** @name First-Level Paging Entry.
458 * In accordance with the Intel spec.
459 * @{ */
460/** P: Present. */
461#define VTD_BF_FLP_ENTRY_P_SHIFT 0
462#define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
463/** R/W: Read/Write. */
464#define VTD_BF_FLP_ENTRY_RW_SHIFT 1
465#define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
466/** U/S: User/Supervisor. */
467#define VTD_BF_FLP_ENTRY_US_SHIFT 2
468#define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
469/** PWT: Page-Level Write Through. */
470#define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
471#define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
472/** PC: Page-Level Cache Disable. */
473#define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
474#define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
475/** A: Accessed. */
476#define VTD_BF_FLP_ENTRY_A_SHIFT 5
477#define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
478/** IGN: Ignored (bit 6). */
479#define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
480#define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
481/** R: Reserved (bit 7). */
482#define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
483#define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
484/** IGN: Ignored (bits 9:8). */
485#define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
486#define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
487/** EA: Extended Accessed. */
488#define VTD_BF_FLP_ENTRY_EA_SHIFT 10
489#define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
490/** IGN: Ignored (bit 11). */
491#define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
492#define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
493/** ADDR: Address. */
494#define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
495#define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
496/** IGN: Ignored (bits 62:52). */
497#define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
498#define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
499/** XD: Execute Disabled. */
500#define VTD_BF_FLP_ENTRY_XD_SHIFT 63
501#define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
502RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
503 (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
504
505/** First-Level Paging Entry. */
506typedef uint64_t VTD_FLP_ENTRY_T;
507/** @} */
508
509
510/** @name Second-Level Paging Entry.
511 * In accordance with the Intel spec.
512 * @{ */
513/** R: Read. */
514#define VTD_BF_SLP_ENTRY_R_SHIFT 0
515#define VTD_BF_SLP_ENTRY_R_MASK UINT64_C(0x0000000000000001)
516/** W: Write. */
517#define VTD_BF_SLP_ENTRY_W_SHIFT 1
518#define VTD_BF_SLP_ENTRY_W_MASK UINT64_C(0x0000000000000002)
519/** X: Execute. */
520#define VTD_BF_SLP_ENTRY_X_SHIFT 2
521#define VTD_BF_SLP_ENTRY_X_MASK UINT64_C(0x0000000000000004)
522/** IGN: Ignored (bits 6:3). */
523#define VTD_BF_SLP_ENTRY_IGN_6_3_SHIFT 3
524#define VTD_BF_SLP_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
525/** R: Reserved (bit 7). */
526#define VTD_BF_SLP_ENTRY_RSVD_7_SHIFT 7
527#define VTD_BF_SLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
528/** A: Accessed. */
529#define VTD_BF_SLP_ENTRY_A_SHIFT 8
530#define VTD_BF_SLP_ENTRY_A_MASK UINT64_C(0x0000000000000100)
531/** IGN: Ignored (bits 10:9). */
532#define VTD_BF_SLP_ENTRY_IGN_10_9_SHIFT 9
533#define VTD_BF_SLP_ENTRY_IGN_10_9_MASK UINT64_C(0x0000000000000600)
534/** R: Reserved (bit 11). */
535#define VTD_BF_SLP_ENTRY_RSVD_11_SHIFT 11
536#define VTD_BF_SLP_ENTRY_RSVD_11_MASK UINT64_C(0x0000000000000800)
537/** ADDR: Address. */
538#define VTD_BF_SLP_ENTRY_ADDR_SHIFT 12
539#define VTD_BF_SLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
540/** IGN: Ignored (bits 61:52). */
541#define VTD_BF_SLP_ENTRY_IGN_61_52_SHIFT 52
542#define VTD_BF_SLP_ENTRY_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
543/** R: Reserved (bit 62). */
544#define VTD_BF_SLP_ENTRY_RSVD_62_SHIFT 62
545#define VTD_BF_SLP_ENTRY_RSVD_62_MASK UINT64_C(0x4000000000000000)
546/** IGN: Ignored (bit 63). */
547#define VTD_BF_SLP_ENTRY_IGN_63_SHIFT 63
548#define VTD_BF_SLP_ENTRY_IGN_63_MASK UINT64_C(0x8000000000000000)
549RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SLP_ENTRY_, UINT64_C(0), UINT64_MAX,
550 (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
551
552/** SL-PML5E: Valid mask. */
553#define VTD_SLP_PML5E_VALID_MASK ( VTD_BF_SLP_ENTRY_R_MASK | VTD_BF_SLP_ENTRY_W_MASK \
554 | VTD_BF_SLP_ENTRY_X_MASK | VTD_BF_SLP_ENTRY_IGN_6_3_MASK \
555 | VTD_BF_SLP_ENTRY_A_MASK | VTD_BF_SLP_ENTRY_IGN_10_9_MASK \
556 | VTD_BF_SLP_ENTRY_ADDR_MASK | VTD_BF_SLP_ENTRY_IGN_61_52_MASK \
557 | VTD_BF_SLP_ENTRY_IGN_63_MASK)
558
559/** Second-Level Paging Entry. */
560typedef uint64_t VTD_SLP_ENTRY_T;
561/** Pointer to a second-level paging entry. */
562typedef uint64_t *PVTD_SLP_ENTRY_T;
563/** Pointer to a const second-level paging entry. */
564typedef uint64_t const *CPVTD_SLP_ENTRY_T;
565/** @} */
566
567
568/** @name Fault Record.
569 * In accordance with the Intel spec.
570 * @{ */
571/** R: Reserved (bits 11:0). */
572#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
573#define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
574/** FI: Fault Information. */
575#define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
576#define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
577RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
578 (RSVD_11_0, FI));
579
580/** SID: Source identifier. */
581#define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
582#define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
583/** R: Reserved (bits 28:16). */
584#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
585#define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
586/** PRIV: Privilege Mode Requested. */
587#define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
588#define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
589/** EXE: Execute Permission Requested. */
590#define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
591#define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
592/** PP: PASID Present. */
593#define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
594#define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
595/** FR: Fault Reason. */
596#define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
597#define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
598/** PV: PASID Value. */
599#define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
600#define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
601/** AT: Address Type. */
602#define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
603#define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
604/** T: Type. */
605#define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
606#define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
607/** R: Reserved (bit 127). */
608#define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
609#define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
610RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
611 (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
612
613/** Fault record. */
614typedef struct VTD_FAULT_RECORD_T
615{
616 /** The qwords in the fault record. */
617 uint64_t au64[2];
618} VTD_FAULT_RECORD_T;
619/** Pointer to a fault record. */
620typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
621/** Pointer to a const fault record. */
622typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
623/** @} */
624
625
626/** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
627 * In accordance with the Intel spec.
628 * @{ */
629/** P: Present. */
630#define VTD_BF_0_IRTE_P_SHIFT 0
631#define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
632/** FPD: Fault Processing Disable. */
633#define VTD_BF_0_IRTE_FPD_SHIFT 1
634#define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
635/** DM: Destination Mode (0=physical, 1=logical). */
636#define VTD_BF_0_IRTE_DM_SHIFT 2
637#define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
638/** RH: Redirection Hint. */
639#define VTD_BF_0_IRTE_RH_SHIFT 3
640#define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
641/** TM: Trigger Mode. */
642#define VTD_BF_0_IRTE_TM_SHIFT 4
643#define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
644/** DLM: Delivery Mode. */
645#define VTD_BF_0_IRTE_DLM_SHIFT 5
646#define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
647/** AVL: Available. */
648#define VTD_BF_0_IRTE_AVAIL_SHIFT 8
649#define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
650/** R: Reserved (bits 14:12). */
651#define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
652#define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
653/** IM: IRTE Mode. */
654#define VTD_BF_0_IRTE_IM_SHIFT 15
655#define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
656/** V: Vector. */
657#define VTD_BF_0_IRTE_V_SHIFT 16
658#define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
659/** R: Reserved (bits 31:24). */
660#define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
661#define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
662/** DST: Desination Id. */
663#define VTD_BF_0_IRTE_DST_SHIFT 32
664#define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
665/** R: Reserved (bits 39:32) when EIME=0. */
666#define VTD_BF_0_IRTE_RSVD_39_32_SHIFT 32
667#define VTD_BF_0_IRTE_RSVD_39_32_MASK UINT64_C(0x000000ff00000000)
668/** DST_XAPIC: Destination Id when EIME=0. */
669#define VTD_BF_0_IRTE_DST_XAPIC_SHIFT 40
670#define VTD_BF_0_IRTE_DST_XAPIC_MASK UINT64_C(0x0000ff0000000000)
671/** R: Reserved (bits 63:48) when EIME=0. */
672#define VTD_BF_0_IRTE_RSVD_63_48_SHIFT 48
673#define VTD_BF_0_IRTE_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
674RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
675 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
676RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
677 (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, RSVD_39_32, DST_XAPIC, RSVD_63_48));
678
679/** SID: Source Identifier. */
680#define VTD_BF_1_IRTE_SID_SHIFT 0
681#define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
682/** SQ: Source-Id Qualifier. */
683#define VTD_BF_1_IRTE_SQ_SHIFT 16
684#define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
685/** SVT: Source Validation Type. */
686#define VTD_BF_1_IRTE_SVT_SHIFT 18
687#define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
688/** R: Reserved (bits 127:84). */
689#define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
690#define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
691RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
692 (SID, SQ, SVT, RSVD_63_20));
693
694/** IRTE: Qword 0 valid mask when EIME=1. */
695#define VTD_IRTE_0_X2APIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
696 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
697 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
698 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
699 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_MASK)
700/** IRTE: Qword 0 valid mask when EIME=0. */
701#define VTD_IRTE_0_XAPIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
702 | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
703 | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
704 | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
705 | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_XAPIC_MASK)
706/** IRTE: Qword 1 valid mask. */
707#define VTD_IRTE_1_VALID_MASK ( VTD_BF_1_IRTE_SID_MASK | VTD_BF_1_IRTE_SQ_MASK \
708 | VTD_BF_1_IRTE_SVT_MASK)
709
710/** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
711typedef struct VTD_IRTE_T
712{
713 /** The qwords in the IRTE. */
714 uint64_t au64[2];
715} VTD_IRTE_T;
716/** Pointer to an IRTE. */
717typedef VTD_IRTE_T *PVTD_IRTE_T;
718/** Pointer to a const IRTE. */
719typedef VTD_IRTE_T const *PCVTD_IRTE_T;
720
721/** IRTE SVT: No validation required. */
722#define VTD_IRTE_SVT_NONE 0
723/** IRTE SVT: Validate using a mask derived from SID and SQT. */
724#define VTD_IRTE_SVT_VALIDATE_MASK 1
725/** IRTE SVT: Validate using Bus range in the SID. */
726#define VTD_IRTE_SVT_VALIDATE_BUS_RANGE 2
727/** IRTE SVT: Reserved. */
728#define VTD_IRTE_SVT_VALIDATE_RSVD 3
729/** @} */
730
731
732/** @name Version Register (VER_REG).
733 * In accordance with the Intel spec.
734 * @{ */
735/** Min: Minor Version Number. */
736#define VTD_BF_VER_REG_MIN_SHIFT 0
737#define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
738/** Max: Major Version Number. */
739#define VTD_BF_VER_REG_MAX_SHIFT 4
740#define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
741/** R: Reserved (bits 31:8). */
742#define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
743#define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
744RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
745 (MIN, MAX, RSVD_31_8));
746/** RW: Read/write mask. */
747#define VTD_VER_REG_RW_MASK UINT32_C(0)
748/** @} */
749
750
751/** @name Capability Register (CAP_REG).
752 * In accordance with the Intel spec.
753 * @{ */
754/** ND: Number of domains supported. */
755#define VTD_BF_CAP_REG_ND_SHIFT 0
756#define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
757/** AFL: Advanced Fault Logging. */
758#define VTD_BF_CAP_REG_AFL_SHIFT 3
759#define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
760/** RWBF: Required Write-Buffer Flushing. */
761#define VTD_BF_CAP_REG_RWBF_SHIFT 4
762#define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
763/** PLMR: Protected Low-Memory Region. */
764#define VTD_BF_CAP_REG_PLMR_SHIFT 5
765#define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
766/** PHMR: Protected High-Memory Region. */
767#define VTD_BF_CAP_REG_PHMR_SHIFT 6
768#define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
769/** CM: Caching Mode. */
770#define VTD_BF_CAP_REG_CM_SHIFT 7
771#define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
772/** SAGAW: Supported Adjusted Guest Address Widths. */
773#define VTD_BF_CAP_REG_SAGAW_SHIFT 8
774#define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
775/** R: Reserved (bits 15:13). */
776#define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
777#define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
778/** MGAW: Maximum Guest Address Width. */
779#define VTD_BF_CAP_REG_MGAW_SHIFT 16
780#define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
781/** ZLR: Zero Length Read. */
782#define VTD_BF_CAP_REG_ZLR_SHIFT 22
783#define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
784/** DEP: Deprecated MBZ. Reserved (bit 23). */
785#define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
786#define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
787/** FRO: Fault-recording Register Offset. */
788#define VTD_BF_CAP_REG_FRO_SHIFT 24
789#define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
790/** SLLPS: Second Level Large Page Support. */
791#define VTD_BF_CAP_REG_SLLPS_SHIFT 34
792#define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
793/** R: Reserved (bit 38). */
794#define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
795#define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
796/** PSI: Page Selective Invalidation. */
797#define VTD_BF_CAP_REG_PSI_SHIFT 39
798#define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
799/** NFR: Number of Fault-recording Registers. */
800#define VTD_BF_CAP_REG_NFR_SHIFT 40
801#define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
802/** MAMV: Maximum Address Mask Value. */
803#define VTD_BF_CAP_REG_MAMV_SHIFT 48
804#define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
805/** DWD: Write Draining. */
806#define VTD_BF_CAP_REG_DWD_SHIFT 54
807#define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
808/** DRD: Read Draining. */
809#define VTD_BF_CAP_REG_DRD_SHIFT 55
810#define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
811/** FL1GP: First Level 1 GB Page Support. */
812#define VTD_BF_CAP_REG_FL1GP_SHIFT 56
813#define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
814/** R: Reserved (bits 58:57). */
815#define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
816#define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
817/** PI: Posted Interrupt Support. */
818#define VTD_BF_CAP_REG_PI_SHIFT 59
819#define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
820/** FL5LP: First Level 5-level Paging Support. */
821#define VTD_BF_CAP_REG_FL5LP_SHIFT 60
822#define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
823/** R: Reserved (bit 61). */
824#define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
825#define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
826/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
827#define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
828#define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
829/** : Enhanced Set Root Table Pointer Support. */
830#define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
831#define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
832RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
833 (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
834 MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
835
836/** RW: Read/write mask. */
837#define VTD_CAP_REG_RW_MASK UINT64_C(0)
838/** @} */
839
840
841/** @name Extended Capability Register (ECAP_REG).
842 * In accordance with the Intel spec.
843 * @{ */
844/** C: Page-walk Coherence. */
845#define VTD_BF_ECAP_REG_C_SHIFT 0
846#define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
847/** QI: Queued Invalidation Support. */
848#define VTD_BF_ECAP_REG_QI_SHIFT 1
849#define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
850/** DT: Device-TLB Support. */
851#define VTD_BF_ECAP_REG_DT_SHIFT 2
852#define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
853/** IR: Interrupt Remapping Support. */
854#define VTD_BF_ECAP_REG_IR_SHIFT 3
855#define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
856/** EIM: Extended Interrupt Mode. */
857#define VTD_BF_ECAP_REG_EIM_SHIFT 4
858#define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
859/** DEP: Deprecated MBZ. Reserved (bit 5). */
860#define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
861#define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
862/** PT: Pass Through. */
863#define VTD_BF_ECAP_REG_PT_SHIFT 6
864#define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
865/** SC: Snoop Control. */
866#define VTD_BF_ECAP_REG_SC_SHIFT 7
867#define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
868/** IRO: IOTLB Register Offset. */
869#define VTD_BF_ECAP_REG_IRO_SHIFT 8
870#define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
871/** R: Reserved (bits 19:18). */
872#define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
873#define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
874/** MHMV: Maximum Handle Mask Value. */
875#define VTD_BF_ECAP_REG_MHMV_SHIFT 20
876#define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
877/** DEP: Deprecated MBZ. Reserved (bit 24). */
878#define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
879#define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
880/** MTS: Memory Type Support. */
881#define VTD_BF_ECAP_REG_MTS_SHIFT 25
882#define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
883/** NEST: Nested Translation Support. */
884#define VTD_BF_ECAP_REG_NEST_SHIFT 26
885#define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
886/** R: Reserved (bit 27). */
887#define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
888#define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
889/** DEP: Deprecated MBZ. Reserved (bit 28). */
890#define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
891#define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
892/** PRS: Page Request Support. */
893#define VTD_BF_ECAP_REG_PRS_SHIFT 29
894#define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
895/** ERS: Execute Request Support. */
896#define VTD_BF_ECAP_REG_ERS_SHIFT 30
897#define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
898/** SRS: Supervisor Request Support. */
899#define VTD_BF_ECAP_REG_SRS_SHIFT 31
900#define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
901/** R: Reserved (bit 32). */
902#define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
903#define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
904/** NWFS: No Write Flag Support. */
905#define VTD_BF_ECAP_REG_NWFS_SHIFT 33
906#define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
907/** EAFS: Extended Accessed Flags Support. */
908#define VTD_BF_ECAP_REG_EAFS_SHIFT 34
909#define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
910/** PSS: PASID Size Supported. */
911#define VTD_BF_ECAP_REG_PSS_SHIFT 35
912#define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
913/** PASID: Process Address Space ID Support. */
914#define VTD_BF_ECAP_REG_PASID_SHIFT 40
915#define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
916/** DIT: Device-TLB Invalidation Throttle. */
917#define VTD_BF_ECAP_REG_DIT_SHIFT 41
918#define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
919/** PDS: Page-request Drain Support. */
920#define VTD_BF_ECAP_REG_PDS_SHIFT 42
921#define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
922/** SMTS: Scalable-Mode Translation Support. */
923#define VTD_BF_ECAP_REG_SMTS_SHIFT 43
924#define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
925/** VCS: Virtual Command Support. */
926#define VTD_BF_ECAP_REG_VCS_SHIFT 44
927#define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
928/** SLADS: Second-Level Accessed/Dirty Support. */
929#define VTD_BF_ECAP_REG_SLADS_SHIFT 45
930#define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
931/** SLTS: Second-Level Translation Support. */
932#define VTD_BF_ECAP_REG_SLTS_SHIFT 46
933#define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
934/** FLTS: First-Level Translation Support. */
935#define VTD_BF_ECAP_REG_FLTS_SHIFT 47
936#define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
937/** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
938#define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
939#define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
940/** RPS: RID-PASID Support. */
941#define VTD_BF_ECAP_REG_RPS_SHIFT 49
942#define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
943/** R: Reserved (bits 51:50). */
944#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
945#define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
946/** ADMS: Abort DMA Mode Support. */
947#define VTD_BF_ECAP_REG_ADMS_SHIFT 52
948#define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
949/** RPRIVS: RID_PRIV Support. */
950#define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
951#define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
952/** R: Reserved (bits 63:54). */
953#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
954#define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
955RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
956 (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
957 PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
958 RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
959
960/** RW: Read/write mask. */
961#define VTD_ECAP_REG_RW_MASK UINT64_C(0)
962/** @} */
963
964
965/** @name Global Command Register (GCMD_REG).
966 * In accordance with the Intel spec.
967 * @{ */
968/** R: Reserved (bits 22:0). */
969#define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
970#define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
971/** CFI: Compatibility Format Interrupt. */
972#define VTD_BF_GCMD_REG_CFI_SHIFT 23
973#define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
974/** SIRTP: Set Interrupt Table Remap Pointer. */
975#define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
976#define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
977/** IRE: Interrupt Remap Enable. */
978#define VTD_BF_GCMD_REG_IRE_SHIFT 25
979#define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
980/** QIE: Queued Invalidation Enable. */
981#define VTD_BF_GCMD_REG_QIE_SHIFT 26
982#define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
983/** WBF: Write Buffer Flush. */
984#define VTD_BF_GCMD_REG_WBF_SHIFT 27
985#define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
986/** EAFL: Enable Advance Fault Logging. */
987#define VTD_BF_GCMD_REG_EAFL_SHIFT 28
988#define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
989/** SFL: Set Fault Log. */
990#define VTD_BF_GCMD_REG_SFL_SHIFT 29
991#define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
992/** SRTP: Set Root Table Pointer. */
993#define VTD_BF_GCMD_REG_SRTP_SHIFT 30
994#define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
995/** TE: Translation Enable. */
996#define VTD_BF_GCMD_REG_TE_SHIFT 31
997#define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
998RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
999 (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
1000
1001/** RW: Read/write mask. */
1002#define VTD_GCMD_REG_RW_MASK ( VTD_BF_GCMD_REG_TE_MASK | VTD_BF_GCMD_REG_SRTP_MASK \
1003 | VTD_BF_GCMD_REG_SFL_MASK | VTD_BF_GCMD_REG_EAFL_MASK \
1004 | VTD_BF_GCMD_REG_WBF_MASK | VTD_BF_GCMD_REG_QIE_MASK \
1005 | VTD_BF_GCMD_REG_IRE_MASK | VTD_BF_GCMD_REG_SIRTP_MASK \
1006 | VTD_BF_GCMD_REG_CFI_MASK)
1007/** @} */
1008
1009
1010/** @name Global Status Register (GSTS_REG).
1011 * In accordance with the Intel spec.
1012 * @{ */
1013/** R: Reserved (bits 22:0). */
1014#define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
1015#define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
1016/** CFIS: Compatibility Format Interrupt Status. */
1017#define VTD_BF_GSTS_REG_CFIS_SHIFT 23
1018#define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
1019/** IRTPS: Interrupt Remapping Table Pointer Status. */
1020#define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
1021#define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
1022/** IRES: Interrupt Remapping Enable Status. */
1023#define VTD_BF_GSTS_REG_IRES_SHIFT 25
1024#define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
1025/** QIES: Queued Invalidation Enable Status. */
1026#define VTD_BF_GSTS_REG_QIES_SHIFT 26
1027#define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
1028/** WBFS: Write Buffer Flush Status. */
1029#define VTD_BF_GSTS_REG_WBFS_SHIFT 27
1030#define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
1031/** AFLS: Advanced Fault Logging Status. */
1032#define VTD_BF_GSTS_REG_AFLS_SHIFT 28
1033#define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
1034/** FLS: Fault Log Status. */
1035#define VTD_BF_GSTS_REG_FLS_SHIFT 29
1036#define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
1037/** RTPS: Root Table Pointer Status. */
1038#define VTD_BF_GSTS_REG_RTPS_SHIFT 30
1039#define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
1040/** TES: Translation Enable Status. */
1041#define VTD_BF_GSTS_REG_TES_SHIFT 31
1042#define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
1043RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
1044 (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
1045
1046/** RW: Read/write mask. */
1047#define VTD_GSTS_REG_RW_MASK UINT32_C(0)
1048/** @} */
1049
1050
1051/** @name Root Table Address Register (RTADDR_REG).
1052 * In accordance with the Intel spec.
1053 * @{ */
1054/** R: Reserved (bits 9:0). */
1055#define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
1056#define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
1057/** TTM: Translation Table Mode. */
1058#define VTD_BF_RTADDR_REG_TTM_SHIFT 10
1059#define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
1060/** RTA: Root Table Address. */
1061#define VTD_BF_RTADDR_REG_RTA_SHIFT 12
1062#define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
1063RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
1064 (RSVD_9_0, TTM, RTA));
1065
1066/** RW: Read/write mask. */
1067#define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
1068
1069/** RTADDR_REG.TTM: Legacy mode. */
1070#define VTD_TTM_LEGACY_MODE 0
1071/** RTADDR_REG.TTM: Scalable mode. */
1072#define VTD_TTM_SCALABLE_MODE 1
1073/** RTADDR_REG.TTM: Reserved. */
1074#define VTD_TTM_RSVD 2
1075/** RTADDR_REG.TTM: Abort DMA mode. */
1076#define VTD_TTM_ABORT_DMA_MODE 3
1077/** @} */
1078
1079
1080/** @name Context Command Register (CCMD_REG).
1081 * In accordance with the Intel spec.
1082 * @{ */
1083/** DID: Domain-ID. */
1084#define VTD_BF_CCMD_REG_DID_SHIFT 0
1085#define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
1086/** SID: Source-ID. */
1087#define VTD_BF_CCMD_REG_SID_SHIFT 16
1088#define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
1089/** FM: Function Mask. */
1090#define VTD_BF_CCMD_REG_FM_SHIFT 32
1091#define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
1092/** R: Reserved (bits 58:34). */
1093#define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
1094#define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
1095/** CAIG: Context Actual Invalidation Granularity. */
1096#define VTD_BF_CCMD_REG_CAIG_SHIFT 59
1097#define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
1098/** CIRG: Context Invalidation Request Granularity. */
1099#define VTD_BF_CCMD_REG_CIRG_SHIFT 61
1100#define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
1101/** ICC: Invalidation Context Cache. */
1102#define VTD_BF_CCMD_REG_ICC_SHIFT 63
1103#define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
1104RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
1105 (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
1106
1107/** RW: Read/write mask. */
1108#define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
1109 | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
1110 | VTD_BF_CCMD_REG_ICC_MASK)
1111/** @} */
1112
1113
1114/** @name IOTLB Invalidation Register (IOTLB_REG).
1115 * In accordance with the Intel spec.
1116 * @{ */
1117/** R: Reserved (bits 31:0). */
1118#define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
1119#define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
1120/** DID: Domain-ID. */
1121#define VTD_BF_IOTLB_REG_DID_SHIFT 32
1122#define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
1123/** DW: Draining Writes. */
1124#define VTD_BF_IOTLB_REG_DW_SHIFT 48
1125#define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
1126/** DR: Draining Reads. */
1127#define VTD_BF_IOTLB_REG_DR_SHIFT 49
1128#define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
1129/** R: Reserved (bits 56:50). */
1130#define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
1131#define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
1132/** IAIG: IOTLB Actual Invalidation Granularity. */
1133#define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
1134#define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
1135/** R: Reserved (bit 59). */
1136#define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
1137#define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
1138/** IIRG: IOTLB Invalidation Request Granularity. */
1139#define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
1140#define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
1141/** R: Reserved (bit 62). */
1142#define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
1143#define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
1144/** IVT: Invalidate IOTLB. */
1145#define VTD_BF_IOTLB_REG_IVT_SHIFT 63
1146#define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
1147RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
1148 (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
1149
1150/** RW: Read/write mask. */
1151#define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK | VTD_BF_IOTLB_REG_DW_MASK \
1152 | VTD_BF_IOTLB_REG_DR_MASK | VTD_BF_IOTLB_REG_IIRG_MASK \
1153 | VTD_BF_IOTLB_REG_IVT_MASK)
1154/** @} */
1155
1156
1157/** @name Invalidate Address Register (IVA_REG).
1158 * In accordance with the Intel spec.
1159 * @{ */
1160/** AM: Address Mask. */
1161#define VTD_BF_IVA_REG_AM_SHIFT 0
1162#define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
1163/** IH: Invalidation Hint. */
1164#define VTD_BF_IVA_REG_IH_SHIFT 6
1165#define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
1166/** R: Reserved (bits 11:7). */
1167#define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
1168#define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
1169/** ADDR: Address. */
1170#define VTD_BF_IVA_REG_ADDR_SHIFT 12
1171#define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
1172RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
1173 (AM, IH, RSVD_11_7, ADDR));
1174
1175/** RW: Read/write mask. */
1176#define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK | VTD_BF_IVA_REG_IH_MASK \
1177 | VTD_BF_IVA_REG_ADDR_MASK)
1178/** @} */
1179
1180
1181/** @name Fault Status Register (FSTS_REG).
1182 * In accordance with the Intel spec.
1183 * @{ */
1184/** PFO: Primary Fault Overflow. */
1185#define VTD_BF_FSTS_REG_PFO_SHIFT 0
1186#define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
1187/** PPF: Primary Pending Fault. */
1188#define VTD_BF_FSTS_REG_PPF_SHIFT 1
1189#define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
1190/** AFO: Advanced Fault Overflow. */
1191#define VTD_BF_FSTS_REG_AFO_SHIFT 2
1192#define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
1193/** APF: Advanced Pending Fault. */
1194#define VTD_BF_FSTS_REG_APF_SHIFT 3
1195#define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
1196/** IQE: Invalidation Queue Error. */
1197#define VTD_BF_FSTS_REG_IQE_SHIFT 4
1198#define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
1199/** ICE: Invalidation Completion Error. */
1200#define VTD_BF_FSTS_REG_ICE_SHIFT 5
1201#define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
1202/** ITE: Invalidation Timeout Error. */
1203#define VTD_BF_FSTS_REG_ITE_SHIFT 6
1204#define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
1205/** DEP: Deprecated MBZ. Reserved (bit 7). */
1206#define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
1207#define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
1208/** FRI: Fault Record Index. */
1209#define VTD_BF_FSTS_REG_FRI_SHIFT 8
1210#define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
1211/** R: Reserved (bits 31:16). */
1212#define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
1213#define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1214RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
1215 (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
1216
1217/** RW: Read/write mask. */
1218#define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1219 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1220 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1221/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1222#define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
1223 | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
1224 | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
1225/** @} */
1226
1227
1228/** @name Fault Event Control Register (FECTL_REG).
1229 * In accordance with the Intel spec.
1230 * @{ */
1231/** R: Reserved (bits 29:0). */
1232#define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
1233#define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1234/** IP: Interrupt Pending. */
1235#define VTD_BF_FECTL_REG_IP_SHIFT 30
1236#define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
1237/** IM: Interrupt Mask. */
1238#define VTD_BF_FECTL_REG_IM_SHIFT 31
1239#define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
1240RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
1241 (RSVD_29_0, IP, IM));
1242
1243/** RW: Read/write mask. */
1244#define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
1245/** @} */
1246
1247
1248/** @name Fault Event Data Register (FEDATA_REG).
1249 * In accordance with the Intel spec.
1250 * @{ */
1251/** IMD: Interrupt Message Data. */
1252#define VTD_BF_FEDATA_REG_IMD_SHIFT 0
1253#define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1254/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1255#define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
1256#define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1257RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
1258 (IMD, RSVD_31_16));
1259
1260/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1261 * Programming". */
1262#define VTD_FEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1263/** @} */
1264
1265
1266/** @name Fault Event Address Register (FEADDR_REG).
1267 * In accordance with the Intel spec.
1268 * @{ */
1269/** R: Reserved (bits 1:0). */
1270#define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
1271#define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1272/** MA: Message Address. */
1273#define VTD_BF_FEADDR_REG_MA_SHIFT 2
1274#define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1275RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
1276 (RSVD_1_0, MA));
1277
1278/** RW: Read/write mask. */
1279#define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
1280/** @} */
1281
1282
1283/** @name Fault Event Upper Address Register (FEUADDR_REG).
1284 * In accordance with the Intel spec.
1285 * @{ */
1286/** MUA: Message Upper Address. */
1287#define VTD_BF_FEUADDR_REG_MA_SHIFT 0
1288#define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
1289
1290/** RW: Read/write mask. */
1291#define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
1292/** @} */
1293
1294
1295/** @name Fault Recording Register (FRCD_REG).
1296 * In accordance with the Intel spec.
1297 * @{ */
1298/** R: Reserved (bits 11:0). */
1299#define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
1300#define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
1301/** FI: Fault Info. */
1302#define VTD_BF_0_FRCD_REG_FI_SHIFT 12
1303#define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
1304RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1305 (RSVD_11_0, FI));
1306
1307/** SID: Source Identifier. */
1308#define VTD_BF_1_FRCD_REG_SID_SHIFT 0
1309#define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
1310/** R: Reserved (bits 27:16). */
1311#define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
1312#define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
1313/** T2: Type bit 2. */
1314#define VTD_BF_1_FRCD_REG_T2_SHIFT 28
1315#define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
1316/** PRIV: Privilege Mode. */
1317#define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
1318#define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
1319/** EXE: Execute Permission Requested. */
1320#define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
1321#define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
1322/** PP: PASID Present. */
1323#define VTD_BF_1_FRCD_REG_PP_SHIFT 31
1324#define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
1325/** FR: Fault Reason. */
1326#define VTD_BF_1_FRCD_REG_FR_SHIFT 32
1327#define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
1328/** PV: PASID Value. */
1329#define VTD_BF_1_FRCD_REG_PV_SHIFT 40
1330#define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
1331/** AT: Address Type. */
1332#define VTD_BF_1_FRCD_REG_AT_SHIFT 60
1333#define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
1334/** T1: Type bit 1. */
1335#define VTD_BF_1_FRCD_REG_T1_SHIFT 62
1336#define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
1337/** F: Fault. */
1338#define VTD_BF_1_FRCD_REG_F_SHIFT 63
1339#define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
1340RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
1341 (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
1342
1343/** RW: Read/write mask. */
1344#define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
1345#define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
1346/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1347#define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
1348#define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
1349/** @} */
1350
1351
1352/**
1353 * VT-d faulted address translation request types (FRCD_REG::T2).
1354 * In accordance with the Intel spec.
1355 */
1356typedef enum VTDREQTYPE
1357{
1358 VTDREQTYPE_WRITE = 0, /**< Memory access write request. */
1359 VTDREQTYPE_PAGE, /**< Page translation request. */
1360 VTDREQTYPE_READ, /**< Memory access read request. */
1361 VTDREQTYPE_ATOMIC_OP /**< Memory access atomic operation. */
1362} VTDREQTYPE;
1363
1364
1365/** @name VT-d faulted request attributes (FRCD_REG::EXE, FRCD_REG::PRIV).
1366 * In accordance with the Intel spec.
1367 * @{
1368 */
1369/** Supervisory privilege was requested. */
1370#define VTD_REQ_ATTR_PRIV RT_BIT(0)
1371/** Execute permission was requested. */
1372#define VTD_REQ_ATTR_EXE RT_BIT(1)
1373/** @} */
1374
1375
1376/** @name Advanced Fault Log Register (AFLOG_REG).
1377 * In accordance with the Intel spec.
1378 * @{ */
1379/** R: Reserved (bits 8:0). */
1380#define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
1381#define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
1382/** FLS: Fault Log Size. */
1383#define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
1384#define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
1385/** FLA: Fault Log Address. */
1386#define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
1387#define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
1388RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
1389 (RSVD_8_0, FLS, FLA));
1390
1391/** RW: Read/write mask. */
1392#define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
1393/** @} */
1394
1395
1396/** @name Protected Memory Enable Register (PMEN_REG).
1397 * In accordance with the Intel spec.
1398 * @{ */
1399/** PRS: Protected Region Status. */
1400#define VTD_BF_PMEN_REG_PRS_SHIFT 0
1401#define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
1402/** R: Reserved (bits 30:1). */
1403#define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
1404#define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
1405/** EPM: Enable Protected Memory. */
1406#define VTD_BF_PMEN_REG_EPM_SHIFT 31
1407#define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
1408RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
1409 (PRS, RSVD_30_1, EPM));
1410
1411/** RW: Read/write mask. */
1412#define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
1413/** @} */
1414
1415
1416/** @name Invalidation Queue Head Register (IQH_REG).
1417 * In accordance with the Intel spec.
1418 * @{ */
1419/** R: Reserved (bits 3:0). */
1420#define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
1421#define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1422/** QH: Queue Head. */
1423#define VTD_BF_IQH_REG_QH_SHIFT 4
1424#define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
1425/** R: Reserved (bits 63:19). */
1426#define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
1427#define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1428RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
1429 (RSVD_3_0, QH, RSVD_63_19));
1430
1431/** RW: Read/write mask. */
1432#define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
1433/** @} */
1434
1435
1436/** @name Invalidation Queue Tail Register (IQT_REG).
1437 * In accordance with the Intel spec.
1438 * @{ */
1439/** R: Reserved (bits 3:0). */
1440#define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
1441#define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
1442/** QH: Queue Tail. */
1443#define VTD_BF_IQT_REG_QT_SHIFT 4
1444#define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
1445/** R: Reserved (bits 63:19). */
1446#define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
1447#define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1448RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
1449 (RSVD_3_0, QT, RSVD_63_19));
1450
1451/** RW: Read/write mask. */
1452#define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
1453/** @} */
1454
1455
1456/** @name Invalidation Queue Address Register (IQA_REG).
1457 * In accordance with the Intel spec.
1458 * @{ */
1459/** QS: Queue Size. */
1460#define VTD_BF_IQA_REG_QS_SHIFT 0
1461#define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
1462/** R: Reserved (bits 10:3). */
1463#define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
1464#define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
1465/** DW: Descriptor Width. */
1466#define VTD_BF_IQA_REG_DW_SHIFT 11
1467#define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
1468/** IQA: Invalidation Queue Base Address. */
1469#define VTD_BF_IQA_REG_IQA_SHIFT 12
1470#define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
1471RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
1472 (QS, RSVD_10_3, DW, IQA));
1473
1474/** RW: Read/write mask. */
1475#define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
1476 | VTD_BF_IQA_REG_IQA_MASK)
1477/** DW: 128-bit descriptor. */
1478#define VTD_IQA_REG_DW_128_BIT 0
1479/** DW: 256-bit descriptor. */
1480#define VTD_IQA_REG_DW_256_BIT 1
1481/** @} */
1482
1483
1484/** @name Invalidation Completion Status Register (ICS_REG).
1485 * In accordance with the Intel spec.
1486 * @{ */
1487/** IWC: Invalidation Wait Descriptor Complete. */
1488#define VTD_BF_ICS_REG_IWC_SHIFT 0
1489#define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
1490/** R: Reserved (bits 31:1). */
1491#define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
1492#define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
1493RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
1494 (IWC, RSVD_31_1));
1495
1496/** RW: Read/write mask. */
1497#define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
1498/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1499#define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
1500/** @} */
1501
1502
1503/** @name Invalidation Event Control Register (IECTL_REG).
1504 * In accordance with the Intel spec.
1505 * @{ */
1506/** R: Reserved (bits 29:0). */
1507#define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
1508#define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1509/** IP: Interrupt Pending. */
1510#define VTD_BF_IECTL_REG_IP_SHIFT 30
1511#define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
1512/** IM: Interrupt Mask. */
1513#define VTD_BF_IECTL_REG_IM_SHIFT 31
1514#define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
1515RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
1516 (RSVD_29_0, IP, IM));
1517
1518/** RW: Read/write mask. */
1519#define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
1520/** @} */
1521
1522
1523/** @name Invalidation Event Data Register (IEDATA_REG).
1524 * In accordance with the Intel spec.
1525 * @{ */
1526/** IMD: Interrupt Message Data. */
1527#define VTD_BF_IEDATA_REG_IMD_SHIFT 0
1528#define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1529/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1530#define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
1531#define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1532RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
1533 (IMD, RSVD_31_16));
1534
1535/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1536 * Programming". */
1537#define VTD_IEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1538/** @} */
1539
1540
1541/** @name Invalidation Event Address Register (IEADDR_REG).
1542 * In accordance with the Intel spec.
1543 * @{ */
1544/** R: Reserved (bits 1:0). */
1545#define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
1546#define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1547/** MA: Message Address. */
1548#define VTD_BF_IEADDR_REG_MA_SHIFT 2
1549#define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1550RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
1551 (RSVD_1_0, MA));
1552
1553/** RW: Read/write mask. */
1554#define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
1555/** @} */
1556
1557
1558/** @name Invalidation Event Upper Address Register (IEUADDR_REG).
1559 * @{ */
1560/** MUA: Message Upper Address. */
1561#define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
1562#define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1563
1564/** RW: Read/write mask. */
1565#define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
1566/** @} */
1567
1568
1569/** @name Invalidation Queue Error Record Register (IQERCD_REG).
1570 * In accordance with the Intel spec.
1571 * @{ */
1572/** IQEI: Invalidation Queue Error Info. */
1573#define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
1574#define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
1575/** R: Reserved (bits 31:4). */
1576#define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
1577#define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
1578/** ITESID: Invalidation Timeout Error Source Identifier. */
1579#define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
1580#define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
1581/** ICESID: Invalidation Completion Error Source Identifier. */
1582#define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
1583#define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
1584RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
1585 (IQEI, RSVD_31_4, ITESID, ICESID));
1586
1587/** RW: Read/write mask. */
1588#define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
1589
1590/** Invalidation Queue Error Information. */
1591typedef enum VTDIQEI
1592{
1593 VTDIQEI_INFO_NOT_AVAILABLE,
1594 VTDIQEI_INVALID_TAIL_PTR,
1595 VTDIQEI_FETCH_DESCRIPTOR_ERR,
1596 VTDIQEI_INVALID_DESCRIPTOR_TYPE,
1597 VTDIQEI_RSVD_FIELD_VIOLATION,
1598 VTDIQEI_INVALID_DESCRIPTOR_WIDTH,
1599 VTDIQEI_QUEUE_TAIL_MISALIGNED,
1600 VTDIQEI_INVALID_TTM
1601} VTDIQEI;
1602/** @} */
1603
1604
1605/** @name Interrupt Remapping Table Address Register (IRTA_REG).
1606 * In accordance with the Intel spec.
1607 * @{ */
1608/** S: Size. */
1609#define VTD_BF_IRTA_REG_S_SHIFT 0
1610#define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
1611/** R: Reserved (bits 10:4). */
1612#define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
1613#define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
1614/** EIME: Extended Interrupt Mode Enable. */
1615#define VTD_BF_IRTA_REG_EIME_SHIFT 11
1616#define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
1617/** IRTA: Interrupt Remapping Table Address. */
1618#define VTD_BF_IRTA_REG_IRTA_SHIFT 12
1619#define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
1620RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
1621 (S, RSVD_10_4, EIME, IRTA));
1622
1623/** RW: Read/write mask. */
1624#define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
1625 | VTD_BF_IRTA_REG_IRTA_MASK)
1626/** IRTA_REG: Get number of interrupt entries. */
1627#define VTD_IRTA_REG_GET_ENTRY_COUNT(a) (UINT32_C(1) << (1 + ((a) & VTD_BF_IRTA_REG_S_MASK)))
1628/** @} */
1629
1630
1631/** @name Page Request Queue Head Register (PQH_REG).
1632 * In accordance with the Intel spec.
1633 * @{ */
1634/** R: Reserved (bits 4:0). */
1635#define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
1636#define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1637/** PQH: Page Queue Head. */
1638#define VTD_BF_PQH_REG_PQH_SHIFT 5
1639#define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
1640/** R: Reserved (bits 63:19). */
1641#define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
1642#define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1643RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
1644 (RSVD_4_0, PQH, RSVD_63_19));
1645
1646/** RW: Read/write mask. */
1647#define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
1648/** @} */
1649
1650
1651/** @name Page Request Queue Tail Register (PQT_REG).
1652 * In accordance with the Intel spec.
1653 * @{ */
1654/** R: Reserved (bits 4:0). */
1655#define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
1656#define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
1657/** PQT: Page Queue Tail. */
1658#define VTD_BF_PQT_REG_PQT_SHIFT 5
1659#define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
1660/** R: Reserved (bits 63:19). */
1661#define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
1662#define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
1663RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
1664 (RSVD_4_0, PQT, RSVD_63_19));
1665
1666/** RW: Read/write mask. */
1667#define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
1668/** @} */
1669
1670
1671/** @name Page Request Queue Address Register (PQA_REG).
1672 * In accordance with the Intel spec.
1673 * @{ */
1674/** PQS: Page Queue Size. */
1675#define VTD_BF_PQA_REG_PQS_SHIFT 0
1676#define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
1677/** R: Reserved bits (11:3). */
1678#define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
1679#define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
1680/** PQA: Page Request Queue Base Address. */
1681#define VTD_BF_PQA_REG_PQA_SHIFT 12
1682#define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
1683RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
1684 (PQS, RSVD_11_3, PQA));
1685
1686/** RW: Read/write mask. */
1687#define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
1688/** @} */
1689
1690
1691/** @name Page Request Status Register (PRS_REG).
1692 * In accordance with the Intel spec.
1693 * @{ */
1694/** PPR: Pending Page Request. */
1695#define VTD_BF_PRS_REG_PPR_SHIFT 0
1696#define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
1697/** PRO: Page Request Overflow. */
1698#define VTD_BF_PRS_REG_PRO_SHIFT 1
1699#define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
1700/** R: Reserved (bits 31:2). */
1701#define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
1702#define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
1703RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
1704 (PPR, PRO, RSVD_31_2));
1705
1706/** RW: Read/write mask. */
1707#define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1708/** RW1C: Read-only-status, Write-1-to-clear status mask. */
1709#define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
1710/** @} */
1711
1712
1713/** @name Page Request Event Control Register (PECTL_REG).
1714 * In accordance with the Intel spec.
1715 * @{ */
1716/** R: Reserved (bits 29:0). */
1717#define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
1718#define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
1719/** IP: Interrupt Pending. */
1720#define VTD_BF_PECTL_REG_IP_SHIFT 30
1721#define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
1722/** IM: Interrupt Mask. */
1723#define VTD_BF_PECTL_REG_IM_SHIFT 31
1724#define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
1725RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
1726 (RSVD_29_0, IP, IM));
1727
1728/** RW: Read/write mask. */
1729#define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
1730/** @} */
1731
1732
1733/** @name Page Request Event Data Register (PEDATA_REG).
1734 * In accordance with the Intel spec.
1735 * @{ */
1736/** IMD: Interrupt Message Data. */
1737#define VTD_BF_PEDATA_REG_IMD_SHIFT 0
1738#define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
1739/** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
1740#define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
1741#define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
1742RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
1743 (IMD, RSVD_31_16));
1744
1745/** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
1746 * Programming". */
1747#define VTD_PEDATA_REG_RW_MASK UINT32_C(0x000001ff)
1748/** @} */
1749
1750
1751/** @name Page Request Event Address Register (PEADDR_REG).
1752 * In accordance with the Intel spec.
1753 * @{ */
1754/** R: Reserved (bits 1:0). */
1755#define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
1756#define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
1757/** MA: Message Address. */
1758#define VTD_BF_PEADDR_REG_MA_SHIFT 2
1759#define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
1760RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
1761 (RSVD_1_0, MA));
1762
1763/** RW: Read/write mask. */
1764#define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
1765/** @} */
1766
1767
1768
1769/** @name Page Request Event Upper Address Register (PEUADDR_REG).
1770 * In accordance with the Intel spec.
1771 * @{ */
1772/** MA: Message Address. */
1773#define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
1774#define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
1775
1776/** RW: Read/write mask. */
1777#define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
1778/** @} */
1779
1780
1781/** @name MTRR Capability Register (MTRRCAP_REG).
1782 * In accordance with the Intel spec.
1783 * @{ */
1784/** VCNT: Variable MTRR Count. */
1785#define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
1786#define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
1787/** FIX: Fixed range MTRRs Supported. */
1788#define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
1789#define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
1790/** R: Reserved (bit 9). */
1791#define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
1792#define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
1793/** WC: Write Combining. */
1794#define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
1795#define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
1796/** R: Reserved (bits 63:11). */
1797#define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
1798#define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
1799RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
1800 (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
1801
1802/** RW: Read/write mask. */
1803#define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
1804/** @} */
1805
1806
1807/** @name MTRR Default Type Register (MTRRDEF_REG).
1808 * In accordance with the Intel spec.
1809 * @{ */
1810/** TYPE: Default Memory Type. */
1811#define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
1812#define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
1813/** R: Reserved (bits 9:8). */
1814#define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
1815#define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
1816/** FE: Fixed Range MTRR Enable. */
1817#define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
1818#define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
1819/** E: MTRR Enable. */
1820#define VTD_BF_MTRRDEF_REG_E_SHIFT 11
1821#define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
1822/** R: Reserved (bits 63:12). */
1823#define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
1824#define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1825RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
1826 (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
1827
1828/** RW: Read/write mask. */
1829#define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
1830 | VTD_BF_MTRRDEF_REG_E_MASK)
1831/** @} */
1832
1833
1834/** @name Virtual Command Capability Register (VCCAP_REG).
1835 * In accordance with the Intel spec.
1836 * @{ */
1837/** PAS: PASID Support. */
1838#define VTD_BF_VCCAP_REG_PAS_SHIFT 0
1839#define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
1840/** R: Reserved (bits 63:1). */
1841#define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
1842#define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
1843RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
1844 (PAS, RSVD_63_1));
1845
1846/** RW: Read/write mask. */
1847#define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
1848/** @} */
1849
1850
1851/** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
1852 * In accordance with the Intel spec.
1853 * @{ */
1854/** OB: Operand B. */
1855#define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
1856#define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
1857
1858/** RW: Read/write mask. */
1859#define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
1860/** @} */
1861
1862
1863/** @name Virtual Command Register (VCMD_REG).
1864 * In accordance with the Intel spec.
1865 * @{ */
1866/** CMD: Command. */
1867#define VTD_BF_VCMD_REG_CMD_SHIFT 0
1868#define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
1869/** OP: Operand. */
1870#define VTD_BF_VCMD_REG_OP_SHIFT 8
1871#define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
1872RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
1873 (CMD, OP));
1874
1875/** RW: Read/write mask. */
1876#define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
1877/** @} */
1878
1879
1880/** @name Virtual Command Response Register (VCRSP_REG).
1881 * In accordance with the Intel spec.
1882 * @{ */
1883/** IP: In Progress. */
1884#define VTD_BF_VCRSP_REG_IP_SHIFT 0
1885#define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
1886/** SC: Status Code. */
1887#define VTD_BF_VCRSP_REG_SC_SHIFT 1
1888#define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
1889/** R: Reserved (bits 7:3). */
1890#define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
1891#define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
1892/** RSLT: Result. */
1893#define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
1894#define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
1895RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
1896 (IP, SC, RSVD_7_3, RSLT));
1897
1898/** RW: Read/write mask. */
1899#define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
1900/** @} */
1901
1902
1903/** @name Generic Invalidation Descriptor.
1904 * In accordance with the Intel spec.
1905 * Non-reserved fields here are common to all invalidation descriptors.
1906 * @{ */
1907/** Type (Lo). */
1908#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
1909#define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1910/** R: Reserved (bits 8:4). */
1911#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
1912#define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
1913/** Type (Hi). */
1914#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
1915#define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1916/** R: Reserved (bits 63:12). */
1917#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
1918#define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
1919RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1920 (TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
1921
1922/** GENERIC_INV_DSC: Type. */
1923#define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
1924 | ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
1925/** @} */
1926
1927
1928/** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
1929 * In accordance with the Intel spec.
1930 * @{ */
1931/** Type (Lo). */
1932#define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
1933#define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1934/** G: Granularity. */
1935#define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
1936#define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1937/** R: Reserved (bits 8:6). */
1938#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
1939#define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1940/** Type (Hi). */
1941#define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
1942#define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1943/** R: Reserved (bits 15:12). */
1944#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
1945#define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1946/** DID: Domain Id. */
1947#define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
1948#define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1949/** SID: Source Id. */
1950#define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
1951#define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
1952/** FM: Function Mask. */
1953#define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
1954#define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
1955/** R: Reserved (bits 63:50). */
1956#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
1957#define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
1958RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1959 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
1960/** @} */
1961
1962
1963/** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
1964 * In accordance with the Intel spec.
1965 * @{ */
1966/** Type (Lo). */
1967#define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
1968#define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
1969/** G: Granularity. */
1970#define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
1971#define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
1972/** R: Reserved (bits 8:6). */
1973#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
1974#define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
1975/** Type (Hi). */
1976#define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
1977#define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
1978/** R: Reserved (bits 15:12). */
1979#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
1980#define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
1981/** DID: Domain Id. */
1982#define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
1983#define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
1984/** PASID: Process Address-Space Id. */
1985#define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
1986#define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
1987/** R: Reserved (bits 63:52). */
1988#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
1989#define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
1990
1991RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
1992 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
1993/** @} */
1994
1995
1996/** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
1997 * In accordance with the Intel spec.
1998 * @{ */
1999/** Type (Lo). */
2000#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2001#define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2002/** G: Granularity. */
2003#define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
2004#define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2005/** DW: Drain Writes. */
2006#define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
2007#define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
2008/** DR: Drain Reads. */
2009#define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
2010#define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
2011/** R: Reserved (bit 8). */
2012#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
2013#define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2014/** Type (Hi). */
2015#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2016#define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2017/** R: Reserved (bits 15:12). */
2018#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2019#define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2020/** DID: Domain Id. */
2021#define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
2022#define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2023/** R: Reserved (bits 63:32). */
2024#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
2025#define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
2026RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2027 (TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
2028
2029/** AM: Address Mask. */
2030#define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
2031#define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2032/** IH: Invalidation Hint. */
2033#define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
2034#define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2035/** R: Reserved (bits 11:7). */
2036#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2037#define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2038/** ADDR: Address. */
2039#define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
2040#define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2041RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2042 (AM, IH, RSVD_11_7, ADDR));
2043/** @} */
2044
2045
2046/** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
2047 * In accordance with the Intel spec.
2048 * @{ */
2049/** Type (Lo). */
2050#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
2051#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2052/** G: Granularity. */
2053#define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
2054#define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
2055/** R: Reserved (bits 8:6). */
2056#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
2057#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
2058/** Type (Hi). */
2059#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
2060#define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2061/** R: Reserved (bits 15:12). */
2062#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
2063#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
2064/** DID: Domain Id. */
2065#define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
2066#define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
2067/** PASID: Process Address-Space Id. */
2068#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
2069#define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2070/** R: Reserved (bits 63:52). */
2071#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
2072#define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
2073RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2074 (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
2075
2076
2077/** AM: Address Mask. */
2078#define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
2079#define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
2080/** IH: Invalidation Hint. */
2081#define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
2082#define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
2083/** R: Reserved (bits 11:7). */
2084#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
2085#define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
2086/** ADDR: Address. */
2087#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
2088#define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2089RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2090 (AM, IH, RSVD_11_7, ADDR));
2091/** @} */
2092
2093
2094/** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
2095 * In accordance with the Intel spec.
2096 * @{ */
2097/** Type (Lo). */
2098#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2099#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2100/** R: Reserved (bits 8:4). */
2101#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
2102#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
2103/** Type (Hi). */
2104#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2105#define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2106/** PFSID: Physical-Function Source Id (Lo). */
2107#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2108#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2109/** MIP: Max Invalidations Pending. */
2110#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
2111#define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
2112/** R: Reserved (bits 31:21). */
2113#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
2114#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
2115/** SID: Source Id. */
2116#define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
2117#define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
2118/** R: Reserved (bits 51:48). */
2119#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
2120#define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
2121/** PFSID: Physical-Function Source Id (Hi). */
2122#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2123#define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2124RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2125 (TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
2126
2127/** S: Size. */
2128#define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
2129#define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
2130/** R: Reserved (bits 11:1). */
2131#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
2132#define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
2133/** ADDR: Address. */
2134#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2135#define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2136RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2137 (S, RSVD_11_1, ADDR));
2138/** @} */
2139
2140
2141/** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
2142 * In accordance with the Intel spec.
2143 * @{ */
2144/** Type (Lo). */
2145#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
2146#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2147/** MIP: Max Invalidations Pending. */
2148#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
2149#define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
2150/** Type (Hi). */
2151#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
2152#define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2153/** PFSID: Physical-Function Source Id (Lo). */
2154#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
2155#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
2156/** SID: Source Id. */
2157#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
2158#define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
2159/** PASID: Process Address-Space Id. */
2160#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
2161#define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
2162/** PFSID: Physical-Function Source Id (Hi). */
2163#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
2164#define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
2165RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2166 (TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
2167
2168/** G: Granularity. */
2169#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
2170#define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
2171/** R: Reserved (bits 10:1). */
2172#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
2173#define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
2174/** S: Size. */
2175#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
2176#define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
2177/** ADDR: Address. */
2178#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
2179#define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
2180RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
2181 (G, RSVD_10_1, S, ADDR));
2182/** @} */
2183
2184
2185/** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
2186 * In accordance with the Intel spec.
2187 * @{ */
2188/** Type (Lo). */
2189#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
2190#define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2191/** G: Granularity. */
2192#define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
2193#define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
2194/** R: Reserved (bits 8:5). */
2195#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
2196#define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
2197/** Type (Hi). */
2198#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
2199#define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2200/** R: Reserved (bits 26:12). */
2201#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
2202#define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
2203/** IM: Index Mask. */
2204#define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
2205#define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
2206/** IIDX: Interrupt Index. */
2207#define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
2208#define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
2209/** R: Reserved (bits 63:48). */
2210#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
2211#define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
2212RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
2213 (TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
2214/** @} */
2215
2216
2217/** @name Invalidation Wait Descriptor (inv_wait_dsc).
2218 * In accordance with the Intel spec.
2219 * @{ */
2220/** Type (Lo). */
2221#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
2222#define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
2223/** IF: Interrupt Flag. */
2224#define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
2225#define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
2226/** SW: Status Write. */
2227#define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
2228#define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
2229/** FN: Fence Flag. */
2230#define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
2231#define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
2232/** PD: Page-Request Drain. */
2233#define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
2234#define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
2235/** R: Reserved (bit 8). */
2236#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
2237#define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
2238/** Type (Hi). */
2239#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
2240#define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
2241/** R: Reserved (bits 31:12). */
2242#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
2243#define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
2244/** STDATA: Status Data. */
2245#define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
2246#define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
2247RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2248 (TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
2249
2250/** R: Reserved (bits 1:0). */
2251#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
2252#define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
2253/** STADDR: Status Address. */
2254#define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
2255#define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
2256RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
2257 (RSVD_1_0, STADDR));
2258
2259/* INV_WAIT_DSC: Qword 0 valid mask. */
2260#define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
2261 | VTD_BF_0_INV_WAIT_DSC_IF_MASK \
2262 | VTD_BF_0_INV_WAIT_DSC_SW_MASK \
2263 | VTD_BF_0_INV_WAIT_DSC_FN_MASK \
2264 | VTD_BF_0_INV_WAIT_DSC_PD_MASK \
2265 | VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
2266 | VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
2267/* INV_WAIT_DSC: Qword 1 valid mask. */
2268#define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
2269/** @} */
2270
2271
2272/** @name Invalidation descriptor types.
2273 * In accordance with the Intel spec.
2274 * @{ */
2275#define VTD_CC_INV_DSC_TYPE 1
2276#define VTD_IOTLB_INV_DSC_TYPE 2
2277#define VTD_DEV_TLB_INV_DSC_TYPE 3
2278#define VTD_IEC_INV_DSC_TYPE 4
2279#define VTD_INV_WAIT_DSC_TYPE 5
2280#define VTD_P_IOTLB_INV_DSC_TYPE 6
2281#define VTD_PC_INV_DSC_TYPE 7
2282#define VTD_P_DEV_TLB_INV_DSC_TYPE 8
2283/** @} */
2284
2285
2286/** @name Remappable Format Interrupt Request.
2287 * In accordance with the Intel spec.
2288 * @{ */
2289/** IGN: Ignored (bits 1:0). */
2290#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_SHIFT 0
2291#define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
2292/** Handle (Hi). */
2293#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_SHIFT 2
2294#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
2295/** SHV: Subhandle Valid. */
2296#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_SHIFT 3
2297#define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_MASK UINT32_C(0x00000008)
2298/** Interrupt format. */
2299#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_SHIFT 4
2300#define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
2301/** Handle (Lo). */
2302#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_SHIFT 5
2303#define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
2304/** Address. */
2305#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_SHIFT 20
2306#define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_MASK UINT32_C(0xfff00000)
2307RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_ADDR_, UINT32_C(0), UINT32_MAX,
2308 (IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
2309
2310/** Subhandle. */
2311#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_SHIFT 0
2312#define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
2313/** R: Reserved (bits 31:16). */
2314#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_SHIFT 16
2315#define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
2316RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_DATA_, UINT32_C(0), UINT32_MAX,
2317 (SUBHANDLE, RSVD_31_16));
2318
2319/** Remappable MSI Address: Valid mask. */
2320#define VTD_REMAPPABLE_MSI_ADDR_VALID_MASK UINT32_MAX
2321/** Remappable MSI Data: Valid mask. */
2322#define VTD_REMAPPABLE_MSI_DATA_VALID_MASK VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK
2323
2324/** Interrupt format: Compatibility. */
2325#define VTD_INTR_FORMAT_COMPAT 0
2326/** Interrupt format: Remappable. */
2327#define VTD_INTR_FORMAT_REMAPPABLE 1
2328/** @} */
2329
2330
2331/** @name Interrupt Remapping Fault Conditions.
2332 * In accordance with the Intel spec.
2333 * @{ */
2334typedef enum VTDIRFAULT
2335{
2336 /** Reserved bits invalid in remappable interrupt. */
2337 VTDIRFAULT_REMAPPABLE_INTR_RSVD = 0x20,
2338
2339 /** Interrupt index for remappable interrupt exceeds table size or referenced
2340 * address above host address width (HAW) */
2341 VTDIRFAULT_INTR_INDEX_INVALID = 0x21,
2342
2343 /** The IRTE is not present. */
2344 VTDIRFAULT_IRTE_NOT_PRESENT = 0x22,
2345 /** Reading IRTE from memory failed. */
2346 VTDIRFAULT_IRTE_READ_FAILED = 0x23,
2347 /** IRTE reserved bits invalid for an IRTE with Present bit set. */
2348 VTDIRFAULT_IRTE_PRESENT_RSVD = 0x24,
2349
2350 /** Compatibility format interrupt (CFI) blocked due to EIME being enabled or CFIs
2351 * were disabled. */
2352 VTDIRFAULT_CFI_BLOCKED = 0x25,
2353
2354 /** IRTE SID, SVT, SQ bits invalid for an IRTE with Present bit set. */
2355 VTDIRFAULT_IRTE_PRESENT_INVALID = 0x26,
2356
2357 /** Reading posted interrupt descriptor (PID) failed. */
2358 VTDIRFAULT_PID_READ_FAILED = 0x27,
2359 /** PID reserved bits invalid. */
2360 VTDIRFAULT_PID_RSVD = 0x28,
2361
2362 /** Untranslated interrupt requested (without PASID) is invalid. */
2363 VTDIRFAULT_IR_WITHOUT_PASID_INVALID = 0x29
2364} VTDIRFAULT;
2365AssertCompileSize(VTDIRFAULT, 4);
2366/** @} */
2367
2368
2369/** @name Address Translation Fault Conditions.
2370 * In accordance with the Intel spec.
2371 * @{ */
2372typedef enum VTDATFAULT
2373{
2374 /* Legacy root table faults (LRT). */
2375 VTDATFAULT_LRT_1 = 0x8,
2376 VTDATFAULT_LRT_2 = 0x1,
2377 VTDATFAULT_LRT_3 = 0xa,
2378
2379 /* Legacy Context-Table Faults (LCT). */
2380 VTDATFAULT_LCT_1 = 0x9,
2381 VTDATFAULT_LCT_2 = 0x2,
2382 VTDATFAULT_LCT_3 = 0xb,
2383 VTDATFAULT_LCT_4_0 = 0x3,
2384 VTDATFAULT_LCT_4_1 = 0x3,
2385 VTDATFAULT_LCT_4_2 = 0x3,
2386 VTDATFAULT_LCT_4_3 = 0x3,
2387 VTDATFAULT_LCT_5 = 0xd,
2388
2389 /* Legacy Second-Level Table Faults (LSL). */
2390 VTDATFAULT_LSL_1 = 0x7,
2391 VTDATFAULT_LSL_2 = 0xc,
2392
2393 /* Legacy General Faults (LGN). */
2394 VTDATFAULT_LGN_1_0 = 0x4,
2395 VTDATFAULT_LGN_1_1 = 0x4,
2396 VTDATFAULT_LGN_1_2 = 0x4,
2397 VTDATFAULT_LGN_1_3 = 0x4,
2398 VTDATFAULT_LGN_2 = 0x5,
2399 VTDATFAULT_LGN_3 = 0x6,
2400 VTDATFAULT_LGN_4 = 0xe,
2401
2402 /* Root-Table Address Register Faults (RTA). */
2403 VTDATFAULT_RTA_1_0 = 0x30,
2404 VTDATFAULT_RTA_1_1 = 0x30,
2405 VTDATFAULT_RTA_1_2 = 0x30,
2406 VTDATFAULT_RTA_1_3 = 0x30,
2407 VTDATFAULT_RTA_2 = 0x31,
2408 VTDATFAULT_RTA_3 = 0x32,
2409 VTDATFAULT_RTA_4 = 0x33,
2410
2411 /* Scalable-Mode Root-Table Faults (SRT). */
2412 VTDATFAULT_SRT_1 = 0x38,
2413 VTDATFAULT_SRT_2 = 0x39,
2414 VTDATFAULT_SRT_3 = 0x3a,
2415
2416 /* Scalable-Mode Context-Table Faults (SCT). */
2417 VTDATFAULT_SCT_1 = 0x40,
2418 VTDATFAULT_SCT_2 = 0x41,
2419 VTDATFAULT_SCT_3 = 0x42,
2420 VTDATFAULT_SCT_4_0 = 0x43,
2421 VTDATFAULT_SCT_4_1 = 0x43,
2422 VTDATFAULT_SCT_4_2 = 0x43,
2423 VTDATFAULT_SCT_5 = 0x44,
2424 VTDATFAULT_SCT_6 = 0x45,
2425 VTDATFAULT_SCT_7 = 0x46,
2426 VTDATFAULT_SCT_8 = 0x47,
2427 VTDATFAULT_SCT_9 = 0x48,
2428
2429 /* Scalable-Mode PASID-Directory Faults (SPD). */
2430 VTDATFAULT_SPD_1 = 0x50,
2431 VTDATFAULT_SPD_2 = 0x51,
2432 VTDATFAULT_SPD_3 = 0x52,
2433
2434 /* Scalable-Mode PASID-Table Faults (SPT). */
2435 VTDATFAULT_SPT_1 = 0x58,
2436 VTDATFAULT_SPT_2 = 0x59,
2437 VTDATFAULT_SPT_3 = 0x5a,
2438 VTDATFAULT_SPT_4_0 = 0x5b,
2439 VTDATFAULT_SPT_4_1 = 0x5b,
2440 VTDATFAULT_SPT_4_2 = 0x5b,
2441 VTDATFAULT_SPT_4_3 = 0x5b,
2442 VTDATFAULT_SPT_4_4 = 0x5b,
2443 VTDATFAULT_SPT_5 = 0x5c,
2444 VTDATFAULT_SPT_6 = 0x5d,
2445
2446 /* Scalable-Mode First-Level Table Faults (SFL). */
2447 VTDATFAULT_SFL_1 = 0x70,
2448 VTDATFAULT_SFL_2 = 0x71,
2449 VTDATFAULT_SFL_3 = 0x72,
2450 VTDATFAULT_SFL_4 = 0x73,
2451 VTDATFAULT_SFL_5 = 0x74,
2452 VTDATFAULT_SFL_6 = 0x75,
2453 VTDATFAULT_SFL_7 = 0x76,
2454 VTDATFAULT_SFL_8 = 0x77,
2455 VTDATFAULT_SFL_9 = 0x90,
2456 VTDATFAULT_SFL_10 = 0x91,
2457
2458 /* Scalable-Mode Second-Level Table Faults (SSL). */
2459 VTDATFAULT_SSL_1 = 0x78,
2460 VTDATFAULT_SSL_2 = 0x79,
2461 VTDATFAULT_SSL_3 = 0x7a,
2462 VTDATFAULT_SSL_4 = 0x7b,
2463 VTDATFAULT_SSL_5 = 0x7c,
2464 VTDATFAULT_SSL_6 = 0x7d,
2465
2466 /* Scalable-Mode General Faults (SGN). */
2467 VTDATFAULT_SGN_1 = 0x80,
2468 VTDATFAULT_SGN_2 = 0x81,
2469 VTDATFAULT_SGN_3 = 0x82,
2470 VTDATFAULT_SGN_4_0 = 0x83,
2471 VTDATFAULT_SGN_4_1 = 0x83,
2472 VTDATFAULT_SGN_4_2 = 0x83,
2473 VTDATFAULT_SGN_5 = 0x84,
2474 VTDATFAULT_SGN_6 = 0x85,
2475 VTDATFAULT_SGN_7 = 0x86,
2476 VTDATFAULT_SGN_8 = 0x87,
2477 VTDATFAULT_SGN_9 = 0x88,
2478 VTDATFAULT_SGN_10 = 0x89
2479} VTDATFAULT;
2480AssertCompileSize(VTDATFAULT, 4);
2481/** @} */
2482
2483
2484/** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
2485 * In accordance with the Intel spec.
2486 * @{ */
2487/** INTR_REMAP: Interrupt remapping supported. */
2488#define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
2489/** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
2490#define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
2491/** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
2492 * memory regions (RMRR). */
2493#define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
2494/** @} */
2495
2496
2497/** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
2498 * In accordance with the Intel spec.
2499 * @{ */
2500/** INCLUDE_PCI_ALL: All PCI devices under scope. */
2501#define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
2502/** @} */
2503
2504
2505/**
2506 * DRHD: DMA-Remapping Hardware Unit Definition.
2507 * In accordance with the Intel spec.
2508 */
2509#pragma pack(1)
2510typedef struct ACPIDRHD
2511{
2512 /** Type (must be 0=DRHD). */
2513 uint16_t uType;
2514 /** Length (must be 16 + size of device scope structure). */
2515 uint16_t cbLength;
2516 /** Flags, see ACPI_DRHD_F_XXX. */
2517 uint8_t fFlags;
2518 /** Reserved (MBZ). */
2519 uint8_t bRsvd;
2520 /** PCI segment number. */
2521 uint16_t uPciSegment;
2522 /** Register Base Address (MMIO). */
2523 uint64_t uRegBaseAddr;
2524 /* Device Scope[] Structures follow. */
2525} ACPIDRHD;
2526#pragma pack()
2527AssertCompileSize(ACPIDRHD, 16);
2528AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
2529AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
2530AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
2531AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
2532
2533
2534/** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
2535 * In accordance with the Intel spec.
2536 * @{ */
2537#define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
2538#define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
2539#define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
2540#define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
2541#define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
2542/** @} */
2543
2544
2545/**
2546 * ACPI Device Scope Structure - PCI device path.
2547 * In accordance with the Intel spec.
2548 */
2549typedef struct ACPIDEVSCOPEPATH
2550{
2551 /** PCI device number. */
2552 uint8_t uDevice;
2553 /** PCI function number. */
2554 uint8_t uFunction;
2555} ACPIDEVSCOPEPATH;
2556AssertCompileSize(ACPIDEVSCOPEPATH, 2);
2557
2558
2559/**
2560 * Device Scope Structure.
2561 * In accordance with the Intel spec.
2562 */
2563#pragma pack(1)
2564typedef struct ACPIDMARDEVSCOPE
2565{
2566 /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
2567 uint8_t uType;
2568 /** Length (must be 6 + size of auPath field). */
2569 uint8_t cbLength;
2570 /** Reserved (MBZ). */
2571 uint8_t abRsvd[2];
2572 /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
2573 uint8_t idEnum;
2574 /** First bus number for this device. */
2575 uint8_t uStartBusNum;
2576 /** Hierarchical path from the Host Bridge to the device. */
2577 ACPIDEVSCOPEPATH Path;
2578} ACPIDMARDEVSCOPE;
2579#pragma pack()
2580AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
2581AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
2582AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
2583AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
2584
2585/** ACPI DMAR revision (not the OEM revision field).
2586 * In accordance with the Intel spec. */
2587#define ACPI_DMAR_REVISION 1
2588
2589
2590#endif /* !VBOX_INCLUDED_iommu_intel_h */
2591
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