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source: vbox/trunk/include/VBox/iommu-amd.h@ 97583

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1/** @file
2 * IOMMU - Input/Output Memory Management Unit (AMD).
3 */
4
5/*
6 * Copyright (C) 2020-2022 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_iommu_amd_h
37#define VBOX_INCLUDED_iommu_amd_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <iprt/types.h>
43#include <iprt/assertcompile.h>
44
45/**
46 * @name PCI configuration register offsets.
47 * In accordance with the AMD spec.
48 * @{
49 */
50#define IOMMU_PCI_OFF_CAP_HDR 0x40
51#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
52#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
53#define IOMMU_PCI_OFF_RANGE_REG 0x4c
54#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
55#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
56#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
57#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
58#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
59#define IOMMU_PCI_OFF_MSI_DATA 0x70
60#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
61/** @} */
62
63/**
64 * @name MMIO register offsets.
65 * In accordance with the AMD spec.
66 * @{
67 */
68#define IOMMU_MMIO_OFF_QWORD_TABLE_0_START IOMMU_MMIO_OFF_DEV_TAB_BAR
69#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
70#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
71#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
72#define IOMMU_MMIO_OFF_CTRL 0x18
73#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
74#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
75#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
76
77#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
78#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
79#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
80#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
81
82#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
83#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
84
85#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
86#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
87
88#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
89#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
90
91#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
92#define IOMMU_MMIO_OFF_DEV_TAB_SEG_1 0x100
93#define IOMMU_MMIO_OFF_DEV_TAB_SEG_2 0x108
94#define IOMMU_MMIO_OFF_DEV_TAB_SEG_3 0x110
95#define IOMMU_MMIO_OFF_DEV_TAB_SEG_4 0x118
96#define IOMMU_MMIO_OFF_DEV_TAB_SEG_5 0x120
97#define IOMMU_MMIO_OFF_DEV_TAB_SEG_6 0x128
98#define IOMMU_MMIO_OFF_DEV_TAB_SEG_7 0x130
99#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
100
101#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
102#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
103#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
104
105#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
106#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
107#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
108#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
109#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
110#define IOMMU_MMIO_OFF_MSI_DATA 0x164
111#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
112
113#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
114
115#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
116#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
117#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
118#define IOMMU_MMIO_OFF_QWORD_TABLE_0_END (IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL + 8)
119
120#define IOMMU_MMIO_OFF_QWORD_TABLE_1_START IOMMU_MMIO_OFF_MARC_APER_BAR_0
121#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
122#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
123#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
124#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
125#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
126#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
127#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
128#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
129#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
130#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
131#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
132#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
133#define IOMMU_MMIO_OFF_QWORD_TABLE_1_END (IOMMU_MMIO_OFF_MARC_APER_LEN_3 + 8)
134
135#define IOMMU_MMIO_OFF_QWORD_TABLE_2_START IOMMU_MMIO_OFF_RSVD_REG
136#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
137
138#define IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR 0x2000
139#define IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR 0x2008
140#define IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR 0x2010
141#define IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR 0x2018
142
143#define IOMMU_MMIO_OFF_STATUS 0x2020
144
145#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
146#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
147
148#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
149#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
150
151#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
152#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
153
154#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
155#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
156
157#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
158#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
159#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
160#define IOMMU_MMIO_OFF_QWORD_TABLE_2_END (IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY + 8)
161/** @} */
162
163/**
164 * @name MMIO register-access table offsets.
165 * Each table [first..last] (both inclusive) represents the range of registers
166 * covered by a distinct register-access table. This is done due to arbitrary large
167 * gaps in the MMIO register offsets themselves.
168 * @{
169 */
170#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
171#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
172
173#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
174#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
175/** @} */
176
177/**
178 * @name Commands.
179 * In accordance with the AMD spec.
180 * @{
181 */
182#define IOMMU_CMD_COMPLETION_WAIT 0x01
183#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
184#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
185#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
186#define IOMMU_CMD_INV_INTR_TABLE 0x05
187#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
188#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
189#define IOMMU_CMD_INV_IOMMU_ALL 0x08
190/** @} */
191
192/**
193 * @name Event codes.
194 * In accordance with the AMD spec.
195 * @{
196 */
197#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
198#define IOMMU_EVT_IO_PAGE_FAULT 0x02
199#define IOMMU_EVT_DEV_TAB_HW_ERROR 0x03
200#define IOMMU_EVT_PAGE_TAB_HW_ERROR 0x04
201#define IOMMU_EVT_ILLEGAL_CMD_ERROR 0x05
202#define IOMMU_EVT_COMMAND_HW_ERROR 0x06
203#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
204#define IOMMU_EVT_INVALID_DEV_REQ 0x08
205#define IOMMU_EVT_INVALID_PPR_REQ 0x09
206#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
207#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
208/** @} */
209
210/**
211 * @name IOMMU Capability Header.
212 * In accordance with the AMD spec.
213 * @{
214 */
215/** CapId: Capability ID. */
216#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
217#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
218/** CapPtr: Capability Pointer. */
219#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
220#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
221/** CapType: Capability Type. */
222#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
223#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
224/** CapRev: Capability Revision. */
225#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
226#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
227/** IoTlbSup: IO TLB Support. */
228#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
229#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
230/** HtTunnel: HyperTransport Tunnel translation support. */
231#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
232#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
233/** NpCache: Not Present table entries Cached. */
234#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
235#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
236/** EFRSup: Extended Feature Register (EFR) Supported. */
237#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
238#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
239/** CapExt: Miscellaneous Information Register Supported . */
240#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
241#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
242/** Bits 31:29 reserved. */
243#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
244#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
245RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
246 (CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
247/** @} */
248
249/**
250 * @name IOMMU Base Address Low Register.
251 * In accordance with the AMD spec.
252 * @{
253 */
254/** Enable: Enables access to the address specified in the Base Address Register. */
255#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
256#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
257/** Bits 13:1 reserved. */
258#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
259#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
260/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
261#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
262#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
263RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
264 (ENABLE, RSVD_1_13, ADDR));
265/** @} */
266
267/**
268 * @name IOMMU Range Register.
269 * In accordance with the AMD spec.
270 * @{
271 */
272/** UnitID: HyperTransport Unit ID. */
273#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
274#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
275/** Bits 6:5 reserved. */
276#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
277#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
278/** RngValid: Range valid. */
279#define IOMMU_BF_RANGE_VALID_SHIFT 7
280#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
281/** BusNumber: Device range bus number. */
282#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
283#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
284/** First Device. */
285#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
286#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
287/** Last Device. */
288#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
289#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
290RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
291 (UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
292/** @} */
293
294/**
295 * @name IOMMU Miscellaneous Information Register 0.
296 * In accordance with the AMD spec.
297 * @{
298 */
299/** MsiNum: MSI message number. */
300#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
301#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
302/** GvaSize: Guest Virtual Address Size. */
303#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
304#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
305/** PaSize: Physical Address Size. */
306#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
307#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
308/** VaSize: Virtual Address Size. */
309#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
310#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
311/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
312#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
313#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
314/** Bits 26:23 reserved. */
315#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
316#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
317/** MsiNumPPR: Peripheral Page Request MSI message number. */
318#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
319#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
320RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
321 (MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
322/** @} */
323
324/**
325 * @name IOMMU Miscellaneous Information Register 1.
326 * In accordance with the AMD spec.
327 * @{
328 */
329/** MsiNumGA: MSI message number for guest virtual-APIC log. */
330#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
331#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
332/** Bits 31:5 reserved. */
333#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
334#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
335RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
336 (MSI_NUM_GA, RSVD_5_31));
337/** @} */
338
339/**
340 * @name MSI Capability Header Register.
341 * In accordance with the AMD spec.
342 * @{
343 */
344/** MsiCapId: Capability ID. */
345#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_SHIFT 0
346#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_MASK UINT32_C(0x000000ff)
347/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
348#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_SHIFT 8
349#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
350/** MsiEn: Message Signal Interrupt enable. */
351#define IOMMU_BF_MSI_CAP_HDR_EN_SHIFT 16
352#define IOMMU_BF_MSI_CAP_HDR_EN_MASK UINT32_C(0x00010000)
353/** MsiMultMessCap: MSI Multi-Message Capability. */
354#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_SHIFT 17
355#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
356/** MsiMultMessEn: MSI Mult-Message Enable. */
357#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_SHIFT 20
358#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
359/** Msi64BitEn: MSI 64-bit Enabled. */
360#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_SHIFT 23
361#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_MASK UINT32_C(0x00800000)
362/** Bits 31:24 reserved. */
363#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_SHIFT 24
364#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_MASK UINT32_C(0xff000000)
365RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAP_HDR_, UINT32_C(0), UINT32_MAX,
366 (CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
367/** @} */
368
369/**
370 * @name MSI Mapping Capability Header Register.
371 * In accordance with the AMD spec.
372 * @{
373 */
374/** MsiMapCapId: Capability ID. */
375#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
376#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
377/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
378#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
379#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
380/** MsiMapEn: MSI mapping capability enable. */
381#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
382#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
383/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
384#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
385#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
386/** Bits 18:28 reserved. */
387#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
388#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
389/** MsiMapCapType: MSI mapping capability. */
390#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
391#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
392RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
393 (CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
394/** @} */
395
396/**
397 * @name IOMMU Status Register Bits.
398 * In accordance with the AMD spec.
399 * @{
400 */
401/** EventOverflow: Event log overflow. */
402#define IOMMU_STATUS_EVT_LOG_OVERFLOW RT_BIT_64(0)
403/** EventLogInt: Event log interrupt. */
404#define IOMMU_STATUS_EVT_LOG_INTR RT_BIT_64(1)
405/** ComWaitInt: Completion wait interrupt. */
406#define IOMMU_STATUS_COMPLETION_WAIT_INTR RT_BIT_64(2)
407/** EventLogRun: Event log is running. */
408#define IOMMU_STATUS_EVT_LOG_RUNNING RT_BIT_64(3)
409/** CmdBufRun: Command buffer is running. */
410#define IOMMU_STATUS_CMD_BUF_RUNNING RT_BIT_64(4)
411/** PprOverflow: Peripheral page request log overflow. */
412#define IOMMU_STATUS_PPR_LOG_OVERFLOW RT_BIT_64(5)
413/** PprInt: Peripheral page request log interrupt. */
414#define IOMMU_STATUS_PPR_LOG_INTR RT_BIT_64(6)
415/** PprLogRun: Peripheral page request log is running. */
416#define IOMMU_STATUS_PPR_LOG_RUN RT_BIT_64(7)
417/** GALogRun: Guest virtual-APIC log is running. */
418#define IOMMU_STATUS_GA_LOG_RUN RT_BIT_64(8)
419/** GALOverflow: Guest virtual-APIC log overflow. */
420#define IOMMU_STATUS_GA_LOG_OVERFLOW RT_BIT_64(9)
421/** GAInt: Guest virtual-APIC log interrupt. */
422#define IOMMU_STATUS_GA_LOG_INTR RT_BIT_64(10)
423/** PprOvrflwB: PPR Log B overflow. */
424#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW RT_BIT_64(11)
425/** PprLogActive: PPR Log B is active. */
426#define IOMMU_STATUS_PPR_LOG_B_ACTIVE RT_BIT_64(12)
427/** EvtOvrflwB: Event log B overflow. */
428#define IOMMU_STATUS_EVT_LOG_B_OVERFLOW RT_BIT_64(15)
429/** EventLogActive: Event log B active. */
430#define IOMMU_STATUS_EVT_LOG_B_ACTIVE RT_BIT_64(16)
431/** PprOvrflwEarlyB: PPR log B overflow early warning. */
432#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW_EARLY RT_BIT_64(17)
433/** PprOverflowEarly: PPR log overflow early warning. */
434#define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY RT_BIT_64(18)
435/** @} */
436
437/** @name IOMMU_IO_PERM_XXX: IOMMU I/O access permissions bits.
438 * In accordance with the AMD spec.
439 *
440 * These values match the shifted values of the IR and IW field of the DTE and the
441 * PTE, PDE of the I/O page tables.
442 *
443 * @{ */
444#define IOMMU_IO_PERM_NONE (0)
445#define IOMMU_IO_PERM_READ RT_BIT_64(0)
446#define IOMMU_IO_PERM_WRITE RT_BIT_64(1)
447#define IOMMU_IO_PERM_READ_WRITE (IOMMU_IO_PERM_READ | IOMMU_IO_PERM_WRITE)
448#define IOMMU_IO_PERM_SHIFT 61
449#define IOMMU_IO_PERM_MASK 0x3
450/** @} */
451
452/** @name SYSMGT_TYPE_XXX: System Management Message Enable Types.
453 * In accordance with the AMD spec.
454 * @{ */
455#define SYSMGTTYPE_DMA_DENY (0)
456#define SYSMGTTYPE_MSG_ALL_ALLOW (1)
457#define SYSMGTTYPE_MSG_INT_ALLOW (2)
458#define SYSMGTTYPE_DMA_ALLOW (3)
459/** @} */
460
461/** @name IOMMU_INTR_CTRL_XX: DTE::IntCtl field values.
462 * These are control bits for handling fixed and arbitrated interrupts.
463 * In accordance with the AMD spec.
464 * @{ */
465#define IOMMU_INTR_CTRL_TARGET_ABORT (0)
466#define IOMMU_INTR_CTRL_FWD_UNMAPPED (1)
467#define IOMMU_INTR_CTRL_REMAP (2)
468#define IOMMU_INTR_CTRL_RSVD (3)
469/** @} */
470
471/** Gets the device table length (in bytes) given the device table pointer. */
472#define IOMMU_GET_DEV_TAB_LEN(a_pDevTab) (((a_pDevTab)->n.u9Size + 1) << X86_PAGE_4K_SHIFT)
473
474/**
475 * The Device ID.
476 * In accordance with VirtualBox's PCI configuration.
477 */
478typedef union
479{
480 struct
481 {
482 RT_GCC_EXTENSION uint16_t u3Function : 3; /**< Bits 2:0 - Function. */
483 RT_GCC_EXTENSION uint16_t u9Device : 9; /**< Bits 11:3 - Device. */
484 RT_GCC_EXTENSION uint16_t u4Bus : 4; /**< Bits 15:12 - Bus. */
485 } n;
486 /** The unsigned integer view. */
487 uint16_t u;
488} DEVICE_ID_T;
489AssertCompileSize(DEVICE_ID_T, 2);
490
491/**
492 * Device Table Entry (DTE).
493 * In accordance with the AMD spec.
494 */
495typedef union
496{
497 struct
498 {
499 RT_GCC_EXTENSION uint64_t u1Valid : 1; /**< Bit 0 - V: Valid. */
500 RT_GCC_EXTENSION uint64_t u1TranslationValid : 1; /**< Bit 1 - TV: Translation information Valid. */
501 RT_GCC_EXTENSION uint64_t u5Rsvd0 : 5; /**< Bits 6:2 - Reserved. */
502 RT_GCC_EXTENSION uint64_t u2Had : 2; /**< Bits 8:7 - HAD: Host Access Dirty. */
503 RT_GCC_EXTENSION uint64_t u3Mode : 3; /**< Bits 11:9 - Mode: Paging mode. */
504 RT_GCC_EXTENSION uint64_t u40PageTableRootPtrLo : 40; /**< Bits 51:12 - Page Table Root Pointer. */
505 RT_GCC_EXTENSION uint64_t u1Ppr : 1; /**< Bit 52 - PPR: Peripheral Page Request. */
506 RT_GCC_EXTENSION uint64_t u1GstPprRespPasid : 1; /**< Bit 53 - GRPR: Guest PPR Response with PASID. */
507 RT_GCC_EXTENSION uint64_t u1GstIoValid : 1; /**< Bit 54 - GIoV: Guest I/O Protection Valid. */
508 RT_GCC_EXTENSION uint64_t u1GstTranslateValid : 1; /**< Bit 55 - GV: Guest translation Valid. */
509 RT_GCC_EXTENSION uint64_t u2GstMode : 2; /**< Bits 57:56 - GLX: Guest Paging mode levels. */
510 RT_GCC_EXTENSION uint64_t u3GstCr3TableRootPtrLo : 3; /**< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Ptr (Lo). */
511 RT_GCC_EXTENSION uint64_t u1IoRead : 1; /**< Bit 61 - IR: I/O Read permission. */
512 RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /**< Bit 62 - IW: I/O Write permission. */
513 RT_GCC_EXTENSION uint64_t u1Rsvd0 : 1; /**< Bit 63 - Reserved. */
514 RT_GCC_EXTENSION uint64_t u16DomainId : 16; /**< Bits 79:64 - Domain ID. */
515 RT_GCC_EXTENSION uint64_t u16GstCr3TableRootPtrMid : 16; /**< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Ptr (Mid). */
516 RT_GCC_EXTENSION uint64_t u1IoTlbEnable : 1; /**< Bit 96 - I: IOTLB Enable (remote). */
517 RT_GCC_EXTENSION uint64_t u1SuppressPfEvents : 1; /**< Bit 97 - SE: Suppress Page-fault events. */
518 RT_GCC_EXTENSION uint64_t u1SuppressAllPfEvents : 1; /**< Bit 98 - SA: Suppress All Page-fault events. */
519 RT_GCC_EXTENSION uint64_t u2IoCtl : 2; /**< Bits 100:99 - IoCtl: Port I/O Control. */
520 RT_GCC_EXTENSION uint64_t u1Cache : 1; /**< Bit 101 - Cache: IOTLB Cache Hint. */
521 RT_GCC_EXTENSION uint64_t u1SnoopDisable : 1; /**< Bit 102 - SD: Snoop Disable. */
522 RT_GCC_EXTENSION uint64_t u1AllowExclusion : 1; /**< Bit 103 - EX: Allow Exclusion. */
523 RT_GCC_EXTENSION uint64_t u2SysMgt : 2; /**< Bits 105:104 - SysMgt: System Management message enable. */
524 RT_GCC_EXTENSION uint64_t u1Rsvd1 : 1; /**< Bit 106 - Reserved. */
525 RT_GCC_EXTENSION uint64_t u21GstCr3TableRootPtrHi : 21; /**< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Ptr (Hi). */
526 RT_GCC_EXTENSION uint64_t u1IntrMapValid : 1; /**< Bit 128 - IV: Interrupt map Valid. */
527 RT_GCC_EXTENSION uint64_t u4IntrTableLength : 4; /**< Bits 132:129 - IntTabLen: Interrupt Table Length. */
528 RT_GCC_EXTENSION uint64_t u1IgnoreUnmappedIntrs : 1; /**< Bits 133 - IG: Ignore unmapped interrupts. */
529 RT_GCC_EXTENSION uint64_t u46IntrTableRootPtr : 46; /**< Bits 179:134 - Interrupt Root Table Pointer. */
530 RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /**< Bits 183:180 - Reserved. */
531 RT_GCC_EXTENSION uint64_t u1InitPassthru : 1; /**< Bits 184 - INIT Pass-through. */
532 RT_GCC_EXTENSION uint64_t u1ExtIntPassthru : 1; /**< Bits 185 - External Interrupt Pass-through. */
533 RT_GCC_EXTENSION uint64_t u1NmiPassthru : 1; /**< Bits 186 - NMI Pass-through. */
534 RT_GCC_EXTENSION uint64_t u1Rsvd2 : 1; /**< Bits 187 - Reserved. */
535 RT_GCC_EXTENSION uint64_t u2IntrCtrl : 2; /**< Bits 189:188 - IntCtl: Interrupt Control. */
536 RT_GCC_EXTENSION uint64_t u1Lint0Passthru : 1; /**< Bit 190 - Lint0Pass: LINT0 Pass-through. */
537 RT_GCC_EXTENSION uint64_t u1Lint1Passthru : 1; /**< Bit 191 - Lint1Pass: LINT1 Pass-through. */
538 RT_GCC_EXTENSION uint64_t u32Rsvd0 : 32; /**< Bits 223:192 - Reserved. */
539 RT_GCC_EXTENSION uint64_t u22Rsvd0 : 22; /**< Bits 245:224 - Reserved. */
540 RT_GCC_EXTENSION uint64_t u1AttrOverride : 1; /**< Bit 246 - AttrV: Attribute Override. */
541 RT_GCC_EXTENSION uint64_t u1Mode0FC : 1; /**< Bit 247 - Mode0FC. */
542 RT_GCC_EXTENSION uint64_t u8SnoopAttr : 8; /**< Bits 255:248 - Snoop Attribute. */
543 } n;
544 /** The 32-bit unsigned integer view. */
545 uint32_t au32[8];
546 /** The 64-bit unsigned integer view. */
547 uint64_t au64[4];
548} DTE_T;
549AssertCompileSize(DTE_T, 32);
550/** Pointer to a device table entry. */
551typedef DTE_T *PDTE_T;
552/** Pointer to a const device table entry. */
553typedef DTE_T const *PCDTE_T;
554
555/** Mask of valid bits for EPHSUP (Enhanced Peripheral Page Request Handling
556 * Support) feature (bits 52:53). */
557#define IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK UINT64_C(0x0030000000000000)
558
559/** Mask of valid bits for GTSup (Guest Translation Support) feature (bits 55:60,
560 * bits 80:95). */
561#define IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK UINT64_C(0x1f80000000000000)
562#define IOMMU_DTE_QWORD_1_FEAT_GTSUP_MASK UINT64_C(0x00000000ffff0000)
563
564/** Mask of valid bits for GIoSup (Guest I/O Protection Support) feature (bit 54). */
565#define IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK UINT64_C(0x0040000000000000)
566
567/** Mask of valid DTE feature bits. */
568#define IOMMU_DTE_QWORD_0_FEAT_MASK ( IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK \
569 | IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK \
570 | IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
571#define IOMMU_DTE_QWORD_1_FEAT_MASK IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK
572
573/** Mask of all valid DTE bits (including all feature bits). */
574#define IOMMU_DTE_QWORD_0_VALID_MASK UINT64_C(0x7fffffffffffff83)
575#define IOMMU_DTE_QWORD_1_VALID_MASK UINT64_C(0xfffffbffffffffff)
576#define IOMMU_DTE_QWORD_2_VALID_MASK UINT64_C(0xff0fffffffffffff)
577#define IOMMU_DTE_QWORD_3_VALID_MASK UINT64_C(0xffc0000000000000)
578
579/** Mask of the interrupt table root pointer. */
580#define IOMMU_DTE_IRTE_ROOT_PTR_MASK UINT64_C(0x000fffffffffffc0)
581/** Number of bits to shift to get the interrupt root table pointer at
582 qword 2 (qword 0 being the first one) - 128-byte aligned. */
583#define IOMMU_DTE_IRTE_ROOT_PTR_SHIFT 6
584
585/** Maximum encoded IRTE length (exclusive). */
586#define IOMMU_DTE_INTR_TAB_LEN_MAX 12
587/** Gets the interrupt table entries (in bytes) given the DTE pointer. */
588#define IOMMU_DTE_GET_INTR_TAB_ENTRIES(a_pDte) (UINT64_C(1) << (a_pDte)->n.u4IntrTableLength)
589/** Gets the interrupt table length (in bytes) given the DTE pointer. */
590#define IOMMU_DTE_GET_INTR_TAB_LEN(a_pDte) (IOMMU_DTE_GET_INTR_TAB_ENTRIES(a_pDte) * sizeof(IRTE_T))
591/** Mask of interrupt control bits. */
592#define IOMMU_DTE_INTR_CTRL_MASK 0x3
593/** Gets the interrupt control bits from the DTE. */
594#define IOMMU_DTE_GET_INTR_CTRL(a_pDte) (((a_pDte)->au64[2] >> 60) & IOMMU_DTE_INTR_CTRL_MASK)
595/** Gets the ignore unmapped interrupt bit from DTE. */
596#define IOMMU_DTE_GET_IG(a_pDte) (((a_pDte)->au64[2] >> 5) & 0x1)
597
598/**
599 * I/O Page Translation Entry.
600 * In accordance with the AMD spec.
601 */
602typedef union
603{
604 struct
605 {
606 RT_GCC_EXTENSION uint64_t u1Present : 1; /**< Bit 0 - PR: Present. */
607 RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /**< Bits 4:1 - Ignored. */
608 RT_GCC_EXTENSION uint64_t u1Accessed : 1; /**< Bit 5 - A: Accessed. */
609 RT_GCC_EXTENSION uint64_t u1Dirty : 1; /**< Bit 6 - D: Dirty. */
610 RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /**< Bits 8:7 - Ignored. */
611 RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /**< Bits 11:9 - Next Level: Next page translation level. */
612 RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /**< Bits 51:12 - Page address. */
613 RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /**< Bits 58:52 - Reserved. */
614 RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /**< Bit 59 - U: Untranslated Access Only. */
615 RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /**< Bit 60 - FC: Force Coherent. */
616 RT_GCC_EXTENSION uint64_t u1IoRead : 1; /**< Bit 61 - IR: I/O Read permission. */
617 RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /**< Bit 62 - IW: I/O Wead permission. */
618 RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /**< Bit 63 - Ignored. */
619 } n;
620 /** The 64-bit unsigned integer view. */
621 uint64_t u64;
622} IOPTE_T;
623AssertCompileSize(IOPTE_T, 8);
624
625/**
626 * I/O Page Directory Entry.
627 * In accordance with the AMD spec.
628 */
629typedef union
630{
631 struct
632 {
633 RT_GCC_EXTENSION uint64_t u1Present : 1; /**< Bit 0 - PR: Present. */
634 RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /**< Bits 4:1 - Ignored. */
635 RT_GCC_EXTENSION uint64_t u1Accessed : 1; /**< Bit 5 - A: Accessed. */
636 RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /**< Bits 8:6 - Ignored. */
637 RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /**< Bits 11:9 - Next Level: Next page translation level. */
638 RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /**< Bits 51:12 - Page address (Next Table Address). */
639 RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /**< Bits 60:52 - Reserved. */
640 RT_GCC_EXTENSION uint64_t u1IoRead : 1; /**< Bit 61 - IR: I/O Read permission. */
641 RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /**< Bit 62 - IW: I/O Wead permission. */
642 RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /**< Bit 63 - Ignored. */
643 } n;
644 /** The 64-bit unsigned integer view. */
645 uint64_t u64;
646} IOPDE_T;
647AssertCompileSize(IOPDE_T, 8);
648
649/**
650 * I/O Page Table Entity.
651 * In accordance with the AMD spec.
652 *
653 * This a common subset of an DTE.au64[0], PTE and PDE.
654 * Named as an "entity" to avoid confusing it with PTE.
655 */
656typedef union
657{
658 struct
659 {
660 RT_GCC_EXTENSION uint64_t u1Present : 1; /**< Bit 0 - PR: Present. */
661 RT_GCC_EXTENSION uint64_t u8Ign0 : 8; /**< Bits 8:1 - Ignored. */
662 RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /**< Bits 11:9 - Mode / Next Level: Next page translation level. */
663 RT_GCC_EXTENSION uint64_t u40Addr : 40; /**< Bits 51:12 - Page address. */
664 RT_GCC_EXTENSION uint64_t u9Ign0 : 9; /**< Bits 60:52 - Ignored. */
665 RT_GCC_EXTENSION uint64_t u1IoRead : 1; /**< Bit 61 - IR: I/O Read permission. */
666 RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /**< Bit 62 - IW: I/O Wead permission. */
667 RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /**< Bit 63 - Ignored. */
668 } n;
669 /** The 64-bit unsigned integer view. */
670 uint64_t u64;
671} IOPTENTITY_T;
672AssertCompileSize(IOPTENTITY_T, 8);
673AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPTE_T));
674AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPDE_T));
675/** Pointer to an IOPT_ENTITY_T struct. */
676typedef IOPTENTITY_T *PIOPTENTITY_T;
677/** Pointer to a const IOPT_ENTITY_T struct. */
678typedef IOPTENTITY_T const *PCIOPTENTITY_T;
679/** Mask of the address field. */
680#define IOMMU_PTENTITY_ADDR_MASK UINT64_C(0x000ffffffffff000)
681/** Reserved bits in the PDE (bits 60:52). */
682#define IOMMU_PDE_RSVD_MASK UINT64_C(0x1ff0000000000000)
683/** Reserved bits in the PTE (bits 58:52 - U, FC bits not reserved). */
684#define IOMMU_PTE_RSVD_MASK UINT64_C(0x07f0000000000000)
685
686/**
687 * Interrupt Remapping Table Entry (IRTE) - Basic Format.
688 * In accordance with the AMD spec.
689 */
690typedef union
691{
692 struct
693 {
694 uint32_t u1RemapEnable : 1; /**< Bit 0 - RemapEn: Remap Enable. */
695 uint32_t u1SuppressIoPf : 1; /**< Bit 1 - SupIOPF: Suppress I/O Page Fault. */
696 uint32_t u3IntrType : 3; /**< Bits 4:2 - IntType: Interrupt Type. */
697 uint32_t u1ReqEoi : 1; /**< Bit 5 - RqEoi: Request EOI. */
698 uint32_t u1DestMode : 1; /**< Bit 6 - DM: Destination Mode. */
699 uint32_t u1GuestMode : 1; /**< Bit 7 - GuestMode. */
700 uint32_t u8Dest : 8; /**< Bits 15:8 - Destination. */
701 uint32_t u8Vector : 8; /**< Bits 23:16 - Vector. */
702 uint32_t u8Rsvd0 : 8; /**< Bits 31:24 - Reserved. */
703 } n;
704 /** The 32-bit unsigned integer view. */
705 uint32_t u32;
706} IRTE_T;
707AssertCompileSize(IRTE_T, 4);
708/** Pointer to an IRTE_T struct. */
709typedef IRTE_T *PIRTE_T;
710/** Pointer to a const IRTE_T struct. */
711typedef IRTE_T const *PCIRTE_T;
712
713/** The IRTE offset corresponds directly to bits 10:0 of the originating MSI
714 * interrupt message. See AMD IOMMU spec. 2.2.5 "Interrupt Remapping Tables". */
715#define IOMMU_MSI_DATA_IRTE_OFFSET_MASK UINT32_C(0x000007ff)
716/** Gets the IRTE offset from the originating MSI interrupt message. */
717#define IOMMU_GET_IRTE_OFF(a_u32MsiData) (((a_u32MsiData) & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T))
718
719/**
720 * Interrupt Remapping Table Entry (IRTE) - Guest Virtual APIC Enabled.
721 * In accordance with the AMD spec.
722 */
723typedef union
724{
725 struct
726 {
727 uint32_t u1RemapEnable : 1; /**< Bit 0 - RemapEn: Remap Enable. */
728 uint32_t u1SuppressIoPf : 1; /**< Bit 1 - SupIOPF: Suppress I/O Page Fault. */
729 uint32_t u1GALogIntr : 1; /**< Bit 2 - GALogIntr: Guest APIC Log Interrupt. */
730 uint32_t u3Rsvd : 3; /**< Bits 5:3 - Reserved. */
731 uint32_t u1IsRunning : 1; /**< Bit 6 - IsRun: Hint whether the guest is running. */
732 uint32_t u1GuestMode : 1; /**< Bit 7 - GuestMode. */
733 uint32_t u8Dest : 8; /**< Bits 15:8 - Destination. */
734 uint32_t u8Rsvd0 : 8; /**< Bits 31:16 - Reserved. */
735 uint32_t u32GATag : 32; /**< Bits 63:31 - GATag: Tag used when writing to GA log. */
736 uint32_t u8Vector : 8; /**< Bits 71:64 - Vector: Interrupt vector. */
737 uint32_t u4Reserved : 4; /**< Bits 75:72 - Reserved or ignored depending on RemapEn. */
738 uint32_t u20GATableRootPtrLo : 20; /**< Bits 95:76 - Bits [31:12] of Guest vAPIC Table Root Pointer. */
739 uint32_t u20GATableRootPtrHi : 20; /**< Bits 115:76 - Bits [51:32] of Guest vAPIC Table Root Pointer. */
740 uint32_t u12Rsvd : 12; /**< Bits 127:116 - Reserved. */
741 } n;
742 /** The 64-bit unsigned integer view. */
743 uint64_t u64[2];
744} IRTE_GVA_T;
745AssertCompileSize(IRTE_GVA_T, 16);
746/** Pointer to an IRTE_GVA_T struct. */
747typedef IRTE_GVA_T *PIRTE_GVA_T;
748/** Pointer to a const IRTE_GVA_T struct. */
749typedef IRTE_GVA_T const *PCIRTE_GVA_T;
750
751/**
752 * Command: Generic Command Buffer Entry.
753 * In accordance with the AMD spec.
754 */
755typedef union
756{
757 struct
758 {
759 uint32_t u32Operand1Lo; /**< Bits 31:0 - Operand 1 (Lo). */
760 uint32_t u28Operand1Hi : 28; /**< Bits 59:32 - Operand 1 (Hi). */
761 uint32_t u4Opcode : 4; /**< Bits 63:60 - Op Code. */
762 uint64_t u64Operand2; /**< Bits 127:64 - Operand 2. */
763 } n;
764 /** The 64-bit unsigned integer view. */
765 uint64_t au64[2];
766} CMD_GENERIC_T;
767AssertCompileSize(CMD_GENERIC_T, 16);
768/** Pointer to a generic command buffer entry. */
769typedef CMD_GENERIC_T *PCMD_GENERIC_T;
770/** Pointer to a const generic command buffer entry. */
771typedef CMD_GENERIC_T const *PCCMD_GENERIC_T;
772
773/** Number of bits to shift the byte offset of a command in the command buffer to
774 * get its index. */
775#define IOMMU_CMD_GENERIC_SHIFT 4
776
777/**
778 * Command: COMPLETION_WAIT.
779 * In accordance with the AMD spec.
780 */
781typedef union
782{
783 struct
784 {
785 uint32_t u1Store : 1; /**< Bit 0 - S: Completion Store. */
786 uint32_t u1Interrupt : 1; /**< Bit 1 - I: Completion Interrupt. */
787 uint32_t u1Flush : 1; /**< Bit 2 - F: Flush Queue. */
788 uint32_t u29StoreAddrLo : 29; /**< Bits 31:3 - Store Address (Lo). */
789 uint32_t u20StoreAddrHi : 20; /**< Bits 51:32 - Store Address (Hi). */
790 uint32_t u8Rsvd0 : 8; /**< Bits 59:52 - Reserved. */
791 uint32_t u4OpCode : 4; /**< Bits 63:60 - OpCode (Command). */
792 uint64_t u64StoreData; /**< Bits 127:64 - Store Data. */
793 } n;
794 /** The 64-bit unsigned integer view. */
795 uint64_t au64[2];
796} CMD_COMWAIT_T;
797AssertCompileSize(CMD_COMWAIT_T, 16);
798/** Pointer to a completion wait command. */
799typedef CMD_COMWAIT_T *PCMD_COMWAIT_T;
800/** Pointer to a const completion wait command. */
801typedef CMD_COMWAIT_T const *PCCMD_COMWAIT_T;
802#define IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK UINT64_C(0xf00fffffffffffff)
803
804/**
805 * Command: INVALIDATE_DEVTAB_ENTRY.
806 * In accordance with the AMD spec.
807 */
808typedef union
809{
810 struct
811 {
812 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
813 uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */
814 uint32_t u28Rsvd0 : 28; /**< Bits 59:32 - Reserved. */
815 uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */
816 uint64_t u64Rsvd0; /**< Bits 127:64 - Reserved. */
817 } n;
818 /** The 64-bit unsigned integer view. */
819 uint64_t au64[2];
820} CMD_INV_DTE_T;
821AssertCompileSize(CMD_INV_DTE_T, 16);
822/** Pointer to a invalidate DTE command. */
823typedef CMD_INV_DTE_T *PCMD_INV_DTE_T;
824/** Pointer to a const invalidate DTE command. */
825typedef CMD_INV_DTE_T const *PCCMD_INV_DTE_T;
826#define IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK UINT64_C(0xf00000000000ffff)
827#define IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK UINT64_C(0x0000000000000000)
828
829/**
830 * Command: INVALIDATE_IOMMU_PAGES.
831 * In accordance with the AMD spec.
832 */
833typedef union
834{
835 struct
836 {
837 uint32_t u20Pasid : 20; /**< Bits 19:0 - PASID: Process Address-Space ID. */
838 uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. */
839 uint32_t u16DomainId : 16; /**< Bits 47:32 - Domain ID. */
840 uint32_t u12Rsvd1 : 12; /**< Bits 59:48 - Reserved. */
841 uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */
842 uint32_t u1Size : 1; /**< Bit 64 - S: Size. */
843 uint32_t u1PageDirEntries : 1; /**< Bit 65 - PDE: Page Directory Entries. */
844 uint32_t u1GuestOrNested : 1; /**< Bit 66 - GN: Guest (GPA) or Nested (GVA). */
845 uint32_t u9Rsvd0 : 9; /**< Bits 75:67 - Reserved. */
846 uint32_t u20AddrLo : 20; /**< Bits 95:76 - Address (Lo). */
847 uint32_t u32AddrHi; /**< Bits 127:96 - Address (Hi). */
848 } n;
849 /** The 64-bit unsigned integer view. */
850 uint64_t au64[2];
851} CMD_INV_IOMMU_PAGES_T;
852AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
853/** Pointer to a invalidate iommu pages command. */
854typedef CMD_INV_IOMMU_PAGES_T *PCMD_INV_IOMMU_PAGES_T;
855/** Pointer to a const invalidate iommu pages command. */
856typedef CMD_INV_IOMMU_PAGES_T const *PCCMD_INV_IOMMU_PAGES_T;
857#define IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK UINT64_C(0xf000ffff000fffff)
858#define IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK UINT64_C(0xfffffffffffff007)
859
860/**
861 * Command: INVALIDATE_IOTLB_PAGES.
862 * In accordance with the AMD spec.
863 */
864typedef union
865{
866 struct
867 {
868 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
869 uint8_t u8PasidLo; /**< Bits 23:16 - PASID: Process Address-Space ID (Lo). */
870 uint8_t u8MaxPend; /**< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. */
871 uint32_t u16QueueId : 16; /**< Bits 47:32 - Queue ID. */
872 uint32_t u12PasidHi : 12; /**< Bits 59:48 - PASID: Process Address-Space ID (Hi). */
873 uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */
874 uint32_t u1Size : 1; /**< Bit 64 - S: Size. */
875 uint32_t u1Rsvd0: 1; /**< Bit 65 - Reserved. */
876 uint32_t u1GuestOrNested : 1; /**< Bit 66 - GN: Guest (GPA) or Nested (GVA). */
877 uint32_t u1Rsvd1 : 1; /**< Bit 67 - Reserved. */
878 uint32_t u2Type : 2; /**< Bit 69:68 - Type. */
879 uint32_t u6Rsvd0 : 6; /**< Bits 75:70 - Reserved. */
880 uint32_t u20AddrLo : 20; /**< Bits 95:76 - Address (Lo). */
881 uint32_t u32AddrHi; /**< Bits 127:96 - Address (Hi). */
882 } n;
883 /** The 64-bit unsigned integer view. */
884 uint64_t au64[2];
885} CMD_INV_IOTLB_PAGES_T;
886AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
887
888/**
889 * Command: INVALIDATE_INTR_TABLE.
890 * In accordance with the AMD spec.
891 */
892typedef union
893{
894 struct
895 {
896 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
897 uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */
898 uint32_t u32Rsvd0 : 28; /**< Bits 59:32 - Reserved. */
899 uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */
900 uint64_t u64Rsvd0; /**< Bits 127:64 - Reserved. */
901 } u;
902 /** The 64-bit unsigned integer view. */
903 uint64_t au64[2];
904} CMD_INV_INTR_TABLE_T;
905AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
906/** Pointer to a invalidate interrupt table command. */
907typedef CMD_INV_INTR_TABLE_T *PCMD_INV_INTR_TABLE_T;
908/** Pointer to a const invalidate interrupt table command. */
909typedef CMD_INV_INTR_TABLE_T const *PCCMD_INV_INTR_TABLE_T;
910#define IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK UINT64_C(0xf00000000000ffff)
911#define IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK UINT64_C(0x0000000000000000)
912
913/**
914 * Command: PREFETCH_IOMMU_PAGES.
915 * In accordance with the AMD spec.
916 */
917typedef union
918{
919 struct
920 {
921 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
922 uint8_t u8Rsvd0; /**< Bits 23:16 - Reserved. */
923 uint8_t u8PrefCount; /**< Bits 31:24 - PFCount: Number of translations to prefetch. */
924 uint32_t u20Pasid : 20; /**< Bits 51:32 - PASID: Process Address-Space ID. */
925 uint32_t u8Rsvd1 : 8; /**< Bits 59:52 - Reserved. */
926 uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */
927 uint32_t u1Size : 1; /**< Bit 64 - S: Size of the prefetched pages. */
928 uint32_t u1Rsvd0 : 1; /**< Bit 65 - Reserved. */
929 uint32_t u1GuestOrNested : 1; /**< Bit 66 - GN: Guest (GPA) or Nested (GVA). */
930 uint32_t u1Rsvd1 : 1; /**< Bit 67 - Reserved. */
931 uint32_t u1Invalidate : 1; /**< Bit 68 - Inval: Invalidate prior to prefetch. */
932 uint32_t u7Rsvd0 : 7; /**< Bits 75:69 - Reserved */
933 uint32_t u20AddrLo : 7; /**< Bits 95:76 - Address (Lo). */
934 uint32_t u32AddrHi; /**< Bits 127:96 - Address (Hi). */
935 } u;
936 /** The 64-bit unsigned integer view. */
937 uint64_t au64[2];
938} CMD_PREF_IOMMU_PAGES_T;
939AssertCompileSize(CMD_PREF_IOMMU_PAGES_T, 16);
940/** Pointer to a invalidate iommu pages command. */
941typedef CMD_PREF_IOMMU_PAGES_T *PCMD_PREF_IOMMU_PAGES_T;
942/** Pointer to a const invalidate iommu pages command. */
943typedef CMD_PREF_IOMMU_PAGES_T const *PCCMD_PREF_IOMMU_PAGES_T;
944#define IOMMU_CMD_PREF_IOMMU_PAGES_QWORD_0_VALID_MASK UINT64_C(0x780fffffff00ffff)
945#define IOMMU_CMD_PREF_IOMMU_PAGES_QWORD_1_VALID_MASK UINT64_C(0xfffffffffffff015)
946
947
948/**
949 * Command: COMPLETE_PPR_REQ.
950 * In accordance with the AMD spec.
951 */
952typedef union
953{
954 struct
955 {
956 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
957 uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */
958 uint32_t u20Pasid : 20; /**< Bits 51:32 - PASID: Process Address-Space ID. */
959 uint32_t u8Rsvd0 : 8; /**< Bits 59:52 - Reserved. */
960 uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */
961 uint32_t u2Rsvd0 : 2; /**< Bits 65:64 - Reserved. */
962 uint32_t u1GuestOrNested : 1; /**< Bit 66 - GN: Guest (GPA) or Nested (GVA). */
963 uint32_t u29Rsvd0 : 29; /**< Bits 95:67 - Reserved. */
964 uint32_t u16CompletionTag : 16; /**< Bits 111:96 - Completion Tag. */
965 uint32_t u16Rsvd1 : 16; /**< Bits 127:112 - Reserved. */
966 } n;
967 /** The 64-bit unsigned integer view. */
968 uint64_t au64[2];
969} CMD_COMPLETE_PPR_REQ_T;
970AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
971
972/**
973 * Command: INV_IOMMU_ALL.
974 * In accordance with the AMD spec.
975 */
976typedef union
977{
978 struct
979 {
980 uint32_t u32Rsvd0; /**< Bits 31:0 - Reserved. */
981 uint32_t u28Rsvd0 : 28; /**< Bits 59:32 - Reserved. */
982 uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */
983 uint64_t u64Rsvd0; /**< Bits 127:64 - Reserved. */
984 } n;
985 /** The 64-bit unsigned integer view. */
986 uint64_t au64[2];
987} CMD_INV_IOMMU_ALL_T;
988AssertCompileSize(CMD_INV_IOMMU_ALL_T, 16);
989/** Pointer to a invalidate IOMMU all command. */
990typedef CMD_INV_IOMMU_ALL_T *PCMD_INV_IOMMU_ALL_T;
991/** Pointer to a const invalidate IOMMU all command. */
992typedef CMD_INV_IOMMU_ALL_T const *PCCMD_INV_IOMMU_ALL_T;
993#define IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK UINT64_C(0xf000000000000000)
994#define IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK UINT64_C(0x0000000000000000)
995
996/**
997 * Event Log Entry: Generic.
998 * In accordance with the AMD spec.
999 */
1000typedef union
1001{
1002 struct
1003 {
1004 uint32_t u32Operand1Lo; /**< Bits 31:0 - Operand 1 (Lo). */
1005 uint32_t u28Operand1Hi : 28; /**< Bits 59:32 - Operand 1 (Hi). */
1006 uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. */
1007 uint32_t u32Operand2Lo; /**< Bits 95:64 - Operand 2 (Lo). */
1008 uint32_t u32Operand2Hi; /**< Bits 127:96 - Operand 2 (Hi). */
1009 } n;
1010 /** The 32-bit unsigned integer view. */
1011 uint32_t au32[4];
1012} EVT_GENERIC_T;
1013AssertCompileSize(EVT_GENERIC_T, 16);
1014/** Number of bits to shift the byte offset of an event entry in the event log
1015 * buffer to get its index. */
1016#define IOMMU_EVT_GENERIC_SHIFT 4
1017/** Pointer to a generic event log entry. */
1018typedef EVT_GENERIC_T *PEVT_GENERIC_T;
1019/** Pointer to a const generic event log entry. */
1020typedef const EVT_GENERIC_T *PCEVT_GENERIC_T;
1021
1022/**
1023 * Hardware event types.
1024 * In accordance with the AMD spec.
1025 */
1026typedef enum HWEVTTYPE
1027{
1028 HWEVTTYPE_RSVD = 0,
1029 HWEVTTYPE_MASTER_ABORT,
1030 HWEVTTYPE_TARGET_ABORT,
1031 HWEVTTYPE_DATA_ERROR
1032} HWEVTTYPE;
1033AssertCompileSize(HWEVTTYPE, 4);
1034
1035/**
1036 * Event Log Entry: ILLEGAL_DEV_TABLE_ENTRY.
1037 * In accordance with the AMD spec.
1038 */
1039typedef union
1040{
1041 struct
1042 {
1043 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
1044 RT_GCC_EXTENSION uint16_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). */
1045 RT_GCC_EXTENSION uint16_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. */
1046 uint16_t u16PasidLo; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). */
1047 RT_GCC_EXTENSION uint16_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). */
1048 RT_GCC_EXTENSION uint16_t u2Rsvd0 : 2; /**< Bits 50:49 - Reserved. */
1049 RT_GCC_EXTENSION uint16_t u1Interrupt : 1; /**< Bit 51 - I: Interrupt. */
1050 RT_GCC_EXTENSION uint16_t u1Rsvd0 : 1; /**< Bit 52 - Reserved. */
1051 RT_GCC_EXTENSION uint16_t u1ReadWrite : 1; /**< Bit 53 - RW: Read/Write. */
1052 RT_GCC_EXTENSION uint16_t u1Rsvd1 : 1; /**< Bit 54 - Reserved. */
1053 RT_GCC_EXTENSION uint16_t u1RsvdNotZero : 1; /**< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). */
1054 RT_GCC_EXTENSION uint16_t u1Translation : 1; /**< Bit 56 - TN: Translation. */
1055 RT_GCC_EXTENSION uint16_t u3Rsvd0 : 3; /**< Bits 59:57 - Reserved. */
1056 RT_GCC_EXTENSION uint16_t u4EvtCode : 4; /**< Bits 63:60 - Event code. */
1057 uint64_t u64Addr; /**< Bits 127:64 - Address: I/O Virtual Address (IOVA). */
1058 } n;
1059 /** The 32-bit unsigned integer view. */
1060 uint32_t au32[4];
1061 /** The 64-bit unsigned integer view. */
1062 uint64_t au64[2];
1063} EVT_ILLEGAL_DTE_T;
1064AssertCompileSize(EVT_ILLEGAL_DTE_T, 16);
1065/** Pointer to an illegal device table entry event. */
1066typedef EVT_ILLEGAL_DTE_T *PEVT_ILLEGAL_DTE_T;
1067/** Pointer to a const illegal device table entry event. */
1068typedef EVT_ILLEGAL_DTE_T const *PCEVT_ILLEGAL_DTE_T;
1069
1070/**
1071 * Event Log Entry: IO_PAGE_FAULT_EVENT.
1072 * In accordance with the AMD spec.
1073 */
1074typedef union
1075{
1076 struct
1077 {
1078 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
1079 RT_GCC_EXTENSION uint16_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). */
1080 RT_GCC_EXTENSION uint16_t u16DomainOrPasidLo; /**< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). */
1081 RT_GCC_EXTENSION uint16_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). */
1082 RT_GCC_EXTENSION uint16_t u1NoExecute : 1; /**< Bit 49 - NX: No Execute. */
1083 RT_GCC_EXTENSION uint16_t u1User : 1; /**< Bit 50 - US: User/Supervisor. */
1084 RT_GCC_EXTENSION uint16_t u1Interrupt : 1; /**< Bit 51 - I: Interrupt. */
1085 RT_GCC_EXTENSION uint16_t u1Present : 1; /**< Bit 52 - PR: Present. */
1086 RT_GCC_EXTENSION uint16_t u1ReadWrite : 1; /**< Bit 53 - RW: Read/Write. */
1087 RT_GCC_EXTENSION uint16_t u1PermDenied : 1; /**< Bit 54 - PE: Permission Indicator. */
1088 RT_GCC_EXTENSION uint16_t u1RsvdNotZero : 1; /**< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). */
1089 RT_GCC_EXTENSION uint16_t u1Translation : 1; /**< Bit 56 - TN: Translation. */
1090 RT_GCC_EXTENSION uint16_t u3Rsvd0 : 3; /**< Bit 59:57 - Reserved. */
1091 RT_GCC_EXTENSION uint16_t u4EvtCode : 4; /**< Bits 63:60 - Event code. */
1092 uint64_t u64Addr; /**< Bits 127:64 - Address: I/O Virtual Address (IOVA). */
1093 } n;
1094 /** The 32-bit unsigned integer view. */
1095 uint32_t au32[4];
1096 /** The 64-bit unsigned integer view. */
1097 uint64_t au64[2];
1098} EVT_IO_PAGE_FAULT_T;
1099AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
1100/** Pointer to an I/O page fault event. */
1101typedef EVT_IO_PAGE_FAULT_T *PEVT_IO_PAGE_FAULT_T;
1102/** Pointer to a const I/O page fault event. */
1103typedef EVT_IO_PAGE_FAULT_T const *PCEVT_IO_PAGE_FAULT_T;
1104
1105
1106/**
1107 * Event Log Entry: DEV_TAB_HARDWARE_ERROR.
1108 * In accordance with the AMD spec.
1109 */
1110typedef union
1111{
1112 struct
1113 {
1114 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
1115 uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */
1116 uint32_t u19Rsvd0 : 19; /**< Bits 50:32 - Reserved. */
1117 uint32_t u1Intr : 1; /**< Bit 51 - I: Interrupt (1=interrupt request, 0=memory request). */
1118 uint32_t u1Rsvd0 : 1; /**< Bit 52 - Reserved. */
1119 uint32_t u1ReadWrite : 1; /**< Bit 53 - RW: Read/Write transaction (only meaninful when I=0 and TR=0). */
1120 uint32_t u2Rsvd0 : 2; /**< Bits 55:54 - Reserved. */
1121 uint32_t u1Translation : 1; /**< Bit 56 - TR: Translation (1=translation, 0=transaction). */
1122 uint32_t u2Type : 2; /**< Bits 58:57 - Type: The type of hardware error. */
1123 uint32_t u1Rsvd1 : 1; /**< Bit 59 - Reserved. */
1124 uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. */
1125 uint64_t u64Addr; /**< Bits 127:64 - Address. */
1126 } n;
1127 /** The 32-bit unsigned integer view. */
1128 uint32_t au32[4];
1129 /** The 64-bit unsigned integer view. */
1130 uint64_t au64[2];
1131} EVT_DEV_TAB_HW_ERROR_T;
1132AssertCompileSize(EVT_DEV_TAB_HW_ERROR_T, 16);
1133/** Pointer to a device table hardware error event. */
1134typedef EVT_DEV_TAB_HW_ERROR_T *PEVT_DEV_TAB_HW_ERROR_T;
1135/** Pointer to a const device table hardware error event. */
1136typedef EVT_DEV_TAB_HW_ERROR_T const *PCEVT_DEV_TAB_HW_ERROR_T;
1137
1138/**
1139 * Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
1140 * In accordance with the AMD spec.
1141 */
1142typedef union
1143{
1144 struct
1145 {
1146 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
1147 uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */
1148 uint32_t u16DomainOrPasidLo : 16; /**< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). */
1149 uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). */
1150 uint32_t u2Rsvd0 : 2; /**< Bits 50:49 - Reserved. */
1151 uint32_t u1Interrupt : 1; /**< Bit 51 - I: Interrupt. */
1152 uint32_t u1Rsvd0 : 1; /**< Bit 52 - Reserved. */
1153 uint32_t u1ReadWrite : 1; /**< Bit 53 - RW: Read/Write. */
1154 uint32_t u2Rsvd1 : 2; /**< Bit 55:54 - Reserved. */
1155 uint32_t u1Translation : 1; /**< Bit 56 - TR: Translation. */
1156 uint32_t u2Type : 2; /**< Bits 58:57 - Type: The type of hardware error. */
1157 uint32_t u1Rsvd1 : 1; /**< Bit 59 - Reserved. */
1158 uint32_t u4EvtCode : 4; /**< Bit 63:60 - Event code. */
1159 /** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
1160 * table 58 mentions Addr[31:4], we just use the full 64-bits. Looks like a
1161 * typo in the figure.See AMD AMD IOMMU spec (3.05-PUB, Jan 2020). */
1162 uint64_t u64Addr; /** Bits 127:64 - Address: SPA of the page table entry. */
1163 } n;
1164 /** The 32-bit unsigned integer view. */
1165 uint32_t au32[4];
1166 /** The 64-bit unsigned integer view. */
1167 uint64_t au64[2];
1168} EVT_PAGE_TAB_HW_ERR_T;
1169AssertCompileSize(EVT_PAGE_TAB_HW_ERR_T, 16);
1170/** Pointer to a page table hardware error event. */
1171typedef EVT_PAGE_TAB_HW_ERR_T *PEVT_PAGE_TAB_HW_ERR_T;
1172/** Pointer to a const page table hardware error event. */
1173typedef EVT_PAGE_TAB_HW_ERR_T const *PCEVT_PAGE_TAB_HW_ERR_T;
1174
1175/**
1176 * Event Log Entry: ILLEGAL_COMMAND_ERROR.
1177 * In accordance with the AMD spec.
1178 */
1179typedef union
1180{
1181 struct
1182 {
1183 uint32_t u32Rsvd0; /**< Bits 31:0 - Reserved. */
1184 uint32_t u28Rsvd0 : 28; /**< Bits 47:32 - Reserved. */
1185 uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. */
1186 uint64_t u64Addr; /**< Bits 127:64 - Address: SPA of the invalid command. */
1187 } n;
1188 /** The 32-bit unsigned integer view. */
1189 uint32_t au32[4];
1190 /** The 64-bit unsigned integer view. */
1191 uint64_t au64[2];
1192} EVT_ILLEGAL_CMD_ERR_T;
1193AssertCompileSize(EVT_ILLEGAL_CMD_ERR_T, 16);
1194/** Pointer to an illegal command error event. */
1195typedef EVT_ILLEGAL_CMD_ERR_T *PEVT_ILLEGAL_CMD_ERR_T;
1196/** Pointer to a const illegal command error event. */
1197typedef EVT_ILLEGAL_CMD_ERR_T const *PCEVT_ILLEGAL_CMD_ERR_T;
1198
1199/**
1200 * Event Log Entry: COMMAND_HARDWARE_ERROR.
1201 * In accordance with the AMD spec.
1202 */
1203typedef union
1204{
1205 struct
1206 {
1207 uint32_t u32Rsvd0; /**< Bits 31:0 - Reserved. */
1208 uint32_t u25Rsvd1 : 25; /**< Bits 56:32 - Reserved. */
1209 uint32_t u2Type : 2; /**< Bits 58:57 - Type: The type of hardware error. */
1210 uint32_t u1Rsvd1 : 1; /**< Bit 59 - Reserved. */
1211 uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. */
1212 uint64_t u64Addr; /**< Bits 128:64 - Address: SPA of the attempted access. */
1213 } n;
1214 /** The 32-bit unsigned integer view. */
1215 uint32_t au32[4];
1216 /** The 64-bit unsigned integer view. */
1217 uint64_t au64[2];
1218} EVT_CMD_HW_ERR_T;
1219AssertCompileSize(EVT_CMD_HW_ERR_T, 16);
1220/** Pointer to a command hardware error event. */
1221typedef EVT_CMD_HW_ERR_T *PEVT_CMD_HW_ERR_T;
1222/** Pointer to a const command hardware error event. */
1223typedef EVT_CMD_HW_ERR_T const *PCEVT_CMD_HW_ERR_T;
1224
1225/**
1226 * Event Log Entry: IOTLB_INV_TIMEOUT.
1227 * In accordance with the AMD spec.
1228 */
1229typedef union
1230{
1231 struct
1232 {
1233 uint16_t u16DevId; /**< Bits 15:0 - Device ID. */
1234 uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved.*/
1235 uint32_t u28Rsvd0 : 28; /**< Bits 59:32 - Reserved. */
1236 uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. */
1237 uint32_t u4Rsvd0 : 4; /**< Bits 67:64 - Reserved. */
1238 uint32_t u28AddrLo : 28; /**< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). */
1239 uint32_t u32AddrHi; /**< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). */
1240 } n;
1241 /** The 32-bit unsigned integer view. */
1242 uint32_t au32[4];
1243} EVT_IOTLB_INV_TIMEOUT_T;
1244AssertCompileSize(EVT_IOTLB_INV_TIMEOUT_T, 16);
1245
1246/**
1247 * Event Log Entry: INVALID_DEVICE_REQUEST.
1248 * In accordance with the AMD spec.
1249 */
1250typedef union
1251{
1252 struct
1253 {
1254 uint32_t u16DevId : 16; /***< Bits 15:0 - Device ID. */
1255 uint32_t u4PasidHi : 4; /***< Bits 19:16 - PASID: Process Address-Space ID (Hi). */
1256 uint32_t u12Rsvd0 : 12; /***< Bits 31:20 - Reserved. */
1257 uint32_t u16PasidLo : 16; /***< Bits 47:32 - PASID: Process Address-Space ID (Lo). */
1258 uint32_t u1GuestOrNested : 1; /***< Bit 48 - GN: Guest (GPA) or Nested (GVA). */
1259 uint32_t u1User : 1; /***< Bit 49 - US: User/Supervisor. */
1260 uint32_t u6Rsvd0 : 6; /***< Bits 55:50 - Reserved. */
1261 uint32_t u1Translation: 1; /***< Bit 56 - TR: Translation. */
1262 uint32_t u3Type: 3; /***< Bits 59:57 - Type: The type of hardware error. */
1263 uint32_t u4EvtCode : 4; /***< Bits 63:60 - Event code. */
1264 uint64_t u64Addr; /***< Bits 127:64 - Address: Translation or access address. */
1265 } n;
1266 /** The 32-bit unsigned integer view. */
1267 uint32_t au32[4];
1268} EVT_INVALID_DEV_REQ_T;
1269AssertCompileSize(EVT_INVALID_DEV_REQ_T, 16);
1270
1271/**
1272 * Event Log Entry: EVENT_COUNTER_ZERO.
1273 * In accordance with the AMD spec.
1274 */
1275typedef union
1276{
1277 struct
1278 {
1279 uint32_t u32Rsvd0; /**< Bits 31:0 - Reserved. */
1280 uint32_t u28Rsvd0 : 28; /**< Bits 59:32 - Reserved. */
1281 uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. */
1282 uint32_t u20CounterNoteHi : 20; /**< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). */
1283 uint32_t u12Rsvd0 : 12; /**< Bits 95:84 - Reserved. */
1284 uint32_t u32CounterNoteLo; /**< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). */
1285 } n;
1286 /** The 32-bit unsigned integer view. */
1287 uint32_t au32[4];
1288} EVT_EVENT_COUNTER_ZERO_T;
1289AssertCompileSize(EVT_EVENT_COUNTER_ZERO_T, 16);
1290
1291/**
1292 * IOMMU Capability Header (PCI).
1293 * In accordance with the AMD spec.
1294 */
1295typedef union
1296{
1297 struct
1298 {
1299 uint32_t u8CapId : 8; /**< Bits 7:0 - CapId: Capability ID. */
1300 uint32_t u8CapPtr : 8; /**< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. */
1301 uint32_t u3CapType : 3; /**< Bits 18:16 - CapType: Capability Type. */
1302 uint32_t u5CapRev : 5; /**< Bits 23:19 - CapRev: Capability revision. */
1303 uint32_t u1IoTlbSup : 1; /**< Bit 24 - IotlbSup: IOTLB Support. */
1304 uint32_t u1HtTunnel : 1; /**< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. */
1305 uint32_t u1NpCache : 1; /**< Bit 26 - NpCache: Not Present table entries are cached. */
1306 uint32_t u1EfrSup : 1; /**< Bit 27 - EFRSup: Extended Feature Register Support. */
1307 uint32_t u1CapExt : 1; /**< Bit 28 - CapExt: Misc. Information Register 1 Support. */
1308 uint32_t u3Rsvd0 : 3; /**< Bits 31:29 - Reserved. */
1309 } n;
1310 /** The 32-bit unsigned integer view. */
1311 uint32_t u32;
1312} IOMMU_CAP_HDR_T;
1313AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1314
1315/**
1316 * IOMMU Base Address (Lo and Hi) Register (PCI).
1317 * In accordance with the AMD spec.
1318 */
1319typedef union
1320{
1321 struct
1322 {
1323 uint32_t u1Enable : 1; /**< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. */
1324 uint32_t u12Rsvd0 : 12; /**< Bits 13:1 - Reserved. */
1325 uint32_t u18BaseAddrLo : 18; /**< Bits 31:14 - Base address (Lo) of the MMIO region. */
1326 uint32_t u32BaseAddrHi; /**< Bits 63:32 - Base address (Hi) of the MMIO region. */
1327 } n;
1328 /** The 32-bit unsigned integer view. */
1329 uint32_t au32[2];
1330 /** The 64-bit unsigned integer view. */
1331 uint64_t u64;
1332} IOMMU_BAR_T;
1333AssertCompileSize(IOMMU_BAR_T, 8);
1334#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1335
1336/**
1337 * IOMMU Range Register (PCI).
1338 * In accordance with the AMD spec.
1339 */
1340typedef union
1341{
1342 struct
1343 {
1344 uint32_t u5HtUnitId : 5; /**< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). */
1345 uint32_t u2Rsvd0 : 2; /**< Bits 6:5 - Reserved. */
1346 uint32_t u1RangeValid : 1; /**< Bit 7 - RngValid: Range Valid. */
1347 uint32_t u8Bus : 8; /**< Bits 15:8 - BusNumber: Bus number of the first and last device. */
1348 uint32_t u8FirstDevice : 8; /**< Bits 23:16 - FirstDevice: Device and function number of the first device. */
1349 uint32_t u8LastDevice: 8; /**< Bits 31:24 - LastDevice: Device and function number of the last device. */
1350 } n;
1351 /** The 32-bit unsigned integer view. */
1352 uint32_t u32;
1353} IOMMU_RANGE_T;
1354AssertCompileSize(IOMMU_RANGE_T, 4);
1355
1356/**
1357 * Device Table Base Address Register (MMIO).
1358 * In accordance with the AMD spec.
1359 */
1360typedef union
1361{
1362 struct
1363 {
1364 RT_GCC_EXTENSION uint64_t u9Size : 9; /**< Bits 8:0 - Size: Size of the device table. */
1365 RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /**< Bits 11:9 - Reserved. */
1366 RT_GCC_EXTENSION uint64_t u40Base : 40; /**< Bits 51:12 - DevTabBase: Device table base address. */
1367 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bits 63:52 - Reserved. */
1368 } n;
1369 /** The 64-bit unsigned integer view. */
1370 uint64_t u64;
1371} DEV_TAB_BAR_T;
1372AssertCompileSize(DEV_TAB_BAR_T, 8);
1373#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff1ff)
1374#define IOMMU_DEV_TAB_SEG_BAR_VALID_MASK UINT64_C(0x000ffffffffff0ff)
1375
1376/**
1377 * Command Buffer Base Address Register (MMIO).
1378 * In accordance with the AMD spec.
1379 */
1380typedef union
1381{
1382 struct
1383 {
1384 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bits 11:0 - Reserved. */
1385 RT_GCC_EXTENSION uint64_t u40Base : 40; /**< Bits 51:12 - ComBase: Command buffer base address. */
1386 RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /**< Bits 55:52 - Reserved. */
1387 RT_GCC_EXTENSION uint64_t u4Len : 4; /**< Bits 59:56 - ComLen: Command buffer length. */
1388 RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /**< Bits 63:60 - Reserved. */
1389 } n;
1390 /** The 64-bit unsigned integer view. */
1391 uint64_t u64;
1392} CMD_BUF_BAR_T;
1393AssertCompileSize(CMD_BUF_BAR_T, 8);
1394#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1395
1396/**
1397 * Event Log Base Address Register (MMIO).
1398 * In accordance with the AMD spec.
1399 */
1400typedef union
1401{
1402 struct
1403 {
1404 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bits 11:0 - Reserved. */
1405 RT_GCC_EXTENSION uint64_t u40Base : 40; /**< Bits 51:12 - EventBase: Event log base address. */
1406 RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /**< Bits 55:52 - Reserved. */
1407 RT_GCC_EXTENSION uint64_t u4Len : 4; /**< Bits 59:56 - EventLen: Event log length. */
1408 RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /**< Bits 63:60 - Reserved. */
1409 } n;
1410 /** The 64-bit unsigned integer view. */
1411 uint64_t u64;
1412} EVT_LOG_BAR_T;
1413AssertCompileSize(EVT_LOG_BAR_T, 8);
1414#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1415
1416/**
1417 * IOMMU Control Register (MMIO).
1418 * In accordance with the AMD spec.
1419 */
1420typedef union
1421{
1422 struct
1423 {
1424 uint32_t u1IommuEn : 1; /**< Bit 0 - IommuEn: IOMMU Enable. */
1425 uint32_t u1HtTunEn : 1; /**< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. */
1426 uint32_t u1EvtLogEn : 1; /**< Bit 2 - EventLogEn: Event Log Enable. */
1427 uint32_t u1EvtIntrEn : 1; /**< Bit 3 - EventIntEn: Event Log Interrupt Enable. */
1428 uint32_t u1CompWaitIntrEn : 1; /**< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. */
1429 uint32_t u3InvTimeOut : 3; /**< Bits 7:5 - InvTimeOut: Invalidation Timeout. */
1430 uint32_t u1PassPW : 1; /**< Bit 8 - PassPW: Pass Posted Write. */
1431 uint32_t u1ResPassPW : 1; /**< Bit 9 - ResPassPW: Response Pass Posted Write. */
1432 uint32_t u1Coherent : 1; /**< Bit 10 - Coherent: HT read request packet Coherent bit. */
1433 uint32_t u1Isoc : 1; /**< Bit 11 - Isoc: HT read request packet Isochronous bit. */
1434 uint32_t u1CmdBufEn : 1; /**< Bit 12 - CmdBufEn: Command Buffer Enable. */
1435 uint32_t u1PprLogEn : 1; /**< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. */
1436 uint32_t u1PprIntrEn : 1; /**< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. */
1437 uint32_t u1PprEn : 1; /**< Bit 15 - PprEn: Peripheral Page Request processing Enable. */
1438 uint32_t u1GstTranslateEn : 1; /**< Bit 16 - GTEn: Guest Translate Enable. */
1439 uint32_t u1GstVirtApicEn : 1; /**< Bit 17 - GAEn: Guest Virtual-APIC Enable. */
1440 uint32_t u4Crw : 1; /**< Bits 21:18 - CRW: Intended for future use (not documented). */
1441 uint32_t u1SmiFilterEn : 1; /**< Bit 22 - SmiFEn: SMI Filter Enable. */
1442 uint32_t u1SelfWriteBackDis : 1; /**< Bit 23 - SlfWBDis: Self Write-Back Disable. */
1443 uint32_t u1SmiFilterLogEn : 1; /**< Bit 24 - SmiFLogEn: SMI Filter Log Enable. */
1444 uint32_t u3GstVirtApicModeEn : 3; /**< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. */
1445 uint32_t u1GstLogEn : 1; /**< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. */
1446 uint32_t u1GstIntrEn : 1; /**< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. */
1447 uint32_t u2DualPprLogEn : 2; /**< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. */
1448 uint32_t u2DualEvtLogEn : 2; /**< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. */
1449 uint32_t u3DevTabSegEn : 3; /**< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. */
1450 uint32_t u2PrivAbortEn : 2; /**< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. */
1451 uint32_t u1PprAutoRespEn : 1; /**< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. */
1452 uint32_t u1MarcEn : 1; /**< Bit 40 - MarcEn: Memory Address Routing and Control Enable. */
1453 uint32_t u1BlockStopMarkEn : 1; /**< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. */
1454 uint32_t u1PprAutoRespAlwaysOnEn : 1; /**< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. */
1455 uint32_t u1DomainIDPNE : 1; /**< Bit 43 - DomainIDPE: Reserved (not documented). */
1456 uint32_t u1Rsvd0 : 1; /**< Bit 44 - Reserved. */
1457 uint32_t u1EnhancedPpr : 1; /**< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. */
1458 uint32_t u2HstAccDirtyBitUpdate : 2; /**< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. */
1459 uint32_t u1GstDirtyUpdateDis : 1; /**< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. */
1460 uint32_t u1Rsvd1 : 1; /**< Bit 49 - Reserved. */
1461 uint32_t u1X2ApicEn : 1; /**< Bit 50 - XTEn: Enable X2APIC. */
1462 uint32_t u1X2ApicIntrGenEn : 1; /**< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. */
1463 uint32_t u2Rsvd0 : 2; /**< Bits 53:52 - Reserved. */
1464 uint32_t u1GstAccessUpdateDis : 1; /**< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. */
1465 uint32_t u8Rsvd0 : 8; /**< Bits 63:55 - Reserved. */
1466 } n;
1467 /** The 64-bit unsigned integer view. */
1468 uint64_t u64;
1469} IOMMU_CTRL_T;
1470AssertCompileSize(IOMMU_CTRL_T, 8);
1471#define IOMMU_CTRL_VALID_MASK UINT64_C(0x004defffffffffff)
1472#define IOMMU_CTRL_CMD_BUF_EN_MASK UINT64_C(0x0000000000001001)
1473
1474/**
1475 * IOMMU Exclusion Base Register (MMIO).
1476 * In accordance with the AMD spec.
1477 */
1478typedef union
1479{
1480 struct
1481 {
1482 RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /**< Bit 0 - ExEn: Exclusion Range Enable. */
1483 RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /**< Bit 1 - Allow: Allow All Devices. */
1484 RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /**< Bits 11:2 - Reserved. */
1485 RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /**< Bits 51:12 - Exclusion Range Base Address. */
1486 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bits 63:52 - Reserved. */
1487 } n;
1488 /** The 64-bit unsigned integer view. */
1489 uint64_t u64;
1490} IOMMU_EXCL_RANGE_BAR_T;
1491AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1492#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1493
1494/**
1495 * IOMMU Exclusion Range Limit Register (MMIO).
1496 * In accordance with the AMD spec.
1497 */
1498typedef union
1499{
1500 struct
1501 {
1502 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bits 63:52 - Reserved. */
1503 RT_GCC_EXTENSION uint64_t u40ExclRangeLimit : 40; /**< Bits 51:12 - Exclusion Range Limit Address. */
1504 RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /**< Bits 63:52 - Reserved (treated as 1s). */
1505 } n;
1506 /** The 64-bit unsigned integer view. */
1507 uint64_t u64;
1508} IOMMU_EXCL_RANGE_LIMIT_T;
1509AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1510#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000fffffffffffff)
1511
1512/**
1513 * IOMMU Extended Feature Register (MMIO).
1514 * In accordance with the AMD spec.
1515 */
1516typedef union
1517{
1518 struct
1519 {
1520 uint32_t u1PrefetchSup : 1; /**< Bit 0 - PreFSup: Prefetch Support. */
1521 uint32_t u1PprSup : 1; /**< Bit 1 - PPRSup: Peripheral Page Request Support. */
1522 uint32_t u1X2ApicSup : 1; /**< Bit 2 - XTSup: x2Apic Support. */
1523 uint32_t u1NoExecuteSup : 1; /**< Bit 3 - NXSup: No-Execute and Privilege Level Support. */
1524 uint32_t u1GstTranslateSup : 1; /**< Bit 4 - GTSup: Guest Translations (for GVAs) Support. */
1525 uint32_t u1Rsvd0 : 1; /**< Bit 5 - Reserved. */
1526 uint32_t u1InvAllSup : 1; /**< Bit 6 - IASup: Invalidate-All Support. */
1527 uint32_t u1GstVirtApicSup : 1; /**< Bit 7 - GASup: Guest Virtual-APIC Support. */
1528 uint32_t u1HwErrorSup : 1; /**< Bit 8 - HESup: Hardware Error registers Support. */
1529 uint32_t u1PerfCounterSup : 1; /**< Bit 9 - PCSup: Performance Counter Support. */
1530 uint32_t u2HostAddrTranslateSize : 2; /**< Bits 11:10 - HATS: Host Address Translation Size. */
1531 uint32_t u2GstAddrTranslateSize : 2; /**< Bits 13:12 - GATS: Guest Address Translation Size. */
1532 uint32_t u2GstCr3RootTblLevel : 2; /**< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. */
1533 uint32_t u2SmiFilterSup : 2; /**< Bits 17:16 - SmiFSup: SMI Filter Register Support. */
1534 uint32_t u3SmiFilterCount : 3; /**< Bits 20:18 - SmiFRC: SMI Filter Register Count. */
1535 uint32_t u3GstVirtApicModeSup : 3; /**< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. */
1536 uint32_t u2DualPprLogSup : 2; /**< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. */
1537 uint32_t u2Rsvd0 : 2; /**< Bits 27:26 - Reserved. */
1538 uint32_t u2DualEvtLogSup : 2; /**< Bits 29:28 - DualEventLogSup: Dual Event Log Support. */
1539 uint32_t u2Rsvd1 : 2; /**< Bits 31:30 - Reserved. */
1540 uint32_t u5MaxPasidSup : 5; /**< Bits 36:32 - PASMax: Maximum PASID Supported. */
1541 uint32_t u1UserSupervisorSup : 1; /**< Bit 37 - USSup: User/Supervisor Page Protection Support. */
1542 uint32_t u2DevTabSegSup : 2; /**< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. */
1543 uint32_t u1PprLogOverflowWarn : 1; /**< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. */
1544 uint32_t u1PprAutoRespSup : 1; /**< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. */
1545 uint32_t u2MarcSup : 2; /**< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. */
1546 uint32_t u1BlockStopMarkSup : 1; /**< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. */
1547 uint32_t u1PerfOptSup : 1; /**< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. */
1548 uint32_t u1MsiCapMmioSup : 1; /**< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. */
1549 uint32_t u1Rsvd1 : 1; /**< Bit 47 - Reserved. */
1550 uint32_t u1GstIoSup : 1; /**< Bit 48 - GIoSup: Guest I/O Protection Support. */
1551 uint32_t u1HostAccessSup : 1; /**< Bit 49 - HASup: Host Access Support. */
1552 uint32_t u1EnhancedPprSup : 1; /**< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. */
1553 uint32_t u1AttrForwardSup : 1; /**< Bit 51 - AttrFWSup: Attribute Forward Support. */
1554 uint32_t u1HostDirtySup : 1; /**< Bit 52 - HDSup: Host Dirty Support. */
1555 uint32_t u1Rsvd2 : 1; /**< Bit 53 - Reserved. */
1556 uint32_t u1InvIoTlbTypeSup : 1; /**< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. */
1557 uint32_t u6Rsvd0 : 6; /**< Bit 60:55 - Reserved. */
1558 uint32_t u1GstUpdateDisSup : 1; /**< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. */
1559 uint32_t u1ForcePhysDstSup : 1; /**< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. */
1560 uint32_t u1Rsvd3 : 1; /**< Bit 63 - Reserved. */
1561 } n;
1562 /** The 64-bit unsigned integer view. */
1563 uint64_t u64;
1564} IOMMU_EXT_FEAT_T;
1565AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1566
1567/**
1568 * Peripheral Page Request Log Base Address Register (MMIO).
1569 * In accordance with the AMD spec.
1570 */
1571typedef union
1572{
1573 struct
1574 {
1575 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bit 11:0 - Reserved. */
1576 RT_GCC_EXTENSION uint64_t u40Base : 40; /**< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. */
1577 RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /**< Bits 55:52 - Reserved. */
1578 RT_GCC_EXTENSION uint64_t u4Len : 4; /**< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. */
1579 RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /**< Bits 63:60 - Reserved. */
1580 } n;
1581 /** The 64-bit unsigned integer view. */
1582 uint64_t u64;
1583} PPR_LOG_BAR_T;
1584AssertCompileSize(PPR_LOG_BAR_T, 8);
1585#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1586
1587/**
1588 * IOMMU Hardware Event Upper Register (MMIO).
1589 * In accordance with the AMD spec.
1590 */
1591typedef union
1592{
1593 struct
1594 {
1595 RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /**< Bits 59:0 - First event code dependent operand. */
1596 RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /**< Bits 63:60 - Event Code. */
1597 } n;
1598 /** The 64-bit unsigned integer view. */
1599 uint64_t u64;
1600} IOMMU_HW_EVT_HI_T;
1601AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1602
1603/**
1604 * IOMMU Hardware Event Lower Register (MMIO).
1605 * In accordance with the AMD spec.
1606 */
1607typedef uint64_t IOMMU_HW_EVT_LO_T;
1608
1609/**
1610 * IOMMU Hardware Event Status (MMIO).
1611 * In accordance with the AMD spec.
1612 */
1613typedef union
1614{
1615 struct
1616 {
1617 uint32_t u1Valid : 1; /**< Bit 0 - HEV: Hardware Event Valid. */
1618 uint32_t u1Overflow : 1; /**< Bit 1 - HEO: Hardware Event Overflow. */
1619 uint32_t u30Rsvd0 : 30; /**< Bits 31:2 - Reserved. */
1620 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved. */
1621 } n;
1622 /** The 64-bit unsigned integer view. */
1623 uint64_t u64;
1624} IOMMU_HW_EVT_STATUS_T;
1625AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1626#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1627
1628/**
1629 * Guest Virtual-APIC Log Base Address Register (MMIO).
1630 * In accordance with the AMD spec.
1631 */
1632typedef union
1633{
1634 struct
1635 {
1636 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bit 11:0 - Reserved. */
1637 RT_GCC_EXTENSION uint64_t u40Base : 40; /**< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. */
1638 RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /**< Bits 55:52 - Reserved. */
1639 RT_GCC_EXTENSION uint64_t u4Len : 4; /**< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. */
1640 RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /**< Bits 63:60 - Reserved. */
1641 } n;
1642 /** The 64-bit unsigned integer view. */
1643 uint64_t u64;
1644} GALOG_BAR_T;
1645AssertCompileSize(GALOG_BAR_T, 8);
1646
1647/**
1648 * Guest Virtual-APIC Log Tail Address Register (MMIO).
1649 * In accordance with the AMD spec.
1650 */
1651typedef union
1652{
1653 struct
1654 {
1655 RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /**< Bits 2:0 - Reserved. */
1656 RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /**< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. */
1657 RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /**< Bits 63:52 - Reserved. */
1658 } n;
1659 /** The 64-bit unsigned integer view. */
1660 uint64_t u64;
1661} GALOG_TAIL_ADDR_T;
1662AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1663
1664/**
1665 * PPR Log B Base Address Register (MMIO).
1666 * In accordance with the AMD spec.
1667 * Currently identical to PPR_LOG_BAR_T.
1668 */
1669typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1670
1671/**
1672 * Event Log B Base Address Register (MMIO).
1673 * In accordance with the AMD spec.
1674 * Currently identical to EVT_LOG_BAR_T.
1675 */
1676typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1677
1678/**
1679 * Device-specific Feature Extension (DSFX) Register (MMIO).
1680 * In accordance with the AMD spec.
1681 */
1682typedef union
1683{
1684 struct
1685 {
1686 uint32_t u24DevSpecFeat : 24; /**< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. */
1687 uint32_t u4RevMinor : 4; /**< Bits 27:24 - RevMinor: Minor revision identifier. */
1688 uint32_t u4RevMajor : 4; /**< Bits 31:28 - RevMajor: Major revision identifier. */
1689 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved.*/
1690 } n;
1691 /** The 64-bit unsigned integer view. */
1692 uint64_t u64;
1693} DEV_SPECIFIC_FEAT_T;
1694AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1695
1696/**
1697 * Device-specific Control Extension (DSCX) Register (MMIO).
1698 * In accordance with the AMD spec.
1699 */
1700typedef union
1701{
1702 struct
1703 {
1704 uint32_t u24DevSpecCtrl : 24; /**< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. */
1705 uint32_t u4RevMinor : 4; /**< Bits 27:24 - RevMinor: Minor revision identifier. */
1706 uint32_t u4RevMajor : 4; /**< Bits 31:28 - RevMajor: Major revision identifier. */
1707 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved.*/
1708 } n;
1709 /** The 64-bit unsigned integer view. */
1710 uint64_t u64;
1711} DEV_SPECIFIC_CTRL_T;
1712AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1713
1714/**
1715 * Device-specific Status Extension (DSSX) Register (MMIO).
1716 * In accordance with the AMD spec.
1717 */
1718typedef union
1719{
1720 struct
1721 {
1722 uint32_t u24DevSpecStatus : 24; /**< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. */
1723 uint32_t u4RevMinor : 4; /**< Bits 27:24 - RevMinor: Minor revision identifier. */
1724 uint32_t u4RevMajor : 4; /**< Bits 31:28 - RevMajor: Major revision identifier. */
1725 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved.*/
1726 } n;
1727 /** The 64-bit unsigned integer view. */
1728 uint64_t u64;
1729} DEV_SPECIFIC_STATUS_T;
1730AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1731
1732/**
1733 * MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1734 * In accordance with the AMD spec.
1735 */
1736typedef union
1737{
1738 struct
1739 {
1740 uint32_t u5MsiNumEvtLog : 5; /**< Bits 4:0 - MsiNum: Event Log MSI message number. */
1741 uint32_t u3GstVirtAddrSize: 3; /**< Bits 7:5 - GVAsize: Guest Virtual Address Size. */
1742 uint32_t u7PhysAddrSize : 7; /**< Bits 14:8 - PAsize: Physical Address Size. */
1743 uint32_t u7VirtAddrSize : 7; /**< Bits 21:15 - VAsize: Virtual Address Size. */
1744 uint32_t u1HtAtsResv: 1; /**< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. */
1745 uint32_t u4Rsvd0 : 4; /**< Bits 26:23 - Reserved. */
1746 uint32_t u5MsiNumPpr : 5; /**< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. */
1747 uint32_t u5MsiNumGa : 5; /**< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. */
1748 uint32_t u27Rsvd0: 27; /**< Bits 63:37 - Reserved. */
1749 } n;
1750 /** The 32-bit unsigned integer view. */
1751 uint32_t au32[2];
1752 /** The 64-bit unsigned integer view. */
1753 uint64_t u64;
1754} MSI_MISC_INFO_T;
1755AssertCompileSize(MSI_MISC_INFO_T, 8);
1756/** MSI Vector Register 0 and 1 (MMIO). */
1757typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1758/** Mask of valid bits in MSI Vector Register 1 (or high dword of MSI Misc.
1759 * info). */
1760#define IOMMU_MSI_VECTOR_1_VALID_MASK UINT32_C(0x1f)
1761
1762/**
1763 * MSI Capability Header Register (PCI + MMIO).
1764 * In accordance with the AMD spec.
1765 */
1766typedef union
1767{
1768 struct
1769 {
1770 uint32_t u8MsiCapId : 8; /**< Bits 7:0 - MsiCapId: Capability ID. */
1771 uint32_t u8MsiCapPtr : 8; /**< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. */
1772 uint32_t u1MsiEnable : 1; /**< Bit 16 - MsiEn: Message Signal Interrupt Enable. */
1773 uint32_t u3MsiMultiMessCap : 3; /**< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. */
1774 uint32_t u3MsiMultiMessEn : 3; /**< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. */
1775 uint32_t u1Msi64BitEn : 1; /**< Bit 23 - Msi64BitEn: MSI 64-bit Enable. */
1776 uint32_t u8Rsvd0 : 8; /**< Bits 31:24 - Reserved. */
1777 } n;
1778 /** The 32-bit unsigned integer view. */
1779 uint32_t u32;
1780} MSI_CAP_HDR_T;
1781AssertCompileSize(MSI_CAP_HDR_T, 4);
1782#define IOMMU_MSI_CAP_HDR_MSI_EN_MASK RT_BIT(16)
1783
1784/**
1785 * MSI Mapping Capability Header Register (PCI + MMIO).
1786 * In accordance with the AMD spec.
1787 */
1788typedef union
1789{
1790 struct
1791 {
1792 uint32_t u8MsiMapCapId : 8; /**< Bits 7:0 - MsiMapCapId: MSI Map capability ID. */
1793 uint32_t u8Rsvd0 : 8; /**< Bits 15:8 - Reserved. */
1794 uint32_t u1MsiMapEn : 1; /**< Bit 16 - MsiMapEn: MSI Map enable. */
1795 uint32_t u1MsiMapFixed : 1; /**< Bit 17 - MsiMapFixd: MSI Map fixed. */
1796 uint32_t u9Rsvd0 : 9; /**< Bits 26:18 - Reserved. */
1797 uint32_t u5MapCapType : 5; /**< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. */
1798 } n;
1799 /** The 32-bit unsigned integer view. */
1800 uint32_t u32;
1801} MSI_MAP_CAP_HDR_T;
1802AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1803
1804/**
1805 * Performance Optimization Control Register (MMIO).
1806 * In accordance with the AMD spec.
1807 */
1808typedef union
1809{
1810 struct
1811 {
1812 uint32_t u13Rsvd0 : 13; /**< Bits 12:0 - Reserved. */
1813 uint32_t u1PerfOptEn : 1; /**< Bit 13 - PerfOptEn: Performance Optimization Enable. */
1814 uint32_t u17Rsvd0 : 18; /**< Bits 31:14 - Reserved. */
1815 } n;
1816 /** The 32-bit unsigned integer view. */
1817 uint32_t u32;
1818} IOMMU_PERF_OPT_CTRL_T;
1819AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1820
1821/**
1822 * XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1823 * In accordance with the AMD spec.
1824 */
1825typedef union
1826{
1827 struct
1828 {
1829 uint32_t u2Rsvd0 : 2; /**< Bits 1:0 - Reserved.*/
1830 uint32_t u1X2ApicIntrDstMode : 1; /**< Bit 2 - Destination Mode for general interrupt.*/
1831 uint32_t u4Rsvd0 : 4; /**< Bits 7:3 - Reserved.*/
1832 uint32_t u24X2ApicIntrDstLo : 24; /**< Bits 31:8 - Destination for general interrupt (Lo).*/
1833 uint32_t u8X2ApicIntrVector : 8; /**< Bits 39:32 - Vector for general interrupt.*/
1834 uint32_t u1X2ApicIntrDeliveryMode : 1; /**< Bit 40 - Delivery Mode for general interrupt.*/
1835 uint32_t u15Rsvd0 : 15; /**< Bits 55:41 - Reserved.*/
1836 uint32_t u7X2ApicIntrDstHi : 7; /**< Bits 63:56 - Destination for general interrupt (Hi) .*/
1837 } n;
1838 /** The 64-bit unsigned integer view. */
1839 uint64_t u64;
1840} IOMMU_XT_GEN_INTR_CTRL_T;
1841AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1842
1843/**
1844 * XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1845 * In accordance with the AMD spec.
1846 */
1847typedef union
1848{
1849 struct
1850 {
1851 uint32_t u2Rsvd0 : 2; /**< Bits 1:0 - Reserved.*/
1852 uint32_t u1X2ApicIntrDstMode : 1; /**< Bit 2 - Destination Mode for the interrupt.*/
1853 uint32_t u4Rsvd0 : 4; /**< Bits 7:3 - Reserved.*/
1854 uint32_t u24X2ApicIntrDstLo : 24; /**< Bits 31:8 - Destination for the interrupt (Lo).*/
1855 uint32_t u8X2ApicIntrVector : 8; /**< Bits 39:32 - Vector for the interrupt.*/
1856 uint32_t u1X2ApicIntrDeliveryMode : 1; /**< Bit 40 - Delivery Mode for the interrupt.*/
1857 uint32_t u15Rsvd0 : 15; /**< Bits 55:41 - Reserved.*/
1858 uint32_t u7X2ApicIntrDstHi : 7; /**< Bits 63:56 - Destination for the interrupt (Hi) .*/
1859 } n;
1860 /** The 64-bit unsigned integer view. */
1861 uint64_t u64;
1862} IOMMU_XT_INTR_CTRL_T;
1863AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1864
1865/**
1866 * XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1867 * In accordance with the AMD spec.
1868 * Currently identical to IOMMU_XT_INTR_CTRL_T.
1869 */
1870typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1871
1872/**
1873 * XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1874 * In accordance with the AMD spec.
1875 * Currently identical to IOMMU_XT_INTR_CTRL_T.
1876 */
1877typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1878
1879/**
1880 * Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1881 * In accordance with the AMD spec.
1882 */
1883typedef union
1884{
1885 struct
1886 {
1887 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bits 11:0 - Reserved. */
1888 RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /**< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. */
1889 RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /**< Bits 63:52 - Reserved. */
1890 } n;
1891 /** The 64-bit unsigned integer view. */
1892 uint64_t u64;
1893} MARC_APER_BAR_T;
1894AssertCompileSize(MARC_APER_BAR_T, 8);
1895
1896/**
1897 * Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1898 * In accordance with the AMD spec.
1899 */
1900typedef union
1901{
1902 struct
1903 {
1904 RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /**< Bit 0 - RelocEn: Relocation Enabled. */
1905 RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /**< Bit 1 - ReadOnly: Whether only read-only acceses allowed. */
1906 RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /**< Bits 11:2 - Reserved. */
1907 RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /**< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. */
1908 RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /**< Bits 63:52 - Reserved. */
1909 } n;
1910 /** The 64-bit unsigned integer view. */
1911 uint64_t u64;
1912} MARC_APER_RELOC_T;
1913AssertCompileSize(MARC_APER_RELOC_T, 8);
1914
1915/**
1916 * Memory Access and Routing Control (MARC) Length Register (MMIO).
1917 * In accordance with the AMD spec.
1918 */
1919typedef union
1920{
1921 struct
1922 {
1923 RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /**< Bits 11:0 - Reserved. */
1924 RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /**< Bits 51:12 - MarcLength: MARC Aperture Length. */
1925 RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /**< Bits 63:52 - Reserved. */
1926 } n;
1927 /** The 64-bit unsigned integer view. */
1928 uint64_t u64;
1929} MARC_APER_LEN_T;
1930
1931/**
1932 * Memory Access and Routing Control (MARC) Aperture Register.
1933 * This combines other registers to match the MMIO layout for convenient access.
1934 */
1935typedef struct
1936{
1937 MARC_APER_BAR_T Base;
1938 MARC_APER_RELOC_T Reloc;
1939 MARC_APER_LEN_T Length;
1940} MARC_APER_T;
1941AssertCompileSize(MARC_APER_T, 24);
1942
1943/**
1944 * IOMMU Reserved Register (MMIO).
1945 * In accordance with the AMD spec.
1946 * This register is reserved for hardware use (although RW?).
1947 */
1948typedef uint64_t IOMMU_RSVD_REG_T;
1949
1950/**
1951 * Command Buffer Head Pointer Register (MMIO).
1952 * In accordance with the AMD spec.
1953 */
1954typedef union
1955{
1956 struct
1957 {
1958 uint32_t off; /**< Bits 31:0 - Buffer pointer (offset; 16 byte aligned, 512 KB max). */
1959 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved. */
1960 } n;
1961 /** The 32-bit unsigned integer view. */
1962 uint32_t au32[2];
1963 /** The 64-bit unsigned integer view. */
1964 uint64_t u64;
1965} CMD_BUF_HEAD_PTR_T;
1966AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1967#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1968
1969/**
1970 * Command Buffer Tail Pointer Register (MMIO).
1971 * In accordance with the AMD spec.
1972 * Currently identical to CMD_BUF_HEAD_PTR_T.
1973 */
1974typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1975#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1976
1977/**
1978 * Event Log Head Pointer Register (MMIO).
1979 * In accordance with the AMD spec.
1980 * Currently identical to CMD_BUF_HEAD_PTR_T.
1981 */
1982typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
1983#define IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1984
1985/**
1986 * Event Log Tail Pointer Register (MMIO).
1987 * In accordance with the AMD spec.
1988 * Currently identical to CMD_BUF_HEAD_PTR_T.
1989 */
1990typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
1991#define IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1992
1993
1994/**
1995 * IOMMU Status Register (MMIO).
1996 * In accordance with the AMD spec.
1997 */
1998typedef union
1999{
2000 struct
2001 {
2002 uint32_t u1EvtOverflow : 1; /**< Bit 0 - EventOverflow: Event log overflow. */
2003 uint32_t u1EvtLogIntr : 1; /**< Bit 1 - EventLogInt: Event log interrupt. */
2004 uint32_t u1CompWaitIntr : 1; /**< Bit 2 - ComWaitInt: Completion wait interrupt . */
2005 uint32_t u1EvtLogRunning : 1; /**< Bit 3 - EventLogRun: Event logging is running. */
2006 uint32_t u1CmdBufRunning : 1; /**< Bit 4 - CmdBufRun: Command buffer is running. */
2007 uint32_t u1PprOverflow : 1; /**< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. */
2008 uint32_t u1PprIntr : 1; /**< Bit 6 - PprInt: PPR interrupt. */
2009 uint32_t u1PprLogRunning : 1; /**< Bit 7 - PprLogRun: PPR logging is running. */
2010 uint32_t u1GstLogRunning : 1; /**< Bit 8 - GALogRun: Guest virtual-APIC logging is running. */
2011 uint32_t u1GstLogOverflow : 1; /**< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. */
2012 uint32_t u1GstLogIntr : 1; /**< Bit 10 - GAInt: Guest virtual-APIC log interrupt. */
2013 uint32_t u1PprOverflowB : 1; /**< Bit 11 - PprOverflowB: PPR log B overflow. */
2014 uint32_t u1PprLogActive : 1; /**< Bit 12 - PprLogActive: PPR log A is active. */
2015 uint32_t u2Rsvd0 : 2; /**< Bits 14:13 - Reserved. */
2016 uint32_t u1EvtOverflowB : 1; /**< Bit 15 - EvtOverflowB: Event log B overflow. */
2017 uint32_t u1EvtLogActive : 1; /**< Bit 16 - EvtLogActive: Event log A active. */
2018 uint32_t u1PprOverflowEarlyB : 1; /**< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. */
2019 uint32_t u1PprOverflowEarly : 1; /**< Bit 18 - PprOverflowEarly: PPR log overflow early warning. */
2020 uint32_t u13Rsvd0 : 13; /**< Bits 31:19 - Reserved. */
2021 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved . */
2022 } n;
2023 /** The 32-bit unsigned integer view. */
2024 uint32_t au32[2];
2025 /** The 64-bit unsigned integer view. */
2026 uint64_t u64;
2027} IOMMU_STATUS_T;
2028AssertCompileSize(IOMMU_STATUS_T, 8);
2029#define IOMMU_STATUS_VALID_MASK UINT64_C(0x0000000000079fff)
2030#define IOMMU_STATUS_RW1C_MASK UINT64_C(0x0000000000068e67)
2031
2032/**
2033 * PPR Log Head Pointer Register (MMIO).
2034 * In accordance with the AMD spec.
2035 * Currently identical to CMD_BUF_HEAD_PTR_T.
2036 */
2037typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
2038
2039/**
2040 * PPR Log Tail Pointer Register (MMIO).
2041 * In accordance with the AMD spec.
2042 * Currently identical to CMD_BUF_HEAD_PTR_T.
2043 */
2044typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
2045
2046/**
2047 * Guest Virtual-APIC Log Head Pointer Register (MMIO).
2048 * In accordance with the AMD spec.
2049 */
2050typedef union
2051{
2052 struct
2053 {
2054 uint32_t u2Rsvd0 : 2; /**< Bits 2:0 - Reserved. */
2055 uint32_t u12GALogPtr : 12; /**< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. */
2056 uint32_t u16Rsvd0 : 16; /**< Bits 31:16 - Reserved. */
2057 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved. */
2058 } n;
2059 /** The 32-bit unsigned integer view. */
2060 uint32_t au32[2];
2061 /** The 64-bit unsigned integer view. */
2062 uint64_t u64;
2063} GALOG_HEAD_PTR_T;
2064AssertCompileSize(GALOG_HEAD_PTR_T, 8);
2065
2066/**
2067 * Guest Virtual-APIC Log Tail Pointer Register (MMIO).
2068 * In accordance with the AMD spec.
2069 * Currently identical to GALOG_HEAD_PTR_T.
2070 */
2071typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
2072
2073/**
2074 * PPR Log B Head Pointer Register (MMIO).
2075 * In accordance with the AMD spec.
2076 * Currently identical to CMD_BUF_HEAD_PTR_T.
2077 */
2078typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
2079
2080/**
2081 * PPR Log B Tail Pointer Register (MMIO).
2082 * In accordance with the AMD spec.
2083 * Currently identical to CMD_BUF_HEAD_PTR_T.
2084 */
2085typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
2086
2087/**
2088 * Event Log B Head Pointer Register (MMIO).
2089 * In accordance with the AMD spec.
2090 * Currently identical to CMD_BUF_HEAD_PTR_T.
2091 */
2092typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
2093
2094/**
2095 * Event Log B Tail Pointer Register (MMIO).
2096 * In accordance with the AMD spec.
2097 * Currently identical to CMD_BUF_HEAD_PTR_T.
2098 */
2099typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
2100
2101/**
2102 * PPR Log Auto Response Register (MMIO).
2103 * In accordance with the AMD spec.
2104 */
2105typedef union
2106{
2107 struct
2108 {
2109 uint32_t u4AutoRespCode : 4; /**< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. */
2110 uint32_t u1AutoRespMaskGen : 1; /**< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. */
2111 uint32_t u27Rsvd0 : 27; /**< Bits 31:5 - Reserved. */
2112 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved.*/
2113 } n;
2114 /** The 32-bit unsigned integer view. */
2115 uint32_t au32[2];
2116 /** The 64-bit unsigned integer view. */
2117 uint64_t u64;
2118} PPR_LOG_AUTO_RESP_T;
2119AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
2120
2121/**
2122 * PPR Log Overflow Early Indicator Register (MMIO).
2123 * In accordance with the AMD spec.
2124 */
2125typedef union
2126{
2127 struct
2128 {
2129 uint32_t u15Threshold : 15; /**< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. */
2130 uint32_t u15Rsvd0 : 15; /**< Bits 29:15 - Reserved. */
2131 uint32_t u1IntrEn : 1; /**< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. */
2132 uint32_t u1Enable : 1; /**< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. */
2133 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved. */
2134 } n;
2135 /** The 32-bit unsigned integer view. */
2136 uint32_t au32[2];
2137 /** The 64-bit unsigned integer view. */
2138 uint64_t u64;
2139} PPR_LOG_OVERFLOW_EARLY_T;
2140AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
2141
2142/**
2143 * PPR Log B Overflow Early Indicator Register (MMIO).
2144 * In accordance with the AMD spec.
2145 * Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
2146 */
2147typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
2148
2149/**
2150 * ILLEGAL_DEV_TABLE_ENTRY Event Types.
2151 * In accordance with the AMD spec.
2152 */
2153typedef enum EVT_ILLEGAL_DTE_TYPE_T
2154{
2155 kIllegalDteType_RsvdNotZero = 0,
2156 kIllegalDteType_RsvdIntTabLen,
2157 kIllegalDteType_RsvdIoCtl,
2158 kIllegalDteType_RsvdIntCtl
2159} EVT_ILLEGAL_DTE_TYPE_T;
2160
2161/**
2162 * ILLEGAL_DEV_TABLE_ENTRY Event Types.
2163 * In accordance with the AMD spec.
2164 */
2165typedef enum EVT_IO_PAGE_FAULT_TYPE_T
2166{
2167 /* Memory transaction. */
2168 kIoPageFaultType_DteRsvdPagingMode = 0,
2169 kIoPageFaultType_PteInvalidPageSize,
2170 kIoPageFaultType_PteInvalidLvlEncoding,
2171 kIoPageFaultType_SkippedLevelIovaNotZero,
2172 kIoPageFaultType_PteRsvdNotZero,
2173 kIoPageFaultType_PteValidNotSet,
2174 kIoPageFaultType_DteTranslationDisabled,
2175 kIoPageFaultType_PasidInvalidRange,
2176 kIoPageFaultType_PermDenied,
2177 kIoPageFaultType_UserSupervisor,
2178 /* Interrupt remapping */
2179 kIoPageFaultType_IrteAddrInvalid,
2180 kIoPageFaultType_IrteRsvdNotZero,
2181 kIoPageFaultType_IrteRemapEn,
2182 kIoPageFaultType_IrteRsvdIntType,
2183 kIoPageFaultType_IntrReqAborted,
2184 kIoPageFaultType_IntrWithPasid,
2185 kIoPageFaultType_SmiFilterMismatch,
2186 /* Memory transaction or interrupt remapping. */
2187 kIoPageFaultType_DevId_Invalid
2188} EVT_IO_PAGE_FAULT_TYPE_T;
2189
2190/**
2191 * IOTLB_INV_TIMEOUT Event Types.
2192 * In accordance with the AMD spec.
2193 */
2194typedef enum EVT_IOTLB_INV_TIMEOUT_TYPE_T
2195{
2196 InvTimeoutType_NoResponse = 0
2197} EVT_IOTLB_INV_TIMEOUT_TYPE_T;
2198
2199/**
2200 * INVALID_DEVICE_REQUEST Event Types.
2201 * In accordance with the AMD spec.
2202 */
2203typedef enum EVT_INVALID_DEV_REQ_TYPE_T
2204{
2205 /* Access. */
2206 kInvalidDevReqType_ReadOrNonPostedWrite = 0,
2207 kInvalidDevReqType_PretranslatedTransaction,
2208 kInvalidDevReqType_PortIo,
2209 kInvalidDevReqType_SysMgt,
2210 kInvalidDevReqType_IntrRange,
2211 kInvalidDevReqType_RsvdIntrRange,
2212 kInvalidDevReqType_SysMgtAddr,
2213 /* Translation Request. */
2214 kInvalidDevReqType_TrAccessInvalid,
2215 kInvalidDevReqType_TrDisabled,
2216 kInvalidDevReqType_DevIdInvalid
2217} EVT_INVALID_DEV_REQ_TYPE_T;
2218
2219/**
2220 * INVALID_PPR_REQUEST Event Types.
2221 * In accordance with the AMD spec.
2222 */
2223typedef enum EVT_INVALID_PPR_REQ_TYPE_T
2224{
2225 kInvalidPprReqType_PriNotSupported,
2226 kInvalidPprReqType_GstTranslateDisabled
2227} EVT_INVALID_PPR_REQ_TYPE_T;
2228
2229
2230/** @name IVRS format revision field.
2231 * In accordance with the AMD spec.
2232 * @{ */
2233/** Fixed: Supports only pre-assigned device IDs and type 10h and 11h IVHD
2234 * blocks. */
2235#define ACPI_IVRS_FMT_REV_FIXED 0x1
2236/** Mixed: Supports pre-assigned and ACPI HID device naming and all IVHD blocks. */
2237#define ACPI_IVRS_FMT_REV_MIXED 0x2
2238/** @} */
2239
2240/** @name IVHD special device entry variety field.
2241 * In accordance with the AMD spec.
2242 * @{ */
2243/** I/O APIC. */
2244#define ACPI_IVHD_VARIETY_IOAPIC 0x1
2245/** HPET. */
2246#define ACPI_IVHD_VARIETY_HPET 0x2
2247/** @} */
2248
2249/** @name IVHD device entry type codes.
2250 * In accordance with the AMD spec.
2251 * @{ */
2252/** Reserved. */
2253#define ACPI_IVHD_DEVENTRY_TYPE_RSVD 0x0
2254/** All: DTE setting applies to all Device IDs. */
2255#define ACPI_IVHD_DEVENTRY_TYPE_ALL 0x1
2256/** Select: DTE setting applies to the device specified in DevId field. */
2257#define ACPI_IVHD_DEVENTRY_TYPE_SELECT 0x2
2258/** Start of range: DTE setting applies to all devices from start of range specified
2259 * by the DevId field. */
2260#define ACPI_IVHD_DEVENTRY_TYPE_START_RANGE 0x3
2261/** End of range: DTE setting from previous type 3 entry applies to all devices
2262 * incl. DevId specified by this entry. */
2263#define ACPI_IVHD_DEVENTRY_TYPE_END_RANGE 0x4
2264/** @} */
2265
2266/** @name IVHD DTE (Device Table Entry) Settings.
2267 * In accordance with the AMD spec.
2268 * @{ */
2269/** INITPass: Identifies a device able to assert INIT interrupts. */
2270#define ACPI_IVHD_DTE_INIT_PASS_SHIFT 0
2271#define ACPI_IVHD_DTE_INIT_PASS_MASK UINT8_C(0x01)
2272/** EIntPass: Identifies a device able to assert ExtInt interrupts. */
2273#define ACPI_IVHD_DTE_EXTINT_PASS_SHIFT 1
2274#define ACPI_IVHD_DTE_EXTINT_PASS_MASK UINT8_C(0x02)
2275/** NMIPass: Identifies a device able to assert NMI interrupts. */
2276#define ACPI_IVHD_DTE_NMI_PASS_SHIFT 2
2277#define ACPI_IVHD_DTE_NMI_PASS_MASK UINT8_C(0x04)
2278/** Bit 3 reserved. */
2279#define ACPI_IVHD_DTE_RSVD_3_SHIFT 3
2280#define ACPI_IVHD_DTE_RSVD_3_MASK UINT8_C(0x08)
2281/** SysMgt: Identifies a device able to assert system management messages. */
2282#define ACPI_IVHD_DTE_SYS_MGT_SHIFT 4
2283#define ACPI_IVHD_DTE_SYS_MGT_MASK UINT8_C(0x30)
2284/** Lint0Pass: Identifies a device able to assert LINT0 interrupts. */
2285#define ACPI_IVHD_DTE_LINT0_PASS_SHIFT 6
2286#define ACPI_IVHD_DTE_LINT0_PASS_MASK UINT8_C(0x40)
2287/** Lint0Pass: Identifies a device able to assert LINT1 interrupts. */
2288#define ACPI_IVHD_DTE_LINT1_PASS_SHIFT 7
2289#define ACPI_IVHD_DTE_LINT1_PASS_MASK UINT8_C(0x80)
2290RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IVHD_DTE_, UINT8_C(0), UINT8_MAX,
2291 (INIT_PASS, EXTINT_PASS, NMI_PASS, RSVD_3, SYS_MGT, LINT0_PASS, LINT1_PASS));
2292/** @} */
2293
2294/**
2295 * AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Device Entry (4-byte).
2296 * In accordance with the AMD spec.
2297 */
2298#pragma pack(1)
2299typedef struct ACPIIVHDDEVENTRY4
2300{
2301 uint8_t u8DevEntryType; /**< Device entry type. */
2302 uint16_t u16DevId; /**< Device ID. */
2303 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */
2304} ACPIIVHDDEVENTRY4;
2305#pragma pack()
2306AssertCompileSize(ACPIIVHDDEVENTRY4, 4);
2307
2308/**
2309 * AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Device Entry (8-byte).
2310 * In accordance with the AMD spec.
2311 */
2312#pragma pack(1)
2313typedef struct ACPIIVHDDEVENTRY8
2314{
2315 uint8_t u8DevEntryType; /**< Device entry type. */
2316 union
2317 {
2318 /** Reserved: When u8DevEntryType is 0x40, 0x41, 0x44 or 0x45 (or 0x49-0x7F). */
2319 struct
2320 {
2321 uint8_t au8Rsvd0[7]; /**< Reserved (MBZ). */
2322 } rsvd;
2323 /** Alias Select: When u8DevEntryType is 0x42 or 0x43. */
2324 struct
2325 {
2326 uint16_t u16DevIdA; /**< Device ID A. */
2327 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */
2328 uint8_t u8Rsvd0; /**< Reserved (MBZ). */
2329 uint16_t u16DevIdB; /**< Device ID B. */
2330 uint8_t u8Rsvd1; /**< Reserved (MBZ). */
2331 } alias;
2332 /** Extended Select: When u8DevEntryType is 0x46 or 0x47. */
2333 struct
2334 {
2335 uint16_t u16DevId; /**< Device ID. */
2336 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */
2337 uint32_t u32ExtDteSetting; /**< Extended DTE setting. */
2338 } ext;
2339 /** Special Device: When u8DevEntryType is 0x48. */
2340 struct
2341 {
2342 uint16_t u16Rsvd0; /**< Reserved (MBZ). */
2343 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */
2344 uint8_t u8Handle; /**< Handle contains I/O APIC ID or HPET number. */
2345 uint16_t u16DevIdB; /**< Device ID B (I/O APIC or HPET). */
2346 uint8_t u8Variety; /**< Whether this is the HPET or I/O APIC. */
2347 } special;
2348 } u;
2349} ACPIIVHDDEVENTRY8;
2350#pragma pack()
2351AssertCompileSize(ACPIIVHDDEVENTRY8, 8);
2352
2353/** @name IVHD Type 10h Flags.
2354 * In accordance with the AMD spec.
2355 * @{ */
2356/** Peripheral page request support. */
2357#define ACPI_IVHD_10H_F_PPR_SUP RT_BIT(7)
2358/** Prefetch IOMMU pages command support. */
2359#define ACPI_IVHD_10H_F_PREF_SUP RT_BIT(6)
2360/** Coherent control. */
2361#define ACPI_IVHD_10H_F_COHERENT RT_BIT(5)
2362/** Remote IOTLB support. */
2363#define ACPI_IVHD_10H_F_IOTLB_SUP RT_BIT(4)
2364/** Isochronous control. */
2365#define ACPI_IVHD_10H_F_ISOC RT_BIT(3)
2366/** Response Pass Posted Write. */
2367#define ACPI_IVHD_10H_F_RES_PASS_PW RT_BIT(2)
2368/** Pass Posted Write. */
2369#define ACPI_IVHD_10H_F_PASS_PW RT_BIT(1)
2370/** HyperTransport Tunnel. */
2371#define ACPI_IVHD_10H_F_HT_TUNNEL RT_BIT(0)
2372/** @} */
2373
2374/** @name IVRS IVinfo field.
2375 * In accordance with the AMD spec.
2376 * @{ */
2377/** EFRSup: Extended Feature Support. */
2378#define ACPI_IVINFO_BF_EFR_SUP_SHIFT 0
2379#define ACPI_IVINFO_BF_EFR_SUP_MASK UINT32_C(0x00000001)
2380/** DMA Remap Sup: DMA remapping support (pre-boot DMA protection with
2381 * mandatory remapping of device accessed memory). */
2382#define ACPI_IVINFO_BF_DMA_REMAP_SUP_SHIFT 1
2383#define ACPI_IVINFO_BF_DMA_REMAP_SUP_MASK UINT32_C(0x00000002)
2384/** Bits 4:2 reserved. */
2385#define ACPI_IVINFO_BF_RSVD_2_4_SHIFT 2
2386#define ACPI_IVINFO_BF_RSVD_2_4_MASK UINT32_C(0x0000001c)
2387/** GVASize: Guest virtual-address size. */
2388#define ACPI_IVINFO_BF_GVA_SIZE_SHIFT 5
2389#define ACPI_IVINFO_BF_GVA_SIZE_MASK UINT32_C(0x000000e0)
2390/** PASize: System physical address size. */
2391#define ACPI_IVINFO_BF_PA_SIZE_SHIFT 8
2392#define ACPI_IVINFO_BF_PA_SIZE_MASK UINT32_C(0x00007f00)
2393/** VASize: Virtual address size. */
2394#define ACPI_IVINFO_BF_VA_SIZE_SHIFT 15
2395#define ACPI_IVINFO_BF_VA_SIZE_MASK UINT32_C(0x003f8000)
2396/** HTAtsResv: HyperTransport ATS-response address translation range reserved. */
2397#define ACPI_IVINFO_BF_HT_ATS_RESV_SHIFT 22
2398#define ACPI_IVINFO_BF_HT_ATS_RESV_MASK UINT32_C(0x00400000)
2399/** Bits 31:23 reserved. */
2400#define ACPI_IVINFO_BF_RSVD_23_31_SHIFT 23
2401#define ACPI_IVINFO_BF_RSVD_23_31_MASK UINT32_C(0xff800000)
2402RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IVINFO_BF_, UINT32_C(0), UINT32_MAX,
2403 (EFR_SUP, DMA_REMAP_SUP, RSVD_2_4, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_31));
2404/** @} */
2405
2406/** @name IVHD IOMMU info flags.
2407 * In accordance with the AMD spec.
2408 * @{ */
2409/** MSI message number for the event log. */
2410#define ACPI_IOMMU_INFO_BF_MSI_NUM_SHIFT 0
2411#define ACPI_IOMMU_INFO_BF_MSI_NUM_MASK UINT16_C(0x001f)
2412/** Bits 7:5 reserved. */
2413#define ACPI_IOMMU_INFO_BF_RSVD_5_7_SHIFT 5
2414#define ACPI_IOMMU_INFO_BF_RSVD_5_7_MASK UINT16_C(0x00e0)
2415/** IOMMU HyperTransport Unit ID number. */
2416#define ACPI_IOMMU_INFO_BF_UNIT_ID_SHIFT 8
2417#define ACPI_IOMMU_INFO_BF_UNIT_ID_MASK UINT16_C(0x1f00)
2418/** Bits 15:13 reserved. */
2419#define ACPI_IOMMU_INFO_BF_RSVD_13_15_SHIFT 13
2420#define ACPI_IOMMU_INFO_BF_RSVD_13_15_MASK UINT16_C(0xe000)
2421RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_INFO_BF_, UINT16_C(0), UINT16_MAX,
2422 (MSI_NUM, RSVD_5_7, UNIT_ID, RSVD_13_15));
2423/** @} */
2424
2425/** @name IVHD IOMMU feature reporting field.
2426 * In accordance with the AMD spec.
2427 * @{ */
2428/** x2APIC supported for peripherals. */
2429#define ACPI_IOMMU_FEAT_BF_XT_SUP_SHIFT 0
2430#define ACPI_IOMMU_FEAT_BF_XT_SUP_MASK UINT32_C(0x00000001)
2431/** NX supported for I/O. */
2432#define ACPI_IOMMU_FEAT_BF_NX_SUP_SHIFT 1
2433#define ACPI_IOMMU_FEAT_BF_NX_SUP_MASK UINT32_C(0x00000002)
2434/** GT (Guest Translation) supported. */
2435#define ACPI_IOMMU_FEAT_BF_GT_SUP_SHIFT 2
2436#define ACPI_IOMMU_FEAT_BF_GT_SUP_MASK UINT32_C(0x00000004)
2437/** GLX (Number of guest CR3 tables) supported. */
2438#define ACPI_IOMMU_FEAT_BF_GLX_SUP_SHIFT 3
2439#define ACPI_IOMMU_FEAT_BF_GLX_SUP_MASK UINT32_C(0x00000018)
2440/** IA (INVALIDATE_IOMMU_ALL) command supported. */
2441#define ACPI_IOMMU_FEAT_BF_IA_SUP_SHIFT 5
2442#define ACPI_IOMMU_FEAT_BF_IA_SUP_MASK UINT32_C(0x00000020)
2443/** GA (Guest virtual APIC) supported. */
2444#define ACPI_IOMMU_FEAT_BF_GA_SUP_SHIFT 6
2445#define ACPI_IOMMU_FEAT_BF_GA_SUP_MASK UINT32_C(0x00000040)
2446/** HE (Hardware error) registers supported. */
2447#define ACPI_IOMMU_FEAT_BF_HE_SUP_SHIFT 7
2448#define ACPI_IOMMU_FEAT_BF_HE_SUP_MASK UINT32_C(0x00000080)
2449/** PASMax (maximum PASID) supported. Ignored if PPRSup=0. */
2450#define ACPI_IOMMU_FEAT_BF_PAS_MAX_SHIFT 8
2451#define ACPI_IOMMU_FEAT_BF_PAS_MAX_MASK UINT32_C(0x00001f00)
2452/** PNCounters (Number of performance counters per counter bank) supported. */
2453#define ACPI_IOMMU_FEAT_BF_PN_COUNTERS_SHIFT 13
2454#define ACPI_IOMMU_FEAT_BF_PN_COUNTERS_MASK UINT32_C(0x0001e000)
2455/** PNBanks (Number of performance counter banks) supported. */
2456#define ACPI_IOMMU_FEAT_BF_PN_BANKS_SHIFT 17
2457#define ACPI_IOMMU_FEAT_BF_PN_BANKS_MASK UINT32_C(0x007e0000)
2458/** MSINumPPR (MSI number for peripheral page requests). */
2459#define ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR_SHIFT 23
2460#define ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR_MASK UINT32_C(0x0f800000)
2461/** GATS (Guest address translation size). MBZ when GTSup=0. */
2462#define ACPI_IOMMU_FEAT_BF_GATS_SHIFT 28
2463#define ACPI_IOMMU_FEAT_BF_GATS_MASK UINT32_C(0x30000000)
2464/** HATS (Host address translation size). */
2465#define ACPI_IOMMU_FEAT_BF_HATS_SHIFT 30
2466#define ACPI_IOMMU_FEAT_BF_HATS_MASK UINT32_C(0xc0000000)
2467RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_FEAT_BF_, UINT32_C(0), UINT32_MAX,
2468 (XT_SUP, NX_SUP, GT_SUP, GLX_SUP, IA_SUP, GA_SUP, HE_SUP, PAS_MAX, PN_COUNTERS, PN_BANKS,
2469 MSI_NUM_PPR, GATS, HATS));
2470/** @} */
2471
2472/** @name IOMMU Extended Feature Register (PCI/MMIO/ACPI).
2473 * In accordance with the AMD spec.
2474 * @{ */
2475/** PreFSup: Prefetch support (RO). */
2476#define IOMMU_EXT_FEAT_BF_PREF_SUP_SHIFT 0
2477#define IOMMU_EXT_FEAT_BF_PREF_SUP_MASK UINT64_C(0x0000000000000001)
2478/** PPRSup: Peripheral Page Request (PPR) support (RO). */
2479#define IOMMU_EXT_FEAT_BF_PPR_SUP_SHIFT 1
2480#define IOMMU_EXT_FEAT_BF_PPR_SUP_MASK UINT64_C(0x0000000000000002)
2481/** XTSup: x2APIC support (RO). */
2482#define IOMMU_EXT_FEAT_BF_X2APIC_SUP_SHIFT 2
2483#define IOMMU_EXT_FEAT_BF_X2APIC_SUP_MASK UINT64_C(0x0000000000000004)
2484/** NXSup: No Execute (PMR and PRIV) support (RO). */
2485#define IOMMU_EXT_FEAT_BF_NO_EXEC_SUP_SHIFT 3
2486#define IOMMU_EXT_FEAT_BF_NO_EXEC_SUP_MASK UINT64_C(0x0000000000000008)
2487/** GTSup: Guest Translation support (RO). */
2488#define IOMMU_EXT_FEAT_BF_GT_SUP_SHIFT 4
2489#define IOMMU_EXT_FEAT_BF_GT_SUP_MASK UINT64_C(0x0000000000000010)
2490/** Bit 5 reserved. */
2491#define IOMMU_EXT_FEAT_BF_RSVD_5_SHIFT 5
2492#define IOMMU_EXT_FEAT_BF_RSVD_5_MASK UINT64_C(0x0000000000000020)
2493/** IASup: INVALIDATE_IOMMU_ALL command support (RO). */
2494#define IOMMU_EXT_FEAT_BF_IA_SUP_SHIFT 6
2495#define IOMMU_EXT_FEAT_BF_IA_SUP_MASK UINT64_C(0x0000000000000040)
2496/** GASup: Guest virtual-APIC support (RO). */
2497#define IOMMU_EXT_FEAT_BF_GA_SUP_SHIFT 7
2498#define IOMMU_EXT_FEAT_BF_GA_SUP_MASK UINT64_C(0x0000000000000080)
2499/** HESup: Hardware error registers support (RO). */
2500#define IOMMU_EXT_FEAT_BF_HE_SUP_SHIFT 8
2501#define IOMMU_EXT_FEAT_BF_HE_SUP_MASK UINT64_C(0x0000000000000100)
2502/** PCSup: Performance counters support (RO). */
2503#define IOMMU_EXT_FEAT_BF_PC_SUP_SHIFT 9
2504#define IOMMU_EXT_FEAT_BF_PC_SUP_MASK UINT64_C(0x0000000000000200)
2505/** HATS: Host Address Translation Size (RO). */
2506#define IOMMU_EXT_FEAT_BF_HATS_SHIFT 10
2507#define IOMMU_EXT_FEAT_BF_HATS_MASK UINT64_C(0x0000000000000c00)
2508/** GATS: Guest Address Translation Size (RO). */
2509#define IOMMU_EXT_FEAT_BF_GATS_SHIFT 12
2510#define IOMMU_EXT_FEAT_BF_GATS_MASK UINT64_C(0x0000000000003000)
2511/** GLXSup: Guest CR3 root table level support (RO). */
2512#define IOMMU_EXT_FEAT_BF_GLX_SUP_SHIFT 14
2513#define IOMMU_EXT_FEAT_BF_GLX_SUP_MASK UINT64_C(0x000000000000c000)
2514/** SmiFSup: SMI filter register support (RO). */
2515#define IOMMU_EXT_FEAT_BF_SMI_FLT_SUP_SHIFT 16
2516#define IOMMU_EXT_FEAT_BF_SMI_FLT_SUP_MASK UINT64_C(0x0000000000030000)
2517/** SmiFRC: SMI filter register count (RO). */
2518#define IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT_SHIFT 18
2519#define IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT_MASK UINT64_C(0x00000000001c0000)
2520/** GAMSup: Guest virtual-APIC modes support (RO). */
2521#define IOMMU_EXT_FEAT_BF_GAM_SUP_SHIFT 21
2522#define IOMMU_EXT_FEAT_BF_GAM_SUP_MASK UINT64_C(0x0000000000e00000)
2523/** DualPprLogSup: Dual PPR Log support (RO). */
2524#define IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP_SHIFT 24
2525#define IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP_MASK UINT64_C(0x0000000003000000)
2526/** Bits 27:26 reserved. */
2527#define IOMMU_EXT_FEAT_BF_RSVD_26_27_SHIFT 26
2528#define IOMMU_EXT_FEAT_BF_RSVD_26_27_MASK UINT64_C(0x000000000c000000)
2529/** DualEventLogSup: Dual Event Log support (RO). */
2530#define IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP_SHIFT 28
2531#define IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP_MASK UINT64_C(0x0000000030000000)
2532/** Bits 31:30 reserved. */
2533#define IOMMU_EXT_FEAT_BF_RSVD_30_31_SHIFT 30
2534#define IOMMU_EXT_FEAT_BF_RSVD_30_31_MASK UINT64_C(0x00000000c0000000)
2535/** PASMax: Maximum PASID support (RO). */
2536#define IOMMU_EXT_FEAT_BF_PASID_MAX_SHIFT 32
2537#define IOMMU_EXT_FEAT_BF_PASID_MAX_MASK UINT64_C(0x0000001f00000000)
2538/** USSup: User/Supervisor support (RO). */
2539#define IOMMU_EXT_FEAT_BF_US_SUP_SHIFT 37
2540#define IOMMU_EXT_FEAT_BF_US_SUP_MASK UINT64_C(0x0000002000000000)
2541/** DevTblSegSup: Segmented Device Table support (RO). */
2542#define IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP_SHIFT 38
2543#define IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP_MASK UINT64_C(0x000000c000000000)
2544/** PprOverflwEarlySup: PPR Log Overflow Early warning support (RO). */
2545#define IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY_SHIFT 40
2546#define IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY_MASK UINT64_C(0x0000010000000000)
2547/** PprAutoRspSup: PPR Automatic Response support (RO). */
2548#define IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP_SHIFT 41
2549#define IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP_MASK UINT64_C(0x0000020000000000)
2550/** MarcSup: Memory Access and Routing (MARC) support (RO). */
2551#define IOMMU_EXT_FEAT_BF_MARC_SUP_SHIFT 42
2552#define IOMMU_EXT_FEAT_BF_MARC_SUP_MASK UINT64_C(0x00000c0000000000)
2553/** BlkStopMrkSup: Block StopMark message support (RO). */
2554#define IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP_SHIFT 44
2555#define IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP_MASK UINT64_C(0x0000100000000000)
2556/** PerfOptSup: IOMMU Performance Optimization support (RO). */
2557#define IOMMU_EXT_FEAT_BF_PERF_OPT_SUP_SHIFT 45
2558#define IOMMU_EXT_FEAT_BF_PERF_OPT_SUP_MASK UINT64_C(0x0000200000000000)
2559/** MsiCapMmioSup: MSI-Capability Register MMIO access support (RO). */
2560#define IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP_SHIFT 46
2561#define IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP_MASK UINT64_C(0x0000400000000000)
2562/** Bit 47 reserved. */
2563#define IOMMU_EXT_FEAT_BF_RSVD_47_SHIFT 47
2564#define IOMMU_EXT_FEAT_BF_RSVD_47_MASK UINT64_C(0x0000800000000000)
2565/** GIoSup: Guest I/O Protection support (RO). */
2566#define IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP_SHIFT 48
2567#define IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP_MASK UINT64_C(0x0001000000000000)
2568/** HASup: Host Access support (RO). */
2569#define IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP_SHIFT 49
2570#define IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP_MASK UINT64_C(0x0002000000000000)
2571/** EPHSup: Enhandled PPR Handling support (RO). */
2572#define IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP_SHIFT 50
2573#define IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP_MASK UINT64_C(0x0004000000000000)
2574/** AttrFWSup: Attribute Forward support (RO). */
2575#define IOMMU_EXT_FEAT_BF_ATTR_FW_SUP_SHIFT 51
2576#define IOMMU_EXT_FEAT_BF_ATTR_FW_SUP_MASK UINT64_C(0x0008000000000000)
2577/** HDSup: Host Dirty Support (RO). */
2578#define IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP_SHIFT 52
2579#define IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP_MASK UINT64_C(0x0010000000000000)
2580/** Bit 53 reserved. */
2581#define IOMMU_EXT_FEAT_BF_RSVD_53_SHIFT 53
2582#define IOMMU_EXT_FEAT_BF_RSVD_53_MASK UINT64_C(0x0020000000000000)
2583/** InvIotlbTypeSup: Invalidate IOTLB type support (RO). */
2584#define IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP_SHIFT 54
2585#define IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP_MASK UINT64_C(0x0040000000000000)
2586/** Bits 60:55 reserved. */
2587#define IOMMU_EXT_FEAT_BF_RSVD_55_60_SHIFT 55
2588#define IOMMU_EXT_FEAT_BF_RSVD_55_60_MASK UINT64_C(0x1f80000000000000)
2589/** GAUpdateDisSup: Support disabling hardware update on guest page table access
2590 * (RO). */
2591#define IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP_SHIFT 61
2592#define IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP_MASK UINT64_C(0x2000000000000000)
2593/** ForcePhysDestSup: Force Physical Destination Mode for Remapped Interrupt
2594 * support (RO). */
2595#define IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP_SHIFT 62
2596#define IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP_MASK UINT64_C(0x4000000000000000)
2597/** Bit 63 reserved. */
2598#define IOMMU_EXT_FEAT_BF_RSVD_63_SHIFT 63
2599#define IOMMU_EXT_FEAT_BF_RSVD_63_MASK UINT64_C(0x8000000000000000)
2600RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_EXT_FEAT_BF_, UINT64_C(0), UINT64_MAX,
2601 (PREF_SUP, PPR_SUP, X2APIC_SUP, NO_EXEC_SUP, GT_SUP, RSVD_5, IA_SUP, GA_SUP, HE_SUP, PC_SUP,
2602 HATS, GATS, GLX_SUP, SMI_FLT_SUP, SMI_FLT_REG_CNT, GAM_SUP, DUAL_PPR_LOG_SUP, RSVD_26_27,
2603 DUAL_EVT_LOG_SUP, RSVD_30_31, PASID_MAX, US_SUP, DEV_TBL_SEG_SUP, PPR_OVERFLOW_EARLY,
2604 PPR_AUTO_RES_SUP, MARC_SUP, BLKSTOP_MARK_SUP, PERF_OPT_SUP, MSI_CAP_MMIO_SUP, RSVD_47,
2605 GST_IO_PROT_SUP, HST_ACCESS_SUP, ENHANCED_PPR_SUP, ATTR_FW_SUP, HST_DIRTY_SUP, RSVD_53,
2606 INV_IOTLB_TYPE_SUP, RSVD_55_60, GA_UPDATE_DIS_SUP, FORCE_PHYS_DST_SUP, RSVD_63));
2607/** @} */
2608
2609/**
2610 * IVHD (I/O Virtualization Hardware Definition) Type 10h.
2611 * In accordance with the AMD spec.
2612 */
2613#pragma pack(1)
2614typedef struct ACPIIVHDTYPE10
2615{
2616 uint8_t u8Type; /**< Type: Must be 0x10. */
2617 uint8_t u8Flags; /**< Flags (see ACPI_IVHD_10H_F_XXX). */
2618 uint16_t u16Length; /**< Length of IVHD including IVHD device entries. */
2619 uint16_t u16DeviceId; /**< Device ID of the IOMMU. */
2620 uint16_t u16CapOffset; /**< Offset in Capability space for control fields of IOMMU. */
2621 uint64_t u64BaseAddress; /**< Base address of IOMMU control registers in MMIO space. */
2622 uint16_t u16PciSegmentGroup; /**< PCI segment group number. */
2623 uint16_t u16IommuInfo; /**< Interrupt number and Unit ID. */
2624 uint32_t u32Features; /**< IOMMU feature reporting. */
2625 /* IVHD device entry block follows. */
2626} ACPIIVHDTYPE10;
2627#pragma pack()
2628AssertCompileSize(ACPIIVHDTYPE10, 24);
2629AssertCompileMemberOffset(ACPIIVHDTYPE10, u8Type, 0);
2630AssertCompileMemberOffset(ACPIIVHDTYPE10, u8Flags, 1);
2631AssertCompileMemberOffset(ACPIIVHDTYPE10, u16Length, 2);
2632AssertCompileMemberOffset(ACPIIVHDTYPE10, u16DeviceId, 4);
2633AssertCompileMemberOffset(ACPIIVHDTYPE10, u16CapOffset, 6);
2634AssertCompileMemberOffset(ACPIIVHDTYPE10, u64BaseAddress, 8);
2635AssertCompileMemberOffset(ACPIIVHDTYPE10, u16PciSegmentGroup, 16);
2636AssertCompileMemberOffset(ACPIIVHDTYPE10, u16IommuInfo, 18);
2637AssertCompileMemberOffset(ACPIIVHDTYPE10, u32Features, 20);
2638
2639/** @name IVHD Type 11h Flags.
2640 * In accordance with the AMD spec.
2641 * @{ */
2642/** Coherent control. */
2643#define ACPI_IVHD_11H_F_COHERENT RT_BIT(5)
2644/** Remote IOTLB support. */
2645#define ACPI_IVHD_11H_F_IOTLB_SUP RT_BIT(4)
2646/** Isochronous control. */
2647#define ACPI_IVHD_11H_F_ISOC RT_BIT(3)
2648/** Response Pass Posted Write. */
2649#define ACPI_IVHD_11H_F_RES_PASS_PW RT_BIT(2)
2650/** Pass Posted Write. */
2651#define ACPI_IVHD_11H_F_PASS_PW RT_BIT(1)
2652/** HyperTransport Tunnel. */
2653#define ACPI_IVHD_11H_F_HT_TUNNEL RT_BIT(0)
2654/** @} */
2655
2656/** @name IVHD IOMMU Type 11 Attributes field.
2657 * In accordance with the AMD spec.
2658 * @{ */
2659/** Bits 12:0 reserved. */
2660#define ACPI_IOMMU_ATTR_BF_RSVD_0_12_SHIFT 0
2661#define ACPI_IOMMU_ATTR_BF_RSVD_0_12_MASK UINT32_C(0x00001fff)
2662/** PNCounters: Number of performance counters per counter bank. */
2663#define ACPI_IOMMU_ATTR_BF_PN_COUNTERS_SHIFT 13
2664#define ACPI_IOMMU_ATTR_BF_PN_COUNTERS_MASK UINT32_C(0x0001e000)
2665/** PNBanks: Number of performance counter banks. */
2666#define ACPI_IOMMU_ATTR_BF_PN_BANKS_SHIFT 17
2667#define ACPI_IOMMU_ATTR_BF_PN_BANKS_MASK UINT32_C(0x007e0000)
2668/** MSINumPPR: MSI number for peripheral page requests (PPR). */
2669#define ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR_SHIFT 23
2670#define ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR_MASK UINT32_C(0x0f800000)
2671/** Bits 31:28 reserved. */
2672#define ACPI_IOMMU_ATTR_BF_RSVD_28_31_SHIFT 28
2673#define ACPI_IOMMU_ATTR_BF_RSVD_28_31_MASK UINT32_C(0xf0000000)
2674RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_ATTR_BF_, UINT32_C(0), UINT32_MAX,
2675 (RSVD_0_12, PN_COUNTERS, PN_BANKS, MSI_NUM_PPR, RSVD_28_31));
2676/** @} */
2677
2678/**
2679 * AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Type 11h.
2680 * In accordance with the AMD spec.
2681 */
2682#pragma pack(1)
2683typedef struct ACPIIVHDTYPE11
2684{
2685 uint8_t u8Type; /**< Type: Must be 0x11. */
2686 uint8_t u8Flags; /**< Flags. */
2687 uint16_t u16Length; /**< Length: Size starting from Type fields incl. IVHD device entries. */
2688 uint16_t u16DeviceId; /**< Device ID of the IOMMU. */
2689 uint16_t u16CapOffset; /**< Offset in Capability space for control fields of IOMMU. */
2690 uint64_t u64BaseAddress; /**< Base address of IOMMU control registers in MMIO space. */
2691 uint16_t u16PciSegmentGroup; /**< PCI segment group number. */
2692 uint16_t u16IommuInfo; /**< Interrupt number and unit ID. */
2693 uint32_t u32IommuAttr; /**< IOMMU info. not reported in EFR. */
2694 uint64_t u64EfrRegister; /**< Extended Feature Register (must be identical to its MMIO shadow). */
2695 uint64_t u64Rsvd0; /**< Reserved for future. */
2696 /* IVHD device entry block follows. */
2697} ACPIIVHDTYPE11;
2698#pragma pack()
2699AssertCompileSize(ACPIIVHDTYPE11, 40);
2700AssertCompileMemberOffset(ACPIIVHDTYPE11, u8Type, 0);
2701AssertCompileMemberOffset(ACPIIVHDTYPE11, u8Flags, 1);
2702AssertCompileMemberOffset(ACPIIVHDTYPE11, u16Length, 2);
2703AssertCompileMemberOffset(ACPIIVHDTYPE11, u16DeviceId, 4);
2704AssertCompileMemberOffset(ACPIIVHDTYPE11, u16CapOffset, 6);
2705AssertCompileMemberOffset(ACPIIVHDTYPE11, u64BaseAddress, 8);
2706AssertCompileMemberOffset(ACPIIVHDTYPE11, u16PciSegmentGroup, 16);
2707AssertCompileMemberOffset(ACPIIVHDTYPE11, u16IommuInfo, 18);
2708AssertCompileMemberOffset(ACPIIVHDTYPE11, u32IommuAttr, 20);
2709AssertCompileMemberOffset(ACPIIVHDTYPE11, u64EfrRegister, 24);
2710AssertCompileMemberOffset(ACPIIVHDTYPE11, u64Rsvd0, 32);
2711
2712/**
2713 * AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Type 40h.
2714 * In accordance with the AMD spec.
2715 */
2716typedef struct ACPIIVHDTYPE11 ACPIIVHDTYPE40;
2717
2718#endif /* !VBOX_INCLUDED_iommu_amd_h */
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