VirtualBox

source: vbox/trunk/include/VBox/hwacc_vmx.h@ 7109

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1/** @file
2 * HWACC/VMX - VMX Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmx_h
27#define ___VBox_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <VBox/cpum.h>
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34
35/** @defgroup grp_vmx vmx Types and Definitions
36 * @ingroup grp_hwaccm
37 * @{
38 */
39
40/** VMX Basic Exit Reasons.
41 * @{
42 */
43/* And-mask for setting reserved bits to zero */
44#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
45/* Or-mask for setting reserved bits to 1 */
46#define VMX_EFLAGS_RESERVED_1 0x00000002
47/** @} */
48
49/** VMX Basic Exit Reasons.
50 * @{
51 */
52/** 0 Exception or non-maskable interrupt (NMI). */
53#define VMX_EXIT_EXCEPTION 0
54/** 1 External interrupt. */
55#define VMX_EXIT_EXTERNAL_IRQ 1
56/** 2 Triple fault. */
57#define VMX_EXIT_TRIPLE_FAULT 2
58/** 3 INIT signal. */
59#define VMX_EXIT_INIT_SIGNAL 3
60/** 4 Start-up IPI (SIPI). */
61#define VMX_EXIT_SIPI 4
62/** 5 I/O system-management interrupt (SMI). */
63#define VMX_EXIT_IO_SMI_IRQ 5
64/** 6 Other SMI. */
65#define VMX_EXIT_SMI_IRQ 6
66/** 7 Interrupt window. */
67#define VMX_EXIT_IRQ_WINDOW 7
68/** 9 Task switch. */
69#define VMX_EXIT_TASK_SWITCH 9
70/** 10 Guest software attempted to execute CPUID. */
71#define VMX_EXIT_CPUID 10
72/** 12 Guest software attempted to execute HLT. */
73#define VMX_EXIT_HLT 12
74/** 13 Guest software attempted to execute INVD. */
75#define VMX_EXIT_INVD 13
76/** 14 Guest software attempted to execute INVPG. */
77#define VMX_EXIT_INVPG 14
78/** 15 Guest software attempted to execute RDPMC. */
79#define VMX_EXIT_RDPMC 15
80/** 16 Guest software attempted to execute RDTSC. */
81#define VMX_EXIT_RDTSC 16
82/** 17 Guest software attempted to execute RSM in SMM. */
83#define VMX_EXIT_RSM 17
84/** 18 Guest software executed VMCALL. */
85#define VMX_EXIT_VMCALL 18
86/** 19 Guest software executed VMCLEAR. */
87#define VMX_EXIT_VMCLEAR 19
88/** 20 Guest software executed VMLAUNCH. */
89#define VMX_EXIT_VMLAUNCH 20
90/** 21 Guest software executed VMPTRLD. */
91#define VMX_EXIT_VMPTRLD 21
92/** 22 Guest software executed VMPTRST. */
93#define VMX_EXIT_VMPTRST 22
94/** 23 Guest software executed VMREAD. */
95#define VMX_EXIT_VMREAD 23
96/** 24 Guest software executed VMRESUME. */
97#define VMX_EXIT_VMRESUME 24
98/** 25 Guest software executed VMWRITE. */
99#define VMX_EXIT_VMWRITE 25
100/** 26 Guest software executed VMXOFF. */
101#define VMX_EXIT_VMXOFF 26
102/** 27 Guest software executed VMXON. */
103#define VMX_EXIT_VMXON 27
104/** 28 Control-register accesses. */
105#define VMX_EXIT_CRX_MOVE 28
106/** 29 Debug-register accesses. */
107#define VMX_EXIT_DRX_MOVE 29
108/** 30 I/O instruction. */
109#define VMX_EXIT_PORT_IO 30
110/** 31 RDMSR. Guest software attempted to execute RDMSR. */
111#define VMX_EXIT_RDMSR 31
112/** 32 WRMSR. Guest software attempted to execute WRMSR. */
113#define VMX_EXIT_WRMSR 32
114/** 33 VM-entry failure due to invalid guest state. */
115#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
116/** 34 VM-entry failure due to MSR loading. */
117#define VMX_EXIT_ERR_MSR_LOAD 34
118/** 36 Guest software executed MWAIT. */
119#define VMX_EXIT_MWAIT 36
120/** 39 Guest software attempted to execute MONITOR. */
121#define VMX_EXIT_MONITOR 39
122/** 40 Guest software attempted to execute PAUSE. */
123#define VMX_EXIT_PAUSE 40
124/** 41 VM-entry failure due to machine-check. */
125#define VMX_EXIT_ERR_MACHINE_CHECK 41
126/** 43 TPR below threshold. Guest software executed MOV to CR8. */
127#define VMX_EXIT_TPR 43
128
129/** @} */
130
131
132/** VM Instruction Errors
133 * @{
134 */
135/** 1 VMCALL executed in VMX root operation. */
136#define VMX_ERROR_VMCALL 1
137/** 2 VMCLEAR with invalid physical address. */
138#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
139/** 3 VMCLEAR with VMXON pointer. */
140#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
141/** 4 VMLAUNCH with non-clear VMCS. */
142#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
143/** 5 VMRESUME with non-launched VMCS. */
144#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
145/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
146#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
147/** 7 VM entry with invalid control field(s). */
148#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
149/** 8 VM entry with invalid host-state field(s). */
150#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
151/** 9 VMPTRLD with invalid physical address. */
152#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
153/** 10 VMPTRLD with VMXON pointer. */
154#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
155/** 11 VMPTRLD with incorrect VMCS revision identifier. */
156#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
157/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
158#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
159#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
160/** 13 VMWRITE to read-only VMCS component. */
161#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
162/** 15 VMXON executed in VMX root operation. */
163#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
164/** 16 VM entry with invalid executive-VMCS pointer. */
165#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
166/** 17 VM entry with non-launched executive VMCS. */
167#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
168/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
169#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
170/** 19 VMCALL with non-clear VMCS. */
171#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
172/** 20 VMCALL with invalid VM-exit control fields. */
173#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
174/** 22 VMCALL with incorrect MSEG revision identifier. */
175#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
176/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
177#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
178/** 24 VMCALL with invalid SMM-monitor features. */
179#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
180/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
181#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
182/** 26 VM entry with events blocked by MOV SS. */
183#define VMX_ERROR_VMENTRY_MOV_SS 26
184
185/** @} */
186
187
188/** VMX MSR bit definitions
189 * @{
190 */
191
192/** Basic VMX information.
193 * @{
194 */
195/** VMCS revision identifier used by the processor. */
196#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
197/** Size of the VMCS. */
198#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 31ULL) & 0xFFF)
199/** Width of physical address used for the VMCS.
200 * 0 -> limited to the available amount of physical ram
201 * 1 -> within the first 4 GB
202 */
203#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
204/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
205#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
206/** Memory type that must be used for the VMCS. */
207#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
208/** @} */
209
210
211/** Misc VMX info.
212 * @{
213 */
214/** Activity states supported by the implementation. */
215#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
216/** Number of CR3 target values supported by the processor. (0-256) */
217#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
218/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
219#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
220/** MSEG revision identifier used by the processor. */
221#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
222/** @} */
223
224
225/** VMCS enumeration field info
226 * @{
227 */
228/** Highest field index. */
229#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
230
231/** @} */
232
233/** @} */
234
235
236/** VMCS field encoding
237 * @{
238 */
239
240/* 16 bits guest fields
241 * @{
242 */
243#define VMX_VMCS_GUEST_FIELD_ES 0x800
244#define VMX_VMCS_GUEST_FIELD_CS 0x802
245#define VMX_VMCS_GUEST_FIELD_SS 0x804
246#define VMX_VMCS_GUEST_FIELD_DS 0x806
247#define VMX_VMCS_GUEST_FIELD_FS 0x808
248#define VMX_VMCS_GUEST_FIELD_GS 0x80A
249#define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
250#define VMX_VMCS_GUEST_FIELD_TR 0x80E
251/** @} */
252
253/** 16 bits host fields
254 * @{
255 */
256#define VMX_VMCS_HOST_FIELD_ES 0xC00
257#define VMX_VMCS_HOST_FIELD_CS 0xC02
258#define VMX_VMCS_HOST_FIELD_SS 0xC04
259#define VMX_VMCS_HOST_FIELD_DS 0xC06
260#define VMX_VMCS_HOST_FIELD_FS 0xC08
261#define VMX_VMCS_HOST_FIELD_GS 0xC0A
262#define VMX_VMCS_HOST_FIELD_TR 0xC0C
263/** @} */
264
265/** 64 Bits control fields
266 * @{
267 */
268#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
269#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
270#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
271#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
272
273/* Optional */
274#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
275#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
276
277#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
278#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
279#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
280#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
281
282#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
283#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
284
285#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
286#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
287
288#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
289#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
290
291/* Optional */
292#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
293#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
294/** @} */
295
296
297/** 64 Bits guest fields
298 * @{
299 */
300#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
301#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
302#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /* MSR IA32_DEBUGCTL */
303#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /* MSR IA32_DEBUGCTL */
304/** @} */
305
306
307/** 32 Bits control fields
308 * @{
309 */
310#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
311#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
312#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
313#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
314#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
315#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
316#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
317#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
318#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
319#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
320#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
321#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
322#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
323#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
324/* Optional */
325#define VMX_VMCS_CTRL_TPR_TRESHOLD 0x401C
326/** @} */
327
328
329/** VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
330 * @{
331 */
332/* External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
333#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
334/* Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
335#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
336/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
337/** @} */
338
339
340/** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
341 * @{
342 */
343/* VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
344#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
345/* Use timestamp counter offset. */
346#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
347/* VM Exit when executing the HLT instruction. */
348#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
349/* VM Exit when executing the INVLPG instruction. */
350#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
351/* VM Exit when executing the MWAIT instruction. */
352#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
353/* VM Exit when executing the RDPMC instruction. */
354#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
355/* VM Exit when executing the RDTSC instruction. */
356#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
357/* VM Exit on CR8 loads. */
358#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
359/* VM Exit on CR8 stores. */
360#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
361/* Use TPR shadow. */
362#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
363/* VM Exit when executing a MOV DRx instruction. */
364#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
365/* VM Exit when executing IO instructions. */
366#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
367/* Use IO bitmaps. */
368#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
369/* Use MSR bitmaps. */
370#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
371/* VM Exit when executing the MONITOR instruction. */
372#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
373/* VM Exit when executing the PAUSE instruction. */
374#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
375/** @} */
376
377
378/** VMX_VMCS_CTRL_ENTRY_CONTROLS
379 * @{
380 */
381/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
382#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
383/** In SMM mode after VM-entry. */
384#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
385/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
386#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
387/** @} */
388
389
390/** VMX_VMCS_CTRL_EXIT_CONTROLS
391 * @{
392 */
393/** Return to long mode after a VM-exit. */
394#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
395/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
396#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
397/** @} */
398
399/** 32 Bits read-only fields
400 * @{
401 */
402#define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
403#define VMX_VMCS_RO_EXIT_REASON 0x4402
404#define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
405#define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
406#define VMX_VMCS_RO_IDT_INFO 0x4408
407#define VMX_VMCS_RO_IDT_ERRCODE 0x440A
408#define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
409#define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
410/** @} */
411
412/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
413 * @{
414 */
415#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
416#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
417#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
418#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
419#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
420#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
421#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
422#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
423/* Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
424#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
425/** @} */
426
427/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
428 * @{
429 */
430#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
431#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
432#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
433#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /* int xx */
434#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
435/** @} */
436
437
438/** 32 Bits guest state fields
439 * @{
440 */
441#define VMX_VMCS_GUEST_ES_LIMIT 0x4800
442#define VMX_VMCS_GUEST_CS_LIMIT 0x4802
443#define VMX_VMCS_GUEST_SS_LIMIT 0x4804
444#define VMX_VMCS_GUEST_DS_LIMIT 0x4806
445#define VMX_VMCS_GUEST_FS_LIMIT 0x4808
446#define VMX_VMCS_GUEST_GS_LIMIT 0x480A
447#define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
448#define VMX_VMCS_GUEST_TR_LIMIT 0x480E
449#define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
450#define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
451#define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
452#define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
453#define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
454#define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
455#define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
456#define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
457#define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
458#define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
459#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
460#define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
461#define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /* MSR IA32_SYSENTER_CS */
462/** @} */
463
464
465/** VMX_VMCS_GUEST_ACTIVITY_STATE
466 * @{
467 */
468/* The logical processor is active. */
469#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
470/* The logical processor is inactive, because executed a HLT instruction. */
471#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
472/* The logical processor is inactive, because of a triple fault or other serious error. */
473#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
474/* The logical processor is inactive, because it's waiting for a startup-IPI */
475#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
476/** @} */
477
478
479/** VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
480 * @{
481 */
482#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
483#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
484#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
485#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
486/** @} */
487
488
489/** 32 Bits host state fields
490 * @{
491 */
492#define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
493/** @} */
494
495/** Natural width control fields
496 * @{
497 */
498#define VMX_VMCS_CTRL_CR0_MASK 0x6000
499#define VMX_VMCS_CTRL_CR4_MASK 0x6002
500#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
501#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
502#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
503#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
504#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
505#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
506/** @} */
507
508
509/** Natural width read-only data fields
510 * @{
511 */
512#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
513#define VMX_VMCS_RO_IO_RCX 0x6402
514#define VMX_VMCS_RO_IO_RSX 0x6404
515#define VMX_VMCS_RO_IO_RDI 0x6406
516#define VMX_VMCS_RO_IO_RIP 0x6408
517#define VMX_VMCS_GUEST_LINEAR_ADDR 0x640A
518/** @} */
519
520
521/** VMX_VMCS_RO_EXIT_QUALIFICATION
522 * @{
523 */
524
525/** DRx moves
526 * @{
527 */
528/** 0-2: Debug register number */
529#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
530/** 3: Reserved; cleared to 0. */
531#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
532/** 4: Direction of move (0 = write, 1 = read) */
533#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
534/** 5-7: Reserved; cleared to 0. */
535#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
536/** 8-11: General purpose register number. */
537#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
538/** Rest: reserved. */
539
540/** VMX_EXIT_QUALIFICATION_DRX_DIRECTION
541 * @{
542 */
543#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
544#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
545/** @} */
546
547/** @} */
548
549
550/** CRx accesses
551 * @{
552 */
553/** 0-3: Control register number (0 for CLTS & LMSW) */
554#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
555/** 4-5: Access type. */
556#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
557/** 6: LMSW operand type */
558#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
559/** 7: Reserved; cleared to 0. */
560#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
561/** 8-11: General purpose register number (0 for CLTS & LMSW). */
562#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
563/** 12-15: Reserved; cleared to 0. */
564#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
565/** 16-31: LMSW source data (else 0). */
566#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
567/** Rest: reserved. */
568
569
570/** VMX_EXIT_QUALIFICATION_CRX_ACCESS
571 * @{
572 */
573#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
574#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
575#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
576#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
577/** @} */
578
579/** @} */
580
581
582/** VMX_EXIT_PORT_IO
583 * @{
584 */
585/** 0-2: IO operation width. */
586#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
587/** 3: IO operation direction. */
588#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
589/** 4: String IO operation. */
590#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
591/** 5: Repeated IO operation. */
592#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
593/** 6: Operand encoding. */
594#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
595/** 16-31: IO Port (0-0xffff). */
596#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
597/* Rest reserved. */
598/** @} */
599
600/** VMX_EXIT_QUALIFICATION_IO_DIRECTION
601 * @{
602 */
603#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
604#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
605/** @} */
606
607
608/** VMX_EXIT_QUALIFICATION_IO_ENCODING
609 * @{
610 */
611#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
612#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
613/** @} */
614
615/** @} */
616
617/** Natural width guest state fields
618 * @{
619 */
620#define VMX_VMCS_GUEST_CR0 0x6800
621#define VMX_VMCS_GUEST_CR3 0x6802
622#define VMX_VMCS_GUEST_CR4 0x6804
623#define VMX_VMCS_GUEST_ES_BASE 0x6806
624#define VMX_VMCS_GUEST_CS_BASE 0x6808
625#define VMX_VMCS_GUEST_SS_BASE 0x680A
626#define VMX_VMCS_GUEST_DS_BASE 0x680C
627#define VMX_VMCS_GUEST_FS_BASE 0x680E
628#define VMX_VMCS_GUEST_GS_BASE 0x6810
629#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
630#define VMX_VMCS_GUEST_TR_BASE 0x6814
631#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
632#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
633#define VMX_VMCS_GUEST_DR7 0x681A
634#define VMX_VMCS_GUEST_RSP 0x681C
635#define VMX_VMCS_GUEST_RIP 0x681E
636#define VMX_VMCS_GUEST_RFLAGS 0x6820
637#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
638#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /* MSR IA32_SYSENTER_ESP */
639#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /* MSR IA32_SYSENTER_EIP */
640/** @} */
641
642
643/** VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
644 * @{
645 */
646/* Hardware breakpoint 0 was met. */
647#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
648/* Hardware breakpoint 1 was met. */
649#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
650/* Hardware breakpoint 2 was met. */
651#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
652/* Hardware breakpoint 3 was met. */
653#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
654/* At least one data or IO breakpoint was hit. */
655#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
656/* A debug exception would have been triggered by single-step execution mode. */
657#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
658/* Bits 4-11, 13 and 15-63 are reserved. */
659
660
661
662
663/** @} */
664
665/** Natural width host state fields
666 * @{
667 */
668#define VMX_VMCS_HOST_CR0 0x6C00
669#define VMX_VMCS_HOST_CR3 0x6C02
670#define VMX_VMCS_HOST_CR4 0x6C04
671#define VMX_VMCS_HOST_FS_BASE 0x6C06
672#define VMX_VMCS_HOST_GS_BASE 0x6C08
673#define VMX_VMCS_HOST_TR_BASE 0x6C0A
674#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
675#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
676#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
677#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
678#define VMX_VMCS_HOST_RSP 0x6C14
679#define VMX_VMCS_HOST_RIP 0x6C16
680/** @} */
681
682/** @} */
683
684
685#if RT_INLINE_ASM_GNU_STYLE
686# define __STR(x) #x
687# define STR(x) __STR(x)
688#endif
689
690
691/** @} */
692
693/** @defgroup grp_vmx_asm vmx assembly helpers
694 * @ingroup grp_vmx
695 * @{
696 */
697
698/**
699 * Executes VMXON
700 *
701 * @returns VBox status code
702 * @param pVMXOn Physical address of VMXON structure
703 */
704#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
705DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
706#else
707DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
708{
709 int rc = VINF_SUCCESS;
710# if RT_INLINE_ASM_GNU_STYLE
711 __asm__ __volatile__ (
712 "push %3 \n\t"
713 "push %2 \n\t"
714 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
715 "ja 2f \n\t"
716 "je 1f \n\t"
717 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
718 "jmp 2f \n\t"
719 "1: \n\t"
720 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
721 "2: \n\t"
722 "add $8, %%esp \n\t"
723 :"=rm"(rc)
724 :"0"(VINF_SUCCESS),
725 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
726 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
727 :"memory"
728 );
729# else
730 __asm
731 {
732 push dword ptr [pVMXOn+4]
733 push dword ptr [pVMXOn]
734 _emit 0xF3
735 _emit 0x0F
736 _emit 0xC7
737 _emit 0x34
738 _emit 0x24 /* VMXON [esp] */
739 jnc vmxon_good
740 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
741 jmp the_end
742
743vmxon_good:
744 jnz the_end
745 mov dword ptr [rc], VERR_VMX_GENERIC
746the_end:
747 add esp, 8
748 }
749# endif
750 return rc;
751}
752#endif
753
754
755/**
756 * Executes VMXOFF
757 */
758#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
759DECLASM(void) VMXDisable(void);
760#else
761DECLINLINE(void) VMXDisable(void)
762{
763# if RT_INLINE_ASM_GNU_STYLE
764 __asm__ __volatile__ (
765 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
766 );
767# else
768 __asm
769 {
770 _emit 0x0F
771 _emit 0x01
772 _emit 0xC4 /* VMXOFF */
773 }
774# endif
775}
776#endif
777
778
779/**
780 * Executes VMCLEAR
781 *
782 * @returns VBox status code
783 * @param pVMCS Physical address of VM control structure
784 */
785#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
786DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
787#else
788DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
789{
790 int rc = VINF_SUCCESS;
791# if RT_INLINE_ASM_GNU_STYLE
792 __asm__ __volatile__ (
793 "push %3 \n\t"
794 "push %2 \n\t"
795 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
796 "jnc 1f \n\t"
797 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
798 "1: \n\t"
799 "add $8, %%esp \n\t"
800 :"=rm"(rc)
801 :"0"(VINF_SUCCESS),
802 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
803 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
804 :"memory"
805 );
806# else
807 __asm
808 {
809 push dword ptr [pVMCS+4]
810 push dword ptr [pVMCS]
811 _emit 0x66
812 _emit 0x0F
813 _emit 0xC7
814 _emit 0x34
815 _emit 0x24 /* VMCLEAR [esp] */
816 jnc success
817 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
818success:
819 add esp, 8
820 }
821# endif
822 return rc;
823}
824#endif
825
826
827/**
828 * Executes VMPTRLD
829 *
830 * @returns VBox status code
831 * @param pVMCS Physical address of VMCS structure
832 */
833#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
834DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
835#else
836DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
837{
838 int rc = VINF_SUCCESS;
839# if RT_INLINE_ASM_GNU_STYLE
840 __asm__ __volatile__ (
841 "push %3 \n\t"
842 "push %2 \n\t"
843 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
844 "jnc 1f \n\t"
845 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
846 "1: \n\t"
847 "add $8, %%esp \n\t"
848 :"=rm"(rc)
849 :"0"(VINF_SUCCESS),
850 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
851 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
852 );
853# else
854 __asm
855 {
856 push dword ptr [pVMCS+4]
857 push dword ptr [pVMCS]
858 _emit 0x0F
859 _emit 0xC7
860 _emit 0x34
861 _emit 0x24 /* VMPTRLD [esp] */
862 jnc success
863 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
864
865success:
866 add esp, 8
867 }
868# endif
869 return rc;
870}
871#endif
872
873
874/**
875 * Executes VMWRITE
876 *
877 * @returns VBox status code
878 * @param idxField VMCS index
879 * @param u64Val 16, 32 or 64 bits value
880 */
881DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
882
883/**
884 * Executes VMWRITE
885 *
886 * @returns VBox status code
887 * @param idxField VMCS index
888 * @param u32Val 32 bits value
889 */
890#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
891DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
892#else
893DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
894{
895 int rc = VINF_SUCCESS;
896# if RT_INLINE_ASM_GNU_STYLE
897 __asm__ __volatile__ (
898 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
899 "ja 2f \n\t"
900 "je 1f \n\t"
901 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
902 "jmp 2f \n\t"
903 "1: \n\t"
904 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
905 "2: \n\t"
906 :"=rm"(rc)
907 :"0"(VINF_SUCCESS),
908 "a"(idxField),
909 "d"(u32Val)
910 );
911# else
912 __asm
913 {
914 push dword ptr [u32Val]
915 mov eax, [idxField]
916 _emit 0x0F
917 _emit 0x79
918 _emit 0x04
919 _emit 0x24 /* VMWRITE eax, [esp] */
920 jnc valid_vmcs
921 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
922 jmp the_end
923
924valid_vmcs:
925 jnz the_end
926 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
927the_end:
928 add esp, 4
929 }
930# endif
931 return rc;
932}
933#endif
934
935#if HC_ARCH_BITS == 64
936#define VMXWriteVMCS VMXWriteVMCS64
937#else
938#define VMXWriteVMCS VMXWriteVMCS32
939#endif /* HC_ARCH_BITS == 64 */
940
941
942/**
943 * Executes VMREAD
944 *
945 * @returns VBox status code
946 * @param idxField VMCS index
947 * @param pData Ptr to store VM field value
948 */
949DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
950
951/**
952 * Executes VMREAD
953 *
954 * @returns VBox status code
955 * @param idxField VMCS index
956 * @param pData Ptr to store VM field value
957 */
958#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
959DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
960#else
961DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
962{
963 int rc = VINF_SUCCESS;
964# if RT_INLINE_ASM_GNU_STYLE
965 __asm__ __volatile__ (
966 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
967 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
968 "ja 2f \n\t"
969 "je 1f \n\t"
970 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
971 "jmp 2f \n\t"
972 "1: \n\t"
973 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
974 "2: \n\t"
975 :"=&r"(rc),
976 "=d"(*pData)
977 :"a"(idxField),
978 "d"(0)
979 );
980# else
981 __asm
982 {
983 sub esp, 4
984 mov dword ptr [esp], 0
985 mov eax, [idxField]
986 _emit 0x0F
987 _emit 0x78
988 _emit 0x04
989 _emit 0x24 /* VMREAD eax, [esp] */
990 mov edx, pData
991 pop dword ptr [edx]
992 jnc valid_vmcs
993 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
994 jmp the_end
995
996valid_vmcs:
997 jnz the_end
998 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
999the_end:
1000 }
1001# endif
1002 return rc;
1003}
1004#endif
1005
1006#if HC_ARCH_BITS == 64
1007#define VMXReadVMCS VMXReadVMCS64
1008#else
1009#define VMXReadVMCS VMXReadVMCS32
1010#endif /* HC_ARCH_BITS == 64 */
1011
1012/**
1013 * Prepares for and executes VMLAUNCH
1014 *
1015 * @returns VBox status code
1016 * @param pCtx Guest context
1017 */
1018DECLASM(int) VMXStartVM(PCPUMCTX pCtx);
1019
1020/**
1021 * Prepares for and executes VMRESUME
1022 *
1023 * @returns VBox status code
1024 * @param pCtx Guest context
1025 */
1026DECLASM(int) VMXResumeVM(PCPUMCTX pCtx);
1027
1028/**
1029 * Gets the last instruction error value from the current VMCS
1030 *
1031 * @returns error value
1032 */
1033DECLINLINE(uint32_t) VMXGetLastError(void)
1034{
1035#if HC_ARCH_BITS == 64
1036 uint64_t uLastError = 0;
1037 int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1038 AssertRC(rc);
1039 return (uint32_t)uLastError;
1040
1041#else /* 32-bit host: */
1042 uint32_t lasterr = 0;
1043 int rc;
1044
1045 rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &lasterr);
1046 AssertRC(rc);
1047 return lasterr;
1048#endif
1049}
1050
1051/** @} */
1052
1053#endif
1054
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