VirtualBox

source: vbox/trunk/include/VBox/hwacc_vmx.h@ 3362

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1/** @file
2 * HWACC/VMX - VMX Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License as published by the Free Software Foundation,
12 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13 * distribution. VirtualBox OSE is distributed in the hope that it will
14 * be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * If you received this file as part of a commercial VirtualBox
17 * distribution, then only the terms of your commercial VirtualBox
18 * license agreement apply instead of the previous paragraph.
19 */
20
21#ifndef __VBox_vmx_h__
22#define __VBox_vmx_h__
23
24#include <VBox/types.h>
25#include <VBox/err.h>
26#include <VBox/cpum.h>
27#include <iprt/assert.h>
28#include <iprt/asm.h>
29
30/** @defgroup grp_vmx vmx Types and Definitions
31 * @ingroup grp_hwaccm
32 * @{
33 */
34
35/** VMX Basic Exit Reasons.
36 * @{
37 */
38/* And-mask for setting reserved bits to zero */
39#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
40/* Or-mask for setting reserved bits to 1 */
41#define VMX_EFLAGS_RESERVED_1 0x00000002
42/** @} */
43
44/** VMX Basic Exit Reasons.
45 * @{
46 */
47/** 0 Exception or non-maskable interrupt (NMI). */
48#define VMX_EXIT_EXCEPTION 0
49/** 1 External interrupt. */
50#define VMX_EXIT_EXTERNAL_IRQ 1
51/** 2 Triple fault. */
52#define VMX_EXIT_TRIPLE_FAULT 2
53/** 3 INIT signal. */
54#define VMX_EXIT_INIT_SIGNAL 3
55/** 4 Start-up IPI (SIPI). */
56#define VMX_EXIT_SIPI 4
57/** 5 I/O system-management interrupt (SMI). */
58#define VMX_EXIT_IO_SMI_IRQ 5
59/** 6 Other SMI. */
60#define VMX_EXIT_SMI_IRQ 6
61/** 7 Interrupt window. */
62#define VMX_EXIT_IRQ_WINDOW 7
63/** 9 Task switch. */
64#define VMX_EXIT_TASK_SWITCH 9
65/** 10 Guest software attempted to execute CPUID. */
66#define VMX_EXIT_CPUID 10
67/** 12 Guest software attempted to execute HLT. */
68#define VMX_EXIT_HLT 12
69/** 13 Guest software attempted to execute INVD. */
70#define VMX_EXIT_INVD 13
71/** 14 Guest software attempted to execute INVPG. */
72#define VMX_EXIT_INVPG 14
73/** 15 Guest software attempted to execute RDPMC. */
74#define VMX_EXIT_RDPMC 15
75/** 16 Guest software attempted to execute RDTSC. */
76#define VMX_EXIT_RDTSC 16
77/** 17 Guest software attempted to execute RSM in SMM. */
78#define VMX_EXIT_RSM 17
79/** 18 Guest software executed VMCALL. */
80#define VMX_EXIT_VMCALL 18
81/** 19 Guest software executed VMCLEAR. */
82#define VMX_EXIT_VMCLEAR 19
83/** 20 Guest software executed VMLAUNCH. */
84#define VMX_EXIT_VMLAUNCH 20
85/** 21 Guest software executed VMPTRLD. */
86#define VMX_EXIT_VMPTRLD 21
87/** 22 Guest software executed VMPTRST. */
88#define VMX_EXIT_VMPTRST 22
89/** 23 Guest software executed VMREAD. */
90#define VMX_EXIT_VMREAD 23
91/** 24 Guest software executed VMRESUME. */
92#define VMX_EXIT_VMRESUME 24
93/** 25 Guest software executed VMWRITE. */
94#define VMX_EXIT_VMWRITE 25
95/** 26 Guest software executed VMXOFF. */
96#define VMX_EXIT_VMXOFF 26
97/** 27 Guest software executed VMXON. */
98#define VMX_EXIT_VMXON 27
99/** 28 Control-register accesses. */
100#define VMX_EXIT_CRX_MOVE 28
101/** 29 Debug-register accesses. */
102#define VMX_EXIT_DRX_MOVE 29
103/** 30 I/O instruction. */
104#define VMX_EXIT_PORT_IO 30
105/** 31 RDMSR. Guest software attempted to execute RDMSR. */
106#define VMX_EXIT_RDMSR 31
107/** 32 WRMSR. Guest software attempted to execute WRMSR. */
108#define VMX_EXIT_WRMSR 32
109/** 33 VM-entry failure due to invalid guest state. */
110#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
111/** 34 VM-entry failure due to MSR loading. */
112#define VMX_EXIT_ERR_MSR_LOAD 34
113/** 36 Guest software executed MWAIT. */
114#define VMX_EXIT_MWAIT 36
115/** 39 Guest software attempted to execute MONITOR. */
116#define VMX_EXIT_MONITOR 39
117/** 40 Guest software attempted to execute PAUSE. */
118#define VMX_EXIT_PAUSE 40
119/** 41 VM-entry failure due to machine-check. */
120#define VMX_EXIT_ERR_MACHINE_CHECK 41
121/** 43 TPR below threshold. Guest software executed MOV to CR8. */
122#define VMX_EXIT_TPR 43
123
124/** @} */
125
126
127/** VM Instruction Errors
128 * @{
129 */
130/** 1 VMCALL executed in VMX root operation. */
131#define VMX_ERROR_VMCALL 1
132/** 2 VMCLEAR with invalid physical address. */
133#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
134/** 3 VMCLEAR with VMXON pointer. */
135#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
136/** 4 VMLAUNCH with non-clear VMCS. */
137#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
138/** 5 VMRESUME with non-launched VMCS. */
139#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
140/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
141#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
142/** 7 VM entry with invalid control field(s). */
143#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
144/** 8 VM entry with invalid host-state field(s). */
145#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
146/** 9 VMPTRLD with invalid physical address. */
147#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
148/** 10 VMPTRLD with VMXON pointer. */
149#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
150/** 11 VMPTRLD with incorrect VMCS revision identifier. */
151#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
152/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
153#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
154#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
155/** 13 VMWRITE to read-only VMCS component. */
156#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
157/** 15 VMXON executed in VMX root operation. */
158#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
159/** 16 VM entry with invalid executive-VMCS pointer. */
160#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
161/** 17 VM entry with non-launched executive VMCS. */
162#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
163/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
164#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
165/** 19 VMCALL with non-clear VMCS. */
166#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
167/** 20 VMCALL with invalid VM-exit control fields. */
168#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
169/** 22 VMCALL with incorrect MSEG revision identifier. */
170#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
171/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
172#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
173/** 24 VMCALL with invalid SMM-monitor features. */
174#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
175/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
176#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
177/** 26 VM entry with events blocked by MOV SS. */
178#define VMX_ERROR_VMENTRY_MOV_SS 26
179
180/** @} */
181
182
183/** VMX MSR bit definitions
184 * @{
185 */
186
187/** Basic VMX information.
188 * @{
189 */
190/** VMCS revision identifier used by the processor. */
191#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
192/** Size of the VMCS. */
193#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 31ULL) & 0xFFF)
194/** Width of physical address used for the VMCS.
195 * 0 -> limited to the available amount of physical ram
196 * 1 -> within the first 4 GB
197 */
198#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
199/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
200#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
201/** Memory type that must be used for the VMCS. */
202#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
203/** @} */
204
205
206/** Misc VMX info.
207 * @{
208 */
209/** Activity states supported by the implementation. */
210#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
211/** Number of CR3 target values supported by the processor. (0-256) */
212#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
213/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
214#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
215/** MSEG revision identifier used by the processor. */
216#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
217/** @} */
218
219
220/** VMCS enumeration field info
221 * @{
222 */
223/** Highest field index. */
224#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
225
226/** @} */
227
228/** @} */
229
230
231/** VMCS field encoding
232 * @{
233 */
234
235/* 16 bits guest fields
236 * @{
237 */
238#define VMX_VMCS_GUEST_FIELD_ES 0x800
239#define VMX_VMCS_GUEST_FIELD_CS 0x802
240#define VMX_VMCS_GUEST_FIELD_SS 0x804
241#define VMX_VMCS_GUEST_FIELD_DS 0x806
242#define VMX_VMCS_GUEST_FIELD_FS 0x808
243#define VMX_VMCS_GUEST_FIELD_GS 0x80A
244#define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
245#define VMX_VMCS_GUEST_FIELD_TR 0x80E
246/** @} */
247
248/** 16 bits host fields
249 * @{
250 */
251#define VMX_VMCS_HOST_FIELD_ES 0xC00
252#define VMX_VMCS_HOST_FIELD_CS 0xC02
253#define VMX_VMCS_HOST_FIELD_SS 0xC04
254#define VMX_VMCS_HOST_FIELD_DS 0xC06
255#define VMX_VMCS_HOST_FIELD_FS 0xC08
256#define VMX_VMCS_HOST_FIELD_GS 0xC0A
257#define VMX_VMCS_HOST_FIELD_TR 0xC0C
258/** @} */
259
260/** 64 Bits control fields
261 * @{
262 */
263#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
264#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
265#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
266#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
267
268/* Optional */
269#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
270#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
271
272#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
273#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
274#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
275#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
276
277#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
278#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
279
280#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
281#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
282
283#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
284#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
285
286/* Optional */
287#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
288#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
289/** @} */
290
291
292/** 64 Bits guest fields
293 * @{
294 */
295#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
296#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
297#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /* MSR IA32_DEBUGCTL */
298#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /* MSR IA32_DEBUGCTL */
299/** @} */
300
301
302/** 32 Bits control fields
303 * @{
304 */
305#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
306#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
307#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
308#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
309#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
310#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
311#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
312#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
313#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
314#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
315#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
316#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
317#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
318#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
319/* Optional */
320#define VMX_VMCS_CTRL_TPR_TRESHOLD 0x401C
321/** @} */
322
323
324/** VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
325 * @{
326 */
327/* External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
328#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT BIT(0)
329/* Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
330#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT BIT(3)
331/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
332/** @} */
333
334
335/** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
336 * @{
337 */
338/* VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
339#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT BIT(2)
340/* Use timestamp counter offset. */
341#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET BIT(3)
342/* VM Exit when executing the HLT instruction. */
343#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT BIT(7)
344/* VM Exit when executing the INVLPG instruction. */
345#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT BIT(9)
346/* VM Exit when executing the MWAIT instruction. */
347#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT BIT(10)
348/* VM Exit when executing the RDPMC instruction. */
349#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT BIT(11)
350/* VM Exit when executing the RDTSC instruction. */
351#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT BIT(12)
352/* VM Exit on CR8 loads. */
353#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT BIT(19)
354/* VM Exit on CR8 stores. */
355#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT BIT(20)
356/* Use TPR shadow. */
357#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW BIT(21)
358/* VM Exit when executing a MOV DRx instruction. */
359#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT BIT(23)
360/* VM Exit when executing IO instructions. */
361#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT BIT(24)
362/* Use IO bitmaps. */
363#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS BIT(25)
364/* Use MSR bitmaps. */
365#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS BIT(28)
366/* VM Exit when executing the MONITOR instruction. */
367#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT BIT(29)
368/* VM Exit when executing the PAUSE instruction. */
369#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT BIT(30)
370/** @} */
371
372
373/** VMX_VMCS_CTRL_ENTRY_CONTROLS
374 * @{
375 */
376/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
377#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE BIT(9)
378/** In SMM mode after VM-entry. */
379#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM BIT(10)
380/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
381#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON BIT(11)
382/** @} */
383
384
385/** VMX_VMCS_CTRL_EXIT_CONTROLS
386 * @{
387 */
388/** Return to long mode after a VM-exit. */
389#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 BIT(9)
390/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
391#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ BIT(15)
392/** @} */
393
394/** 32 Bits read-only fields
395 * @{
396 */
397#define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
398#define VMX_VMCS_RO_EXIT_REASON 0x4402
399#define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
400#define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
401#define VMX_VMCS_RO_IDT_INFO 0x4408
402#define VMX_VMCS_RO_IDT_ERRCODE 0x440A
403#define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
404#define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
405/** @} */
406
407/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
408 * @{
409 */
410#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
411#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
412#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
413#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID BIT(11)
414#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
415#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & BIT(12))
416#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
417#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & BIT(31))
418/* Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
419#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~BIT(12))
420/** @} */
421
422/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
423 * @{
424 */
425#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
426#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
427#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
428#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /* int xx */
429#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
430/** @} */
431
432
433/** 32 Bits guest state fields
434 * @{
435 */
436#define VMX_VMCS_GUEST_ES_LIMIT 0x4800
437#define VMX_VMCS_GUEST_CS_LIMIT 0x4802
438#define VMX_VMCS_GUEST_SS_LIMIT 0x4804
439#define VMX_VMCS_GUEST_DS_LIMIT 0x4806
440#define VMX_VMCS_GUEST_FS_LIMIT 0x4808
441#define VMX_VMCS_GUEST_GS_LIMIT 0x480A
442#define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
443#define VMX_VMCS_GUEST_TR_LIMIT 0x480E
444#define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
445#define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
446#define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
447#define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
448#define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
449#define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
450#define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
451#define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
452#define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
453#define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
454#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
455#define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
456#define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /* MSR IA32_SYSENTER_CS */
457/** @} */
458
459
460/** VMX_VMCS_GUEST_ACTIVITY_STATE
461 * @{
462 */
463/* The logical processor is active. */
464#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
465/* The logical processor is inactive, because executed a HLT instruction. */
466#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
467/* The logical processor is inactive, because of a triple fault or other serious error. */
468#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
469/* The logical processor is inactive, because it's waiting for a startup-IPI */
470#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
471/** @} */
472
473
474/** VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
475 * @{
476 */
477#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI BIT(0)
478#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS BIT(1)
479#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI BIT(2)
480#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI BIT(3)
481/** @} */
482
483
484/** 32 Bits host state fields
485 * @{
486 */
487#define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
488/** @} */
489
490/** Natural width control fields
491 * @{
492 */
493#define VMX_VMCS_CTRL_CR0_MASK 0x6000
494#define VMX_VMCS_CTRL_CR4_MASK 0x6002
495#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
496#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
497#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
498#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
499#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
500#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
501/** @} */
502
503
504/** Natural width read-only data fields
505 * @{
506 */
507#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
508#define VMX_VMCS_RO_IO_RCX 0x6402
509#define VMX_VMCS_RO_IO_RSX 0x6404
510#define VMX_VMCS_RO_IO_RDI 0x6406
511#define VMX_VMCS_RO_IO_RIP 0x6408
512#define VMX_VMCS_GUEST_LINEAR_ADDR 0x640A
513/** @} */
514
515
516/** VMX_VMCS_RO_EXIT_QUALIFICATION
517 * @{
518 */
519
520/** DRx moves
521 * @{
522 */
523/** 0-2: Debug register number */
524#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
525/** 3: Reserved; cleared to 0. */
526#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
527/** 4: Direction of move (0 = write, 1 = read) */
528#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
529/** 5-7: Reserved; cleared to 0. */
530#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
531/** 8-11: General purpose register number. */
532#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
533/** Rest: reserved. */
534
535/** VMX_EXIT_QUALIFICATION_DRX_DIRECTION
536 * @{
537 */
538#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
539#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
540/** @} */
541
542/** @} */
543
544
545/** CRx accesses
546 * @{
547 */
548/** 0-3: Control register number (0 for CLTS & LMSW) */
549#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
550/** 4-5: Access type. */
551#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
552/** 6: LMSW operand type */
553#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
554/** 7: Reserved; cleared to 0. */
555#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
556/** 8-11: General purpose register number (0 for CLTS & LMSW). */
557#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
558/** 12-15: Reserved; cleared to 0. */
559#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
560/** 16-31: LMSW source data (else 0). */
561#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
562/** Rest: reserved. */
563
564
565/** VMX_EXIT_QUALIFICATION_CRX_ACCESS
566 * @{
567 */
568#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
569#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
570#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
571#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
572/** @} */
573
574/** @} */
575
576
577/** VMX_EXIT_PORT_IO
578 * @{
579 */
580/** 0-2: IO operation width. */
581#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
582/** 3: IO operation direction. */
583#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
584/** 4: String IO operation. */
585#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
586/** 5: Repeated IO operation. */
587#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
588/** 6: Operand encoding. */
589#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
590/** 16-31: IO Port (0-0xffff). */
591#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
592/* Rest reserved. */
593/** @} */
594
595/** VMX_EXIT_QUALIFICATION_IO_DIRECTION
596 * @{
597 */
598#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
599#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
600/** @} */
601
602
603/** VMX_EXIT_QUALIFICATION_IO_ENCODING
604 * @{
605 */
606#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
607#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
608/** @} */
609
610/** @} */
611
612/** Natural width guest state fields
613 * @{
614 */
615#define VMX_VMCS_GUEST_CR0 0x6800
616#define VMX_VMCS_GUEST_CR3 0x6802
617#define VMX_VMCS_GUEST_CR4 0x6804
618#define VMX_VMCS_GUEST_ES_BASE 0x6806
619#define VMX_VMCS_GUEST_CS_BASE 0x6808
620#define VMX_VMCS_GUEST_SS_BASE 0x680A
621#define VMX_VMCS_GUEST_DS_BASE 0x680C
622#define VMX_VMCS_GUEST_FS_BASE 0x680E
623#define VMX_VMCS_GUEST_GS_BASE 0x6810
624#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
625#define VMX_VMCS_GUEST_TR_BASE 0x6814
626#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
627#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
628#define VMX_VMCS_GUEST_DR7 0x681A
629#define VMX_VMCS_GUEST_RSP 0x681C
630#define VMX_VMCS_GUEST_RIP 0x681E
631#define VMX_VMCS_GUEST_RFLAGS 0x6820
632#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
633#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /* MSR IA32_SYSENTER_ESP */
634#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /* MSR IA32_SYSENTER_EIP */
635/** @} */
636
637
638/** VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
639 * @{
640 */
641/* Hardware breakpoint 0 was met. */
642#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 BIT(0)
643/* Hardware breakpoint 1 was met. */
644#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 BIT(1)
645/* Hardware breakpoint 2 was met. */
646#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 BIT(2)
647/* Hardware breakpoint 3 was met. */
648#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 BIT(3)
649/* At least one data or IO breakpoint was hit. */
650#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED BIT(12)
651/* A debug exception would have been triggered by single-step execution mode. */
652#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS BIT(14)
653/* Bits 4-11, 13 and 15-63 are reserved. */
654
655
656
657
658/** @} */
659
660/** Natural width host state fields
661 * @{
662 */
663#define VMX_VMCS_HOST_CR0 0x6C00
664#define VMX_VMCS_HOST_CR3 0x6C02
665#define VMX_VMCS_HOST_CR4 0x6C04
666#define VMX_VMCS_HOST_FS_BASE 0x6C06
667#define VMX_VMCS_HOST_GS_BASE 0x6C08
668#define VMX_VMCS_HOST_TR_BASE 0x6C0A
669#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
670#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
671#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
672#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
673#define VMX_VMCS_HOST_RSP 0x6C14
674#define VMX_VMCS_HOST_RIP 0x6C16
675/** @} */
676
677/** @} */
678
679
680#if RT_INLINE_ASM_GNU_STYLE
681# define __STR(x) #x
682# define STR(x) __STR(x)
683#endif
684
685
686/** @} */
687
688/** @defgroup grp_vmx_asm vmx assembly helpers
689 * @ingroup grp_vmx
690 * @{
691 */
692
693/**
694 * Executes VMXON
695 *
696 * @returns VBox status code
697 * @param pVMXOn Physical address of VMXON structure
698 */
699#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
700DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
701#else
702DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
703{
704 int rc = VINF_SUCCESS;
705# if RT_INLINE_ASM_GNU_STYLE
706 __asm__ __volatile__ (
707 "push %3 \n\t"
708 "push %2 \n\t"
709 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
710 "ja 2f \n\t"
711 "je 1f \n\t"
712 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
713 "jmp 2f \n\t"
714 "1: \n\t"
715 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
716 "2: \n\t"
717 "add $8, %%esp \n\t"
718 :"=rm"(rc)
719 :"0"(VINF_SUCCESS),
720 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
721 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
722 :"memory"
723 );
724# else
725 __asm
726 {
727 push dword ptr [pVMXOn+4]
728 push dword ptr [pVMXOn]
729 _emit 0xF3
730 _emit 0x0F
731 _emit 0xC7
732 _emit 0x34
733 _emit 0x24 /* VMXON [esp] */
734 jnc vmxon_good
735 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
736 jmp the_end
737
738vmxon_good:
739 jnz the_end
740 mov dword ptr [rc], VERR_VMX_GENERIC
741the_end:
742 add esp, 8
743 }
744# endif
745 return rc;
746}
747#endif
748
749
750/**
751 * Executes VMXOFF
752 */
753#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
754DECLASM(void) VMXDisable(void);
755#else
756DECLINLINE(void) VMXDisable(void)
757{
758# if RT_INLINE_ASM_GNU_STYLE
759 __asm__ __volatile__ (
760 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
761 );
762# else
763 __asm
764 {
765 _emit 0x0F
766 _emit 0x01
767 _emit 0xC4 /* VMXOFF */
768 }
769# endif
770}
771#endif
772
773
774/**
775 * Executes VMCLEAR
776 *
777 * @returns VBox status code
778 * @param pVMCS Physical address of VM control structure
779 */
780#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
781DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
782#else
783DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
784{
785 int rc = VINF_SUCCESS;
786# if RT_INLINE_ASM_GNU_STYLE
787 __asm__ __volatile__ (
788 "push %3 \n\t"
789 "push %2 \n\t"
790 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
791 "jnc 1f \n\t"
792 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
793 "1: \n\t"
794 "add $8, %%esp \n\t"
795 :"=rm"(rc)
796 :"0"(VINF_SUCCESS),
797 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
798 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
799 :"memory"
800 );
801# else
802 __asm
803 {
804 push dword ptr [pVMCS+4]
805 push dword ptr [pVMCS]
806 _emit 0x66
807 _emit 0x0F
808 _emit 0xC7
809 _emit 0x34
810 _emit 0x24 /* VMCLEAR [esp] */
811 jnc success
812 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
813success:
814 add esp, 8
815 }
816# endif
817 return rc;
818}
819#endif
820
821
822/**
823 * Executes VMPTRLD
824 *
825 * @returns VBox status code
826 * @param pVMCS Physical address of VMCS structure
827 */
828#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
829DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
830#else
831DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
832{
833 int rc = VINF_SUCCESS;
834# if RT_INLINE_ASM_GNU_STYLE
835 __asm__ __volatile__ (
836 "push %3 \n\t"
837 "push %2 \n\t"
838 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
839 "jnc 1f \n\t"
840 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
841 "1: \n\t"
842 "add $8, %%esp \n\t"
843 :"=rm"(rc)
844 :"0"(VINF_SUCCESS),
845 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
846 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
847 );
848# else
849 __asm
850 {
851 push dword ptr [pVMCS+4]
852 push dword ptr [pVMCS]
853 _emit 0x0F
854 _emit 0xC7
855 _emit 0x34
856 _emit 0x24 /* VMPTRLD [esp] */
857 jnc success
858 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
859
860success:
861 add esp, 8
862 }
863# endif
864 return rc;
865}
866#endif
867
868
869/**
870 * Executes VMWRITE
871 *
872 * @returns VBox status code
873 * @param idxField VMCS index
874 * @param u64Val 16, 32 or 64 bits value
875 */
876DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
877
878/**
879 * Executes VMWRITE
880 *
881 * @returns VBox status code
882 * @param idxField VMCS index
883 * @param u32Val 32 bits value
884 */
885#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
886DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
887#else
888DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
889{
890 int rc = VINF_SUCCESS;
891# if RT_INLINE_ASM_GNU_STYLE
892 __asm__ __volatile__ (
893 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
894 "ja 2f \n\t"
895 "je 1f \n\t"
896 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
897 "jmp 2f \n\t"
898 "1: \n\t"
899 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
900 "2: \n\t"
901 :"=rm"(rc)
902 :"0"(VINF_SUCCESS),
903 "a"(idxField),
904 "d"(u32Val)
905 );
906# else
907 __asm
908 {
909 push dword ptr [u32Val]
910 mov eax, [idxField]
911 _emit 0x0F
912 _emit 0x79
913 _emit 0x04
914 _emit 0x24 /* VMWRITE eax, [esp] */
915 jnc valid_vmcs
916 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
917 jmp the_end
918
919valid_vmcs:
920 jnz the_end
921 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
922the_end:
923 add esp, 4
924 }
925# endif
926 return rc;
927}
928#endif
929
930#if HC_ARCH_BITS == 64
931#define VMXWriteVMCS VMXWriteVMCS64
932#else
933#define VMXWriteVMCS VMXWriteVMCS32
934#endif /* HC_ARCH_BITS == 64 */
935
936
937/**
938 * Executes VMREAD
939 *
940 * @returns VBox status code
941 * @param idxField VMCS index
942 * @param pData Ptr to store VM field value
943 */
944DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
945
946/**
947 * Executes VMREAD
948 *
949 * @returns VBox status code
950 * @param idxField VMCS index
951 * @param pData Ptr to store VM field value
952 */
953#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
954DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
955#else
956DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
957{
958 int rc = VINF_SUCCESS;
959# if RT_INLINE_ASM_GNU_STYLE
960 __asm__ __volatile__ (
961 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
962 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
963 "ja 2f \n\t"
964 "je 1f \n\t"
965 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
966 "jmp 2f \n\t"
967 "1: \n\t"
968 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
969 "2: \n\t"
970 :"=&r"(rc),
971 "=d"(*pData)
972 :"a"(idxField),
973 "d"(0)
974 );
975# else
976 __asm
977 {
978 sub esp, 4
979 mov dword ptr [esp], 0
980 mov eax, [idxField]
981 _emit 0x0F
982 _emit 0x78
983 _emit 0x04
984 _emit 0x24 /* VMREAD eax, [esp] */
985 mov edx, pData
986 pop dword ptr [edx]
987 jnc valid_vmcs
988 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
989 jmp the_end
990
991valid_vmcs:
992 jnz the_end
993 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
994the_end:
995 }
996# endif
997 return rc;
998}
999#endif
1000
1001#if HC_ARCH_BITS == 64
1002#define VMXReadVMCS VMXReadVMCS64
1003#else
1004#define VMXReadVMCS VMXReadVMCS32
1005#endif /* HC_ARCH_BITS == 64 */
1006
1007/**
1008 * Prepares for and executes VMLAUNCH
1009 *
1010 * @returns VBox status code
1011 * @param pCtx Guest context
1012 */
1013DECLASM(int) VMXStartVM(PCPUMCTX pCtx);
1014
1015/**
1016 * Prepares for and executes VMRESUME
1017 *
1018 * @returns VBox status code
1019 * @param pCtx Guest context
1020 */
1021DECLASM(int) VMXResumeVM(PCPUMCTX pCtx);
1022
1023/**
1024 * Gets the last instruction error value from the current VMCS
1025 *
1026 * @returns error value
1027 */
1028DECLINLINE(uint32_t) VMXGetLastError(void)
1029{
1030#if HC_ARCH_BITS == 64
1031 uint64_t uLastError = 0;
1032 int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1033 AssertRC(rc);
1034 return (uint32_t)uLastError;
1035
1036#else /* 32-bit host: */
1037 uint32_t lasterr = 0;
1038 int rc;
1039
1040 rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &lasterr);
1041 AssertRC(rc);
1042 return lasterr;
1043#endif
1044}
1045
1046/** @} */
1047
1048#endif
1049
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