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source: vbox/trunk/include/VBox/hwacc_vmx.h@ 22958

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1/** @file
2 * HWACCM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_vmx_h
31#define ___VBox_vmx_h
32
33#include <VBox/types.h>
34#include <VBox/err.h>
35#include <iprt/assert.h>
36#include <iprt/asm.h>
37#include <VBox/x86.h>
38
39/** @defgroup grp_vmx vmx Types and Definitions
40 * @ingroup grp_hwaccm
41 * @{
42 */
43
44/** @name VMX EPT paging structures
45 * @{
46 */
47
48/**
49 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
50 */
51#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
52
53/**
54 * EPT Page Directory Pointer Entry. Bit view.
55 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
56 * this did cause trouble with one compiler/version).
57 */
58#pragma pack(1)
59typedef struct EPTPML4EBITS
60{
61 /** Present bit. */
62 uint64_t u1Present : 1;
63 /** Writable bit. */
64 uint64_t u1Write : 1;
65 /** Executable bit. */
66 uint64_t u1Execute : 1;
67 /** Reserved (must be 0). */
68 uint64_t u5Reserved : 5;
69 /** Available for software. */
70 uint64_t u4Available : 4;
71 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
72 uint64_t u40PhysAddr : 40;
73 /** Availabe for software. */
74 uint64_t u12Available : 12;
75} EPTPML4EBITS;
76#pragma pack()
77AssertCompileSize(EPTPML4EBITS, 8);
78
79/** Bits 12-51 - - EPT - Physical Page number of the next level. */
80#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK_FULL
81/** The page shift to get the PML4 index. */
82#define EPT_PML4_SHIFT X86_PML4_SHIFT
83/** The PML4 index mask (apply to a shifted page address). */
84#define EPT_PML4_MASK X86_PML4_MASK
85
86/**
87 * EPT PML4E.
88 */
89#pragma pack(1)
90typedef union EPTPML4E
91{
92 /** Normal view. */
93 EPTPML4EBITS n;
94 /** Unsigned integer view. */
95 X86PGPAEUINT u;
96 /** 64 bit unsigned integer view. */
97 uint64_t au64[1];
98 /** 32 bit unsigned integer view. */
99 uint32_t au32[2];
100} EPTPML4E;
101#pragma pack()
102/** Pointer to a PML4 table entry. */
103typedef EPTPML4E *PEPTPML4E;
104/** Pointer to a const PML4 table entry. */
105typedef const EPTPML4E *PCEPTPML4E;
106AssertCompileSize(EPTPML4E, 8);
107
108/**
109 * EPT PML4 Table.
110 */
111#pragma pack(1)
112typedef struct EPTPML4
113{
114 EPTPML4E a[EPT_PG_ENTRIES];
115} EPTPML4;
116#pragma pack()
117/** Pointer to an EPT PML4 Table. */
118typedef EPTPML4 *PEPTPML4;
119/** Pointer to a const EPT PML4 Table. */
120typedef const EPTPML4 *PCEPTPML4;
121
122/**
123 * EPT Page Directory Pointer Entry. Bit view.
124 */
125#pragma pack(1)
126typedef struct EPTPDPTEBITS
127{
128 /** Present bit. */
129 uint64_t u1Present : 1;
130 /** Writable bit. */
131 uint64_t u1Write : 1;
132 /** Executable bit. */
133 uint64_t u1Execute : 1;
134 /** Reserved (must be 0). */
135 uint64_t u5Reserved : 5;
136 /** Available for software. */
137 uint64_t u4Available : 4;
138 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
139 uint64_t u40PhysAddr : 40;
140 /** Availabe for software. */
141 uint64_t u12Available : 12;
142} EPTPDPTEBITS;
143#pragma pack()
144AssertCompileSize(EPTPDPTEBITS, 8);
145
146/** Bits 12-51 - - EPT - Physical Page number of the next level. */
147#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK_FULL
148/** The page shift to get the PDPT index. */
149#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
150/** The PDPT index mask (apply to a shifted page address). */
151#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
152
153/**
154 * EPT Page Directory Pointer.
155 */
156#pragma pack(1)
157typedef union EPTPDPTE
158{
159 /** Normal view. */
160 EPTPDPTEBITS n;
161 /** Unsigned integer view. */
162 X86PGPAEUINT u;
163 /** 64 bit unsigned integer view. */
164 uint64_t au64[1];
165 /** 32 bit unsigned integer view. */
166 uint32_t au32[2];
167} EPTPDPTE;
168#pragma pack()
169/** Pointer to an EPT Page Directory Pointer Entry. */
170typedef EPTPDPTE *PEPTPDPTE;
171/** Pointer to a const EPT Page Directory Pointer Entry. */
172typedef const EPTPDPTE *PCEPTPDPTE;
173AssertCompileSize(EPTPDPTE, 8);
174
175/**
176 * EPT Page Directory Pointer Table.
177 */
178#pragma pack(1)
179typedef struct EPTPDPT
180{
181 EPTPDPTE a[EPT_PG_ENTRIES];
182} EPTPDPT;
183#pragma pack()
184/** Pointer to an EPT Page Directory Pointer Table. */
185typedef EPTPDPT *PEPTPDPT;
186/** Pointer to a const EPT Page Directory Pointer Table. */
187typedef const EPTPDPT *PCEPTPDPT;
188
189
190/**
191 * EPT Page Directory Table Entry. Bit view.
192 */
193#pragma pack(1)
194typedef struct EPTPDEBITS
195{
196 /** Present bit. */
197 uint64_t u1Present : 1;
198 /** Writable bit. */
199 uint64_t u1Write : 1;
200 /** Executable bit. */
201 uint64_t u1Execute : 1;
202 /** Reserved (must be 0). */
203 uint64_t u4Reserved : 4;
204 /** Big page (must be 0 here). */
205 uint64_t u1Big : 1;
206 /** Available for software. */
207 uint64_t u4Available : 4;
208 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
209 uint64_t u40PhysAddr : 40;
210 /** Availabe for software. */
211 uint64_t u12Available : 12;
212} EPTPDEBITS;
213#pragma pack()
214AssertCompileSize(EPTPDEBITS, 8);
215
216/** Bits 12-51 - - EPT - Physical Page number of the next level. */
217#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
218/** The page shift to get the PD index. */
219#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
220/** The PD index mask (apply to a shifted page address). */
221#define EPT_PD_MASK X86_PD_PAE_MASK
222
223/**
224 * EPT 2MB Page Directory Table Entry. Bit view.
225 */
226#pragma pack(1)
227typedef struct EPTPDE2MBITS
228{
229 /** Present bit. */
230 uint64_t u1Present : 1;
231 /** Writable bit. */
232 uint64_t u1Write : 1;
233 /** Executable bit. */
234 uint64_t u1Execute : 1;
235 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
236 uint64_t u3EMT : 3;
237 /** Ignore PAT memory type */
238 uint64_t u1IgnorePAT : 1;
239 /** Big page (must be 1 here). */
240 uint64_t u1Size : 1;
241 /** Available for software. */
242 uint64_t u4Available : 4;
243 /** Reserved (must be 0). */
244 uint64_t u9Reserved : 9;
245 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
246 uint64_t u31PhysAddr : 31;
247 /** Availabe for software. */
248 uint64_t u12Available : 12;
249} EPTPDE2MBITS;
250#pragma pack()
251AssertCompileSize(EPTPDE2MBITS, 8);
252
253/** Bits 21-51 - - EPT - Physical Page number of the next level. */
254#define EPT_PDE2M_PG_MASK ( 0x000fffffffe00000ULL )
255
256/**
257 * EPT Page Directory Table Entry.
258 */
259#pragma pack(1)
260typedef union EPTPDE
261{
262 /** Normal view. */
263 EPTPDEBITS n;
264 /** 2MB view (big). */
265 EPTPDE2MBITS b;
266 /** Unsigned integer view. */
267 X86PGPAEUINT u;
268 /** 64 bit unsigned integer view. */
269 uint64_t au64[1];
270 /** 32 bit unsigned integer view. */
271 uint32_t au32[2];
272} EPTPDE;
273#pragma pack()
274/** Pointer to an EPT Page Directory Table Entry. */
275typedef EPTPDE *PEPTPDE;
276/** Pointer to a const EPT Page Directory Table Entry. */
277typedef const EPTPDE *PCEPTPDE;
278AssertCompileSize(EPTPDE, 8);
279
280/**
281 * EPT Page Directory Table.
282 */
283#pragma pack(1)
284typedef struct EPTPD
285{
286 EPTPDE a[EPT_PG_ENTRIES];
287} EPTPD;
288#pragma pack()
289/** Pointer to an EPT Page Directory Table. */
290typedef EPTPD *PEPTPD;
291/** Pointer to a const EPT Page Directory Table. */
292typedef const EPTPD *PCEPTPD;
293
294
295/**
296 * EPT Page Table Entry. Bit view.
297 */
298#pragma pack(1)
299typedef struct EPTPTEBITS
300{
301 /** Present bit. */
302 uint64_t u1Present : 1;
303 /** Writable bit. */
304 uint64_t u1Write : 1;
305 /** Executable bit. */
306 uint64_t u1Execute : 1;
307 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
308 uint64_t u3EMT : 3;
309 /** Ignore PAT memory type */
310 uint64_t u1IgnorePAT : 1;
311 /** Available for software. */
312 uint64_t u5Available : 5;
313 /** Physical address of page. Restricted by maximum physical address width of the cpu. */
314 uint64_t u40PhysAddr : 40;
315 /** Availabe for software. */
316 uint64_t u12Available : 12;
317} EPTPTEBITS;
318#pragma pack()
319AssertCompileSize(EPTPTEBITS, 8);
320
321/** Bits 12-51 - - EPT - Physical Page number of the next level. */
322#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
323/** The page shift to get the EPT PTE index. */
324#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
325/** The EPT PT index mask (apply to a shifted page address). */
326#define EPT_PT_MASK X86_PT_PAE_MASK
327
328/**
329 * EPT Page Table Entry.
330 */
331#pragma pack(1)
332typedef union EPTPTE
333{
334 /** Normal view. */
335 EPTPTEBITS n;
336 /** Unsigned integer view. */
337 X86PGPAEUINT u;
338 /** 64 bit unsigned integer view. */
339 uint64_t au64[1];
340 /** 32 bit unsigned integer view. */
341 uint32_t au32[2];
342} EPTPTE;
343#pragma pack()
344/** Pointer to an EPT Page Directory Table Entry. */
345typedef EPTPTE *PEPTPTE;
346/** Pointer to a const EPT Page Directory Table Entry. */
347typedef const EPTPTE *PCEPTPTE;
348AssertCompileSize(EPTPTE, 8);
349
350/**
351 * EPT Page Table.
352 */
353#pragma pack(1)
354typedef struct EPTPT
355{
356 EPTPTE a[EPT_PG_ENTRIES];
357} EPTPT;
358#pragma pack()
359/** Pointer to an extended page table. */
360typedef EPTPT *PEPTPT;
361/** Pointer to a const extended table. */
362typedef const EPTPT *PCEPTPT;
363
364/**
365 * VPID and EPT flush types
366 */
367typedef enum
368{
369 /* Invalidate a specific page. */
370 VMX_FLUSH_PAGE = 0,
371 /* Invalidate one context (VPID or EPT) */
372 VMX_FLUSH_SINGLE_CONTEXT = 1,
373 /* Invalidate all contexts (VPIDs or EPTs) */
374 VMX_FLUSH_ALL_CONTEXTS = 2,
375 /* Invalidate a single VPID context retaining global mappings. */
376 VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL = 3,
377 /** 32bit hackishness. */
378 VMX_FLUSH_32BIT_HACK = 0x7fffffff
379} VMX_FLUSH;
380/** @} */
381
382/** @name MSR load/store elements
383 * @{
384 */
385#pragma pack(1)
386typedef struct
387{
388 uint32_t u32IndexMSR;
389 uint32_t u32Reserved;
390 uint64_t u64Value;
391} VMXMSR;
392#pragma pack()
393/** Pointer to an MSR load/store element. */
394typedef VMXMSR *PVMXMSR;
395/** Pointer to a const MSR load/store element. */
396typedef const VMXMSR *PCVMXMSR;
397
398/** @} */
399
400
401/** @name VMX Basic Exit Reasons.
402 * @{
403 */
404/** And-mask for setting reserved bits to zero */
405#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
406/** Or-mask for setting reserved bits to 1 */
407#define VMX_EFLAGS_RESERVED_1 0x00000002
408/** @} */
409
410/** @name VMX Basic Exit Reasons.
411 * @{
412 */
413/** -1 Invalid exit code */
414#define VMX_EXIT_INVALID -1
415/** 0 Exception or non-maskable interrupt (NMI). */
416#define VMX_EXIT_EXCEPTION 0
417/** 1 External interrupt. */
418#define VMX_EXIT_EXTERNAL_IRQ 1
419/** 2 Triple fault. */
420#define VMX_EXIT_TRIPLE_FAULT 2
421/** 3 INIT signal. */
422#define VMX_EXIT_INIT_SIGNAL 3
423/** 4 Start-up IPI (SIPI). */
424#define VMX_EXIT_SIPI 4
425/** 5 I/O system-management interrupt (SMI). */
426#define VMX_EXIT_IO_SMI_IRQ 5
427/** 6 Other SMI. */
428#define VMX_EXIT_SMI_IRQ 6
429/** 7 Interrupt window. */
430#define VMX_EXIT_IRQ_WINDOW 7
431/** 9 Task switch. */
432#define VMX_EXIT_TASK_SWITCH 9
433/** 10 Guest software attempted to execute CPUID. */
434#define VMX_EXIT_CPUID 10
435/** 12 Guest software attempted to execute HLT. */
436#define VMX_EXIT_HLT 12
437/** 13 Guest software attempted to execute INVD. */
438#define VMX_EXIT_INVD 13
439/** 14 Guest software attempted to execute INVPG. */
440#define VMX_EXIT_INVPG 14
441/** 15 Guest software attempted to execute RDPMC. */
442#define VMX_EXIT_RDPMC 15
443/** 16 Guest software attempted to execute RDTSC. */
444#define VMX_EXIT_RDTSC 16
445/** 17 Guest software attempted to execute RSM in SMM. */
446#define VMX_EXIT_RSM 17
447/** 18 Guest software executed VMCALL. */
448#define VMX_EXIT_VMCALL 18
449/** 19 Guest software executed VMCLEAR. */
450#define VMX_EXIT_VMCLEAR 19
451/** 20 Guest software executed VMLAUNCH. */
452#define VMX_EXIT_VMLAUNCH 20
453/** 21 Guest software executed VMPTRLD. */
454#define VMX_EXIT_VMPTRLD 21
455/** 22 Guest software executed VMPTRST. */
456#define VMX_EXIT_VMPTRST 22
457/** 23 Guest software executed VMREAD. */
458#define VMX_EXIT_VMREAD 23
459/** 24 Guest software executed VMRESUME. */
460#define VMX_EXIT_VMRESUME 24
461/** 25 Guest software executed VMWRITE. */
462#define VMX_EXIT_VMWRITE 25
463/** 26 Guest software executed VMXOFF. */
464#define VMX_EXIT_VMXOFF 26
465/** 27 Guest software executed VMXON. */
466#define VMX_EXIT_VMXON 27
467/** 28 Control-register accesses. */
468#define VMX_EXIT_CRX_MOVE 28
469/** 29 Debug-register accesses. */
470#define VMX_EXIT_DRX_MOVE 29
471/** 30 I/O instruction. */
472#define VMX_EXIT_PORT_IO 30
473/** 31 RDMSR. Guest software attempted to execute RDMSR. */
474#define VMX_EXIT_RDMSR 31
475/** 32 WRMSR. Guest software attempted to execute WRMSR. */
476#define VMX_EXIT_WRMSR 32
477/** 33 VM-entry failure due to invalid guest state. */
478#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
479/** 34 VM-entry failure due to MSR loading. */
480#define VMX_EXIT_ERR_MSR_LOAD 34
481/** 36 Guest software executed MWAIT. */
482#define VMX_EXIT_MWAIT 36
483/** 39 Guest software attempted to execute MONITOR. */
484#define VMX_EXIT_MONITOR 39
485/** 40 Guest software attempted to execute PAUSE. */
486#define VMX_EXIT_PAUSE 40
487/** 41 VM-entry failure due to machine-check. */
488#define VMX_EXIT_ERR_MACHINE_CHECK 41
489/** 43 TPR below threshold. Guest software executed MOV to CR8. */
490#define VMX_EXIT_TPR 43
491/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
492#define VMX_EXIT_APIC_ACCESS 44
493/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
494#define VMX_EXIT_XDTR_ACCESS 46
495/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
496#define VMX_EXIT_TR_ACCESS 47
497/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
498#define VMX_EXIT_EPT_VIOLATION 48
499/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
500#define VMX_EXIT_EPT_MISCONFIG 49
501/** 50 INVEPT. Guest software attempted to execute INVEPT. */
502#define VMX_EXIT_INVEPT 50
503/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
504#define VMX_EXIT_PREEMPTION_TIMER 52
505/** 53 INVVPID. Guest software attempted to execute INVVPID. */
506#define VMX_EXIT_INVVPID 53
507/** 54 WBINVD. Guest software attempted to execute WBINVD. */
508#define VMX_EXIT_WBINVD 54
509/** 55 XSETBV. Guest software attempted to execute XSETBV. */
510#define VMX_EXIT_XSETBV 55
511/** @} */
512
513
514/** @name VM Instruction Errors
515 * @{
516 */
517/** 1 VMCALL executed in VMX root operation. */
518#define VMX_ERROR_VMCALL 1
519/** 2 VMCLEAR with invalid physical address. */
520#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
521/** 3 VMCLEAR with VMXON pointer. */
522#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
523/** 4 VMLAUNCH with non-clear VMCS. */
524#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
525/** 5 VMRESUME with non-launched VMCS. */
526#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
527/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
528#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
529/** 7 VM entry with invalid control field(s). */
530#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
531/** 8 VM entry with invalid host-state field(s). */
532#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
533/** 9 VMPTRLD with invalid physical address. */
534#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
535/** 10 VMPTRLD with VMXON pointer. */
536#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
537/** 11 VMPTRLD with incorrect VMCS revision identifier. */
538#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
539/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
540#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
541#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
542/** 13 VMWRITE to read-only VMCS component. */
543#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
544/** 15 VMXON executed in VMX root operation. */
545#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
546/** 16 VM entry with invalid executive-VMCS pointer. */
547#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
548/** 17 VM entry with non-launched executive VMCS. */
549#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
550/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
551#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
552/** 19 VMCALL with non-clear VMCS. */
553#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
554/** 20 VMCALL with invalid VM-exit control fields. */
555#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
556/** 22 VMCALL with incorrect MSEG revision identifier. */
557#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
558/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
559#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
560/** 24 VMCALL with invalid SMM-monitor features. */
561#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
562/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
563#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
564/** 26 VM entry with events blocked by MOV SS. */
565#define VMX_ERROR_VMENTRY_MOV_SS 26
566/** 26 Invalid operand to INVEPT/INVVPID. */
567#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
568
569/** @} */
570
571
572/** @name VMX MSRs - Basic VMX information.
573 * @{
574 */
575/** VMCS revision identifier used by the processor. */
576#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
577/** Size of the VMCS. */
578#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
579/** Width of physical address used for the VMCS.
580 * 0 -> limited to the available amount of physical ram
581 * 1 -> within the first 4 GB
582 */
583#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
584/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
585#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
586/** Memory type that must be used for the VMCS. */
587#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
588/** @} */
589
590
591/** @name VMX MSRs - Misc VMX info.
592 * @{
593 */
594/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
595#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) (a & 0x1f)
596/** Activity states supported by the implementation. */
597#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
598/** Number of CR3 target values supported by the processor. (0-256) */
599#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
600/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
601#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
602/** MSEG revision identifier used by the processor. */
603#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
604/** @} */
605
606
607/** @name VMX MSRs - VMCS enumeration field info
608 * @{
609 */
610/** Highest field index. */
611#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
612
613/** @} */
614
615
616/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
617 * @{
618 */
619#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
620#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
621#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
622#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
623#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
624#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
625#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
626#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
627#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
628#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
629#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
630#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
631#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
632#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
633#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
634#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
635#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
636#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
637#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
638#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
639#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
640#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
641#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
642#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
643#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
644#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
645
646/** @} */
647
648/** @name Extended Page Table Pointer (EPTP)
649 * @{
650 */
651/** Uncachable EPT paging structure memory type. */
652#define VMX_EPT_MEMTYPE_UC 0
653/** Write-back EPT paging structure memory type. */
654#define VMX_EPT_MEMTYPE_WB 6
655/** Shift value to get the EPT page walk length (bits 5-3) */
656#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
657/** Mask value to get the EPT page walk length (bits 5-3) */
658#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
659/** Default EPT page walk length */
660#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
661/** @} */
662
663
664/** @name VMCS field encoding - 16 bits guest fields
665 * @{
666 */
667#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
668#define VMX_VMCS16_GUEST_FIELD_ES 0x800
669#define VMX_VMCS16_GUEST_FIELD_CS 0x802
670#define VMX_VMCS16_GUEST_FIELD_SS 0x804
671#define VMX_VMCS16_GUEST_FIELD_DS 0x806
672#define VMX_VMCS16_GUEST_FIELD_FS 0x808
673#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
674#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
675#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
676/** @} */
677
678/** @name VMCS field encoding - 16 bits host fields
679 * @{
680 */
681#define VMX_VMCS16_HOST_FIELD_ES 0xC00
682#define VMX_VMCS16_HOST_FIELD_CS 0xC02
683#define VMX_VMCS16_HOST_FIELD_SS 0xC04
684#define VMX_VMCS16_HOST_FIELD_DS 0xC06
685#define VMX_VMCS16_HOST_FIELD_FS 0xC08
686#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
687#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
688/** @} */
689
690/** @name VMCS field encoding - 64 bits host fields
691 * @{
692 */
693#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
694#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
695#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
696#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
697#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
698#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
699/** @} */
700
701
702/** @name VMCS field encoding - 64 Bits control fields
703 * @{
704 */
705#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
706#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
707#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
708#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
709
710/* Optional */
711#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
712#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
713
714#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
715#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
716#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
717#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
718
719#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
720#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
721
722#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
723#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
724
725#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
726#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
727
728/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
729#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
730#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
731
732/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
733#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
734#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
735
736/** Extended page table pointer. */
737#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
738#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
739
740/** VM-exit phyiscal address. */
741#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
742#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
743/** @} */
744
745
746/** @name VMCS field encoding - 64 Bits guest fields
747 * @{
748 */
749#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
750#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
751#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
752#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
753#define VMX_VMCS_GUEST_PAT_FULL 0x2804
754#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
755#define VMX_VMCS_GUEST_EFER_FULL 0x2806
756#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
757#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
758#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
759#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
760#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
761#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
762#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
763#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
764#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
765#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
766#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
767/** @} */
768
769
770/** @name VMCS field encoding - 32 Bits control fields
771 * @{
772 */
773#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
774#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
775#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
776#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
777#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
778#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
779#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
780#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
781#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
782#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
783#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
784#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
785#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
786#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
787/** This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control. */
788#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
789/** This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control. */
790#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
791/** @} */
792
793
794/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
795 * @{
796 */
797/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
798#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
799/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
800#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
801/** Virtual NMIs. */
802#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI RT_BIT(5)
803/** Activate VMX preemption timer. */
804#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER RT_BIT(6)
805/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
806/** @} */
807
808/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
809 * @{
810 */
811/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
812#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
813/** Use timestamp counter offset. */
814#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
815/** VM Exit when executing the HLT instruction. */
816#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
817/** VM Exit when executing the INVLPG instruction. */
818#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
819/** VM Exit when executing the MWAIT instruction. */
820#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
821/** VM Exit when executing the RDPMC instruction. */
822#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
823/** VM Exit when executing the RDTSC instruction. */
824#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
825/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
826#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
827/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
828#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
829/** VM Exit on CR8 loads. */
830#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
831/** VM Exit on CR8 stores. */
832#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
833/** Use TPR shadow. */
834#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
835/** VM Exit when virtual nmi blocking is disabled. */
836#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT RT_BIT(22)
837/** VM Exit when executing a MOV DRx instruction. */
838#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
839/** VM Exit when executing IO instructions. */
840#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
841/** Use IO bitmaps. */
842#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
843/** Monitor trap flag. */
844#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
845/** Use MSR bitmaps. */
846#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
847/** VM Exit when executing the MONITOR instruction. */
848#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
849/** VM Exit when executing the PAUSE instruction. */
850#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
851/** Determines whether the secondary processor based VM-execution controls are used. */
852#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
853/** @} */
854
855/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
856 * @{
857 */
858/** Virtualize APIC access. */
859#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
860/** EPT supported/enabled. */
861#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
862/** Descriptor table instructions cause VM-exits. */
863#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT RT_BIT(2)
864/** Virtualize x2APIC mode. */
865#define VMX_VMCS_CTRL_PROC_EXEC2_X2APIC RT_BIT(4)
866/** VPID supported/enabled. */
867#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
868/** VM Exit when executing the WBINVD instruction. */
869#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
870/** @} */
871
872
873/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
874 * @{
875 */
876/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
877#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
878/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
879#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
880/** In SMM mode after VM-entry. */
881#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
882/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
883#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
884/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
885#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
886/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
887#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
888/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
889#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
890/** @} */
891
892
893/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
894 * @{
895 */
896/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
897#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
898/** Return to long mode after a VM-exit. */
899#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
900/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
901#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
902/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
903#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
904/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
905#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
906/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
907#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
908/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
909#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
910/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
911#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
912/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
913#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
914/** @} */
915
916/** @name VMCS field encoding - 32 Bits read-only fields
917 * @{
918 */
919#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
920#define VMX_VMCS32_RO_EXIT_REASON 0x4402
921#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
922#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
923#define VMX_VMCS32_RO_IDT_INFO 0x4408
924#define VMX_VMCS32_RO_IDT_ERRCODE 0x440A
925#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
926#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
927/** @} */
928
929/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
930 * @{
931 */
932#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
933#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
934#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
935#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
936#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
937#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
938#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
939#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
940/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
941#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
942/** @} */
943
944/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
945 * @{
946 */
947#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
948#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
949#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
950#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /**< int xx */
951#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT 5 /**< Why are we getting this one?? */
952#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
953/** @} */
954
955
956/** @name VMCS field encoding - 32 Bits guest state fields
957 * @{
958 */
959#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
960#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
961#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
962#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
963#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
964#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
965#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
966#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
967#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
968#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
969#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
970#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
971#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
972#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
973#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
974#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
975#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
976#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
977#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
978#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
979#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
980#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
981/** @} */
982
983
984/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
985 * @{
986 */
987/** The logical processor is active. */
988#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
989/** The logical processor is inactive, because executed a HLT instruction. */
990#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
991/** The logical processor is inactive, because of a triple fault or other serious error. */
992#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
993/** The logical processor is inactive, because it's waiting for a startup-IPI */
994#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
995/** @} */
996
997
998/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
999 * @{
1000 */
1001#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1002#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1003#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1004#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1005/** @} */
1006
1007
1008/** @name VMCS field encoding - 32 Bits host state fields
1009 * @{
1010 */
1011#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1012/** @} */
1013
1014/** @name Natural width control fields
1015 * @{
1016 */
1017#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1018#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1019#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1020#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1021#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1022#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1023#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1024#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1025/** @} */
1026
1027
1028/** @name Natural width read-only data fields
1029 * @{
1030 */
1031#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1032#define VMX_VMCS_RO_IO_RCX 0x6402
1033#define VMX_VMCS_RO_IO_RSX 0x6404
1034#define VMX_VMCS_RO_IO_RDI 0x6406
1035#define VMX_VMCS_RO_IO_RIP 0x6408
1036#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
1037/** @} */
1038
1039
1040/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1041 * @{
1042 */
1043/** 0-2: Debug register number */
1044#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1045/** 3: Reserved; cleared to 0. */
1046#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1047/** 4: Direction of move (0 = write, 1 = read) */
1048#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1049/** 5-7: Reserved; cleared to 0. */
1050#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1051/** 8-11: General purpose register number. */
1052#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1053/** Rest: reserved. */
1054/** @} */
1055
1056/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1057 * @{
1058 */
1059#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1060#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1061/** @} */
1062
1063
1064
1065/** @name CRx accesses
1066 * @{
1067 */
1068/** 0-3: Control register number (0 for CLTS & LMSW) */
1069#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1070/** 4-5: Access type. */
1071#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1072/** 6: LMSW operand type */
1073#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1074/** 7: Reserved; cleared to 0. */
1075#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1076/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1077#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1078/** 12-15: Reserved; cleared to 0. */
1079#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1080/** 16-31: LMSW source data (else 0). */
1081#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1082/** Rest: reserved. */
1083/** @} */
1084
1085/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1086 * @{
1087 */
1088#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1089#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1090#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1091#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1092/** @} */
1093
1094
1095/** @name VMX_EXIT_EPT_VIOLATION
1096 * @{
1097 */
1098/** Set if the violation was caused by a data read. */
1099#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1100/** Set if the violation was caused by a data write. */
1101#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1102/** Set if the violation was caused by an insruction fetch. */
1103#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1104/** AND of the present bit of all EPT structures. */
1105#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1106/** AND of the write bit of all EPT structures. */
1107#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1108/** AND of the execute bit of all EPT structures. */
1109#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1110/** Set if the guest linear address field contains the faulting address. */
1111#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1112/** If bit 7 is one: (reserved otherwise)
1113 * 1 - violation due to physical address access.
1114 * 0 - violation caused by page walk or access/dirty bit updates
1115 */
1116#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1117/** @} */
1118
1119
1120/** @name VMX_EXIT_PORT_IO
1121 * @{
1122 */
1123/** 0-2: IO operation width. */
1124#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1125/** 3: IO operation direction. */
1126#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1127/** 4: String IO operation. */
1128#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1129/** 5: Repeated IO operation. */
1130#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1131/** 6: Operand encoding. */
1132#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1133/** 16-31: IO Port (0-0xffff). */
1134#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1135/* Rest reserved. */
1136/** @} */
1137
1138/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1139 * @{
1140 */
1141#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1142#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1143/** @} */
1144
1145
1146/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1147 * @{
1148 */
1149#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1150#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1151/** @} */
1152
1153/** @name VMX_EXIT_APIC_ACCESS
1154 * @{
1155 */
1156/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1157#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) (a & 0xfff)
1158/** 12-15: Access type. */
1159#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a >> 12) & 0xf)
1160/* Rest reserved. */
1161/** @} */
1162
1163
1164/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1165 * @{
1166 */
1167/** Linear read access. */
1168#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1169/** Linear write access. */
1170#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1171/** Linear instruction fetch access. */
1172#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1173/** Linear read/write access during event delivery. */
1174#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1175/** Physical read/write access during event delivery. */
1176#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1177/** Physical access for an instruction fetch or during instruction execution. */
1178#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1179/** @} */
1180
1181/** @} */
1182
1183/** @name VMCS field encoding - Natural width guest state fields
1184 * @{
1185 */
1186#define VMX_VMCS64_GUEST_CR0 0x6800
1187#define VMX_VMCS64_GUEST_CR3 0x6802
1188#define VMX_VMCS64_GUEST_CR4 0x6804
1189#define VMX_VMCS64_GUEST_ES_BASE 0x6806
1190#define VMX_VMCS64_GUEST_CS_BASE 0x6808
1191#define VMX_VMCS64_GUEST_SS_BASE 0x680A
1192#define VMX_VMCS64_GUEST_DS_BASE 0x680C
1193#define VMX_VMCS64_GUEST_FS_BASE 0x680E
1194#define VMX_VMCS64_GUEST_GS_BASE 0x6810
1195#define VMX_VMCS64_GUEST_LDTR_BASE 0x6812
1196#define VMX_VMCS64_GUEST_TR_BASE 0x6814
1197#define VMX_VMCS64_GUEST_GDTR_BASE 0x6816
1198#define VMX_VMCS64_GUEST_IDTR_BASE 0x6818
1199#define VMX_VMCS64_GUEST_DR7 0x681A
1200#define VMX_VMCS64_GUEST_RSP 0x681C
1201#define VMX_VMCS64_GUEST_RIP 0x681E
1202#define VMX_VMCS_GUEST_RFLAGS 0x6820
1203#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1204#define VMX_VMCS64_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1205#define VMX_VMCS64_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1206/** @} */
1207
1208
1209/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1210 * @{
1211 */
1212/** Hardware breakpoint 0 was met. */
1213#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1214/** Hardware breakpoint 1 was met. */
1215#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1216/** Hardware breakpoint 2 was met. */
1217#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1218/** Hardware breakpoint 3 was met. */
1219#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1220/** At least one data or IO breakpoint was hit. */
1221#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1222/** A debug exception would have been triggered by single-step execution mode. */
1223#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1224/** Bits 4-11, 13 and 15-63 are reserved. */
1225
1226/** @} */
1227
1228/** @name VMCS field encoding - Natural width host state fields
1229 * @{
1230 */
1231#define VMX_VMCS_HOST_CR0 0x6C00
1232#define VMX_VMCS_HOST_CR3 0x6C02
1233#define VMX_VMCS_HOST_CR4 0x6C04
1234#define VMX_VMCS_HOST_FS_BASE 0x6C06
1235#define VMX_VMCS_HOST_GS_BASE 0x6C08
1236#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1237#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1238#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1239#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1240#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1241#define VMX_VMCS_HOST_RSP 0x6C14
1242#define VMX_VMCS_HOST_RIP 0x6C16
1243/** @} */
1244
1245/** @} */
1246
1247
1248#if RT_INLINE_ASM_GNU_STYLE
1249# define __STR(x) #x
1250# define STR(x) __STR(x)
1251#endif
1252
1253
1254/** @defgroup grp_vmx_asm vmx assembly helpers
1255 * @ingroup grp_vmx
1256 * @{
1257 */
1258
1259/**
1260 * Executes VMXON
1261 *
1262 * @returns VBox status code
1263 * @param pVMXOn Physical address of VMXON structure
1264 */
1265#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1266DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1267#else
1268DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1269{
1270 int rc = VINF_SUCCESS;
1271# if RT_INLINE_ASM_GNU_STYLE
1272 __asm__ __volatile__ (
1273 "push %3 \n\t"
1274 "push %2 \n\t"
1275 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1276 "ja 2f \n\t"
1277 "je 1f \n\t"
1278 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1279 "jmp 2f \n\t"
1280 "1: \n\t"
1281 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1282 "2: \n\t"
1283 "add $8, %%esp \n\t"
1284 :"=rm"(rc)
1285 :"0"(VINF_SUCCESS),
1286 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1287 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1288 :"memory"
1289 );
1290# else
1291 __asm
1292 {
1293 push dword ptr [pVMXOn+4]
1294 push dword ptr [pVMXOn]
1295 _emit 0xF3
1296 _emit 0x0F
1297 _emit 0xC7
1298 _emit 0x34
1299 _emit 0x24 /* VMXON [esp] */
1300 jnc vmxon_good
1301 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1302 jmp the_end
1303
1304vmxon_good:
1305 jnz the_end
1306 mov dword ptr [rc], VERR_VMX_GENERIC
1307the_end:
1308 add esp, 8
1309 }
1310# endif
1311 return rc;
1312}
1313#endif
1314
1315
1316/**
1317 * Executes VMXOFF
1318 */
1319#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1320DECLASM(void) VMXDisable(void);
1321#else
1322DECLINLINE(void) VMXDisable(void)
1323{
1324# if RT_INLINE_ASM_GNU_STYLE
1325 __asm__ __volatile__ (
1326 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1327 );
1328# else
1329 __asm
1330 {
1331 _emit 0x0F
1332 _emit 0x01
1333 _emit 0xC4 /* VMXOFF */
1334 }
1335# endif
1336}
1337#endif
1338
1339
1340/**
1341 * Executes VMCLEAR
1342 *
1343 * @returns VBox status code
1344 * @param pVMCS Physical address of VM control structure
1345 */
1346#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1347DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1348#else
1349DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1350{
1351 int rc = VINF_SUCCESS;
1352# if RT_INLINE_ASM_GNU_STYLE
1353 __asm__ __volatile__ (
1354 "push %3 \n\t"
1355 "push %2 \n\t"
1356 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1357 "jnc 1f \n\t"
1358 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1359 "1: \n\t"
1360 "add $8, %%esp \n\t"
1361 :"=rm"(rc)
1362 :"0"(VINF_SUCCESS),
1363 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1364 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1365 :"memory"
1366 );
1367# else
1368 __asm
1369 {
1370 push dword ptr [pVMCS+4]
1371 push dword ptr [pVMCS]
1372 _emit 0x66
1373 _emit 0x0F
1374 _emit 0xC7
1375 _emit 0x34
1376 _emit 0x24 /* VMCLEAR [esp] */
1377 jnc success
1378 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1379success:
1380 add esp, 8
1381 }
1382# endif
1383 return rc;
1384}
1385#endif
1386
1387
1388/**
1389 * Executes VMPTRLD
1390 *
1391 * @returns VBox status code
1392 * @param pVMCS Physical address of VMCS structure
1393 */
1394#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1395DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1396#else
1397DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1398{
1399 int rc = VINF_SUCCESS;
1400# if RT_INLINE_ASM_GNU_STYLE
1401 __asm__ __volatile__ (
1402 "push %3 \n\t"
1403 "push %2 \n\t"
1404 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1405 "jnc 1f \n\t"
1406 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1407 "1: \n\t"
1408 "add $8, %%esp \n\t"
1409 :"=rm"(rc)
1410 :"0"(VINF_SUCCESS),
1411 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1412 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1413 );
1414# else
1415 __asm
1416 {
1417 push dword ptr [pVMCS+4]
1418 push dword ptr [pVMCS]
1419 _emit 0x0F
1420 _emit 0xC7
1421 _emit 0x34
1422 _emit 0x24 /* VMPTRLD [esp] */
1423 jnc success
1424 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1425
1426success:
1427 add esp, 8
1428 }
1429# endif
1430 return rc;
1431}
1432#endif
1433
1434/**
1435 * Executes VMPTRST
1436 *
1437 * @returns VBox status code
1438 * @param pVMCS Address that will receive the current pointer
1439 */
1440DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1441
1442/**
1443 * Executes VMWRITE
1444 *
1445 * @returns VBox status code
1446 * @param idxField VMCS index
1447 * @param u32Val 32 bits value
1448 */
1449#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1450DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1451#else
1452DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1453{
1454 int rc = VINF_SUCCESS;
1455# if RT_INLINE_ASM_GNU_STYLE
1456 __asm__ __volatile__ (
1457 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1458 "ja 2f \n\t"
1459 "je 1f \n\t"
1460 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1461 "jmp 2f \n\t"
1462 "1: \n\t"
1463 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1464 "2: \n\t"
1465 :"=rm"(rc)
1466 :"0"(VINF_SUCCESS),
1467 "a"(idxField),
1468 "d"(u32Val)
1469 );
1470# else
1471 __asm
1472 {
1473 push dword ptr [u32Val]
1474 mov eax, [idxField]
1475 _emit 0x0F
1476 _emit 0x79
1477 _emit 0x04
1478 _emit 0x24 /* VMWRITE eax, [esp] */
1479 jnc valid_vmcs
1480 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1481 jmp the_end
1482
1483valid_vmcs:
1484 jnz the_end
1485 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1486the_end:
1487 add esp, 4
1488 }
1489# endif
1490 return rc;
1491}
1492#endif
1493
1494/**
1495 * Executes VMWRITE
1496 *
1497 * @returns VBox status code
1498 * @param idxField VMCS index
1499 * @param u64Val 16, 32 or 64 bits value
1500 */
1501#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1502DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1503#else
1504VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1505
1506#define VMXWriteVMCS64(idxField, u64Val) VMXWriteVMCS64Ex(pVCpu, idxField, u64Val)
1507#endif
1508
1509#if HC_ARCH_BITS == 64
1510#define VMXWriteVMCS VMXWriteVMCS64
1511#else
1512#define VMXWriteVMCS VMXWriteVMCS32
1513#endif /* HC_ARCH_BITS == 64 */
1514
1515
1516/**
1517 * Invalidate a page using invept
1518 * @returns VBox status code
1519 * @param enmFlush Type of flush
1520 * @param pDescriptor Descriptor
1521 */
1522DECLASM(int) VMXR0InvEPT(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1523
1524/**
1525 * Invalidate a page using invvpid
1526 * @returns VBox status code
1527 * @param enmFlush Type of flush
1528 * @param pDescriptor Descriptor
1529 */
1530DECLASM(int) VMXR0InvVPID(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1531
1532/**
1533 * Executes VMREAD
1534 *
1535 * @returns VBox status code
1536 * @param idxField VMCS index
1537 * @param pData Ptr to store VM field value
1538 */
1539#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1540DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1541#else
1542DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1543{
1544 int rc = VINF_SUCCESS;
1545# if RT_INLINE_ASM_GNU_STYLE
1546 __asm__ __volatile__ (
1547 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
1548 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1549 "ja 2f \n\t"
1550 "je 1f \n\t"
1551 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1552 "jmp 2f \n\t"
1553 "1: \n\t"
1554 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1555 "2: \n\t"
1556 :"=&r"(rc),
1557 "=d"(*pData)
1558 :"a"(idxField),
1559 "d"(0)
1560 );
1561# else
1562 __asm
1563 {
1564 sub esp, 4
1565 mov dword ptr [esp], 0
1566 mov eax, [idxField]
1567 _emit 0x0F
1568 _emit 0x78
1569 _emit 0x04
1570 _emit 0x24 /* VMREAD eax, [esp] */
1571 mov edx, pData
1572 pop dword ptr [edx]
1573 jnc valid_vmcs
1574 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1575 jmp the_end
1576
1577valid_vmcs:
1578 jnz the_end
1579 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1580the_end:
1581 }
1582# endif
1583 return rc;
1584}
1585#endif
1586
1587/**
1588 * Executes VMREAD
1589 *
1590 * @returns VBox status code
1591 * @param idxField VMCS index
1592 * @param pData Ptr to store VM field value
1593 */
1594#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1595DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1596#else
1597DECLINLINE(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData)
1598{
1599 int rc;
1600
1601 uint32_t val_hi, val;
1602 rc = VMXReadVMCS32(idxField, &val);
1603 rc |= VMXReadVMCS32(idxField + 1, &val_hi);
1604 AssertRC(rc);
1605 *pData = RT_MAKE_U64(val, val_hi);
1606 return rc;
1607}
1608#endif
1609
1610#if HC_ARCH_BITS == 64
1611# define VMXReadVMCS VMXReadVMCS64
1612#else
1613# define VMXReadVMCS VMXReadVMCS32
1614#endif /* HC_ARCH_BITS == 64 */
1615
1616/**
1617 * Gets the last instruction error value from the current VMCS
1618 *
1619 * @returns error value
1620 */
1621DECLINLINE(uint32_t) VMXGetLastError(void)
1622{
1623#if HC_ARCH_BITS == 64
1624 uint64_t uLastError = 0;
1625 int rc = VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1626 AssertRC(rc);
1627 return (uint32_t)uLastError;
1628
1629#else /* 32-bit host: */
1630 uint32_t uLastError = 0;
1631 int rc = VMXReadVMCS32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1632 AssertRC(rc);
1633 return uLastError;
1634#endif
1635}
1636
1637#ifdef IN_RING0
1638VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1639VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1640#endif /* IN_RING0 */
1641
1642/** @} */
1643
1644#endif
1645
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