hwacc_vmx.h@ 13469

Last change on this file since 13469 was 13203, checked in by vboxsync, 16 years ago
Missing shadow cases for EPT.
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1	/** @file
2	* HWACCM - VMX Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	#ifndef ___VBox_vmx_h
31	#define ___VBox_vmx_h
32
33	#include <VBox/types.h>
34	#include <VBox/err.h>
35	#include <iprt/assert.h>
36	#include <iprt/asm.h>
37
38	/** @defgroup grp_vmx vmx Types and Definitions
39	* @ingroup grp_hwaccm
40	* @{
41	*/
42
43	/** @name VMX EPT paging structures
44	* @{
45	*/
46
47	/**
48	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
49	*/
50	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
51
52	/**
53	* EPT Page Directory Pointer Entry. Bit view.
54	*/
55	#pragma pack(1)
56	typedef struct EPTPML4EBITS
57	{
58	/** Present bit. */
59	uint64_t u1Present : 1;
60	/** Writable bit. */
61	uint64_t u1Write : 1;
62	/** Executable bit. */
63	uint64_t u1Execute : 1;
64	/** Reserved (must be 0). */
65	uint64_t u5Reserved : 5;
66	/** Available for software. */
67	uint64_t u4Available : 4;
68	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
69	uint64_t u40PhysAddr : 40;
70	/** Availabe for software. */
71	uint64_t u12Available : 12;
72	} EPTPML4EBITS;
73	#pragma pack()
74	AssertCompileSize(EPTPML4EBITS, 8);
75
76	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
77	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK_FULL
78	/** The page shift to get the PML4 index. */
79	#define EPT_PML4_SHIFT X86_PML4_SHIFT
80	/** The PML4 index mask (apply to a shifted page address). */
81	#define EPT_PML4_MASK X86_PML4_MASK
82
83	/**
84	* EPT PML4E.
85	*/
86	#pragma pack(1)
87	typedef union EPTPML4E
88	{
89	/** Normal view. */
90	EPTPML4EBITS n;
91	/** Unsigned integer view. */
92	X86PGPAEUINT u;
93	/** 64 bit unsigned integer view. */
94	uint64_t au64[1];
95	/** 32 bit unsigned integer view. */
96	uint32_t au32[2];
97	} EPTPML4E;
98	#pragma pack()
99	/** Pointer to a PML4 table entry. */
100	typedef EPTPML4E *PEPTPML4E;
101	/** Pointer to a const PML4 table entry. */
102	typedef const EPTPML4E *PCEPTPML4E;
103	AssertCompileSize(EPTPML4E, 8);
104
105	/**
106	* EPT PML4 Table.
107	*/
108	#pragma pack(1)
109	typedef struct EPTPML4
110	{
111	EPTPML4E a[EPT_PG_ENTRIES];
112	} EPTPML4;
113	#pragma pack()
114	/** Pointer to an EPT PML4 Table. */
115	typedef EPTPML4 *PEPTPML4;
116	/** Pointer to a const EPT PML4 Table. */
117	typedef const EPTPML4 *PCEPTPML4;
118
119	/**
120	* EPT Page Directory Pointer Entry. Bit view.
121	*/
122	#pragma pack(1)
123	typedef struct EPTPDPTEBITS
124	{
125	/** Present bit. */
126	uint64_t u1Present : 1;
127	/** Writable bit. */
128	uint64_t u1Write : 1;
129	/** Executable bit. */
130	uint64_t u1Execute : 1;
131	/** Reserved (must be 0). */
132	uint64_t u5Reserved : 5;
133	/** Available for software. */
134	uint64_t u4Available : 4;
135	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
136	uint64_t u40PhysAddr : 40;
137	/** Availabe for software. */
138	uint64_t u12Available : 12;
139	} EPTPDPTEBITS;
140	#pragma pack()
141	AssertCompileSize(EPTPDPTEBITS, 8);
142
143	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
144	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK_FULL
145	/** The page shift to get the PDPT index. */
146	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
147	/** The PDPT index mask (apply to a shifted page address). */
148	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
149
150	/**
151	* EPT Page Directory Pointer.
152	*/
153	#pragma pack(1)
154	typedef union EPTPDPTE
155	{
156	/** Normal view. */
157	EPTPDPTEBITS n;
158	/** Unsigned integer view. */
159	X86PGPAEUINT u;
160	/** 64 bit unsigned integer view. */
161	uint64_t au64[1];
162	/** 32 bit unsigned integer view. */
163	uint32_t au32[2];
164	} EPTPDPTE;
165	#pragma pack()
166	/** Pointer to an EPT Page Directory Pointer Entry. */
167	typedef EPTPDPTE *PEPTPDPTE;
168	/** Pointer to a const EPT Page Directory Pointer Entry. */
169	typedef const EPTPDPTE *PCEPTPDPTE;
170	AssertCompileSize(EPTPDPTE, 8);
171
172	/**
173	* EPT Page Directory Pointer Table.
174	*/
175	#pragma pack(1)
176	typedef struct EPTPDPT
177	{
178	EPTPDPTE a[EPT_PG_ENTRIES];
179	} EPTPDPT;
180	#pragma pack()
181	/** Pointer to an EPT Page Directory Pointer Table. */
182	typedef EPTPDPT *PEPTPDPT;
183	/** Pointer to a const EPT Page Directory Pointer Table. */
184	typedef const EPTPDPT *PCEPTPDPT;
185
186
187	/**
188	* EPT Page Directory Table Entry. Bit view.
189	*/
190	#pragma pack(1)
191	typedef struct EPTPDEBITS
192	{
193	/** Present bit. */
194	uint64_t u1Present : 1;
195	/** Writable bit. */
196	uint64_t u1Write : 1;
197	/** Executable bit. */
198	uint64_t u1Execute : 1;
199	/** Reserved (must be 0). */
200	uint64_t u4Reserved : 4;
201	/** Big page (must be 0 here). */
202	uint64_t u1Big : 1;
203	/** Available for software. */
204	uint64_t u4Available : 4;
205	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
206	uint64_t u40PhysAddr : 40;
207	/** Availabe for software. */
208	uint64_t u12Available : 12;
209	} EPTPDEBITS;
210	#pragma pack()
211	AssertCompileSize(EPTPDEBITS, 8);
212
213	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
214	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
215	/** The page shift to get the PD index. */
216	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
217	/** The PD index mask (apply to a shifted page address). */
218	#define EPT_PD_MASK X86_PD_PAE_MASK
219
220	/**
221	* EPT 2MB Page Directory Table Entry. Bit view.
222	*/
223	#pragma pack(1)
224	typedef struct EPTPDE2MBITS
225	{
226	/** Present bit. */
227	uint64_t u1Present : 1;
228	/** Writable bit. */
229	uint64_t u1Write : 1;
230	/** Executable bit. */
231	uint64_t u1Execute : 1;
232	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
233	uint64_t u3EMT : 3;
234	/** Ignore PAT memory type */
235	uint64_t u1IgnorePAT : 1;
236	/** Big page (must be 1 here). */
237	uint64_t u1Size : 1;
238	/** Available for software. */
239	uint64_t u4Available : 4;
240	/** Reserved (must be 0). */
241	uint64_t u9Reserved : 9;
242	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
243	uint64_t u31PhysAddr : 31;
244	/** Availabe for software. */
245	uint64_t u12Available : 12;
246	} EPTPDE2MBITS;
247	#pragma pack()
248	AssertCompileSize(EPTPDE2MBITS, 8);
249
250	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
251	#define EPT_PDE2M_PG_MASK ( 0x000fffffffe00000ULL )
252
253	/**
254	* EPT Page Directory Table Entry.
255	*/
256	#pragma pack(1)
257	typedef union EPTPDE
258	{
259	/** Normal view. */
260	EPTPDEBITS n;
261	/** 2MB view (big). */
262	EPTPDE2MBITS b;
263	/** Unsigned integer view. */
264	X86PGPAEUINT u;
265	/** 64 bit unsigned integer view. */
266	uint64_t au64[1];
267	/** 32 bit unsigned integer view. */
268	uint32_t au32[2];
269	} EPTPDE;
270	#pragma pack()
271	/** Pointer to an EPT Page Directory Table Entry. */
272	typedef EPTPDE *PEPTPDE;
273	/** Pointer to a const EPT Page Directory Table Entry. */
274	typedef const EPTPDE *PCEPTPDE;
275	AssertCompileSize(EPTPDE, 8);
276
277	/**
278	* EPT Page Directory Table.
279	*/
280	#pragma pack(1)
281	typedef struct EPTPD
282	{
283	EPTPDE a[EPT_PG_ENTRIES];
284	} EPTPD;
285	#pragma pack()
286	/** Pointer to an EPT Page Directory Table. */
287	typedef EPTPD *PEPTPD;
288	/** Pointer to a const EPT Page Directory Table. */
289	typedef const EPTPD *PCEPTPD;
290
291
292	/**
293	* EPT Page Table Entry. Bit view.
294	*/
295	#pragma pack(1)
296	typedef struct EPTPTEBITS
297	{
298	/** Present bit. */
299	uint64_t u1Present : 1;
300	/** Writable bit. */
301	uint64_t u1Write : 1;
302	/** Executable bit. */
303	uint64_t u1Execute : 1;
304	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
305	uint64_t u3EMT : 3;
306	/** Ignore PAT memory type */
307	uint64_t u1IgnorePAT : 1;
308	/** Available for software. */
309	uint64_t u5Available : 5;
310	/** Physical address of page. Restricted by maximum physical address width of the cpu. */
311	uint64_t u40PhysAddr : 40;
312	/** Availabe for software. */
313	uint64_t u12Available : 12;
314	} EPTPTEBITS;
315	#pragma pack()
316	AssertCompileSize(EPTPTEBITS, 8);
317
318	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
319	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
320	/** The page shift to get the EPT PTE index. */
321	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
322	/** The EPT PT index mask (apply to a shifted page address). */
323	#define EPT_PT_MASK X86_PT_PAE_MASK
324
325	/**
326	* EPT Page Table Entry.
327	*/
328	#pragma pack(1)
329	typedef union EPTPTE
330	{
331	/** Normal view. */
332	EPTPTEBITS n;
333	/** Unsigned integer view. */
334	X86PGPAEUINT u;
335	/** 64 bit unsigned integer view. */
336	uint64_t au64[1];
337	/** 32 bit unsigned integer view. */
338	uint32_t au32[2];
339	} EPTPTE;
340	#pragma pack()
341	/** Pointer to an EPT Page Directory Table Entry. */
342	typedef EPTPTE *PEPTPTE;
343	/** Pointer to a const EPT Page Directory Table Entry. */
344	typedef const EPTPTE *PCEPTPTE;
345	AssertCompileSize(EPTPTE, 8);
346
347	/**
348	* EPT Page Table.
349	*/
350	#pragma pack(1)
351	typedef struct EPTPT
352	{
353	EPTPTE a[EPT_PG_ENTRIES];
354	} EPTPT;
355	#pragma pack()
356	/** Pointer to an extended page table. */
357	typedef EPTPT *PEPTPT;
358	/** Pointer to a const extended table. */
359	typedef const EPTPT *PCEPTPT;
360
361	/**
362	* VPID and EPT flush types
363	*/
364	typedef enum
365	{
366	/* Invalidate a specific page. */
367	VMX_FLUSH_PAGE = 0,
368	/* Invalidate one context (VPID or EPT) */
369	VMX_FLUSH_SINGLE_CONTEXT = 1,
370	/* Invalidate all contexts (VPIDs or EPTs) */
371	VMX_FLUSH_ALL_CONTEXTS = 2,
372	/* Invalidate a single VPID context retaining global mappings. */
373	VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL = 3,
374	/** 32bit hackishness. */
375	VMX_FLUSH_32BIT_HACK = 0x7fffffff
376	} VMX_FLUSH;
377
378	/** @} */
379
380
381	/** @name VMX Basic Exit Reasons.
382	* @{
383	*/
384	/** And-mask for setting reserved bits to zero */
385	#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
386	/** Or-mask for setting reserved bits to 1 */
387	#define VMX_EFLAGS_RESERVED_1 0x00000002
388	/** @} */
389
390	/** @name VMX Basic Exit Reasons.
391	* @{
392	*/
393	/** 0 Exception or non-maskable interrupt (NMI). */
394	#define VMX_EXIT_EXCEPTION 0
395	/** 1 External interrupt. */
396	#define VMX_EXIT_EXTERNAL_IRQ 1
397	/** 2 Triple fault. */
398	#define VMX_EXIT_TRIPLE_FAULT 2
399	/** 3 INIT signal. */
400	#define VMX_EXIT_INIT_SIGNAL 3
401	/** 4 Start-up IPI (SIPI). */
402	#define VMX_EXIT_SIPI 4
403	/** 5 I/O system-management interrupt (SMI). */
404	#define VMX_EXIT_IO_SMI_IRQ 5
405	/** 6 Other SMI. */
406	#define VMX_EXIT_SMI_IRQ 6
407	/** 7 Interrupt window. */
408	#define VMX_EXIT_IRQ_WINDOW 7
409	/** 9 Task switch. */
410	#define VMX_EXIT_TASK_SWITCH 9
411	/** 10 Guest software attempted to execute CPUID. */
412	#define VMX_EXIT_CPUID 10
413	/** 12 Guest software attempted to execute HLT. */
414	#define VMX_EXIT_HLT 12
415	/** 13 Guest software attempted to execute INVD. */
416	#define VMX_EXIT_INVD 13
417	/** 14 Guest software attempted to execute INVPG. */
418	#define VMX_EXIT_INVPG 14
419	/** 15 Guest software attempted to execute RDPMC. */
420	#define VMX_EXIT_RDPMC 15
421	/** 16 Guest software attempted to execute RDTSC. */
422	#define VMX_EXIT_RDTSC 16
423	/** 17 Guest software attempted to execute RSM in SMM. */
424	#define VMX_EXIT_RSM 17
425	/** 18 Guest software executed VMCALL. */
426	#define VMX_EXIT_VMCALL 18
427	/** 19 Guest software executed VMCLEAR. */
428	#define VMX_EXIT_VMCLEAR 19
429	/** 20 Guest software executed VMLAUNCH. */
430	#define VMX_EXIT_VMLAUNCH 20
431	/** 21 Guest software executed VMPTRLD. */
432	#define VMX_EXIT_VMPTRLD 21
433	/** 22 Guest software executed VMPTRST. */
434	#define VMX_EXIT_VMPTRST 22
435	/** 23 Guest software executed VMREAD. */
436	#define VMX_EXIT_VMREAD 23
437	/** 24 Guest software executed VMRESUME. */
438	#define VMX_EXIT_VMRESUME 24
439	/** 25 Guest software executed VMWRITE. */
440	#define VMX_EXIT_VMWRITE 25
441	/** 26 Guest software executed VMXOFF. */
442	#define VMX_EXIT_VMXOFF 26
443	/** 27 Guest software executed VMXON. */
444	#define VMX_EXIT_VMXON 27
445	/** 28 Control-register accesses. */
446	#define VMX_EXIT_CRX_MOVE 28
447	/** 29 Debug-register accesses. */
448	#define VMX_EXIT_DRX_MOVE 29
449	/** 30 I/O instruction. */
450	#define VMX_EXIT_PORT_IO 30
451	/** 31 RDMSR. Guest software attempted to execute RDMSR. */
452	#define VMX_EXIT_RDMSR 31
453	/** 32 WRMSR. Guest software attempted to execute WRMSR. */
454	#define VMX_EXIT_WRMSR 32
455	/** 33 VM-entry failure due to invalid guest state. */
456	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
457	/** 34 VM-entry failure due to MSR loading. */
458	#define VMX_EXIT_ERR_MSR_LOAD 34
459	/** 36 Guest software executed MWAIT. */
460	#define VMX_EXIT_MWAIT 36
461	/** 39 Guest software attempted to execute MONITOR. */
462	#define VMX_EXIT_MONITOR 39
463	/** 40 Guest software attempted to execute PAUSE. */
464	#define VMX_EXIT_PAUSE 40
465	/** 41 VM-entry failure due to machine-check. */
466	#define VMX_EXIT_ERR_MACHINE_CHECK 41
467	/** 43 TPR below threshold. Guest software executed MOV to CR8. */
468	#define VMX_EXIT_TPR 43
469	/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
470	#define VMX_EXIT_APIC_ACCESS 44
471	/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
472	#define VMX_EXIT_XDTR_ACCESS 46
473	/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
474	#define VMX_EXIT_TR_ACCESS 47
475	/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
476	#define VMX_EXIT_EPT_VIOLATION 48
477	/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
478	#define VMX_EXIT_EPT_MISCONFIG 49
479	/** 50 INVEPT. Guest software attempted to execute INVEPT. */
480	#define VMX_EXIT_INVEPT 50
481	/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
482	#define VMX_EXIT_PREEMPTION_TIMER 52
483	/** 53 INVVPID. Guest software attempted to execute INVVPID. */
484	#define VMX_EXIT_INVVPID 53
485	/** 54 WBINVD. Guest software attempted to execute WBINVD. */
486	#define VMX_EXIT_WBINVD 54
487	/** 55 XSETBV. Guest software attempted to execute XSETBV. */
488	#define VMX_EXIT_XSETBV 55
489	/** @} */
490
491
492	/** @name VM Instruction Errors
493	* @{
494	*/
495	/** 1 VMCALL executed in VMX root operation. */
496	#define VMX_ERROR_VMCALL 1
497	/** 2 VMCLEAR with invalid physical address. */
498	#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
499	/** 3 VMCLEAR with VMXON pointer. */
500	#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
501	/** 4 VMLAUNCH with non-clear VMCS. */
502	#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
503	/** 5 VMRESUME with non-launched VMCS. */
504	#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
505	/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
506	#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
507	/** 7 VM entry with invalid control field(s). */
508	#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
509	/** 8 VM entry with invalid host-state field(s). */
510	#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
511	/** 9 VMPTRLD with invalid physical address. */
512	#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
513	/** 10 VMPTRLD with VMXON pointer. */
514	#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
515	/** 11 VMPTRLD with incorrect VMCS revision identifier. */
516	#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
517	/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
518	#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
519	#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
520	/** 13 VMWRITE to read-only VMCS component. */
521	#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
522	/** 15 VMXON executed in VMX root operation. */
523	#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
524	/** 16 VM entry with invalid executive-VMCS pointer. */
525	#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
526	/** 17 VM entry with non-launched executive VMCS. */
527	#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
528	/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
529	#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
530	/** 19 VMCALL with non-clear VMCS. */
531	#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
532	/** 20 VMCALL with invalid VM-exit control fields. */
533	#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
534	/** 22 VMCALL with incorrect MSEG revision identifier. */
535	#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
536	/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
537	#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
538	/** 24 VMCALL with invalid SMM-monitor features. */
539	#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
540	/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
541	#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
542	/** 26 VM entry with events blocked by MOV SS. */
543	#define VMX_ERROR_VMENTRY_MOV_SS 26
544
545	/** @} */
546
547
548	/** @name VMX MSRs - Basic VMX information.
549	* @{
550	*/
551	/** VMCS revision identifier used by the processor. */
552	#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
553	/** Size of the VMCS. */
554	#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
555	/** Width of physical address used for the VMCS.
556	* 0 -> limited to the available amount of physical ram
557	* 1 -> within the first 4 GB
558	*/
559	#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
560	/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
561	#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
562	/** Memory type that must be used for the VMCS. */
563	#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
564	/** @} */
565
566
567	/** @name VMX MSRs - Misc VMX info.
568	* @{
569	*/
570	/** Activity states supported by the implementation. */
571	#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
572	/** Number of CR3 target values supported by the processor. (0-256) */
573	#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
574	/** Maximum nr of MSRs in the VMCS. (N+1)512. /
575	#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
576	/** MSEG revision identifier used by the processor. */
577	#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
578	/** @} */
579
580
581	/** @name VMX MSRs - VMCS enumeration field info
582	* @{
583	*/
584	/** Highest field index. */
585	#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
586
587	/** @} */
588
589
590	/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
591	* @{
592	*/
593	#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
594	#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
595	#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
596	#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
597	#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
598	#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
599	#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
600	#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
601	#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
602	#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
603	#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
604	#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
605	#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
606	#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
607	#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
608	#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
609	#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
610	#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
611	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
612	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
613	#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
614	#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
615	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
616	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
617	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
618	#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
619
620	/** @} */
621
622	/** @name Extended Page Table Pointer (EPTP)
623	* @{
624	*/
625	/** Uncachable EPT paging structure memory type. */
626	#define VMX_EPT_MEMTYPE_UC 0
627	/** Write-back EPT paging structure memory type. */
628	#define VMX_EPT_MEMTYPE_WB 6
629	/** Shift value to get the EPT page walk length (bits 5-3) */
630	#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
631	/** Mask value to get the EPT page walk length (bits 5-3) */
632	#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
633	/** Default EPT page walk length */
634	#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
635	/** @} */
636
637
638	/** @name VMCS field encoding - 16 bits guest fields
639	* @{
640	*/
641	#define VMX_VMCS_GUEST_FIELD_VPID 0x0
642	#define VMX_VMCS_GUEST_FIELD_ES 0x800
643	#define VMX_VMCS_GUEST_FIELD_CS 0x802
644	#define VMX_VMCS_GUEST_FIELD_SS 0x804
645	#define VMX_VMCS_GUEST_FIELD_DS 0x806
646	#define VMX_VMCS_GUEST_FIELD_FS 0x808
647	#define VMX_VMCS_GUEST_FIELD_GS 0x80A
648	#define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
649	#define VMX_VMCS_GUEST_FIELD_TR 0x80E
650	/** @} */
651
652	/** @name VMCS field encoding - 16 bits host fields
653	* @{
654	*/
655	#define VMX_VMCS_HOST_FIELD_ES 0xC00
656	#define VMX_VMCS_HOST_FIELD_CS 0xC02
657	#define VMX_VMCS_HOST_FIELD_SS 0xC04
658	#define VMX_VMCS_HOST_FIELD_DS 0xC06
659	#define VMX_VMCS_HOST_FIELD_FS 0xC08
660	#define VMX_VMCS_HOST_FIELD_GS 0xC0A
661	#define VMX_VMCS_HOST_FIELD_TR 0xC0C
662	/** @} */
663
664	/** @name VMCS field encoding - 64 bits host fields
665	* @{
666	*/
667	#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
668	#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
669	#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
670	#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
671	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /*< MSR IA32_PERF_GLOBAL_CTRL /
672	#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /*< MSR IA32_PERF_GLOBAL_CTRL /
673	/** @} */
674
675
676	/** @name VMCS field encoding - 64 Bits control fields
677	* @{
678	*/
679	#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
680	#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
681	#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
682	#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
683
684	/* Optional */
685	#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
686	#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
687
688	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
689	#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
690	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
691	#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
692
693	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
694	#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
695
696	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
697	#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
698
699	#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
700	#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
701
702	/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
703	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
704	#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
705
706	/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
707	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
708	#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
709
710	/** Extended page table pointer. */
711	#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
712	#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
713
714	/** VM-exit phyiscal address. */
715	#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
716	#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
717	/** @} */
718
719
720	/** @name VMCS field encoding - 64 Bits guest fields
721	* @{
722	*/
723	#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
724	#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
725	#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /*< MSR IA32_DEBUGCTL /
726	#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /*< MSR IA32_DEBUGCTL /
727	#define VMX_VMCS_GUEST_PAT_FULL 0x2804
728	#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
729	#define VMX_VMCS_GUEST_EFER_FULL 0x2806
730	#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
731	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /*< MSR IA32_PERF_GLOBAL_CTRL /
732	#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /*< MSR IA32_PERF_GLOBAL_CTRL /
733	#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
734	#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
735	#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
736	#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
737	#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
738	#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
739	#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
740	#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
741	/** @} */
742
743
744	/** @name VMCS field encoding - 32 Bits control fields
745	* @{
746	*/
747	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
748	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
749	#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
750	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
751	#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
752	#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
753	#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
754	#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
755	#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
756	#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
757	#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
758	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
759	#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
760	#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
761	/** This field exists only on processors that support the 1-setting of the use TPR shadow VM-execution control. */
762	#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
763	/** This field exists only on processors that support the 1-setting of the activate secondary controls VM-execution control. */
764	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
765	/** @} */
766
767
768	/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
769	* @{
770	*/
771	/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
772	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
773	/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
774	#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
775	/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
776	/** @} */
777
778	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
779	* @{
780	*/
781	/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
782	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
783	/** Use timestamp counter offset. */
784	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
785	/** VM Exit when executing the HLT instruction. */
786	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
787	/** VM Exit when executing the INVLPG instruction. */
788	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
789	/** VM Exit when executing the MWAIT instruction. */
790	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
791	/** VM Exit when executing the RDPMC instruction. */
792	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
793	/** VM Exit when executing the RDTSC instruction. */
794	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
795	/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
796	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
797	/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
798	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
799	/** VM Exit on CR8 loads. */
800	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
801	/** VM Exit on CR8 stores. */
802	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
803	/** Use TPR shadow. */
804	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
805	/** VM Exit when executing a MOV DRx instruction. */
806	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
807	/** VM Exit when executing IO instructions. */
808	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
809	/** Use IO bitmaps. */
810	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
811	/** Monitor trap flag. */
812	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
813	/** Use MSR bitmaps. */
814	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
815	/** VM Exit when executing the MONITOR instruction. */
816	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
817	/** VM Exit when executing the PAUSE instruction. */
818	#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
819	/** Determines whether the secondary processor based VM-execution controls are used. */
820	#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
821	/** @} */
822
823	/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
824	* @{
825	*/
826	/** Virtualize APIC access. */
827	#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
828	/** EPT supported/enabled. */
829	#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
830	/** VPID supported/enabled. */
831	#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
832	/** VM Exit when executing the WBINVD instruction. */
833	#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
834	/** @} */
835
836
837	/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
838	* @{
839	*/
840	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
841	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
842	/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
843	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
844	/** In SMM mode after VM-entry. */
845	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
846	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
847	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
848	/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
849	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
850	/** This control determines whether the guest IA32_PAT MSR is loaded on VM exit. */
851	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
852	/** This control determines whether the guest IA32_EFER MSR is loaded on VM exit. */
853	#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
854	/** @} */
855
856
857	/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
858	* @{
859	*/
860	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
861	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
862	/** Return to long mode after a VM-exit. */
863	#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
864	/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
865	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
866	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
867	#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
868	/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
869	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
870	/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
871	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
872	/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
873	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
874	/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
875	#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
876	/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
877	#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
878	/** @} */
879
880	/** @name VMCS field encoding - 32 Bits read-only fields
881	* @{
882	*/
883	#define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
884	#define VMX_VMCS_RO_EXIT_REASON 0x4402
885	#define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
886	#define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
887	#define VMX_VMCS_RO_IDT_INFO 0x4408
888	#define VMX_VMCS_RO_IDT_ERRCODE 0x440A
889	#define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
890	#define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
891	/** @} */
892
893	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
894	* @{
895	*/
896	#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
897	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
898	#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
899	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
900	#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
901	#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
902	#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
903	#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
904	/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
905	#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
906	/** @} */
907
908	/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
909	* @{
910	*/
911	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
912	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
913	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
914	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /*< int xx /
915	#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
916	/** @} */
917
918
919	/** @name VMCS field encoding - 32 Bits guest state fields
920	* @{
921	*/
922	#define VMX_VMCS_GUEST_ES_LIMIT 0x4800
923	#define VMX_VMCS_GUEST_CS_LIMIT 0x4802
924	#define VMX_VMCS_GUEST_SS_LIMIT 0x4804
925	#define VMX_VMCS_GUEST_DS_LIMIT 0x4806
926	#define VMX_VMCS_GUEST_FS_LIMIT 0x4808
927	#define VMX_VMCS_GUEST_GS_LIMIT 0x480A
928	#define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
929	#define VMX_VMCS_GUEST_TR_LIMIT 0x480E
930	#define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
931	#define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
932	#define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
933	#define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
934	#define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
935	#define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
936	#define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
937	#define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
938	#define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
939	#define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
940	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
941	#define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
942	#define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /*< MSR IA32_SYSENTER_CS /
943	#define VMX_VMCS_GUEST_PREEMPTION_TIMER_VALUE 0x482E
944	/** @} */
945
946
947	/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
948	* @{
949	*/
950	/** The logical processor is active. */
951	#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
952	/** The logical processor is inactive, because executed a HLT instruction. */
953	#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
954	/** The logical processor is inactive, because of a triple fault or other serious error. */
955	#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
956	/** The logical processor is inactive, because it's waiting for a startup-IPI */
957	#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
958	/** @} */
959
960
961	/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
962	* @{
963	*/
964	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
965	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
966	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
967	#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
968	/** @} */
969
970
971	/** @name VMCS field encoding - 32 Bits host state fields
972	* @{
973	*/
974	#define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
975	/** @} */
976
977	/** @name Natural width control fields
978	* @{
979	*/
980	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
981	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
982	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
983	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
984	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
985	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
986	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
987	#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
988	/** @} */
989
990
991	/** @name Natural width read-only data fields
992	* @{
993	*/
994	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
995	#define VMX_VMCS_RO_IO_RCX 0x6402
996	#define VMX_VMCS_RO_IO_RSX 0x6404
997	#define VMX_VMCS_RO_IO_RDI 0x6406
998	#define VMX_VMCS_RO_IO_RIP 0x6408
999	#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
1000	/** @} */
1001
1002
1003	/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1004	* @{
1005	*/
1006	/** 0-2: Debug register number */
1007	#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1008	/** 3: Reserved; cleared to 0. */
1009	#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1010	/** 4: Direction of move (0 = write, 1 = read) */
1011	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1012	/** 5-7: Reserved; cleared to 0. */
1013	#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1014	/** 8-11: General purpose register number. */
1015	#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1016	/** Rest: reserved. */
1017	/** @} */
1018
1019	/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1020	* @{
1021	*/
1022	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1023	#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1024	/** @} */
1025
1026
1027
1028	/** @name CRx accesses
1029	* @{
1030	*/
1031	/** 0-3: Control register number (0 for CLTS & LMSW) */
1032	#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1033	/** 4-5: Access type. */
1034	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1035	/** 6: LMSW operand type */
1036	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1037	/** 7: Reserved; cleared to 0. */
1038	#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1039	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1040	#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1041	/** 12-15: Reserved; cleared to 0. */
1042	#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1043	/** 16-31: LMSW source data (else 0). */
1044	#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1045	/** Rest: reserved. */
1046	/** @} */
1047
1048	/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1049	* @{
1050	*/
1051	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1052	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1053	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1054	#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1055	/** @} */
1056
1057
1058	/** @name VMX_EXIT_EPT_VIOLATION
1059	* @{
1060	*/
1061	/** Set if the violation was caused by a data read. */
1062	#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1063	/** Set if the violation was caused by a data write. */
1064	#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1065	/** Set if the violation was caused by an insruction fetch. */
1066	#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1067	/** AND of the present bit of all EPT structures. */
1068	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1069	/** AND of the write bit of all EPT structures. */
1070	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1071	/** AND of the execute bit of all EPT structures. */
1072	#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1073	/** Set if the guest linear address field contains the faulting address. */
1074	#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1075	/** If bit 7 is one: (reserved otherwise)
1076	* 1 - violation due to physical address access.
1077	* 0 - violation caused by page walk or access/dirty bit updates
1078	*/
1079	#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1080	/** @} */
1081
1082
1083	/** @name VMX_EXIT_PORT_IO
1084	* @{
1085	*/
1086	/** 0-2: IO operation width. */
1087	#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1088	/** 3: IO operation direction. */
1089	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1090	/** 4: String IO operation. */
1091	#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1092	/** 5: Repeated IO operation. */
1093	#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1094	/** 6: Operand encoding. */
1095	#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1096	/** 16-31: IO Port (0-0xffff). */
1097	#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1098	/* Rest reserved. */
1099	/** @} */
1100
1101	/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1102	* @{
1103	*/
1104	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1105	#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1106	/** @} */
1107
1108
1109	/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1110	* @{
1111	*/
1112	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1113	#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1114	/** @} */
1115
1116	/** @} */
1117
1118	/** @name VMCS field encoding - Natural width guest state fields
1119	* @{
1120	*/
1121	#define VMX_VMCS_GUEST_CR0 0x6800
1122	#define VMX_VMCS_GUEST_CR3 0x6802
1123	#define VMX_VMCS_GUEST_CR4 0x6804
1124	#define VMX_VMCS_GUEST_ES_BASE 0x6806
1125	#define VMX_VMCS_GUEST_CS_BASE 0x6808
1126	#define VMX_VMCS_GUEST_SS_BASE 0x680A
1127	#define VMX_VMCS_GUEST_DS_BASE 0x680C
1128	#define VMX_VMCS_GUEST_FS_BASE 0x680E
1129	#define VMX_VMCS_GUEST_GS_BASE 0x6810
1130	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
1131	#define VMX_VMCS_GUEST_TR_BASE 0x6814
1132	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
1133	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
1134	#define VMX_VMCS_GUEST_DR7 0x681A
1135	#define VMX_VMCS_GUEST_RSP 0x681C
1136	#define VMX_VMCS_GUEST_RIP 0x681E
1137	#define VMX_VMCS_GUEST_RFLAGS 0x6820
1138	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1139	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /*< MSR IA32_SYSENTER_ESP /
1140	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /*< MSR IA32_SYSENTER_EIP /
1141	/** @} */
1142
1143
1144	/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1145	* @{
1146	*/
1147	/** Hardware breakpoint 0 was met. */
1148	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1149	/** Hardware breakpoint 1 was met. */
1150	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1151	/** Hardware breakpoint 2 was met. */
1152	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1153	/** Hardware breakpoint 3 was met. */
1154	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1155	/** At least one data or IO breakpoint was hit. */
1156	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1157	/** A debug exception would have been triggered by single-step execution mode. */
1158	#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1159	/** Bits 4-11, 13 and 15-63 are reserved. */
1160
1161	/** @} */
1162
1163	/** @name VMCS field encoding - Natural width host state fields
1164	* @{
1165	*/
1166	#define VMX_VMCS_HOST_CR0 0x6C00
1167	#define VMX_VMCS_HOST_CR3 0x6C02
1168	#define VMX_VMCS_HOST_CR4 0x6C04
1169	#define VMX_VMCS_HOST_FS_BASE 0x6C06
1170	#define VMX_VMCS_HOST_GS_BASE 0x6C08
1171	#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1172	#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1173	#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1174	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1175	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1176	#define VMX_VMCS_HOST_RSP 0x6C14
1177	#define VMX_VMCS_HOST_RIP 0x6C16
1178	/** @} */
1179
1180	/** @} */
1181
1182
1183	#if RT_INLINE_ASM_GNU_STYLE
1184	# define __STR(x) #x
1185	# define STR(x) __STR(x)
1186	#endif
1187
1188
1189	/** @defgroup grp_vmx_asm vmx assembly helpers
1190	* @ingroup grp_vmx
1191	* @{
1192	*/
1193
1194	/**
1195	* Executes VMXON
1196	*
1197	* @returns VBox status code
1198	* @param pVMXOn Physical address of VMXON structure
1199	*/
1200	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1201	DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1202	#else
1203	DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1204	{
1205	int rc = VINF_SUCCESS;
1206	# if RT_INLINE_ASM_GNU_STYLE
1207	__asm__ __volatile__ (
1208	"push %3 \n\t"
1209	"push %2 \n\t"
1210	".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1211	"ja 2f \n\t"
1212	"je 1f \n\t"
1213	"movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1214	"jmp 2f \n\t"
1215	"1: \n\t"
1216	"movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1217	"2: \n\t"
1218	"add $8, %%esp \n\t"
1219	:"=rm"(rc)
1220	:"0"(VINF_SUCCESS),
1221	"ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1222	"ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1223	:"memory"
1224	);
1225	# else
1226	__asm
1227	{
1228	push dword ptr [pVMXOn+4]
1229	push dword ptr [pVMXOn]
1230	_emit 0xF3
1231	_emit 0x0F
1232	_emit 0xC7
1233	_emit 0x34
1234	_emit 0x24 /* VMXON [esp] */
1235	jnc vmxon_good
1236	mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1237	jmp the_end
1238
1239	vmxon_good:
1240	jnz the_end
1241	mov dword ptr [rc], VERR_VMX_GENERIC
1242	the_end:
1243	add esp, 8
1244	}
1245	# endif
1246	return rc;
1247	}
1248	#endif
1249
1250
1251	/**
1252	* Executes VMXOFF
1253	*/
1254	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1255	DECLASM(void) VMXDisable(void);
1256	#else
1257	DECLINLINE(void) VMXDisable(void)
1258	{
1259	# if RT_INLINE_ASM_GNU_STYLE
1260	__asm__ __volatile__ (
1261	".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1262	);
1263	# else
1264	__asm
1265	{
1266	_emit 0x0F
1267	_emit 0x01
1268	_emit 0xC4 /* VMXOFF */
1269	}
1270	# endif
1271	}
1272	#endif
1273
1274
1275	/**
1276	* Executes VMCLEAR
1277	*
1278	* @returns VBox status code
1279	* @param pVMCS Physical address of VM control structure
1280	*/
1281	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1282	DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1283	#else
1284	DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1285	{
1286	int rc = VINF_SUCCESS;
1287	# if RT_INLINE_ASM_GNU_STYLE
1288	__asm__ __volatile__ (
1289	"push %3 \n\t"
1290	"push %2 \n\t"
1291	".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1292	"jnc 1f \n\t"
1293	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1294	"1: \n\t"
1295	"add $8, %%esp \n\t"
1296	:"=rm"(rc)
1297	:"0"(VINF_SUCCESS),
1298	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1299	"ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1300	:"memory"
1301	);
1302	# else
1303	__asm
1304	{
1305	push dword ptr [pVMCS+4]
1306	push dword ptr [pVMCS]
1307	_emit 0x66
1308	_emit 0x0F
1309	_emit 0xC7
1310	_emit 0x34
1311	_emit 0x24 /* VMCLEAR [esp] */
1312	jnc success
1313	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1314	success:
1315	add esp, 8
1316	}
1317	# endif
1318	return rc;
1319	}
1320	#endif
1321
1322
1323	/**
1324	* Executes VMPTRLD
1325	*
1326	* @returns VBox status code
1327	* @param pVMCS Physical address of VMCS structure
1328	*/
1329	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1330	DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1331	#else
1332	DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1333	{
1334	int rc = VINF_SUCCESS;
1335	# if RT_INLINE_ASM_GNU_STYLE
1336	__asm__ __volatile__ (
1337	"push %3 \n\t"
1338	"push %2 \n\t"
1339	".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1340	"jnc 1f \n\t"
1341	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1342	"1: \n\t"
1343	"add $8, %%esp \n\t"
1344	:"=rm"(rc)
1345	:"0"(VINF_SUCCESS),
1346	"ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1347	"ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1348	);
1349	# else
1350	__asm
1351	{
1352	push dword ptr [pVMCS+4]
1353	push dword ptr [pVMCS]
1354	_emit 0x0F
1355	_emit 0xC7
1356	_emit 0x34
1357	_emit 0x24 /* VMPTRLD [esp] */
1358	jnc success
1359	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1360
1361	success:
1362	add esp, 8
1363	}
1364	# endif
1365	return rc;
1366	}
1367	#endif
1368
1369	/**
1370	* Executes VMPTRST
1371	*
1372	* @returns VBox status code
1373	* @param pVMCS Address that will receive the current pointer
1374	*/
1375	DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1376
1377	/**
1378	* Executes VMWRITE
1379	*
1380	* @returns VBox status code
1381	* @param idxField VMCS index
1382	* @param u64Val 16, 32 or 64 bits value
1383	*/
1384	DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1385
1386	/**
1387	* Executes VMWRITE
1388	*
1389	* @returns VBox status code
1390	* @param idxField VMCS index
1391	* @param u32Val 32 bits value
1392	*/
1393	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1394	DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1395	#else
1396	DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1397	{
1398	int rc = VINF_SUCCESS;
1399	# if RT_INLINE_ASM_GNU_STYLE
1400	__asm__ __volatile__ (
1401	".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1402	"ja 2f \n\t"
1403	"je 1f \n\t"
1404	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1405	"jmp 2f \n\t"
1406	"1: \n\t"
1407	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1408	"2: \n\t"
1409	:"=rm"(rc)
1410	:"0"(VINF_SUCCESS),
1411	"a"(idxField),
1412	"d"(u32Val)
1413	);
1414	# else
1415	__asm
1416	{
1417	push dword ptr [u32Val]
1418	mov eax, [idxField]
1419	_emit 0x0F
1420	_emit 0x79
1421	_emit 0x04
1422	_emit 0x24 /* VMWRITE eax, [esp] */
1423	jnc valid_vmcs
1424	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1425	jmp the_end
1426
1427	valid_vmcs:
1428	jnz the_end
1429	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1430	the_end:
1431	add esp, 4
1432	}
1433	# endif
1434	return rc;
1435	}
1436	#endif
1437
1438	#if HC_ARCH_BITS == 64
1439	#define VMXWriteVMCS VMXWriteVMCS64
1440	#else
1441	#define VMXWriteVMCS VMXWriteVMCS32
1442	#endif /* HC_ARCH_BITS == 64 */
1443
1444
1445	/**
1446	* Executes VMREAD
1447	*
1448	* @returns VBox status code
1449	* @param idxField VMCS index
1450	* @param pData Ptr to store VM field value
1451	*/
1452	DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1453
1454	/**
1455	* Invalidate a page using invept
1456	* @returns VBox status code
1457	* @param enmFlush Type of flush
1458	* @param pDescriptor Descriptor
1459	*/
1460	DECLASM(int) VMXR0InvEPT(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1461
1462	/**
1463	* Invalidate a page using invvpid
1464	* @returns VBox status code
1465	* @param enmFlush Type of flush
1466	* @param pDescriptor Descriptor
1467	*/
1468	DECLASM(int) VMXR0InvVPID(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1469
1470	/**
1471	* Executes VMREAD
1472	*
1473	* @returns VBox status code
1474	* @param idxField VMCS index
1475	* @param pData Ptr to store VM field value
1476	*/
1477	#if RT_INLINE_ASM_EXTERNAL \|\| HC_ARCH_BITS == 64
1478	DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1479	#else
1480	DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1481	{
1482	int rc = VINF_SUCCESS;
1483	# if RT_INLINE_ASM_GNU_STYLE
1484	__asm__ __volatile__ (
1485	"movl $"STR(VINF_SUCCESS)", %0 \n\t"
1486	".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1487	"ja 2f \n\t"
1488	"je 1f \n\t"
1489	"movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1490	"jmp 2f \n\t"
1491	"1: \n\t"
1492	"movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1493	"2: \n\t"
1494	:"=&r"(rc),
1495	"=d"(*pData)
1496	:"a"(idxField),
1497	"d"(0)
1498	);
1499	# else
1500	__asm
1501	{
1502	sub esp, 4
1503	mov dword ptr [esp], 0
1504	mov eax, [idxField]
1505	_emit 0x0F
1506	_emit 0x78
1507	_emit 0x04
1508	_emit 0x24 /* VMREAD eax, [esp] */
1509	mov edx, pData
1510	pop dword ptr [edx]
1511	jnc valid_vmcs
1512	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1513	jmp the_end
1514
1515	valid_vmcs:
1516	jnz the_end
1517	mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1518	the_end:
1519	}
1520	# endif
1521	return rc;
1522	}
1523	#endif
1524
1525	#if HC_ARCH_BITS == 64
1526	# define VMXReadVMCS VMXReadVMCS64
1527	#else
1528	# define VMXReadVMCS VMXReadVMCS32
1529	#endif /* HC_ARCH_BITS == 64 */
1530
1531	/**
1532	* Gets the last instruction error value from the current VMCS
1533	*
1534	* @returns error value
1535	*/
1536	DECLINLINE(uint32_t) VMXGetLastError(void)
1537	{
1538	#if HC_ARCH_BITS == 64
1539	uint64_t uLastError = 0;
1540	int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1541	AssertRC(rc);
1542	return (uint32_t)uLastError;
1543
1544	#else /* 32-bit host: */
1545	uint32_t uLastError = 0;
1546	int rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1547	AssertRC(rc);
1548	return uLastError;
1549	#endif
1550	}
1551
1552	#ifdef IN_RING0
1553	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, RTGCPTR GCVirt);
1554	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
1555	#endif /* IN_RING0 */
1556
1557	/** @} */
1558
1559	#endif
1560

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source: vbox/trunk/include/VBox/hwacc_vmx.h@ 13469

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