hwacc_svm.h@ 7097

Last change on this file since 7097 was 6243, checked in by vboxsync, 17 years ago
Just use the assembly version of SVMInvlpgA everywhere (was asserting/nop in the gcc country).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 22.2 KB

Line
1	/** @file
2	* SVM Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 innotek GmbH
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_svm_h
27	#define ___VBox_svm_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <VBox/cpum.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34
35	/** @defgroup grp_svm svm Types and Definitions
36	* @ingroup grp_hwaccm
37	* @{
38	*/
39
40
41	/** @name SVM Basic Exit Reasons.
42	* @{
43	*/
44	/** Invalid guest state in VMCB. */
45	#define SVM_EXIT_INVALID -1
46	/** Read from CR0-CR15. */
47	#define SVM_EXIT_READ_CR0 0x0
48	#define SVM_EXIT_READ_CR1 0x1
49	#define SVM_EXIT_READ_CR2 0x2
50	#define SVM_EXIT_READ_CR3 0x3
51	#define SVM_EXIT_READ_CR4 0x4
52	#define SVM_EXIT_READ_CR5 0x5
53	#define SVM_EXIT_READ_CR6 0x6
54	#define SVM_EXIT_READ_CR7 0x7
55	#define SVM_EXIT_READ_CR8 0x8
56	#define SVM_EXIT_READ_CR9 0x9
57	#define SVM_EXIT_READ_CR10 0xA
58	#define SVM_EXIT_READ_CR11 0xB
59	#define SVM_EXIT_READ_CR12 0xC
60	#define SVM_EXIT_READ_CR13 0xD
61	#define SVM_EXIT_READ_CR14 0xE
62	#define SVM_EXIT_READ_CR15 0xF
63	/** Writes to CR0-CR15. */
64	#define SVM_EXIT_WRITE_CR0 0x10
65	#define SVM_EXIT_WRITE_CR1 0x11
66	#define SVM_EXIT_WRITE_CR2 0x12
67	#define SVM_EXIT_WRITE_CR3 0x13
68	#define SVM_EXIT_WRITE_CR4 0x14
69	#define SVM_EXIT_WRITE_CR5 0x15
70	#define SVM_EXIT_WRITE_CR6 0x16
71	#define SVM_EXIT_WRITE_CR7 0x17
72	#define SVM_EXIT_WRITE_CR8 0x18
73	#define SVM_EXIT_WRITE_CR9 0x19
74	#define SVM_EXIT_WRITE_CR10 0x1A
75	#define SVM_EXIT_WRITE_CR11 0x1B
76	#define SVM_EXIT_WRITE_CR12 0x1C
77	#define SVM_EXIT_WRITE_CR13 0x1D
78	#define SVM_EXIT_WRITE_CR14 0x1E
79	#define SVM_EXIT_WRITE_CR15 0x1F
80	/** Read from DR0-DR15. */
81	#define SVM_EXIT_READ_DR0 0x20
82	#define SVM_EXIT_READ_DR1 0x21
83	#define SVM_EXIT_READ_DR2 0x22
84	#define SVM_EXIT_READ_DR3 0x23
85	#define SVM_EXIT_READ_DR4 0x24
86	#define SVM_EXIT_READ_DR5 0x25
87	#define SVM_EXIT_READ_DR6 0x26
88	#define SVM_EXIT_READ_DR7 0x27
89	#define SVM_EXIT_READ_DR8 0x28
90	#define SVM_EXIT_READ_DR9 0x29
91	#define SVM_EXIT_READ_DR10 0x2A
92	#define SVM_EXIT_READ_DR11 0x2B
93	#define SVM_EXIT_READ_DR12 0x2C
94	#define SVM_EXIT_READ_DR13 0x2D
95	#define SVM_EXIT_READ_DR14 0x2E
96	#define SVM_EXIT_READ_DR15 0x2F
97	/** Writes to DR0-DR15. */
98	#define SVM_EXIT_WRITE_DR0 0x30
99	#define SVM_EXIT_WRITE_DR1 0x31
100	#define SVM_EXIT_WRITE_DR2 0x32
101	#define SVM_EXIT_WRITE_DR3 0x33
102	#define SVM_EXIT_WRITE_DR4 0x34
103	#define SVM_EXIT_WRITE_DR5 0x35
104	#define SVM_EXIT_WRITE_DR6 0x36
105	#define SVM_EXIT_WRITE_DR7 0x37
106	#define SVM_EXIT_WRITE_DR8 0x38
107	#define SVM_EXIT_WRITE_DR9 0x39
108	#define SVM_EXIT_WRITE_DR10 0x3A
109	#define SVM_EXIT_WRITE_DR11 0x3B
110	#define SVM_EXIT_WRITE_DR12 0x3C
111	#define SVM_EXIT_WRITE_DR13 0x3D
112	#define SVM_EXIT_WRITE_DR14 0x3E
113	#define SVM_EXIT_WRITE_DR15 0x3F
114	/* Exception 0-31. */
115	#define SVM_EXIT_EXCEPTION_0 0x40
116	#define SVM_EXIT_EXCEPTION_1 0x41
117	#define SVM_EXIT_EXCEPTION_2 0x42
118	#define SVM_EXIT_EXCEPTION_3 0x43
119	#define SVM_EXIT_EXCEPTION_4 0x44
120	#define SVM_EXIT_EXCEPTION_5 0x45
121	#define SVM_EXIT_EXCEPTION_6 0x46
122	#define SVM_EXIT_EXCEPTION_7 0x47
123	#define SVM_EXIT_EXCEPTION_8 0x48
124	#define SVM_EXIT_EXCEPTION_9 0x49
125	#define SVM_EXIT_EXCEPTION_A 0x4A
126	#define SVM_EXIT_EXCEPTION_B 0x4B
127	#define SVM_EXIT_EXCEPTION_C 0x4C
128	#define SVM_EXIT_EXCEPTION_D 0x4D
129	#define SVM_EXIT_EXCEPTION_E 0x4E
130	#define SVM_EXIT_EXCEPTION_F 0x4F
131	#define SVM_EXIT_EXCEPTION_10 0x50
132	#define SVM_EXIT_EXCEPTION_11 0x51
133	#define SVM_EXIT_EXCEPTION_12 0x52
134	#define SVM_EXIT_EXCEPTION_13 0x53
135	#define SVM_EXIT_EXCEPTION_14 0x54
136	#define SVM_EXIT_EXCEPTION_15 0x55
137	#define SVM_EXIT_EXCEPTION_16 0x56
138	#define SVM_EXIT_EXCEPTION_17 0x57
139	#define SVM_EXIT_EXCEPTION_18 0x58
140	#define SVM_EXIT_EXCEPTION_19 0x59
141	#define SVM_EXIT_EXCEPTION_1A 0x5A
142	#define SVM_EXIT_EXCEPTION_1B 0x5B
143	#define SVM_EXIT_EXCEPTION_1C 0x5C
144	#define SVM_EXIT_EXCEPTION_1D 0x5D
145	#define SVM_EXIT_EXCEPTION_1E 0x5E
146	#define SVM_EXIT_EXCEPTION_1F 0x5F
147	/** Physical maskable interrupt. */
148	#define SVM_EXIT_INTR 0x60
149	/** Non-maskable interrupt. */
150	#define SVM_EXIT_NMI 0x61
151	/** System Management interrupt. */
152	#define SVM_EXIT_SMI 0x62
153	/** Physical INIT signal. */
154	#define SVM_EXIT_INIT 0x63
155	/** Virtual interrupt. */
156	#define SVM_EXIT_VINTR 0x64
157	/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
158	#define SVM_EXIT_CR0_SEL_WRITE 0x65
159	/** IDTR read. */
160	#define SVM_EXIT_IDTR_READ 0x66
161	/** GDTR read. */
162	#define SVM_EXIT_GDTR_READ 0x67
163	/** LDTR read. */
164	#define SVM_EXIT_LDTR_READ 0x68
165	/** TR read. */
166	#define SVM_EXIT_TR_READ 0x69
167	/** IDTR write. */
168	#define SVM_EXIT_IDTR_WRITE 0x6A
169	/** GDTR write. */
170	#define SVM_EXIT_GDTR_WRITE 0x6B
171	/** LDTR write. */
172	#define SVM_EXIT_LDTR_WRITE 0x6C
173	/** TR write. */
174	#define SVM_EXIT_TR_WRITE 0x6D
175	/** RDTSC instruction. */
176	#define SVM_EXIT_RDTSC 0x6E
177	/** RDPMC instruction. */
178	#define SVM_EXIT_RDPMC 0x6F
179	/** PUSHF instruction. */
180	#define SVM_EXIT_PUSHF 0x70
181	/** POPF instruction. */
182	#define SVM_EXIT_POPF 0x71
183	/** CPUID instruction. */
184	#define SVM_EXIT_CPUID 0x72
185	/** RSM instruction. */
186	#define SVM_EXIT_RSM 0x73
187	/** IRET instruction. */
188	#define SVM_EXIT_IRET 0x74
189	/** software interrupt (INTn instructions). */
190	#define SVM_EXIT_SWINT 0x75
191	/** INVD instruction. */
192	#define SVM_EXIT_INVD 0x76
193	/** PAUSE instruction. */
194	#define SVM_EXIT_PAUSE 0x77
195	/** HLT instruction. */
196	#define SVM_EXIT_HLT 0x78
197	/** INVLPG instructions. */
198	#define SVM_EXIT_INVLPG 0x79
199	/** INVLPGA instruction. */
200	#define SVM_EXIT_INVLPGA 0x7A
201	/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
202	#define SVM_EXIT_IOIO 0x7B
203	/** RDMSR or WRMSR access to protected MSR. */
204	#define SVM_EXIT_MSR 0x7C
205	/** task switch. */
206	#define SVM_EXIT_TASK_SWITCH 0x7D
207	/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
208	#define SVM_EXIT_FERR_FREEZE 0x7E
209	/** Shutdown. */
210	#define SVM_EXIT_SHUTDOWN 0x7F
211	/** VMRUN instruction. */
212	#define SVM_EXIT_VMRUN 0x80
213	/** VMMCALL instruction. */
214	#define SVM_EXIT_VMMCALL 0x81
215	/** VMLOAD instruction. */
216	#define SVM_EXIT_VMLOAD 0x82
217	/** VMSAVE instruction. */
218	#define SVM_EXIT_VMSAVE 0x83
219	/** STGI instruction. */
220	#define SVM_EXIT_STGI 0x84
221	/** CLGI instruction. */
222	#define SVM_EXIT_CLGI 0x85
223	/** SKINIT instruction. */
224	#define SVM_EXIT_SKINIT 0x86
225	/** RDTSCP instruction. */
226	#define SVM_EXIT_RDTSCP 0x87
227	/** ICEBP instruction. */
228	#define SVM_EXIT_ICEBP 0x88
229	/** WBINVD instruction. */
230	#define SVM_INVD 0x89
231	/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault.). */
232	#define SVM_EXIT_NPF 0x400
233
234	/** @} */
235
236
237	/** @name SVM_VMCB.ctrl.u32InterceptCtrl1
238	* @{
239	*/
240	/* 0 Intercept INTR (physical maskable interrupt) */
241	#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
242	/* 1 Intercept NMI */
243	#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
244	/* 2 Intercept SMI */
245	#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
246	/* 3 Intercept INIT */
247	#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
248	/* 4 Intercept VINTR (virtual maskable interrupt) */
249	#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
250	/* 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
251	#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
252	/* 6 Intercept reads of IDTR */
253	#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
254	/* 7 Intercept reads of GDTR */
255	#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
256	/* 8 Intercept reads of LDTR */
257	#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
258	/* 9 Intercept reads of TR */
259	#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
260	/* 10 Intercept writes of IDTR */
261	#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
262	/* 11 Intercept writes of GDTR */
263	#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
264	/* 12 Intercept writes of LDTR */
265	#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
266	/* 13 Intercept writes of TR */
267	#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
268	/* 14 Intercept RDTSC instruction */
269	#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
270	/* 15 Intercept RDPMC instruction */
271	#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
272	/* 16 Intercept PUSHF instruction */
273	#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
274	/* 17 Intercept POPF instruction */
275	#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
276	/* 18 Intercept CPUID instruction */
277	#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
278	/* 19 Intercept RSM instruction */
279	#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
280	/* 20 Intercept IRET instruction */
281	#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
282	/* 21 Intercept INTn instruction */
283	#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
284	/* 22 Intercept INVD instruction */
285	#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
286	/* 23 Intercept PAUSE instruction */
287	#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
288	/* 24 Intercept HLT instruction */
289	#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
290	/* 25 Intercept INVLPG instruction */
291	#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
292	/* 26 Intercept INVLPGA instruction */
293	#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
294	/* 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
295	#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
296	/* 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
297	#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
298	/* 29 Intercept task switches. */
299	#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
300	/* 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
301	#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
302	/* 31 Intercept shutdown events. */
303	#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
304	/** @} */
305
306
307	/** @name SVM_VMCB.ctrl.u32InterceptCtrl2
308	* @{
309	*/
310	/* 0 Intercept VMRUN instruction */
311	#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
312	/* 1 Intercept VMMCALL instruction */
313	#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
314	/* 2 Intercept VMLOAD instruction */
315	#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
316	/* 3 Intercept VMSAVE instruction */
317	#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
318	/* 4 Intercept STGI instruction */
319	#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
320	/* 5 Intercept CLGI instruction */
321	#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
322	/* 6 Intercept SKINIT instruction */
323	#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
324	/* 7 Intercept RDTSCP instruction */
325	#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
326	/* 8 Intercept ICEBP instruction */
327	#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
328	/* 9 Intercept WBINVD instruction */
329	#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
330	/** @} */
331
332	/** @name SVM_VMCB.ctrl.u64NestedPaging
333	* @{
334	*/
335	#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
336	/** @} */
337
338	/** @name SVM_VMCB.ctrl.u64IntShadow
339	* @{
340	*/
341	#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
342	/** @} */
343
344
345	/** @name SVM_INTCTRL.u3Type
346	* @{
347	*/
348	/** External or virtual interrupt. */
349	#define SVM_EVENT_EXTERNAL_IRQ 0
350	/** Non-maskable interrupt. */
351	#define SVM_EVENT_NMI 1
352	/** Exception; fault or trap. */
353	#define SVM_EVENT_EXCEPTION 3
354	/** Software interrupt. */
355	#define SVM_EVENT_SOFTWARE_INT 4
356	/** @} */
357
358
359
360
361	/**
362	* SVM Selector type; includes hidden parts
363	*/
364	#pragma pack(1)
365	typedef struct
366	{
367	uint16_t u16Sel;
368	uint16_t u16Attr;
369	uint32_t u32Limit;
370	uint64_t u64Base; /* Only lower 32 bits are implemented for CS, DS, ES & SS. */
371	} SVMSEL;
372	#pragma pack()
373
374	/**
375	* SVM GDTR/IDTR type
376	*/
377	#pragma pack(1)
378	typedef struct
379	{
380	uint16_t u16Reserved1;
381	uint16_t u16Reserved2;
382	uint32_t u32Limit; /* Only lower 16 bits are implemented. */
383	uint64_t u64Base;
384	} SVMGDTR;
385	#pragma pack()
386
387	typedef SVMGDTR SVMIDTR;
388
389	/**
390	* SVM Event injection structure
391	*/
392	#pragma pack(1)
393	typedef union
394	{
395	struct
396	{
397	uint32_t u8Vector : 8;
398	uint32_t u3Type : 3;
399	uint32_t u1ErrorCodeValid : 1;
400	uint32_t u19Reserved : 19;
401	uint32_t u1Valid : 1;
402	uint32_t u32ErrorCode : 32;
403	} n;
404	uint64_t au64[1];
405	} SVM_EVENT;
406	#pragma pack()
407
408
409	/**
410	* SVM Interrupt control structure
411	*/
412	#pragma pack(1)
413	typedef union
414	{
415	struct
416	{
417	uint32_t u8VTPR : 8;
418	uint32_t u1VIrqValid : 1;
419	uint32_t u7Reserved : 7;
420	uint32_t u4VIrqPriority : 4;
421	uint32_t u1IgnoreTPR : 1;
422	uint32_t u3Reserved : 3;
423	uint32_t u1VIrqMasking : 1;
424	uint32_t u7Reserved2 : 7;
425	uint32_t u8VIrqVector : 8;
426	uint32_t u24Reserved : 24;
427	} n;
428	uint64_t au64[1];
429	} SVM_INTCTRL;
430	#pragma pack()
431
432
433	/**
434	* SVM TLB control structure
435	*/
436	#pragma pack(1)
437	typedef union
438	{
439	struct
440	{
441	uint32_t u32ASID : 32;
442	uint32_t u1TLBFlush : 1;
443	uint32_t u7Reserved : 7;
444	uint32_t u24Reserved : 24;
445	} n;
446	uint64_t au64[1];
447	} SVM_TLBCTRL;
448	#pragma pack()
449
450
451	/**
452	* SVM IOIO exit structure
453	*/
454	#pragma pack(1)
455	typedef union
456	{
457	struct
458	{
459	uint32_t u1Type : 1; /* 0 = out, 1 = in */
460	uint32_t u1Reserved : 1;
461	uint32_t u1STR : 1;
462	uint32_t u1REP : 1;
463	uint32_t u1OP8 : 1;
464	uint32_t u1OP16 : 1;
465	uint32_t u1OP32 : 1;
466	uint32_t u1ADDR16 : 1;
467	uint32_t u1ADDR32 : 1;
468	uint32_t u1ADDR64 : 1;
469	uint32_t u6Reserved : 6;
470	uint32_t u16Port : 16;
471	} n;
472	uint32_t au32[1];
473	} SVM_IOIO_EXIT;
474	#pragma pack()
475
476
477	/**
478	* SVM VM Control Block. (VMCB)
479	*/
480	#pragma pack(1)
481	typedef struct _SVM_VMCB
482	{
483	/** Control Area. */
484	struct
485	{
486	/** Offset 0x00 - Intercept reads of CR0-15. */
487	uint16_t u16InterceptRdCRx;
488	/** Offset 0x02 - Intercept writes to CR0-15. */
489	uint16_t u16InterceptWrCRx;
490	/** Offset 0x04 - Intercept reads of DR0-15. */
491	uint16_t u16InterceptRdDRx;
492	/** Offset 0x06 - Intercept writes to DR0-15. */
493	uint16_t u16InterceptWrDRx;
494	/** Offset 0x08 - Intercept exception vectors 0-31. */
495	uint32_t u32InterceptException;
496	/** Offset 0x0C - Intercept control field 1. */
497	uint32_t u32InterceptCtrl1;
498	/** Offset 0x0C - Intercept control field 2. */
499	uint32_t u32InterceptCtrl2;
500	/** Offset 0x14-0x3F - Reserved. */
501	uint8_t u8Reserved[0x40-0x14];
502	/** Offset 0x40 - Physical address of IOPM. */
503	uint64_t u64IOPMPhysAddr;
504	/** Offset 0x48 - Physical address of MSRPM. */
505	uint64_t u64MSRPMPhysAddr;
506	/** Offset 0x50 - TSC Offset. */
507	uint64_t u64TSCOffset;
508	/** Offset 0x58 - TLB control field. */
509	SVM_TLBCTRL TLBCtrl;
510	/** Offset 0x60 - Interrupt control field. */
511	SVM_INTCTRL IntCtrl;
512	/** Offset 0x68 - Interrupt shadow. */
513	uint64_t u64IntShadow;
514	/** Offset 0x70 - Exit code. */
515	uint64_t u64ExitCode;
516	/** Offset 0x78 - Exit info 1. */
517	uint64_t u64ExitInfo1;
518	/** Offset 0x80 - Exit info 2. */
519	uint64_t u64ExitInfo2;
520	/** Offset 0x88 - Exit Interrupt info. */
521	SVM_EVENT ExitIntInfo;
522	/** Offset 0x90 - Nested Paging. */
523	uint64_t u64NestedPaging;
524	/** Offset 0x98-0xA7 - Reserved. */
525	uint8_t u8Reserved2[0xA8-0x98];
526	/** Offset 0xA8 - Event injection. */
527	SVM_EVENT EventInject;
528	/** Offset 0xB0 - Host CR3 for nested paging. */
529	uint64_t u64HostCR3;
530	/** Offset 0xB8 - LBR Virtualization. */
531	uint64_t u64LBRVirt;
532	} ctrl;
533
534	/** Offset 0xC0-0x3FF - Reserved. */
535	uint8_t u8Reserved3[0x400-0xC0];
536
537	/* State Save Area. Starts at offset 0x400. */
538	struct
539	{
540	/** Offset 0x400 - Guest ES register + hidden parts. */
541	SVMSEL ES;
542	/** Offset 0x410 - Guest CS register + hidden parts. */
543	SVMSEL CS;
544	/** Offset 0x420 - Guest SS register + hidden parts. */
545	SVMSEL SS;
546	/** Offset 0x430 - Guest DS register + hidden parts. */
547	SVMSEL DS;
548	/** Offset 0x440 - Guest FS register + hidden parts. */
549	SVMSEL FS;
550	/** Offset 0x450 - Guest GS register + hidden parts. */
551	SVMSEL GS;
552	/** Offset 0x460 - Guest GDTR register. */
553	SVMGDTR GDTR;
554	/** Offset 0x470 - Guest LDTR register + hidden parts. */
555	SVMSEL LDTR;
556	/** Offset 0x480 - Guest IDTR register. */
557	SVMIDTR IDTR;
558	/** Offset 0x490 - Guest TR register + hidden parts. */
559	SVMSEL TR;
560	/** Offset 0x4A0-0x4CA - Reserved. */
561	uint8_t u8Reserved4[0x4CB-0x4A0];
562	/** Offset 0x4CB - CPL. */
563	uint8_t u8CPL;
564	/** Offset 0x4CC-0x4CF - Reserved. */
565	uint8_t u8Reserved5[0x4D0-0x4CC];
566	/** Offset 0x4D0 - EFER. */
567	uint64_t u64EFER;
568	/** Offset 0x4D8-0x547 - Reserved. */
569	uint8_t u8Reserved6[0x548-0x4D8];
570	/** Offset 0x548 - CR4. */
571	uint64_t u64CR4;
572	/** Offset 0x550 - CR3. */
573	uint64_t u64CR3;
574	/** Offset 0x558 - CR0. */
575	uint64_t u64CR0;
576	/** Offset 0x560 - DR7. */
577	uint64_t u64DR7;
578	/** Offset 0x568 - DR6. */
579	uint64_t u64DR6;
580	/** Offset 0x570 - RFLAGS. */
581	uint64_t u64RFlags;
582	/** Offset 0x578 - RIP. */
583	uint64_t u64RIP;
584	/** Offset 0x580-0x5D7 - Reserved. */
585	uint8_t u8Reserved7[0x5D8-0x580];
586	/** Offset 0x5D8 - RSP. */
587	uint64_t u64RSP;
588	/** Offset 0x5E0-0x5F7 - Reserved. */
589	uint8_t u8Reserved8[0x5F8-0x5E0];
590	/** Offset 0x5F8 - RAX. */
591	uint64_t u64RAX;
592	/** Offset 0x600 - STAR. */
593	uint64_t u64STAR;
594	/** Offset 0x608 - LSTAR. */
595	uint64_t u64LSTAR;
596	/** Offset 0x610 - CSTAR. */
597	uint64_t u64CSTAR;
598	/** Offset 0x618 - SFMASK. */
599	uint64_t u64SFMASK;
600	/** Offset 0x620 - KernelGSBase. */
601	uint64_t u64KernelGSBase;
602	/** Offset 0x628 - SYSENTER_CS. */
603	uint64_t u64SysEnterCS;
604	/** Offset 0x630 - SYSENTER_ESP. */
605	uint64_t u64SysEnterESP;
606	/** Offset 0x638 - SYSENTER_EIP. */
607	uint64_t u64SysEnterEIP;
608	/** Offset 0x640 - CR2. */
609	uint64_t u64CR2;
610	/** Offset 0x648-0x667 - Reserved. */
611	uint8_t u8Reserved9[0x668-0x648];
612	/** Offset 0x668 - G_PAT. */
613	uint64_t u64GPAT;
614	/** Offset 0x670 - DBGCTL. */
615	uint64_t u64DBGCTL;
616	/** Offset 0x678 - BR_FROM. */
617	uint64_t u64BR_FROM;
618	/** Offset 0x680 - BR_TO. */
619	uint64_t u64BR_TO;
620	/** Offset 0x688 - LASTEXCPFROM. */
621	uint64_t u64LASTEXCPFROM;
622	/** Offset 0x690 - LASTEXCPTO. */
623	uint64_t u64LASTEXCPTO;
624	} guest;
625
626	/** Offset 0x698-0xFFF- Reserved. */
627	uint8_t u8Reserved10[0x1000-0x698];
628	} SVM_VMCB;
629	#pragma pack()
630
631
632	/**
633	* Prepares for and executes VMRUN.
634	*
635	* @returns VBox status code.
636	* @param pVMCBHostPhys Physical address of host VMCB.
637	* @param pVMCBPhys Physical address of the VMCB.
638	* @param pCtx Guest context.
639	*/
640	DECLASM(int) SVMVMRun(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx);
641
642	/**
643	* Executes INVLPGA.
644	*
645	* @param pPageGC Virtual page to invalidate.
646	* @param u32ASID Tagged TLB id.
647	*/
648	DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t u32ASID);
649
650	/** @} */
651
652	#endif
653

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source: vbox/trunk/include/VBox/hwacc_svm.h@ 7097

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