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source: vbox/trunk/include/VBox/hwacc_svm.h@ 23266

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1/** @file
2 * HWACCM - SVM Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_svm_h
31#define ___VBox_svm_h
32
33#include <VBox/types.h>
34#include <VBox/err.h>
35#include <iprt/assert.h>
36#include <iprt/asm.h>
37
38/** @defgroup grp_svm svm Types and Definitions
39 * @ingroup grp_hwaccm
40 * @{
41 */
42
43/** @name SVM features for cpuid 0x8000000a
44 * @{
45 */
46#define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
47#define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
48#define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
49#define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
50#define AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE RT_BIT(9)
51/** @} */
52
53
54/** @name SVM Basic Exit Reasons.
55 * @{
56 */
57/** Invalid guest state in VMCB. */
58#define SVM_EXIT_INVALID -1
59/** Read from CR0-CR15. */
60#define SVM_EXIT_READ_CR0 0x0
61#define SVM_EXIT_READ_CR1 0x1
62#define SVM_EXIT_READ_CR2 0x2
63#define SVM_EXIT_READ_CR3 0x3
64#define SVM_EXIT_READ_CR4 0x4
65#define SVM_EXIT_READ_CR5 0x5
66#define SVM_EXIT_READ_CR6 0x6
67#define SVM_EXIT_READ_CR7 0x7
68#define SVM_EXIT_READ_CR8 0x8
69#define SVM_EXIT_READ_CR9 0x9
70#define SVM_EXIT_READ_CR10 0xA
71#define SVM_EXIT_READ_CR11 0xB
72#define SVM_EXIT_READ_CR12 0xC
73#define SVM_EXIT_READ_CR13 0xD
74#define SVM_EXIT_READ_CR14 0xE
75#define SVM_EXIT_READ_CR15 0xF
76/** Writes to CR0-CR15. */
77#define SVM_EXIT_WRITE_CR0 0x10
78#define SVM_EXIT_WRITE_CR1 0x11
79#define SVM_EXIT_WRITE_CR2 0x12
80#define SVM_EXIT_WRITE_CR3 0x13
81#define SVM_EXIT_WRITE_CR4 0x14
82#define SVM_EXIT_WRITE_CR5 0x15
83#define SVM_EXIT_WRITE_CR6 0x16
84#define SVM_EXIT_WRITE_CR7 0x17
85#define SVM_EXIT_WRITE_CR8 0x18
86#define SVM_EXIT_WRITE_CR9 0x19
87#define SVM_EXIT_WRITE_CR10 0x1A
88#define SVM_EXIT_WRITE_CR11 0x1B
89#define SVM_EXIT_WRITE_CR12 0x1C
90#define SVM_EXIT_WRITE_CR13 0x1D
91#define SVM_EXIT_WRITE_CR14 0x1E
92#define SVM_EXIT_WRITE_CR15 0x1F
93/** Read from DR0-DR15. */
94#define SVM_EXIT_READ_DR0 0x20
95#define SVM_EXIT_READ_DR1 0x21
96#define SVM_EXIT_READ_DR2 0x22
97#define SVM_EXIT_READ_DR3 0x23
98#define SVM_EXIT_READ_DR4 0x24
99#define SVM_EXIT_READ_DR5 0x25
100#define SVM_EXIT_READ_DR6 0x26
101#define SVM_EXIT_READ_DR7 0x27
102#define SVM_EXIT_READ_DR8 0x28
103#define SVM_EXIT_READ_DR9 0x29
104#define SVM_EXIT_READ_DR10 0x2A
105#define SVM_EXIT_READ_DR11 0x2B
106#define SVM_EXIT_READ_DR12 0x2C
107#define SVM_EXIT_READ_DR13 0x2D
108#define SVM_EXIT_READ_DR14 0x2E
109#define SVM_EXIT_READ_DR15 0x2F
110/** Writes to DR0-DR15. */
111#define SVM_EXIT_WRITE_DR0 0x30
112#define SVM_EXIT_WRITE_DR1 0x31
113#define SVM_EXIT_WRITE_DR2 0x32
114#define SVM_EXIT_WRITE_DR3 0x33
115#define SVM_EXIT_WRITE_DR4 0x34
116#define SVM_EXIT_WRITE_DR5 0x35
117#define SVM_EXIT_WRITE_DR6 0x36
118#define SVM_EXIT_WRITE_DR7 0x37
119#define SVM_EXIT_WRITE_DR8 0x38
120#define SVM_EXIT_WRITE_DR9 0x39
121#define SVM_EXIT_WRITE_DR10 0x3A
122#define SVM_EXIT_WRITE_DR11 0x3B
123#define SVM_EXIT_WRITE_DR12 0x3C
124#define SVM_EXIT_WRITE_DR13 0x3D
125#define SVM_EXIT_WRITE_DR14 0x3E
126#define SVM_EXIT_WRITE_DR15 0x3F
127/* Exception 0-31. */
128#define SVM_EXIT_EXCEPTION_0 0x40
129#define SVM_EXIT_EXCEPTION_1 0x41
130#define SVM_EXIT_EXCEPTION_2 0x42
131#define SVM_EXIT_EXCEPTION_3 0x43
132#define SVM_EXIT_EXCEPTION_4 0x44
133#define SVM_EXIT_EXCEPTION_5 0x45
134#define SVM_EXIT_EXCEPTION_6 0x46
135#define SVM_EXIT_EXCEPTION_7 0x47
136#define SVM_EXIT_EXCEPTION_8 0x48
137#define SVM_EXIT_EXCEPTION_9 0x49
138#define SVM_EXIT_EXCEPTION_A 0x4A
139#define SVM_EXIT_EXCEPTION_B 0x4B
140#define SVM_EXIT_EXCEPTION_C 0x4C
141#define SVM_EXIT_EXCEPTION_D 0x4D
142#define SVM_EXIT_EXCEPTION_E 0x4E
143#define SVM_EXIT_EXCEPTION_F 0x4F
144#define SVM_EXIT_EXCEPTION_10 0x50
145#define SVM_EXIT_EXCEPTION_11 0x51
146#define SVM_EXIT_EXCEPTION_12 0x52
147#define SVM_EXIT_EXCEPTION_13 0x53
148#define SVM_EXIT_EXCEPTION_14 0x54
149#define SVM_EXIT_EXCEPTION_15 0x55
150#define SVM_EXIT_EXCEPTION_16 0x56
151#define SVM_EXIT_EXCEPTION_17 0x57
152#define SVM_EXIT_EXCEPTION_18 0x58
153#define SVM_EXIT_EXCEPTION_19 0x59
154#define SVM_EXIT_EXCEPTION_1A 0x5A
155#define SVM_EXIT_EXCEPTION_1B 0x5B
156#define SVM_EXIT_EXCEPTION_1C 0x5C
157#define SVM_EXIT_EXCEPTION_1D 0x5D
158#define SVM_EXIT_EXCEPTION_1E 0x5E
159#define SVM_EXIT_EXCEPTION_1F 0x5F
160/** Physical maskable interrupt. */
161#define SVM_EXIT_INTR 0x60
162/** Non-maskable interrupt. */
163#define SVM_EXIT_NMI 0x61
164/** System Management interrupt. */
165#define SVM_EXIT_SMI 0x62
166/** Physical INIT signal. */
167#define SVM_EXIT_INIT 0x63
168/** Virtual interrupt. */
169#define SVM_EXIT_VINTR 0x64
170/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
171#define SVM_EXIT_CR0_SEL_WRITE 0x65
172/** IDTR read. */
173#define SVM_EXIT_IDTR_READ 0x66
174/** GDTR read. */
175#define SVM_EXIT_GDTR_READ 0x67
176/** LDTR read. */
177#define SVM_EXIT_LDTR_READ 0x68
178/** TR read. */
179#define SVM_EXIT_TR_READ 0x69
180/** IDTR write. */
181#define SVM_EXIT_IDTR_WRITE 0x6A
182/** GDTR write. */
183#define SVM_EXIT_GDTR_WRITE 0x6B
184/** LDTR write. */
185#define SVM_EXIT_LDTR_WRITE 0x6C
186/** TR write. */
187#define SVM_EXIT_TR_WRITE 0x6D
188/** RDTSC instruction. */
189#define SVM_EXIT_RDTSC 0x6E
190/** RDPMC instruction. */
191#define SVM_EXIT_RDPMC 0x6F
192/** PUSHF instruction. */
193#define SVM_EXIT_PUSHF 0x70
194/** POPF instruction. */
195#define SVM_EXIT_POPF 0x71
196/** CPUID instruction. */
197#define SVM_EXIT_CPUID 0x72
198/** RSM instruction. */
199#define SVM_EXIT_RSM 0x73
200/** IRET instruction. */
201#define SVM_EXIT_IRET 0x74
202/** software interrupt (INTn instructions). */
203#define SVM_EXIT_SWINT 0x75
204/** INVD instruction. */
205#define SVM_EXIT_INVD 0x76
206/** PAUSE instruction. */
207#define SVM_EXIT_PAUSE 0x77
208/** HLT instruction. */
209#define SVM_EXIT_HLT 0x78
210/** INVLPG instructions. */
211#define SVM_EXIT_INVLPG 0x79
212/** INVLPGA instruction. */
213#define SVM_EXIT_INVLPGA 0x7A
214/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
215#define SVM_EXIT_IOIO 0x7B
216/** RDMSR or WRMSR access to protected MSR. */
217#define SVM_EXIT_MSR 0x7C
218/** task switch. */
219#define SVM_EXIT_TASK_SWITCH 0x7D
220/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
221#define SVM_EXIT_FERR_FREEZE 0x7E
222/** Shutdown. */
223#define SVM_EXIT_SHUTDOWN 0x7F
224/** VMRUN instruction. */
225#define SVM_EXIT_VMRUN 0x80
226/** VMMCALL instruction. */
227#define SVM_EXIT_VMMCALL 0x81
228/** VMLOAD instruction. */
229#define SVM_EXIT_VMLOAD 0x82
230/** VMSAVE instruction. */
231#define SVM_EXIT_VMSAVE 0x83
232/** STGI instruction. */
233#define SVM_EXIT_STGI 0x84
234/** CLGI instruction. */
235#define SVM_EXIT_CLGI 0x85
236/** SKINIT instruction. */
237#define SVM_EXIT_SKINIT 0x86
238/** RDTSCP instruction. */
239#define SVM_EXIT_RDTSCP 0x87
240/** ICEBP instruction. */
241#define SVM_EXIT_ICEBP 0x88
242/** WBINVD instruction. */
243#define SVM_EXIT_WBINVD 0x89
244/** MONITOR instruction. */
245#define SVM_EXIT_MONITOR 0x8A
246/** MWAIT instruction uncond. */
247#define SVM_EXIT_MWAIT_UNCOND 0x8B
248/** MWAIT instruction when armed. */
249#define SVM_EXIT_MWAIT_ARMED 0x8C
250/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
251#define SVM_EXIT_NPF 0x400
252
253/** @} */
254
255
256/** @name SVM_VMCB.u64ExitInfo2
257 * @{
258 */
259/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
260#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
261/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
262#define SVM_EXIT2_TASK_SWITCH_JMP RT_BIT_64(38)
263/** Set to 1 if the task switch has an error code; else cleared to 0. */
264#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
265/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
266#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
267/** @} */
268
269/** @name SVM_VMCB.ctrl.u32InterceptCtrl1
270 * @{
271 */
272/** 0 Intercept INTR (physical maskable interrupt) */
273#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
274/** 1 Intercept NMI */
275#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
276/** 2 Intercept SMI */
277#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
278/** 3 Intercept INIT */
279#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
280/** 4 Intercept VINTR (virtual maskable interrupt) */
281#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
282/** 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
283#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
284/** 6 Intercept reads of IDTR */
285#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
286/** 7 Intercept reads of GDTR */
287#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
288/** 8 Intercept reads of LDTR */
289#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
290/** 9 Intercept reads of TR */
291#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
292/** 10 Intercept writes of IDTR */
293#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
294/** 11 Intercept writes of GDTR */
295#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
296/** 12 Intercept writes of LDTR */
297#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
298/** 13 Intercept writes of TR */
299#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
300/** 14 Intercept RDTSC instruction */
301#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
302/** 15 Intercept RDPMC instruction */
303#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
304/** 16 Intercept PUSHF instruction */
305#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
306/** 17 Intercept POPF instruction */
307#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
308/** 18 Intercept CPUID instruction */
309#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
310/** 19 Intercept RSM instruction */
311#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
312/** 20 Intercept IRET instruction */
313#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
314/** 21 Intercept INTn instruction */
315#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
316/** 22 Intercept INVD instruction */
317#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
318/** 23 Intercept PAUSE instruction */
319#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
320/** 24 Intercept HLT instruction */
321#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
322/** 25 Intercept INVLPG instruction */
323#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
324/** 26 Intercept INVLPGA instruction */
325#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
326/** 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
327#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
328/** 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
329#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
330/** 29 Intercept task switches. */
331#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
332/** 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
333#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
334/** 31 Intercept shutdown events. */
335#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
336/** @} */
337
338
339/** @name SVM_VMCB.ctrl.u32InterceptCtrl2
340 * @{
341 */
342/** 0 Intercept VMRUN instruction */
343#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
344/** 1 Intercept VMMCALL instruction */
345#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
346/** 2 Intercept VMLOAD instruction */
347#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
348/** 3 Intercept VMSAVE instruction */
349#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
350/** 4 Intercept STGI instruction */
351#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
352/** 5 Intercept CLGI instruction */
353#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
354/** 6 Intercept SKINIT instruction */
355#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
356/** 7 Intercept RDTSCP instruction */
357#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
358/** 8 Intercept ICEBP instruction */
359#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
360/** 9 Intercept WBINVD instruction */
361#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
362/** 10 Intercept MONITOR instruction */
363#define SVM_CTRL2_INTERCEPT_MONITOR RT_BIT(10)
364/** 11 Intercept MWAIT instruction unconditionally */
365#define SVM_CTRL2_INTERCEPT_MWAIT_UNCOND RT_BIT(11)
366/** 12 Intercept MWAIT instruction when armed */
367#define SVM_CTRL2_INTERCEPT_MWAIT_ARMED RT_BIT(12)
368/** @} */
369
370/** @name SVM_VMCB.ctrl.u64NestedPaging
371 * @{
372 */
373#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
374/** @} */
375
376/** @name SVM_VMCB.ctrl.u64IntShadow
377 * @{
378 */
379#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
380/** @} */
381
382
383/** @name SVM_INTCTRL.u3Type
384 * @{
385 */
386/** External or virtual interrupt. */
387#define SVM_EVENT_EXTERNAL_IRQ 0
388/** Non-maskable interrupt. */
389#define SVM_EVENT_NMI 2
390/** Exception; fault or trap. */
391#define SVM_EVENT_EXCEPTION 3
392/** Software interrupt. */
393#define SVM_EVENT_SOFTWARE_INT 4
394/** @} */
395
396
397
398
399/**
400 * SVM Selector type; includes hidden parts
401 */
402#pragma pack(1)
403typedef struct
404{
405 uint16_t u16Sel;
406 uint16_t u16Attr;
407 uint32_t u32Limit;
408 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
409} SVMSEL;
410#pragma pack()
411
412/**
413 * SVM GDTR/IDTR type
414 */
415#pragma pack(1)
416typedef struct
417{
418 uint16_t u16Reserved1;
419 uint16_t u16Reserved2;
420 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
421 uint64_t u64Base;
422} SVMGDTR;
423#pragma pack()
424
425typedef SVMGDTR SVMIDTR;
426
427/**
428 * SVM Event injection structure
429 */
430#pragma pack(1)
431typedef union
432{
433 struct
434 {
435 uint32_t u8Vector : 8;
436 uint32_t u3Type : 3;
437 uint32_t u1ErrorCodeValid : 1;
438 uint32_t u19Reserved : 19;
439 uint32_t u1Valid : 1;
440 uint32_t u32ErrorCode : 32;
441 } n;
442 uint64_t au64[1];
443} SVM_EVENT;
444#pragma pack()
445
446
447/**
448 * SVM Interrupt control structure
449 */
450#pragma pack(1)
451typedef union
452{
453 struct
454 {
455 uint32_t u8VTPR : 8;
456 uint32_t u1VIrqValid : 1;
457 uint32_t u7Reserved : 7;
458 uint32_t u4VIrqPriority : 4;
459 uint32_t u1IgnoreTPR : 1;
460 uint32_t u3Reserved : 3;
461 uint32_t u1VIrqMasking : 1;
462 uint32_t u7Reserved2 : 7;
463 uint32_t u8VIrqVector : 8;
464 uint32_t u24Reserved : 24;
465 } n;
466 uint64_t au64[1];
467} SVM_INTCTRL;
468#pragma pack()
469
470
471/**
472 * SVM TLB control structure
473 */
474#pragma pack(1)
475typedef union
476{
477 struct
478 {
479 uint32_t u32ASID : 32;
480 uint32_t u1TLBFlush : 1;
481 uint32_t u7Reserved : 7;
482 uint32_t u24Reserved : 24;
483 } n;
484 uint64_t au64[1];
485} SVM_TLBCTRL;
486#pragma pack()
487
488
489/**
490 * SVM IOIO exit structure
491 */
492#pragma pack(1)
493typedef union
494{
495 struct
496 {
497 uint32_t u1Type : 1; /**< 0 = out, 1 = in */
498 uint32_t u1Reserved : 1;
499 uint32_t u1STR : 1;
500 uint32_t u1REP : 1;
501 uint32_t u1OP8 : 1;
502 uint32_t u1OP16 : 1;
503 uint32_t u1OP32 : 1;
504 uint32_t u1ADDR16 : 1;
505 uint32_t u1ADDR32 : 1;
506 uint32_t u1ADDR64 : 1;
507 uint32_t u6Reserved : 6;
508 uint32_t u16Port : 16;
509 } n;
510 uint32_t au32[1];
511} SVM_IOIO_EXIT;
512#pragma pack()
513
514/**
515 * SVM nested paging structure
516 */
517#pragma pack(1)
518typedef union
519{
520 struct
521 {
522 uint32_t u1NestedPaging : 1; /**< enabled/disabled */
523 } n;
524 uint64_t au64[1];
525} SVM_NPCTRL;
526#pragma pack()
527
528/**
529 * SVM VM Control Block. (VMCB)
530 */
531#pragma pack(1)
532typedef struct _SVM_VMCB
533{
534 /** Control Area. */
535 struct
536 {
537 /** Offset 0x00 - Intercept reads of CR0-15. */
538 uint16_t u16InterceptRdCRx;
539 /** Offset 0x02 - Intercept writes to CR0-15. */
540 uint16_t u16InterceptWrCRx;
541 /** Offset 0x04 - Intercept reads of DR0-15. */
542 uint16_t u16InterceptRdDRx;
543 /** Offset 0x06 - Intercept writes to DR0-15. */
544 uint16_t u16InterceptWrDRx;
545 /** Offset 0x08 - Intercept exception vectors 0-31. */
546 uint32_t u32InterceptException;
547 /** Offset 0x0C - Intercept control field 1. */
548 uint32_t u32InterceptCtrl1;
549 /** Offset 0x0C - Intercept control field 2. */
550 uint32_t u32InterceptCtrl2;
551 /** Offset 0x14-0x3F - Reserved. */
552 uint8_t u8Reserved[0x40-0x14];
553 /** Offset 0x40 - Physical address of IOPM. */
554 uint64_t u64IOPMPhysAddr;
555 /** Offset 0x48 - Physical address of MSRPM. */
556 uint64_t u64MSRPMPhysAddr;
557 /** Offset 0x50 - TSC Offset. */
558 uint64_t u64TSCOffset;
559 /** Offset 0x58 - TLB control field. */
560 SVM_TLBCTRL TLBCtrl;
561 /** Offset 0x60 - Interrupt control field. */
562 SVM_INTCTRL IntCtrl;
563 /** Offset 0x68 - Interrupt shadow. */
564 uint64_t u64IntShadow;
565 /** Offset 0x70 - Exit code. */
566 uint64_t u64ExitCode;
567 /** Offset 0x78 - Exit info 1. */
568 uint64_t u64ExitInfo1;
569 /** Offset 0x80 - Exit info 2. */
570 uint64_t u64ExitInfo2;
571 /** Offset 0x88 - Exit Interrupt info. */
572 SVM_EVENT ExitIntInfo;
573 /** Offset 0x90 - Nested Paging. */
574 SVM_NPCTRL NestedPaging;
575 /** Offset 0x98-0xA7 - Reserved. */
576 uint8_t u8Reserved2[0xA8-0x98];
577 /** Offset 0xA8 - Event injection. */
578 SVM_EVENT EventInject;
579 /** Offset 0xB0 - Host CR3 for nested paging. */
580 uint64_t u64NestedPagingCR3;
581 /** Offset 0xB8 - LBR Virtualization. */
582 uint64_t u64LBRVirt;
583 } ctrl;
584
585 /** Offset 0xC0-0x3FF - Reserved. */
586 uint8_t u8Reserved3[0x400-0xC0];
587
588 /** State Save Area. Starts at offset 0x400. */
589 struct
590 {
591 /** Offset 0x400 - Guest ES register + hidden parts. */
592 SVMSEL ES;
593 /** Offset 0x410 - Guest CS register + hidden parts. */
594 SVMSEL CS;
595 /** Offset 0x420 - Guest SS register + hidden parts. */
596 SVMSEL SS;
597 /** Offset 0x430 - Guest DS register + hidden parts. */
598 SVMSEL DS;
599 /** Offset 0x440 - Guest FS register + hidden parts. */
600 SVMSEL FS;
601 /** Offset 0x450 - Guest GS register + hidden parts. */
602 SVMSEL GS;
603 /** Offset 0x460 - Guest GDTR register. */
604 SVMGDTR GDTR;
605 /** Offset 0x470 - Guest LDTR register + hidden parts. */
606 SVMSEL LDTR;
607 /** Offset 0x480 - Guest IDTR register. */
608 SVMIDTR IDTR;
609 /** Offset 0x490 - Guest TR register + hidden parts. */
610 SVMSEL TR;
611 /** Offset 0x4A0-0x4CA - Reserved. */
612 uint8_t u8Reserved4[0x4CB-0x4A0];
613 /** Offset 0x4CB - CPL. */
614 uint8_t u8CPL;
615 /** Offset 0x4CC-0x4CF - Reserved. */
616 uint8_t u8Reserved5[0x4D0-0x4CC];
617 /** Offset 0x4D0 - EFER. */
618 uint64_t u64EFER;
619 /** Offset 0x4D8-0x547 - Reserved. */
620 uint8_t u8Reserved6[0x548-0x4D8];
621 /** Offset 0x548 - CR4. */
622 uint64_t u64CR4;
623 /** Offset 0x550 - CR3. */
624 uint64_t u64CR3;
625 /** Offset 0x558 - CR0. */
626 uint64_t u64CR0;
627 /** Offset 0x560 - DR7. */
628 uint64_t u64DR7;
629 /** Offset 0x568 - DR6. */
630 uint64_t u64DR6;
631 /** Offset 0x570 - RFLAGS. */
632 uint64_t u64RFlags;
633 /** Offset 0x578 - RIP. */
634 uint64_t u64RIP;
635 /** Offset 0x580-0x5D7 - Reserved. */
636 uint8_t u8Reserved7[0x5D8-0x580];
637 /** Offset 0x5D8 - RSP. */
638 uint64_t u64RSP;
639 /** Offset 0x5E0-0x5F7 - Reserved. */
640 uint8_t u8Reserved8[0x5F8-0x5E0];
641 /** Offset 0x5F8 - RAX. */
642 uint64_t u64RAX;
643 /** Offset 0x600 - STAR. */
644 uint64_t u64STAR;
645 /** Offset 0x608 - LSTAR. */
646 uint64_t u64LSTAR;
647 /** Offset 0x610 - CSTAR. */
648 uint64_t u64CSTAR;
649 /** Offset 0x618 - SFMASK. */
650 uint64_t u64SFMASK;
651 /** Offset 0x620 - KernelGSBase. */
652 uint64_t u64KernelGSBase;
653 /** Offset 0x628 - SYSENTER_CS. */
654 uint64_t u64SysEnterCS;
655 /** Offset 0x630 - SYSENTER_ESP. */
656 uint64_t u64SysEnterESP;
657 /** Offset 0x638 - SYSENTER_EIP. */
658 uint64_t u64SysEnterEIP;
659 /** Offset 0x640 - CR2. */
660 uint64_t u64CR2;
661 /** Offset 0x648-0x667 - Reserved. */
662 uint8_t u8Reserved9[0x668-0x648];
663 /** Offset 0x668 - G_PAT. */
664 uint64_t u64GPAT;
665 /** Offset 0x670 - DBGCTL. */
666 uint64_t u64DBGCTL;
667 /** Offset 0x678 - BR_FROM. */
668 uint64_t u64BR_FROM;
669 /** Offset 0x680 - BR_TO. */
670 uint64_t u64BR_TO;
671 /** Offset 0x688 - LASTEXCPFROM. */
672 uint64_t u64LASTEXCPFROM;
673 /** Offset 0x690 - LASTEXCPTO. */
674 uint64_t u64LASTEXCPTO;
675 } guest;
676
677 /** Offset 0x698-0xFFF- Reserved. */
678 uint8_t u8Reserved10[0x1000-0x698];
679} SVM_VMCB;
680#pragma pack()
681
682#ifdef IN_RING0
683VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
684#endif /* IN_RING0 */
685
686/** @} */
687
688#endif
689
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