VirtualBox

source: vbox/trunk/include/VBox/hwacc_svm.h@ 1586

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1/** @file
2 * SVM Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006 InnoTek Systemberatung GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License as published by the Free Software Foundation,
12 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13 * distribution. VirtualBox OSE is distributed in the hope that it will
14 * be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * If you received this file as part of a commercial VirtualBox
17 * distribution, then only the terms of your commercial VirtualBox
18 * license agreement apply instead of the previous paragraph.
19 */
20
21#ifndef __VBox_svm_h__
22#define __VBox_svm_h__
23
24#include <VBox/types.h>
25#include <VBox/err.h>
26#include <VBox/cpum.h>
27#include <iprt/assert.h>
28#include <iprt/asm.h>
29
30/** @defgroup grp_svm svm Types and Definitions
31 * @ingroup grp_hwaccm
32 * @{
33 */
34
35
36/** @name SVM Basic Exit Reasons.
37 * @{
38 */
39/** Invalid guest state in VMCB. */
40#define SVM_EXIT_INVALID -1
41/** Read from CR0-CR15. */
42#define SVM_EXIT_READ_CR0 0x0
43#define SVM_EXIT_READ_CR1 0x1
44#define SVM_EXIT_READ_CR2 0x2
45#define SVM_EXIT_READ_CR3 0x3
46#define SVM_EXIT_READ_CR4 0x4
47#define SVM_EXIT_READ_CR5 0x5
48#define SVM_EXIT_READ_CR6 0x6
49#define SVM_EXIT_READ_CR7 0x7
50#define SVM_EXIT_READ_CR8 0x8
51#define SVM_EXIT_READ_CR9 0x9
52#define SVM_EXIT_READ_CR10 0xA
53#define SVM_EXIT_READ_CR11 0xB
54#define SVM_EXIT_READ_CR12 0xC
55#define SVM_EXIT_READ_CR13 0xD
56#define SVM_EXIT_READ_CR14 0xE
57#define SVM_EXIT_READ_CR15 0xF
58/** Writes to CR0-CR15. */
59#define SVM_EXIT_WRITE_CR0 0x10
60#define SVM_EXIT_WRITE_CR1 0x11
61#define SVM_EXIT_WRITE_CR2 0x12
62#define SVM_EXIT_WRITE_CR3 0x13
63#define SVM_EXIT_WRITE_CR4 0x14
64#define SVM_EXIT_WRITE_CR5 0x15
65#define SVM_EXIT_WRITE_CR6 0x16
66#define SVM_EXIT_WRITE_CR7 0x17
67#define SVM_EXIT_WRITE_CR8 0x18
68#define SVM_EXIT_WRITE_CR9 0x19
69#define SVM_EXIT_WRITE_CR10 0x1A
70#define SVM_EXIT_WRITE_CR11 0x1B
71#define SVM_EXIT_WRITE_CR12 0x1C
72#define SVM_EXIT_WRITE_CR13 0x1D
73#define SVM_EXIT_WRITE_CR14 0x1E
74#define SVM_EXIT_WRITE_CR15 0x1F
75/** Read from DR0-DR15. */
76#define SVM_EXIT_READ_DR0 0x20
77#define SVM_EXIT_READ_DR1 0x21
78#define SVM_EXIT_READ_DR2 0x22
79#define SVM_EXIT_READ_DR3 0x23
80#define SVM_EXIT_READ_DR4 0x24
81#define SVM_EXIT_READ_DR5 0x25
82#define SVM_EXIT_READ_DR6 0x26
83#define SVM_EXIT_READ_DR7 0x27
84#define SVM_EXIT_READ_DR8 0x28
85#define SVM_EXIT_READ_DR9 0x29
86#define SVM_EXIT_READ_DR10 0x2A
87#define SVM_EXIT_READ_DR11 0x2B
88#define SVM_EXIT_READ_DR12 0x2C
89#define SVM_EXIT_READ_DR13 0x2D
90#define SVM_EXIT_READ_DR14 0x2E
91#define SVM_EXIT_READ_DR15 0x2F
92/** Writes to DR0-DR15. */
93#define SVM_EXIT_WRITE_DR0 0x30
94#define SVM_EXIT_WRITE_DR1 0x31
95#define SVM_EXIT_WRITE_DR2 0x32
96#define SVM_EXIT_WRITE_DR3 0x33
97#define SVM_EXIT_WRITE_DR4 0x34
98#define SVM_EXIT_WRITE_DR5 0x35
99#define SVM_EXIT_WRITE_DR6 0x36
100#define SVM_EXIT_WRITE_DR7 0x37
101#define SVM_EXIT_WRITE_DR8 0x38
102#define SVM_EXIT_WRITE_DR9 0x39
103#define SVM_EXIT_WRITE_DR10 0x3A
104#define SVM_EXIT_WRITE_DR11 0x3B
105#define SVM_EXIT_WRITE_DR12 0x3C
106#define SVM_EXIT_WRITE_DR13 0x3D
107#define SVM_EXIT_WRITE_DR14 0x3E
108#define SVM_EXIT_WRITE_DR15 0x3F
109/* Exception 0-31. */
110#define SVM_EXIT_EXCEPTION_0 0x40
111#define SVM_EXIT_EXCEPTION_1 0x41
112#define SVM_EXIT_EXCEPTION_2 0x42
113#define SVM_EXIT_EXCEPTION_3 0x43
114#define SVM_EXIT_EXCEPTION_4 0x44
115#define SVM_EXIT_EXCEPTION_5 0x45
116#define SVM_EXIT_EXCEPTION_6 0x46
117#define SVM_EXIT_EXCEPTION_7 0x47
118#define SVM_EXIT_EXCEPTION_8 0x48
119#define SVM_EXIT_EXCEPTION_9 0x49
120#define SVM_EXIT_EXCEPTION_A 0x4A
121#define SVM_EXIT_EXCEPTION_B 0x4B
122#define SVM_EXIT_EXCEPTION_C 0x4C
123#define SVM_EXIT_EXCEPTION_D 0x4D
124#define SVM_EXIT_EXCEPTION_E 0x4E
125#define SVM_EXIT_EXCEPTION_F 0x4F
126#define SVM_EXIT_EXCEPTION_10 0x50
127#define SVM_EXIT_EXCEPTION_11 0x51
128#define SVM_EXIT_EXCEPTION_12 0x52
129#define SVM_EXIT_EXCEPTION_13 0x53
130#define SVM_EXIT_EXCEPTION_14 0x54
131#define SVM_EXIT_EXCEPTION_15 0x55
132#define SVM_EXIT_EXCEPTION_16 0x56
133#define SVM_EXIT_EXCEPTION_17 0x57
134#define SVM_EXIT_EXCEPTION_18 0x58
135#define SVM_EXIT_EXCEPTION_19 0x59
136#define SVM_EXIT_EXCEPTION_1A 0x5A
137#define SVM_EXIT_EXCEPTION_1B 0x5B
138#define SVM_EXIT_EXCEPTION_1C 0x5C
139#define SVM_EXIT_EXCEPTION_1D 0x5D
140#define SVM_EXIT_EXCEPTION_1E 0x5E
141#define SVM_EXIT_EXCEPTION_1F 0x5F
142/** Physical maskable interrupt. */
143#define SVM_EXIT_INTR 0x60
144/** Non-maskable interrupt. */
145#define SVM_EXIT_NMI 0x61
146/** System Management interrupt. */
147#define SVM_EXIT_SMI 0x62
148/** Physical INIT signal. */
149#define SVM_EXIT_INIT 0x63
150/** Virtual interrupt. */
151#define SVM_EXIT_VINTR 0x64
152/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
153#define SVM_EXIT_CR0_SEL_WRITE 0x65
154/** IDTR read. */
155#define SVM_EXIT_IDTR_READ 0x66
156/** GDTR read. */
157#define SVM_EXIT_GDTR_READ 0x67
158/** LDTR read. */
159#define SVM_EXIT_LDTR_READ 0x68
160/** TR read. */
161#define SVM_EXIT_TR_READ 0x69
162/** IDTR write. */
163#define SVM_EXIT_IDTR_WRITE 0x6A
164/** GDTR write. */
165#define SVM_EXIT_GDTR_WRITE 0x6B
166/** LDTR write. */
167#define SVM_EXIT_LDTR_WRITE 0x6C
168/** TR write. */
169#define SVM_EXIT_TR_WRITE 0x6D
170/** RDTSC instruction. */
171#define SVM_EXIT_RDTSC 0x6E
172/** RDPMC instruction. */
173#define SVM_EXIT_RDPMC 0x6F
174/** PUSHF instruction. */
175#define SVM_EXIT_PUSHF 0x70
176/** POPF instruction. */
177#define SVM_EXIT_POPF 0x71
178/** CPUID instruction. */
179#define SVM_EXIT_CPUID 0x72
180/** RSM instruction. */
181#define SVM_EXIT_RSM 0x73
182/** IRET instruction. */
183#define SVM_EXIT_IRET 0x74
184/** software interrupt (INTn instructions). */
185#define SVM_EXIT_SWINT 0x75
186/** INVD instruction. */
187#define SVM_EXIT_INVD 0x76
188/** PAUSE instruction. */
189#define SVM_EXIT_PAUSE 0x77
190/** HLT instruction. */
191#define SVM_EXIT_HLT 0x78
192/** INVLPG instructions. */
193#define SVM_EXIT_INVLPG 0x79
194/** INVLPGA instruction. */
195#define SVM_EXIT_INVLPGA 0x7A
196/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
197#define SVM_EXIT_IOIO 0x7B
198/** RDMSR or WRMSR access to protected MSR. */
199#define SVM_EXIT_MSR 0x7C
200/** task switch. */
201#define SVM_EXIT_TASK_SWITCH 0x7D
202/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
203#define SVM_EXIT_FERR_FREEZE 0x7E
204/** Shutdown. */
205#define SVM_EXIT_SHUTDOWN 0x7F
206/** VMRUN instruction. */
207#define SVM_EXIT_VMRUN 0x80
208/** VMMCALL instruction. */
209#define SVM_EXIT_VMMCALL 0x81
210/** VMLOAD instruction. */
211#define SVM_EXIT_VMLOAD 0x82
212/** VMSAVE instruction. */
213#define SVM_EXIT_VMSAVE 0x83
214/** STGI instruction. */
215#define SVM_EXIT_STGI 0x84
216/** CLGI instruction. */
217#define SVM_EXIT_CLGI 0x85
218/** SKINIT instruction. */
219#define SVM_EXIT_SKINIT 0x86
220/** RDTSCP instruction. */
221#define SVM_EXIT_RDTSCP 0x87
222/** ICEBP instruction. */
223#define SVM_EXIT_ICEBP 0x88
224/** WBINVD instruction. */
225#define SVM_INVD 0x89
226/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault.). */
227#define SVM_EXIT_NPF 0x400
228
229/** @} */
230
231
232/** @name SVM_VMCB.ctrl.u32InterceptCtrl1
233 * @{
234 */
235/* 0 Intercept INTR (physical maskable interrupt) */
236#define SVM_CTRL1_INTERCEPT_INTR BIT(0)
237/* 1 Intercept NMI */
238#define SVM_CTRL1_INTERCEPT_NMI BIT(1)
239/* 2 Intercept SMI */
240#define SVM_CTRL1_INTERCEPT_SMI BIT(2)
241/* 3 Intercept INIT */
242#define SVM_CTRL1_INTERCEPT_INIT BIT(3)
243/* 4 Intercept VINTR (virtual maskable interrupt) */
244#define SVM_CTRL1_INTERCEPT_VINTR BIT(4)
245/* 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
246#define SVM_CTRL1_INTERCEPT_CR0 BIT(5)
247/* 6 Intercept reads of IDTR */
248#define SVM_CTRL1_INTERCEPT_IDTR_READS BIT(6)
249/* 7 Intercept reads of GDTR */
250#define SVM_CTRL1_INTERCEPT_GDTR_READS BIT(7)
251/* 8 Intercept reads of LDTR */
252#define SVM_CTRL1_INTERCEPT_LDTR_READS BIT(8)
253/* 9 Intercept reads of TR */
254#define SVM_CTRL1_INTERCEPT_TR_READS BIT(9)
255/* 10 Intercept writes of IDTR */
256#define SVM_CTRL1_INTERCEPT_IDTR_WRITES BIT(10)
257/* 11 Intercept writes of GDTR */
258#define SVM_CTRL1_INTERCEPT_GDTR_WRITES BIT(11)
259/* 12 Intercept writes of LDTR */
260#define SVM_CTRL1_INTERCEPT_LDTR_WRITES BIT(12)
261/* 13 Intercept writes of TR */
262#define SVM_CTRL1_INTERCEPT_TR_WRITES BIT(13)
263/* 14 Intercept RDTSC instruction */
264#define SVM_CTRL1_INTERCEPT_RDTSC BIT(14)
265/* 15 Intercept RDPMC instruction */
266#define SVM_CTRL1_INTERCEPT_RDPMC BIT(15)
267/* 16 Intercept PUSHF instruction */
268#define SVM_CTRL1_INTERCEPT_PUSHF BIT(16)
269/* 17 Intercept POPF instruction */
270#define SVM_CTRL1_INTERCEPT_POPF BIT(17)
271/* 18 Intercept CPUID instruction */
272#define SVM_CTRL1_INTERCEPT_CPUID BIT(18)
273/* 19 Intercept RSM instruction */
274#define SVM_CTRL1_INTERCEPT_RSM BIT(19)
275/* 20 Intercept IRET instruction */
276#define SVM_CTRL1_INTERCEPT_IRET BIT(20)
277/* 21 Intercept INTn instruction */
278#define SVM_CTRL1_INTERCEPT_INTN BIT(21)
279/* 22 Intercept INVD instruction */
280#define SVM_CTRL1_INTERCEPT_INVD BIT(22)
281/* 23 Intercept PAUSE instruction */
282#define SVM_CTRL1_INTERCEPT_PAUSE BIT(23)
283/* 24 Intercept HLT instruction */
284#define SVM_CTRL1_INTERCEPT_HLT BIT(24)
285/* 25 Intercept INVLPG instruction */
286#define SVM_CTRL1_INTERCEPT_INVLPG BIT(25)
287/* 26 Intercept INVLPGA instruction */
288#define SVM_CTRL1_INTERCEPT_INVLPGA BIT(26)
289/* 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
290#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP BIT(27)
291/* 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
292#define SVM_CTRL1_INTERCEPT_MSR_SHADOW BIT(28)
293/* 29 Intercept task switches. */
294#define SVM_CTRL1_INTERCEPT_TASK_SWITCH BIT(29)
295/* 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
296#define SVM_CTRL1_INTERCEPT_FERR_FREEZE BIT(30)
297/* 31 Intercept shutdown events. */
298#define SVM_CTRL1_INTERCEPT_SHUTDOWN BIT(31)
299/** @} */
300
301
302/** @name SVM_VMCB.ctrl.u32InterceptCtrl2
303 * @{
304 */
305/* 0 Intercept VMRUN instruction */
306#define SVM_CTRL2_INTERCEPT_VMRUN BIT(0)
307/* 1 Intercept VMMCALL instruction */
308#define SVM_CTRL2_INTERCEPT_VMMCALL BIT(1)
309/* 2 Intercept VMLOAD instruction */
310#define SVM_CTRL2_INTERCEPT_VMLOAD BIT(2)
311/* 3 Intercept VMSAVE instruction */
312#define SVM_CTRL2_INTERCEPT_VMSAVE BIT(3)
313/* 4 Intercept STGI instruction */
314#define SVM_CTRL2_INTERCEPT_STGI BIT(4)
315/* 5 Intercept CLGI instruction */
316#define SVM_CTRL2_INTERCEPT_CLGI BIT(5)
317/* 6 Intercept SKINIT instruction */
318#define SVM_CTRL2_INTERCEPT_SKINIT BIT(6)
319/* 7 Intercept RDTSCP instruction */
320#define SVM_CTRL2_INTERCEPT_RDTSCP BIT(7)
321/* 8 Intercept ICEBP instruction */
322#define SVM_CTRL2_INTERCEPT_ICEBP BIT(8)
323/* 9 Intercept WBINVD instruction */
324#define SVM_CTRL2_INTERCEPT_WBINVD BIT(9)
325/** @} */
326
327/** @name SVM_VMCB.ctrl.u64NestedPaging
328 * @{
329 */
330#define SVM_NESTED_PAGING_ENABLE BIT(0)
331/** @} */
332
333/** @name SVM_VMCB.ctrl.u64IntShadow
334 * @{
335 */
336#define SVM_INTERRUPT_SHADOW_ACTIVE BIT(0)
337/** @} */
338
339
340/** @name SVM_INTCTRL.u3Type
341 * @{
342 */
343/** External or virtual interrupt. */
344#define SVM_EVENT_EXTERNAL_IRQ 0
345/** Non-maskable interrupt. */
346#define SVM_EVENT_NMI 1
347/** Exception; fault or trap. */
348#define SVM_EVENT_EXCEPTION 3
349/** Software interrupt. */
350#define SVM_EVENT_SOFTWARE_INT 4
351/** @} */
352
353
354
355
356/**
357 * SVM Selector type; includes hidden parts
358 */
359#pragma pack(1)
360typedef struct
361{
362 uint16_t u16Sel;
363 uint16_t u16Attr;
364 uint32_t u32Limit;
365 uint64_t u64Base; /* Only lower 32 bits are implemented for CS, DS, ES & SS. */
366} SVMSEL;
367#pragma pack()
368
369/**
370 * SVM GDTR/IDTR type
371 */
372#pragma pack(1)
373typedef struct
374{
375 uint16_t u16Reserved1;
376 uint16_t u16Reserved2;
377 uint32_t u32Limit; /* Only lower 16 bits are implemented. */
378 uint64_t u64Base;
379} SVMGDTR;
380#pragma pack()
381
382typedef SVMGDTR SVMIDTR;
383
384/**
385 * SVM Event injection structure
386 */
387#pragma pack(1)
388typedef union
389{
390 struct
391 {
392 uint32_t u8Vector : 8;
393 uint32_t u3Type : 3;
394 uint32_t u1ErrorCodeValid : 1;
395 uint32_t u19Reserved : 19;
396 uint32_t u1Valid : 1;
397 uint32_t u32ErrorCode : 32;
398 } n;
399 uint64_t au64[1];
400} SVM_EVENT;
401#pragma pack()
402
403
404/**
405 * SVM Interrupt control structure
406 */
407#pragma pack(1)
408typedef union
409{
410 struct
411 {
412 uint32_t u8VTPR : 8;
413 uint32_t u1VIrqValid : 1;
414 uint32_t u7Reserved : 7;
415 uint32_t u4VIrqPriority : 4;
416 uint32_t u1IgnoreTPR : 1;
417 uint32_t u3Reserved : 3;
418 uint32_t u1VIrqMasking : 1;
419 uint32_t u7Reserved2 : 7;
420 uint32_t u8VIrqVector : 8;
421 uint32_t u24Reserved : 24;
422 } n;
423 uint64_t au64[1];
424} SVM_INTCTRL;
425#pragma pack()
426
427
428/**
429 * SVM TLB control structure
430 */
431#pragma pack(1)
432typedef union
433{
434 struct
435 {
436 uint32_t u32ASID : 32;
437 uint32_t u1TLBFlush : 1;
438 uint32_t u7Reserved : 7;
439 uint32_t u24Reserved : 24;
440 } n;
441 uint64_t au64[1];
442} SVM_TLBCTRL;
443#pragma pack()
444
445
446/**
447 * SVM IOIO exit structure
448 */
449#pragma pack(1)
450typedef union
451{
452 struct
453 {
454 uint32_t u1Type : 1; /* 0 = out, 1 = in */
455 uint32_t u1Reserved : 1;
456 uint32_t u1STR : 1;
457 uint32_t u1REP : 1;
458 uint32_t u1OP8 : 1;
459 uint32_t u1OP16 : 1;
460 uint32_t u1OP32 : 1;
461 uint32_t u1ADDR16 : 1;
462 uint32_t u1ADDR32 : 1;
463 uint32_t u1ADDR64 : 1;
464 uint32_t u6Reserved : 6;
465 uint32_t u16Port : 16;
466 } n;
467 uint32_t au32[1];
468} SVM_IOIO_EXIT;
469#pragma pack()
470
471
472/**
473 * SVM VM Control Block. (VMCB)
474 */
475#pragma pack(1)
476typedef struct _SVM_VMCB
477{
478 /** Control Area. */
479 struct
480 {
481 /** Offset 0x00 - Intercept reads of CR0-15. */
482 uint16_t u16InterceptRdCRx;
483 /** Offset 0x02 - Intercept writes to CR0-15. */
484 uint16_t u16InterceptWrCRx;
485 /** Offset 0x04 - Intercept reads of DR0-15. */
486 uint16_t u16InterceptRdDRx;
487 /** Offset 0x06 - Intercept writes to DR0-15. */
488 uint16_t u16InterceptWrDRx;
489 /** Offset 0x08 - Intercept exception vectors 0-31. */
490 uint32_t u32InterceptException;
491 /** Offset 0x0C - Intercept control field 1. */
492 uint32_t u32InterceptCtrl1;
493 /** Offset 0x0C - Intercept control field 2. */
494 uint32_t u32InterceptCtrl2;
495 /** Offset 0x14-0x3F - Reserved. */
496 uint8_t u8Reserved[0x40-0x14];
497 /** Offset 0x40 - Physical address of IOPM. */
498 uint64_t u64IOPMPhysAddr;
499 /** Offset 0x48 - Physical address of MSRPM. */
500 uint64_t u64MSRPMPhysAddr;
501 /** Offset 0x50 - TSC Offset. */
502 uint64_t u64TSCOffset;
503 /** Offset 0x58 - TLB control field. */
504 SVM_TLBCTRL TLBCtrl;
505 /** Offset 0x60 - Interrupt control field. */
506 SVM_INTCTRL IntCtrl;
507 /** Offset 0x68 - Interrupt shadow. */
508 uint64_t u64IntShadow;
509 /** Offset 0x70 - Exit code. */
510 uint64_t u64ExitCode;
511 /** Offset 0x78 - Exit info 1. */
512 uint64_t u64ExitInfo1;
513 /** Offset 0x80 - Exit info 2. */
514 uint64_t u64ExitInfo2;
515 /** Offset 0x88 - Exit Interrupt info. */
516 SVM_EVENT ExitIntInfo;
517 /** Offset 0x90 - Nested Paging. */
518 uint64_t u64NestedPaging;
519 /** Offset 0x98-0xA7 - Reserved. */
520 uint8_t u8Reserved2[0xA8-0x98];
521 /** Offset 0xA8 - Event injection. */
522 SVM_EVENT EventInject;
523 /** Offset 0xB0 - Host CR3 for nested paging. */
524 uint64_t u64HostCR3;
525 /** Offset 0xB8 - LBR Virtualization. */
526 uint64_t u64LBRVirt;
527 } ctrl;
528
529 /** Offset 0xC0-0x3FF - Reserved. */
530 uint8_t u8Reserved3[0x400-0xC0];
531
532 /* State Save Area. Starts at offset 0x400. */
533 struct
534 {
535 /** Offset 0x400 - Guest ES register + hidden parts. */
536 SVMSEL ES;
537 /** Offset 0x410 - Guest CS register + hidden parts. */
538 SVMSEL CS;
539 /** Offset 0x420 - Guest SS register + hidden parts. */
540 SVMSEL SS;
541 /** Offset 0x430 - Guest DS register + hidden parts. */
542 SVMSEL DS;
543 /** Offset 0x440 - Guest FS register + hidden parts. */
544 SVMSEL FS;
545 /** Offset 0x450 - Guest GS register + hidden parts. */
546 SVMSEL GS;
547 /** Offset 0x460 - Guest GDTR register. */
548 SVMGDTR GDTR;
549 /** Offset 0x470 - Guest LDTR register + hidden parts. */
550 SVMSEL LDTR;
551 /** Offset 0x480 - Guest IDTR register. */
552 SVMIDTR IDTR;
553 /** Offset 0x490 - Guest TR register + hidden parts. */
554 SVMSEL TR;
555 /** Offset 0x4A0-0x4CA - Reserved. */
556 uint8_t u8Reserved4[0x4CB-0x4A0];
557 /** Offset 0x4CB - CPL. */
558 uint8_t u8CPL;
559 /** Offset 0x4CC-0x4CF - Reserved. */
560 uint8_t u8Reserved5[0x4D0-0x4CC];
561 /** Offset 0x4D0 - EFER. */
562 uint64_t u64EFER;
563 /** Offset 0x4D8-0x547 - Reserved. */
564 uint8_t u8Reserved6[0x548-0x4D8];
565 /** Offset 0x548 - CR4. */
566 uint64_t u64CR4;
567 /** Offset 0x550 - CR3. */
568 uint64_t u64CR3;
569 /** Offset 0x558 - CR0. */
570 uint64_t u64CR0;
571 /** Offset 0x560 - DR7. */
572 uint64_t u64DR7;
573 /** Offset 0x568 - DR6. */
574 uint64_t u64DR6;
575 /** Offset 0x570 - RFLAGS. */
576 uint64_t u64RFlags;
577 /** Offset 0x578 - RIP. */
578 uint64_t u64RIP;
579 /** Offset 0x580-0x5D7 - Reserved. */
580 uint8_t u8Reserved7[0x5D8-0x580];
581 /** Offset 0x5D8 - RSP. */
582 uint64_t u64RSP;
583 /** Offset 0x5E0-0x5F7 - Reserved. */
584 uint8_t u8Reserved8[0x5F8-0x5E0];
585 /** Offset 0x5F8 - RAX. */
586 uint64_t u64RAX;
587 /** Offset 0x600 - STAR. */
588 uint64_t u64STAR;
589 /** Offset 0x608 - LSTAR. */
590 uint64_t u64LSTAR;
591 /** Offset 0x610 - CSTAR. */
592 uint64_t u64CSTAR;
593 /** Offset 0x618 - SFMASK. */
594 uint64_t u64SFMASK;
595 /** Offset 0x620 - KernelGSBase. */
596 uint64_t u64KernelGSBase;
597 /** Offset 0x628 - SYSENTER_CS. */
598 uint64_t u64SysEnterCS;
599 /** Offset 0x630 - SYSENTER_ESP. */
600 uint64_t u64SysEnterESP;
601 /** Offset 0x638 - SYSENTER_EIP. */
602 uint64_t u64SysEnterEIP;
603 /** Offset 0x640 - CR2. */
604 uint64_t u64CR2;
605 /** Offset 0x648-0x667 - Reserved. */
606 uint8_t u8Reserved9[0x668-0x648];
607 /** Offset 0x668 - G_PAT. */
608 uint64_t u64GPAT;
609 /** Offset 0x670 - DBGCTL. */
610 uint64_t u64DBGCTL;
611 /** Offset 0x678 - BR_FROM. */
612 uint64_t u64BR_FROM;
613 /** Offset 0x680 - BR_TO. */
614 uint64_t u64BR_TO;
615 /** Offset 0x688 - LASTEXCPFROM. */
616 uint64_t u64LASTEXCPFROM;
617 /** Offset 0x690 - LASTEXCPTO. */
618 uint64_t u64LASTEXCPTO;
619 } guest;
620
621 /** Offset 0x698-0xFFF- Reserved. */
622 uint8_t u8Reserved10[0x1000-0x698];
623} SVM_VMCB;
624#pragma pack()
625
626
627/**
628 * Prepares for and executes VMRUN
629 *
630 * @returns VBox status code
631 * @param pVMCBHostPhys Physical address of host VMCB
632 * @param pVMCBPhys Physical address of the VMCB
633 * @param pCtx Guest context
634 */
635DECLASM(int) SVMVMRun(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx);
636
637
638/**
639 * Executes INVLPGA
640 *
641 * @param pPageGC Virtual page to invalidate
642 * @param uASID Tagged TLB id
643 */
644#if RT_INLINE_ASM_EXTERNAL
645DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t uASID);
646#else
647DECLINLINE(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t uASID)
648{
649# if RT_INLINE_ASM_GNU_STYLE
650 AssertFailed();
651# else
652 __asm
653 {
654# ifdef __AMD64__
655 mov rax, pPageGC
656# else
657 mov eax, pPageGC
658# endif
659 push ecx
660 mov ecx, uASID
661 _emit 0x0F
662 _emit 0x01
663 _emit 0xDF /* invlpga rAX, ECX */
664
665 pop ecx
666 }
667# endif
668}
669#endif
670
671
672
673/** @} */
674
675#endif
676
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